upgrade to default kernel

diff --git a/target/linux/visionfive/config-5.15 b/target/linux/visionfive/config-5.15
index b79770e90e7c5cc4f715510f3890d3584c680019..93f062dfb6317933f7adb7ec37e8d60884b1ea63 100644 (file)
--- a/target/linux/visionfive/config-5.15
+++ b/target/linux/visionfive/config-5.15
@@ -1,4 +1,70 @@
 CONFIG_64BIT=y
+CONFIG_6PACK=m
+CONFIG_8139CP=m
+CONFIG_8139TOO=m
+CONFIG_8139TOO_8129=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+CONFIG_842_COMPRESS=y
+CONFIG_842_DECOMPRESS=y
+CONFIG_9P_FS=m
+CONFIG_9P_FSCACHE=y
+CONFIG_9P_FS_POSIX_ACL=y
+CONFIG_9P_FS_SECURITY=y
+CONFIG_ABP060MG=m
+CONFIG_AC97_BUS=m
+CONFIG_ACCESSIBILITY=y
+CONFIG_ACENIC=m
+# CONFIG_ACENIC_OMIT_TIGON_I is not set
+CONFIG_AD5272=m
+CONFIG_AD5770R=m
+CONFIG_AD7124=m
+CONFIG_AD7292=m
+CONFIG_AD7766=m
+CONFIG_AD7949=m
+CONFIG_AD9467=m
+CONFIG_ADAPTEC_STARFIRE=m
+CONFIG_ADIN_PHY=m
+CONFIG_ADIS16475=m
+CONFIG_ADI_AXI_ADC=m
+CONFIG_ADUX1020=m
+CONFIG_ADXL372=m
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372_SPI=m
+CONFIG_ADXRS290=m
+CONFIG_AD_SIGMA_DELTA=m
+CONFIG_AFFS_FS=m
+CONFIG_AFS_DEBUG=y
+CONFIG_AFS_FS=m
+CONFIG_AFS_FSCACHE=y
+CONFIG_AF_KCM=m
+CONFIG_AF_RXRPC=m
+CONFIG_AF_RXRPC_DEBUG=y
+CONFIG_AIC79XX_CMDS_PER_DEVICE=4
+# CONFIG_AIC79XX_DEBUG_ENABLE is not set
+CONFIG_AIC79XX_DEBUG_MASK=0
+# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
+CONFIG_AIC79XX_RESET_DELAY_MS=15000
+CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
+# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
+CONFIG_AIC7XXX_DEBUG_MASK=0
+# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
+CONFIG_AIC7XXX_RESET_DELAY_MS=15000
+CONFIG_AIX_PARTITION=y
+CONFIG_AL3010=m
+CONFIG_ALIM7101_WDT=m
+# CONFIG_ALTERA_FREEZE_BRIDGE is not set
+CONFIG_ALTERA_MSGDMA=m
+CONFIG_ALTERA_PR_IP_CORE=m
+CONFIG_ALTERA_PR_IP_CORE_PLAT=m
+CONFIG_ALTERA_TSE=m
+CONFIG_ALX=m
+CONFIG_AMD8111_ETH=m
+CONFIG_AMD_PHY=m
+CONFIG_AMIGA_PARTITION=y
+CONFIG_APDS9802ALS=m
+CONFIG_AQUANTIA_PHY=m
 CONFIG_ARCH_CLOCKSOURCE_INIT=y
 CONFIG_ARCH_DMA_ADDR_T_64BIT=y
 CONFIG_ARCH_MMAP_RND_BITS=18
@@ -15,95 +81,744 @@ CONFIG_ASN1=y
 CONFIG_ASSOCIATIVE_ARRAY=y
 CONFIG_ASYMMETRIC_KEY_TYPE=y
 CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ASYNC_TX_DMA=y
+CONFIG_ASYNC_XOR=m
+CONFIG_AT803X_PHY=m
 CONFIG_ATA=y
-CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATALK=m
+CONFIG_ATA_GENERIC=m
+CONFIG_ATA_OVER_ETH=m
+CONFIG_ATA_PIIX=y
+CONFIG_ATL1=m
+CONFIG_ATL1C=m
+CONFIG_ATL1E=m
+CONFIG_ATL2=m
+CONFIG_ATM=m
+CONFIG_ATM_BR2684=m
+CONFIG_ATM_CLIP=m
+CONFIG_ATM_LANE=m
+CONFIG_ATOMIC64_SELFTEST=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUXDISPLAY=y
+CONFIG_AUXILIARY_BUS=y
+CONFIG_AX25=m
+CONFIG_B44=m
+CONFIG_B44_PCI=y
+CONFIG_B44_PCICORE_AUTOSELECT=y
+CONFIG_B44_PCI_AUTOSELECT=y
+CONFIG_B53=m
+CONFIG_B53_MDIO_DRIVER=m
+CONFIG_B53_MMAP_DRIVER=m
+CONFIG_B53_SERDES=m
+CONFIG_B53_SPI_DRIVER=m
+CONFIG_B53_SRAB_DRIVER=m
+CONFIG_BACKLIGHT_ARCXCNN=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_KTD253=m
+CONFIG_BACKLIGHT_LED=m
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_BAREUDP=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_BATMAN_V=y
+CONFIG_BATMAN_ADV_BLA=y
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_BATMAN_ADV_DEBUG is not set
+CONFIG_BATMAN_ADV_MCAST=y
+CONFIG_BATMAN_ADV_NC=y
+CONFIG_BATTERY_CW2015=m
+CONFIG_BAYCOM_SER_FDX=m
+CONFIG_BAYCOM_SER_HDX=m
+CONFIG_BCACHE=m
+# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
+# CONFIG_BCACHE_CLOSURES_DEBUG is not set
+# CONFIG_BCACHE_DEBUG is not set
+CONFIG_BCM54140_PHY=m
+CONFIG_BCM7XXX_PHY=m
+CONFIG_BCM87XX_PHY=m
+CONFIG_BCMGENET=m
+CONFIG_BCM_NET_PHYLIB=m
+CONFIG_BE2ISCSI=m
+CONFIG_BE2NET=m
+CONFIG_BE2NET_BE2=y
+CONFIG_BE2NET_BE3=y
+# CONFIG_BE2NET_HWMON is not set
+CONFIG_BE2NET_LANCER=y
+CONFIG_BE2NET_SKYHAWK=y
+# CONFIG_BEFS_DEBUG is not set
+CONFIG_BEFS_FS=m
+# CONFIG_BFQ_CGROUP_DEBUG is not set
+CONFIG_BFQ_GROUP_IOSCHED=y
+CONFIG_BH1750=m
+CONFIG_BINFMT_MISC=m
+CONFIG_BLK_CGROUP=y
+# CONFIG_BLK_CGROUP_FC_APPID is not set
+CONFIG_BLK_CGROUP_IOCOST=y
+CONFIG_BLK_CGROUP_IOLATENCY=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_DEV_3W_XXXX_RAID=m
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DRBD=m
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
+CONFIG_BLK_DEV_MD=y
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_NULL_BLK=m
+CONFIG_BLK_DEV_NVME=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_RBD=m
+CONFIG_BLK_DEV_RNBD=y
+CONFIG_BLK_DEV_RNBD_CLIENT=m
+CONFIG_BLK_DEV_RNBD_SERVER=m
 CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SX8=m
+CONFIG_BLK_DEV_THROTTLING=y
+# CONFIG_BLK_DEV_THROTTLING_LOW is not set
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_INLINE_ENCRYPTION=y
+# CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK is not set
 CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_RDMA=y
 CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_CAVIUM_PTP=y
+CONFIG_BLK_RQ_ALLOC_TIME=y
+CONFIG_BLK_SED_OPAL=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_MQ=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BMC150_ACCEL=m
+CONFIG_BMC150_ACCEL_I2C=m
+CONFIG_BMC150_ACCEL_SPI=m
+CONFIG_BME680=m
+CONFIG_BME680_I2C=m
+CONFIG_BME680_SPI=m
+CONFIG_BMP280=m
+CONFIG_BMP280_I2C=m
+CONFIG_BMP280_SPI=m
+CONFIG_BNA=m
+CONFIG_BNX2=m
+CONFIG_BNX2X=m
+CONFIG_BNXT=m
+CONFIG_BNXT_DCB=y
+CONFIG_BNXT_FLOWER_OFFLOAD=y
+CONFIG_BNXT_HWMON=y
+CONFIG_BNXT_SRIOV=y
+CONFIG_BONDING=m
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_BPF_STREAM_PARSER=y
+CONFIG_BPQETHER=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_MRP=y
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_BSD_DISKLABEL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BT=m
+CONFIG_BTREE=y
+CONFIG_BTRFS_FS=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_BT_BCM=m
+# CONFIG_BT_DEBUGFS is not set
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_AG6XX=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_MRVL=y
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_BT_HCIUART_SERDEV=y
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_INTEL=m
+CONFIG_BT_LEDS=y
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_BT_MSFTEXT=y
+CONFIG_BT_MTKSDIO=m
+CONFIG_BT_QCA=m
+CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_CACHEFILES=m
+# CONFIG_CACHEFILES_DEBUG is not set
+CONFIG_CAN=m
+CONFIG_CAN_SLCAN=m
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_VXCAN=m
+CONFIG_CASSINI=m
+CONFIG_CB710_CORE=m
+# CONFIG_CB710_DEBUG is not set
+CONFIG_CB710_DEBUG_ASSUMPTIONS=y
 CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CDROM=y
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_CEC_CORE=y
+CONFIG_CEC_NOTIFIER=y
+CONFIG_CEPH_FS=m
+CONFIG_CEPH_FSCACHE=y
+CONFIG_CEPH_FS_POSIX_ACL=y
+CONFIG_CEPH_FS_SECURITY_LABEL=y
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+CONFIG_CFG80211=m
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_DEBUGFS=y
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_NET_CLASSID=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_CGROUP_PIDS=y
+# CONFIG_CGROUP_RDMA is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CHARGER_BD99954=m
+CONFIG_CHARGER_BQ2515X=m
+CONFIG_CHARGER_LT3651=m
+CONFIG_CHARGER_MAX77650=m
+CONFIG_CHARGER_SMB347=m
+CONFIG_CHARGER_UCS1002=m
+CONFIG_CHARLCD=m
+CONFIG_CHARLCD_BL_FLASH=y
+# CONFIG_CHARLCD_BL_OFF is not set
+# CONFIG_CHARLCD_BL_ON is not set
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHECK_SIGNATURE=y
+CONFIG_CHELSIO_INLINE_CRYPTO=y
+CONFIG_CHELSIO_IPSEC_INLINE=m
+CONFIG_CHELSIO_LIB=m
+CONFIG_CHELSIO_T1=m
+CONFIG_CHELSIO_T1_1G=y
+CONFIG_CHELSIO_T3=m
+CONFIG_CHELSIO_T4=m
+CONFIG_CHELSIO_T4VF=m
+CONFIG_CHELSIO_T4_DCB=y
+# CONFIG_CHELSIO_T4_FCOE is not set
+CONFIG_CHELSIO_TLS_DEVICE=m
+CONFIG_CHR_DEV_SCH=m
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CICADA_PHY=m
+CONFIG_CIFS=m
+CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_CIFS_FSCACHE=y
+# CONFIG_CIFS_SMB_DIRECT is not set
+CONFIG_CIFS_UPCALL=y
+CONFIG_CLEANCACHE=y
 CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
 CONFIG_CLK_SIFIVE=y
 CONFIG_CLK_SIFIVE_PRCI=y
 CONFIG_CLK_STARFIVE_JH7100=y
+CONFIG_CLK_STARFIVE_JH7100_AUDIO=y
 CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLS_U32_PERF=y
 CONFIG_CLZ_TAB=y
+CONFIG_CM32181=m
+CONFIG_CM3605=m
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+CONFIG_CMA_DEBUGFS=y
+CONFIG_CMA_SIZE_MBYTES=32
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
 CONFIG_CMODEL_MEDANY=y
 # CONFIG_CMODEL_MEDLOW is not set
+CONFIG_CNIC=m
+CONFIG_CODA_FS=m
 CONFIG_COMMON_CLK=y
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_COMPAT_BRK=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_COMMON_CLK_PWM=m
+CONFIG_COMMON_CLK_SI544=m
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_LOGLEVEL_QUIET=3
+CONFIG_CONTEXT_TRACKING=y
+# CONFIG_CONTEXT_TRACKING_FORCE is not set
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CORTINA_PHY=m
+CONFIG_CPUSETS=y
 CONFIG_CPU_ISOLATION=y
 CONFIG_CPU_RMAP=y
+CONFIG_CRAMFS=m
+CONFIG_CRASH_CORE=y
 CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC4=m
+CONFIG_CRC64=m
 CONFIG_CRC7=y
+CONFIG_CRC8=m
+CONFIG_CRC_CCITT=m
 CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRYPTO_842=y
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_AEGIS128=m
+CONFIG_CRYPTO_AES_TI=m
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_BLAKE2B=y
+CONFIG_CRYPTO_BLAKE2S=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_CHACHA20=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_CRC32=m
 CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CURVE25519=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_DH=y
 CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_DRBG_HASH=y
 CONFIG_CRYPTO_DRBG_HMAC=y
 CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_ECC=m
+CONFIG_CRYPTO_ECDH=m
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_ESSIV=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_FIPS=y
 CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_LIB_BLAKE2S=m
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_DES=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
 CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
 CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_SM4=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_NHPOLY1305=m
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_POLY1305=m
+CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_RNG_DEFAULT=y
 CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA3=m
 CONFIG_CRYPTO_SHA512=y
-CONFIG_DA9063_WATCHDOG=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DEVMEM=y
+CONFIG_CRYPTO_SM2=m
+CONFIG_CRYPTO_SM3=m
+CONFIG_CRYPTO_SM4=m
+CONFIG_CRYPTO_STATS=y
+CONFIG_CRYPTO_STREEBOG=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER_API_AEAD=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_RNG=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_XXHASH=y
+CONFIG_CRYPTO_ZSTD=m
+CONFIG_CUSE=m
+CONFIG_DA280=m
+CONFIG_DA311=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_DAX=y
+CONFIG_DCB=y
+CONFIG_DE2104X=m
+CONFIG_DE2104X_DSL=0
+CONFIG_DEBUG_DEVRES=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_KERNEL_DC is not set
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_RODATA_TEST=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_VM_PGFLAGS is not set
+# CONFIG_DEBUG_VM_RB is not set
+# CONFIG_DEBUG_VM_VMACACHE is not set
+CONFIG_DEBUG_WX=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DNOTIFY=y
+CONFIG_DEV_APPLETALK=m
+CONFIG_DEV_COREDUMP=y
+CONFIG_DHT11=m
+CONFIG_DIMLIB=y
+CONFIG_DL2K=m
+CONFIG_DLM=m
+CONFIG_DLM_DEBUG=y
+CONFIG_DM9102=m
+CONFIG_DMABUF_HEAPS=y
+# CONFIG_DMABUF_HEAPS_CMA is not set
+CONFIG_DMABUF_HEAPS_SYSTEM=y
+CONFIG_DMADEVICES=y
+CONFIG_DMARD10=m
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DM_BIO_PRISON=m
+CONFIG_DM_BUFIO=y
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_CLONE=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_DEBUG=y
+CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y
+# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set
+CONFIG_DM_DELAY=m
+CONFIG_DM_DUST=m
+CONFIG_DM_EBS=m
+CONFIG_DM_FLAKEY=m
+CONFIG_DM_INIT=y
+CONFIG_DM_INTEGRITY=m
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_LOG_WRITES=m
+CONFIG_DM_MIRROR=y
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_HST=m
+# CONFIG_DM_MULTIPATH_IOA is not set
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_PERSISTENT_DATA=m
+CONFIG_DM_RAID=m
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_SWITCH=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_UEVENT=y
+CONFIG_DM_UNSTRIPED=m
+CONFIG_DM_VERITY=m
+CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
+# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_ZERO=y
+CONFIG_DM_ZONED=m
+CONFIG_DNET=m
+CONFIG_DNS_RESOLVER=m
+CONFIG_DP83822_PHY=m
+CONFIG_DP83848_PHY=m
+CONFIG_DP83869_PHY=m
+CONFIG_DPOT_DAC=m
+# CONFIG_DRBD_FAULT_INJECTION is not set
+CONFIG_DRM=y
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU_SI=y
+CONFIG_DRM_AMDGPU_USERPTR=y
+CONFIG_DRM_AMD_ACP=y
+CONFIG_DRM_AMD_DC=y
+CONFIG_DRM_AMD_DC_HDCP=y
+CONFIG_DRM_AMD_DC_SI=y
+CONFIG_DRM_ANALOGIX_ANX6345=m
+CONFIG_DRM_ANALOGIX_ANX78XX=m
+CONFIG_DRM_ANALOGIX_DP=m
+CONFIG_DRM_AST=m
+CONFIG_DRM_BOCHS=m
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_CHRONTEL_CH7033=m
+CONFIG_DRM_CIRRUS_QEMU=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+CONFIG_DRM_DP_AUX_BUS=m
+CONFIG_DRM_DP_AUX_CHARDEV=y
+CONFIG_DRM_DP_CEC=y
+CONFIG_DRM_GEM_CMA_HELPER=y
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+CONFIG_DRM_I2C_NXP_TDA9950=y
+CONFIG_DRM_I2C_NXP_TDA998X=y
+CONFIG_DRM_KMS_CMA_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_MGAG200=m
+CONFIG_DRM_MIPI_DBI=m
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_NOUVEAU_BACKLIGHT=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ELIDA_KD35T133=m
+CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
+CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
+CONFIG_DRM_PANEL_NOVATEK_NT35510=m
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
+CONFIG_DRM_PANEL_RONBO_RB070D30=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
+CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
+CONFIG_DRM_PANEL_VISIONOX_RM69299=m
+CONFIG_DRM_PARADE_PS8640=m
+CONFIG_DRM_QXL=m
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_RADEON_USERPTR=y
+CONFIG_DRM_SCHED=m
+CONFIG_DRM_SII9234=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
+CONFIG_DRM_STARFIVE=y
+CONFIG_DRM_TI_SN65DSI86=m
+CONFIG_DRM_TI_TFP410=m
+CONFIG_DRM_TI_TPD12S015=m
+CONFIG_DRM_TOSHIBA_TC358762=m
+CONFIG_DRM_TOSHIBA_TC358764=m
+CONFIG_DRM_TOSHIBA_TC358768=m
+CONFIG_DRM_TOSHIBA_TC358775=m
+CONFIG_DRM_TTM=m
+CONFIG_DRM_TTM_HELPER=m
+CONFIG_DRM_VGEM=m
+CONFIG_DRM_VIRTIO_GPU=m
+CONFIG_DRM_VRAM_HELPER=m
+CONFIG_DST_CACHE=y
 CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
+# CONFIG_DTPM is not set
+CONFIG_DUMMY=m
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_DVB_B2C2_FLEXCOP_PCI=m
+# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
+CONFIG_DVB_BUDGET=m
+CONFIG_DVB_BUDGET_CORE=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_DDBRIDGE=m
+# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
+CONFIG_DVB_FIREDTV=m
+CONFIG_DVB_NGENE=m
+CONFIG_DVB_PLUTO2=m
+CONFIG_DVB_PT1=m
+# CONFIG_DVB_PT3 is not set
+CONFIG_DVB_TDA1004X=m
+CONFIG_DW_AXI_DMAC=y
+# CONFIG_DW_AXI_DMAC_STARFIVE is not set
+CONFIG_DW_DMAC=m
+CONFIG_DW_DMAC_CORE=m
+CONFIG_DW_DMAC_PCI=m
+CONFIG_DW_EDMA=m
+CONFIG_DW_EDMA_PCIE=m
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_E100=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_ECHO=m
+CONFIG_ECRYPT_FS=m
+# CONFIG_ECRYPT_FS_MESSAGING is not set
 CONFIG_EDAC=y
 # CONFIG_EDAC_DEBUG is not set
 CONFIG_EDAC_LEGACY_SYSFS=y
 CONFIG_EDAC_SIFIVE=y
 CONFIG_EDAC_SUPPORT=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_GENERIC_STUB=y
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-CONFIG_ELF_CORE=y
+CONFIG_EEPROM_93CX6=m
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_EE1004=m
+CONFIG_EEPROM_IDT_89HPESX=m
+CONFIG_EEPROM_LEGACY=m
+CONFIG_EEPROM_MAX6875=m
+CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_ENIC=m
+CONFIG_ENVELOPE_DETECTOR=m
+CONFIG_EPIC100=m
+CONFIG_EQUALIZER=m
+CONFIG_EROFS_FS=m
+# CONFIG_EROFS_FS_DEBUG is not set
+CONFIG_EROFS_FS_POSIX_ACL=y
+CONFIG_EROFS_FS_SECURITY=y
+CONFIG_EROFS_FS_XATTR=y
+CONFIG_EROFS_FS_ZIP=y
 CONFIG_ERRATA_SIFIVE=y
 CONFIG_ERRATA_SIFIVE_CIP_1200=y
 CONFIG_ERRATA_SIFIVE_CIP_453=y
+CONFIG_ET131X=m
+CONFIG_ETHOC=m
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_EXFAT_FS=m
+CONFIG_EXPORTFS_BLOCK_OPS=y
 CONFIG_EXT4_FS=y
-CONFIG_FAILOVER=y
-CONFIG_FHANDLE=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_F2FS_FS=m
+CONFIG_F2FS_FS_COMPRESSION=y
+CONFIG_F2FS_FS_LZ4=y
+CONFIG_F2FS_FS_LZ4HC=y
+CONFIG_F2FS_FS_LZO=y
+CONFIG_F2FS_FS_LZORLE=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_FS_ZSTD=y
+CONFIG_FAILOVER=m
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_FAT_FS=m
+CONFIG_FB=y
+CONFIG_FB_BACKLIGHT=m
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SM501 is not set
+CONFIG_FB_SSD1307=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FB_VIRTUAL=m
+CONFIG_FCOE=m
+CONFIG_FEALNX=m
+CONFIG_FIREWIRE=m
+CONFIG_FIREWIRE_NET=m
+CONFIG_FIREWIRE_NOSY=m
+CONFIG_FIREWIRE_OHCI=m
+CONFIG_FIREWIRE_SBP2=m
+CONFIG_FIRMWARE_EDID=y
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_FM10K=m
+CONFIG_FORCEDETH=m
+CONFIG_FPGA=m
+CONFIG_FPGA_BRIDGE=m
+CONFIG_FPGA_DFL=m
+CONFIG_FPGA_DFL_AFU=m
+# CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000 is not set
+CONFIG_FPGA_DFL_PCI=m
+CONFIG_FPGA_MGR_ALTERA_CVP=m
+CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
+CONFIG_FPGA_MGR_ICE40_SPI=m
+CONFIG_FPGA_MGR_MACHXO2_SPI=m
+CONFIG_FPGA_MGR_XILINX_SPI=m
+CONFIG_FPGA_REGION=m
 CONFIG_FPU=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FRAME_WARN=2048
+CONFIG_FREEZER=y
+CONFIG_FRONTSWAP=y
+CONFIG_FSCACHE=m
+# CONFIG_FSCACHE_DEBUG is not set
+CONFIG_FSCACHE_STATS=y
+CONFIG_FSI=m
+# CONFIG_FSI_MASTER_ASPEED is not set
+CONFIG_FSI_MASTER_GPIO=m
+CONFIG_FSI_MASTER_HUB=m
+# CONFIG_FSI_NEW_DEV_NODE is not set
+# CONFIG_FSI_SBEFIFO is not set
+CONFIG_FSI_SCOM=m
+CONFIG_FS_DAX=y
+CONFIG_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_ALGS=y
+CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
 CONFIG_FS_IOMAP=y
 CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FS_VERITY=y
+# CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set
+# CONFIG_FS_VERITY_DEBUG is not set
+CONFIG_FUNCTION_ERROR_INJECTION=y
+CONFIG_FUSE_FS=m
+CONFIG_FUSION=y
+CONFIG_FUSION_CTL=m
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_LAN=m
+CONFIG_FUSION_LOGGING=y
+CONFIG_FUSION_MAX_SGE=40
+CONFIG_FUSION_SAS=m
+CONFIG_FUSION_SPI=m
 CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_COMPRESS=y
 CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FXAS21002C=m
+CONFIG_FXAS21002C_I2C=m
+CONFIG_FXAS21002C_SPI=m
+CONFIG_FXOS8700=m
+CONFIG_FXOS8700_I2C=m
+CONFIG_FXOS8700_SPI=m
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_GENERIC_ARCH_TOPOLOGY=y
 CONFIG_GENERIC_BUG=y
@@ -116,6 +831,7 @@ CONFIG_GENERIC_GETTIMEOFDAY=y
 CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IOREMAP=y
 CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
 CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
@@ -123,6 +839,7 @@ CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
 CONFIG_GENERIC_MSI_IRQ=y
 CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
 CONFIG_GENERIC_PINCONF=y
 CONFIG_GENERIC_PINCTRL_GROUPS=y
 CONFIG_GENERIC_PINMUX_FUNCTIONS=y
@@ -131,275 +848,2279 @@ CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENEVE=m
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
 CONFIG_GLOB=y
+CONFIG_GNSS=m
+CONFIG_GNSS_MTK_SERIAL=m
+CONFIG_GNSS_SERIAL=m
+CONFIG_GNSS_SIRF_SERIAL=m
+CONFIG_GNSS_UBX_SERIAL=m
 CONFIG_GOLDFISH=y
 # CONFIG_GOLDFISH_PIPE is not set
 # CONFIG_GOLDFISH_TTY is not set
+CONFIG_GP2AP002=m
 CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_FASTPATH_LIMIT=256
 CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_AGGREGATOR=m
+CONFIG_GPIO_BD9571MWV=m
+CONFIG_GPIO_CADENCE=m
 CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_CDEV_V1=y
 CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MAX77650=m
+CONFIG_GPIO_PCA953X=m
+CONFIG_GPIO_PCA9570=m
+CONFIG_GPIO_PCI_IDIO_16=m
 CONFIG_GPIO_SIFIVE=y
+CONFIG_GPIO_SYSCON=m
+CONFIG_GPIO_TPS65086=m
+CONFIG_GRACE_PERIOD=m
+CONFIG_GRO_CELLS=y
+CONFIG_GTP=m
+CONFIG_HAMACHI=m
+CONFIG_HAMRADIO=y
 CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HAPPYMEAL=m
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
+CONFIG_HD44780=m
+CONFIG_HD44780_COMMON=m
+CONFIG_HDC2010=m
+CONFIG_HDMI=y
+CONFIG_HEADERS_INSTALL=y
+CONFIG_HFSPLUS_FS=m
+CONFIG_HFS_FS=m
+CONFIG_HMC425=m
+CONFIG_HMM_MIRROR=y
+CONFIG_HOTPLUG_CPU=y
 CONFIG_HOTPLUG_PCI=y
 # CONFIG_HOTPLUG_PCI_CPCI is not set
 CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_HOTPLUG_PCI_SHPC=y
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HTS221=m
+CONFIG_HTS221_I2C=m
+CONFIG_HTS221_SPI=m
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
 CONFIG_HVC_DRIVER=y
 CONFIG_HVC_RISCV_SBI=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_HZ_PERIODIC=y
+CONFIG_HWMON=m
+CONFIG_HWMON_VID=m
+CONFIG_HWSPINLOCK=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_STARFIVE_VIC=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_HW_RANDOM_XIPHERA=m
 CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ALGOPCA=m
 CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PCI=m
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_OCORES=y
+CONFIG_I2C_DESIGNWARE_SLAVE=y
+# CONFIG_I2C_FSI is not set
+CONFIG_I2C_MUX=m
+CONFIG_I2C_MUX_GPMUX=m
+CONFIG_I2C_MUX_LTC4306=m
+CONFIG_I2C_MUX_MLXCPLD=m
+CONFIG_I2C_NFORCE2=m
+CONFIG_I2C_NVIDIA_GPU=m
+CONFIG_I2C_PCA_PLATFORM=m
+CONFIG_I2C_SIMTEC=m
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=m
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_I2C_STUB=m
+CONFIG_I40E=m
+CONFIG_I40EVF=m
+# CONFIG_I40E_DCB is not set
+CONFIG_I6300ESB_WDT=m
+CONFIG_IAVF=m
+CONFIG_ICE=m
+CONFIG_ICP10100=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_IEEE802154=m
+CONFIG_IEEE802154_ADF7242=m
+CONFIG_IEEE802154_AT86RF230=m
+# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
+CONFIG_IEEE802154_CA8210=m
+# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
+CONFIG_IEEE802154_CC2520=m
+CONFIG_IEEE802154_DRIVERS=m
+CONFIG_IEEE802154_FAKELB=m
+CONFIG_IEEE802154_MCR20A=m
+CONFIG_IEEE802154_MRF24J40=m
+# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
+CONFIG_IEEE802154_SOCKET=m
+CONFIG_IFB=m
+CONFIG_IFCVF=m
+CONFIG_IGB=m
+CONFIG_IGBVF=m
+CONFIG_IGB_HWMON=y
+CONFIG_IGC=m
+CONFIG_IIO=m
+CONFIG_IIO_ADIS_LIB=m
+CONFIG_IIO_ADIS_LIB_BUFFER=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_BUFFER_CB=m
+CONFIG_IIO_BUFFER_DMA=m
+CONFIG_IIO_BUFFER_DMAENGINE=m
+CONFIG_IIO_BUFFER_HW_CONSUMER=m
+CONFIG_IIO_CONFIGFS=m
+# CONFIG_IIO_HRTIMER_TRIGGER is not set
+CONFIG_IIO_INTERRUPT_TRIGGER=m
+CONFIG_IIO_KFIFO_BUF=m
+CONFIG_IIO_MUX=m
+CONFIG_IIO_RESCALE=m
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
+CONFIG_IIO_ST_GYRO_3AXIS=m
+CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
+CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
+CONFIG_IIO_ST_LSM6DSX=m
+CONFIG_IIO_ST_LSM6DSX_I2C=m
+CONFIG_IIO_ST_LSM6DSX_SPI=m
+CONFIG_IIO_ST_MAGN_3AXIS=m
+CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
+CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
+CONFIG_IIO_ST_SENSORS_CORE=m
+CONFIG_IIO_ST_SENSORS_I2C=m
+CONFIG_IIO_ST_SENSORS_SPI=m
+CONFIG_IIO_SW_DEVICE=m
+CONFIG_IIO_SW_TRIGGER=m
+CONFIG_IIO_TIGHTLOOP_TRIGGER=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=m
+CONFIG_IIO_TRIGGERED_EVENT=m
+CONFIG_IKCONFIG=m
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKHEADERS=m
+# CONFIG_IMG_ASCII_LCD is not set
+CONFIG_INET_AH=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_INET_ESP=m
+CONFIG_INET_ESPINTCP=y
+CONFIG_INET_ESP_OFFLOAD=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_MPTCP_DIAG=m
+CONFIG_INET_RAW_DIAG=m
+CONFIG_INET_SCTP_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_UDP_DIAG=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_ADDR_TRANS=y
+CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
+# CONFIG_INFINIBAND_BNXT_RE is not set
+CONFIG_INFINIBAND_CXGB4=m
+CONFIG_INFINIBAND_EFA=m
+CONFIG_INFINIBAND_IPOIB=m
+CONFIG_INFINIBAND_IPOIB_CM=y
+CONFIG_INFINIBAND_IPOIB_DEBUG=y
+CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y
+# CONFIG_INFINIBAND_IRDMA is not set
+CONFIG_INFINIBAND_ISER=m
+CONFIG_INFINIBAND_ISERT=m
+CONFIG_INFINIBAND_MTHCA=m
+CONFIG_INFINIBAND_MTHCA_DEBUG=y
+CONFIG_INFINIBAND_OCRDMA=m
+CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
+CONFIG_INFINIBAND_QEDR=m
+CONFIG_INFINIBAND_RTRS=m
+CONFIG_INFINIBAND_RTRS_CLIENT=m
+CONFIG_INFINIBAND_RTRS_SERVER=m
+CONFIG_INFINIBAND_SRP=m
+CONFIG_INFINIBAND_SRPT=m
+CONFIG_INFINIBAND_USER_ACCESS=m
+CONFIG_INFINIBAND_USER_MAD=m
+CONFIG_INFINIBAND_USER_MEM=y
+CONFIG_INFINIBAND_VIRT_DMA=y
 CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_INPUT_DA9063_ONKEY is not set
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IO_URING=y
+CONFIG_INTEL_XWAY_PHY=m
+CONFIG_INTERCONNECT=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_INV_ICM42600=m
+CONFIG_INV_ICM42600_I2C=m
+CONFIG_INV_ICM42600_SPI=m
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_IOVA=m
+CONFIG_IONIC=m
+CONFIG_IOSCHED_BFQ=y
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_HANDLER=m
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_PLAT_DATA=y
+CONFIG_IPMI_POWEROFF=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_SSIF=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPVLAN=m
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVTAP=m
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_COMMON=y
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_SCTP=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPMAC=m
+CONFIG_IP_SET_HASH_IPMARK=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_MAC=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_HASH_NETNET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETPORTNET=m
+CONFIG_IP_SET_LIST_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_FO=m
+CONFIG_IP_VS_FTP=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_MH=m
+CONFIG_IP_VS_NFCT=y
+CONFIG_IP_VS_NQ=m
+CONFIG_IP_VS_OVF=m
+CONFIG_IP_VS_PE_SIP=m
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_SCTP=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SH_TAB_BITS=8
+CONFIG_IP_VS_TAB_BITS=12
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_WRR=m
 CONFIG_IRQCHIP=y
+CONFIG_IRQ_BYPASS_MANAGER=m
 CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_DOMAIN_HIERARCHY=y
 CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_POLL=y
 CONFIG_IRQ_WORK=y
+CONFIG_ISCSI_BOOT_SYSFS=m
+CONFIG_ISCSI_TARGET=m
+CONFIG_ISCSI_TARGET_CXGB4=m
+CONFIG_ISCSI_TCP=m
+CONFIG_ISDN_CAPI=y
+CONFIG_ISL29003=m
+CONFIG_ISL29020=m
+CONFIG_ISO9660_FS=m
+CONFIG_IXGB=m
+CONFIG_IXGBE=m
+CONFIG_IXGBEVF=m
+CONFIG_IXGBEVF_IPSEC=y
+CONFIG_IXGBE_DCB=y
+CONFIG_IXGBE_HWMON=y
+CONFIG_IXGBE_IPSEC=y
 CONFIG_JBD2=y
+CONFIG_JFFS2_FS=m
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+CONFIG_JFS_SECURITY=y
+CONFIG_JME=m
+CONFIG_JUMP_LABEL=y
 CONFIG_KALLSYMS=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_KCMP=y
 CONFIG_KEYS=y
-CONFIG_LEDS_PWM=y
+CONFIG_KEYS_REQUEST_CACHE=y
+CONFIG_KEY_DH_OPERATIONS=y
+CONFIG_KEY_NOTIFICATIONS=y
+CONFIG_KGDB=y
+CONFIG_KGDB_HONOUR_BLOCKLIST=y
+# CONFIG_KGDB_KDB is not set
+CONFIG_KGDB_TESTS=y
+# CONFIG_KGDB_TESTS_ON_BOOT is not set
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_KSM=y
+CONFIG_KSZ884X_PCI=m
+CONFIG_KXCJK1013=m
+CONFIG_L2TP=m
+CONFIG_L2TP_DEBUGFS=m
+CONFIG_L2TP_ETH=m
+CONFIG_L2TP_IP=m
+CONFIG_L2TP_V3=y
+# CONFIG_LCD2S is not set
+CONFIG_LCD_CLASS_DEVICE=m
+CONFIG_LCD_PLATFORM=m
+# CONFIG_LDM_DEBUG is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LEDS_AAT1290 is not set
+CONFIG_LEDS_AN30259A=m
+CONFIG_LEDS_AS3645A=m
+CONFIG_LEDS_BLINKM=m
+CONFIG_LEDS_CLASS_FLASH=m
+CONFIG_LEDS_CLASS_MULTICOLOR=m
+CONFIG_LEDS_CR0014114=m
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_IS31FL32XX=m
+# CONFIG_LEDS_KTD2692 is not set
+CONFIG_LEDS_LM3530=m
+CONFIG_LEDS_LM3532=m
+CONFIG_LEDS_LM3601X=m
+CONFIG_LEDS_LM3692X=m
+CONFIG_LEDS_LP3944=m
+CONFIG_LEDS_LP3952=m
+CONFIG_LEDS_LP50XX=m
+CONFIG_LEDS_LT3593=m
+CONFIG_LEDS_MAX77650=m
+CONFIG_LEDS_MLXREG=m
+CONFIG_LEDS_PWM=m
+CONFIG_LEDS_REGULATOR=m
+# CONFIG_LEDS_RT4505 is not set
+# CONFIG_LEDS_RT8515 is not set
+# CONFIG_LEDS_SGM3140 is not set
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=m
+CONFIG_LEDS_TRIGGER_AUDIO=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CAMERA=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
 CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_NETDEV=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_TRANSIENT=m
+CONFIG_LEDS_USER=m
+CONFIG_LED_TRIGGER_PHY=y
+CONFIG_LIB80211=m
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFC=m
+CONFIG_LIBFCOE=m
 CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LLC=m
+CONFIG_LMP91000=m
+CONFIG_LOCKD=m
+CONFIG_LOCKUP_DETECTOR=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set
+# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set
+CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MACB=y
-# CONFIG_MACB_PCI is not set
-CONFIG_MACB_USE_HWSTAMP=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_LRU_CACHE=m
+CONFIG_LSI_ET1011C_PHY=m
+CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
+CONFIG_LTC1660=m
+CONFIG_LTC2983=m
+CONFIG_LTR501=m
+CONFIG_LV0104CS=m
+CONFIG_LXT_PHY=m
+CONFIG_LZ4HC_COMPRESS=m
+CONFIG_LZ4_COMPRESS=m
+CONFIG_LZ4_DECOMPRESS=m
+CONFIG_LZMA_COMPRESS=m
+CONFIG_LZMA_DECOMPRESS=m
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAC80211=m
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_HWSIM=m
+# CONFIG_MAC80211_LEDS is not set
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC802154=m
+CONFIG_MACB=m
+CONFIG_MACB_PCI=m
+CONFIG_MACSEC=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_MAC_PARTITION=y
+CONFIG_MARVELL_10G_PHY=m
+CONFIG_MARVELL_PHY=y
+CONFIG_MAX1241=m
+CONFIG_MAX1363=m
+CONFIG_MAX30100=m
+CONFIG_MAX31856=m
+CONFIG_MAX44009=m
+CONFIG_MAXIM_THERMOCOUPLE=m
+CONFIG_MB1232=m
+CONFIG_MCP3911=m
+CONFIG_MCP4018=m
+CONFIG_MCP41010=m
+CONFIG_MD=y
+CONFIG_MDIO=m
+CONFIG_MDIO_BCM_UNIMAC=m
+CONFIG_MDIO_BITBANG=m
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MDIO_I2C=m
+CONFIG_MD_AUTODETECT=y
+# CONFIG_MD_CLUSTER is not set
+CONFIG_MD_FAULTY=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MEDIATEK_GE_PHY=m
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_COMMON_OPTIONS=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PCI_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEGARAID_LEGACY=m
+CONFIG_MEGARAID_MAILBOX=m
+CONFIG_MEGARAID_MM=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_SAS=m
+CONFIG_MEMCG=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_MEMCG_SWAP=y
 CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MEMSTICK=m
+# CONFIG_MEMSTICK_DEBUG is not set
+CONFIG_MEMSTICK_JMICRON_38X=m
+CONFIG_MEMSTICK_R592=m
+CONFIG_MEMSTICK_REALTEK_PCI=m
+CONFIG_MEMSTICK_TIFM_MS=m
+# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
+CONFIG_MFD_BD9571MWV=m
 CONFIG_MFD_CORE=y
-CONFIG_MFD_DA9063=y
+CONFIG_MFD_INTEL_M10_BMC=m
+CONFIG_MFD_MAX77650=m
+CONFIG_MFD_SM501=m
+CONFIG_MFD_SM501_GPIO=y
 CONFIG_MFD_SYSCON=y
-CONFIG_MICROSEMI_PHY=y
+CONFIG_MFD_TPS65086=y
+CONFIG_MFD_VX855=m
+CONFIG_MICREL_PHY=m
+CONFIG_MICROSEMI_PHY=m
 CONFIG_MIGRATION=y
+CONFIG_MINIX_FS=m
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_MISC_ALCOR_PCI=m
+CONFIG_MISC_RTSX=m
+CONFIG_MISC_RTSX_PCI=m
+CONFIG_MKISS=m
+CONFIG_MLX4_CORE=m
+CONFIG_MLX4_CORE_GEN2=y
+CONFIG_MLX4_DEBUG=y
+CONFIG_MLX4_EN=m
+CONFIG_MLX4_EN_DCB=y
+CONFIG_MLX4_INFINIBAND=m
+CONFIG_MLX5_ACCEL=y
+CONFIG_MLX5_BRIDGE=y
+CONFIG_MLX5_CLS_ACT=y
+CONFIG_MLX5_CORE=m
+CONFIG_MLX5_CORE_EN=y
+CONFIG_MLX5_CORE_EN_DCB=y
+CONFIG_MLX5_CORE_IPOIB=y
+CONFIG_MLX5_EN_ARFS=y
+CONFIG_MLX5_EN_IPSEC=y
+CONFIG_MLX5_EN_RXNFC=y
+CONFIG_MLX5_ESWITCH=y
+# CONFIG_MLX5_FPGA is not set
+CONFIG_MLX5_INFINIBAND=m
+CONFIG_MLX5_IPSEC=y
+CONFIG_MLX5_MPFS=y
+CONFIG_MLX5_SW_STEERING=y
+CONFIG_MLX5_TC_SAMPLE=y
+# CONFIG_MLX5_TLS is not set
+CONFIG_MLX5_VDPA=y
+CONFIG_MLX5_VDPA_NET=m
+CONFIG_MLX90614=m
+CONFIG_MLX90632=m
+CONFIG_MLXFW=m
+CONFIG_MLXSW_CORE=m
+CONFIG_MLXSW_CORE_HWMON=y
+CONFIG_MLXSW_I2C=m
+CONFIG_MLXSW_MINIMAL=m
+CONFIG_MLXSW_PCI=m
+CONFIG_MLXSW_SPECTRUM=m
+CONFIG_MLXSW_SPECTRUM_DCB=y
+CONFIG_MMA7660=m
 CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
+CONFIG_MMC_ALCOR=m
+CONFIG_MMC_CB710=m
+CONFIG_MMC_CQHCI=y
+# CONFIG_MMC_CRYPTO is not set
+CONFIG_MMC_DW=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+CONFIG_MMC_DW_PCI=y
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_HSQ=y
+CONFIG_MMC_REALTEK_PCI=m
+CONFIG_MMC_RICOH_MMC=y
 CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_CADENCE=y
-# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_CADENCE=m
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_MMC_SDHCI_PCI=m
 CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_XENON=m
 CONFIG_MMC_SPI=y
+CONFIG_MMC_TIFM_SD=m
+CONFIG_MMC_VIA_SDMMC=m
 CONFIG_MMIOWB=y
+CONFIG_MMU_NOTIFIER=y
 CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MODULE_COMPRESS_NONE is not set
+CONFIG_MODULE_COMPRESS_XZ=y
 CONFIG_MODULE_SECTIONS=y
+CONFIG_MODULE_SIG=y
+CONFIG_MODULE_SIG_ALL=y
+# CONFIG_MODULE_SIG_FORCE is not set
+CONFIG_MODULE_SIG_FORMAT=y
+CONFIG_MODULE_SIG_HASH="sha512"
+CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
+# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set
+CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
+# CONFIG_MODULE_SIG_SHA1 is not set
+# CONFIG_MODULE_SIG_SHA224 is not set
+# CONFIG_MODULE_SIG_SHA256 is not set
+# CONFIG_MODULE_SIG_SHA384 is not set
+CONFIG_MODULE_SIG_SHA512=y
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
 CONFIG_MPILIB=y
+CONFIG_MPL115=m
+CONFIG_MPL115_I2C=m
+CONFIG_MPLS=y
+CONFIG_MPLS_ROUTING=m
+CONFIG_MPTCP=y
+CONFIG_MPU3050=m
+CONFIG_MPU3050_I2C=m
 CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MSDOS_FS=m
+CONFIG_MSPRO_BLOCK=m
+# CONFIG_MS_BLOCK is not set
+CONFIG_MTD=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK2MTD=m
+# CONFIG_MTD_BLOCK_RO is not set
+CONFIG_MTD_CFI=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_GEN_PROBE=m
+CONFIG_MTD_NAND_CADENCE=m
+CONFIG_MTD_NAND_CORE=m
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_OF_PARTS=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_RAW_NAND=m
+CONFIG_MTD_SPI_NOR=m
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTIPLEXER=m
 CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MUX_ADG792A=m
+CONFIG_MUX_GPIO=m
+CONFIG_MUX_MMIO=m
+CONFIG_MVMDIO=m
+CONFIG_MXC4005=m
+CONFIG_MXC6255=m
+CONFIG_MYRI10GE=m
 CONFIG_NAMESPACES=y
+CONFIG_NATIONAL_PHY=m
+CONFIG_NATSEMI=m
+CONFIG_NCSI_OEM_CMD_GET_MAC=y
+# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set
+CONFIG_NE2K_PCI=m
 CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FAILOVER=y
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETDEVSIM=m
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_FAMILY_ARP=y
+CONFIG_NETFILTER_FAMILY_BRIDGE=y
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_NAT=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFS_STATS=y
+CONFIG_NETFS_SUPPORT=m
+CONFIG_NETLABEL=y
+CONFIG_NETLINK_DIAG=m
+CONFIG_NETPOLL=y
+CONFIG_NETROM=m
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETXEN_NIC=m
+CONFIG_NET_9P=m
+# CONFIG_NET_9P_DEBUG is not set
+CONFIG_NET_9P_RDMA=m
+CONFIG_NET_9P_VIRTIO=m
+CONFIG_NET_ACT_BPF=m
+CONFIG_NET_ACT_CSUM=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_NET_ACT_GATE=m
+CONFIG_NET_ACT_IFE=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_MPLS=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_SAMPLE=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_ACT_SKBMOD=m
+CONFIG_NET_ACT_TUNNEL_KEY=m
+CONFIG_NET_ACT_VLAN=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_BPF=m
+CONFIG_NET_CLS_CGROUP=y
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_FLOWER=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_MATCHALL=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_U32=m
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=m
+CONFIG_NET_DSA_BCM_SF2=m
+CONFIG_NET_DSA_LOOP=m
+CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
+# CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C is not set
+CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
+CONFIG_NET_DSA_MT7530=m
+CONFIG_NET_DSA_MV88E6XXX=m
+CONFIG_NET_DSA_QCA8K=m
+CONFIG_NET_DSA_SMSC_LAN9303=m
+CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
+CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
+CONFIG_NET_DSA_TAG_BRCM=m
+CONFIG_NET_DSA_TAG_BRCM_COMMON=m
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
+CONFIG_NET_DSA_TAG_DSA=m
+CONFIG_NET_DSA_TAG_DSA_COMMON=m
+CONFIG_NET_DSA_TAG_EDSA=m
+CONFIG_NET_DSA_TAG_GSWIP=m
+CONFIG_NET_DSA_TAG_KSZ=m
+CONFIG_NET_DSA_TAG_LAN9303=m
+CONFIG_NET_DSA_TAG_MTK=m
+CONFIG_NET_DSA_TAG_QCA=m
+CONFIG_NET_DSA_TAG_RTL4_A=m
+CONFIG_NET_DSA_TAG_SJA1105=m
+CONFIG_NET_DSA_TAG_TRAILER=m
+CONFIG_NET_EGRESS=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CANID=m
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_IPSET=m
+CONFIG_NET_EMATCH_IPT=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_FAILOVER=m
+CONFIG_NET_FC=y
 CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_FOU=m
+CONFIG_NET_FOU_IP_TUNNELS=y
+CONFIG_NET_IFE=m
+CONFIG_NET_IFE_SKBMARK=m
+CONFIG_NET_IFE_SKBPRIO=m
+CONFIG_NET_IFE_SKBTCINDEX=m
+CONFIG_NET_INGRESS=y
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPVTI=m
+CONFIG_NET_IP_TUNNEL=m
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_NET_L3_MASTER_DEV=y
+CONFIG_NET_MPLS_GSO=m
+CONFIG_NET_NCSI=y
 CONFIG_NET_NS=y
+CONFIG_NET_NSH=m
+CONFIG_NET_PKTGEN=m
+CONFIG_NET_POLL_CONTROLLER=y
 CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_REDIRECT=y
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_CAKE=m
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_CBS=m
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_ETF=m
+CONFIG_NET_SCH_ETS=m
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_PIE=m
+CONFIG_NET_SCH_PLUG=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TAPRIO=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_TEQL=m
 CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NR_CPUS=8
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_TC_SKB_EXT=y
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TULIP=y
+CONFIG_NET_UDP_TUNNEL=m
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_I825XX is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+CONFIG_NET_VRF=m
+CONFIG_NFC=m
+CONFIG_NFC_DIGITAL=m
+# CONFIG_NFC_FDP is not set
+CONFIG_NFC_HCI=m
+CONFIG_NFC_MICROREAD=m
+CONFIG_NFC_MICROREAD_I2C=m
+CONFIG_NFC_NCI=m
+CONFIG_NFC_NCI_SPI=m
+# CONFIG_NFC_NCI_UART is not set
+CONFIG_NFC_NXP_NCI=m
+CONFIG_NFC_NXP_NCI_I2C=m
+# CONFIG_NFC_PN532_UART is not set
+CONFIG_NFC_PN533=m
+CONFIG_NFC_PN533_I2C=m
+CONFIG_NFC_PN544=m
+CONFIG_NFC_PN544_I2C=m
+# CONFIG_NFC_S3FWRN5_I2C is not set
+# CONFIG_NFC_S3FWRN82_UART is not set
+CONFIG_NFC_SHDLC=y
+CONFIG_NFC_SIM=m
+CONFIG_NFC_ST21NFCA=m
+CONFIG_NFC_ST21NFCA_I2C=m
+# CONFIG_NFC_ST95HF is not set
+# CONFIG_NFC_ST_NCI_I2C is not set
+# CONFIG_NFC_ST_NCI_SPI is not set
+CONFIG_NFC_TRF7970A=m
+# CONFIG_NFC_VIRTUAL_NCI is not set
+CONFIG_NFP=m
+# CONFIG_NFP_APP_ABM_NIC is not set
+CONFIG_NFP_APP_FLOWER=y
+# CONFIG_NFP_DEBUG is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_BLOCKLAYOUT=y
+CONFIG_NFSD_FLEXFILELAYOUT=y
+CONFIG_NFSD_PNFS=y
+CONFIG_NFSD_SCSILAYOUT=y
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_V4_2_INTER_SSC=y
+CONFIG_NFSD_V4_SECURITY_LABEL=y
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_DEBUG=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_FSCACHE=y
+CONFIG_NFS_SWAP=y
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_V3=m
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=m
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+# CONFIG_NFS_V4_1_MIGRATION is not set
+CONFIG_NFS_V4_2=y
+# CONFIG_NFS_V4_2_READ_PLUS is not set
+CONFIG_NFS_V4_2_SSC_HELPER=y
+CONFIG_NFS_V4_SECURITY_LABEL=y
+CONFIG_NFT_BRIDGE_META=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NFT_COUNTER=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_DUP_IPV4=m
+CONFIG_NFT_DUP_NETDEV=m
+CONFIG_NFT_FIB=m
+CONFIG_NFT_FIB_IPV4=m
+CONFIG_NFT_FWD_NETDEV=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_NUMGEN=m
+CONFIG_NFT_OBJREF=m
+CONFIG_NFT_QUOTA=m
+CONFIG_NFT_REDIR=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_REJECT_IPV4=m
+CONFIG_NFT_SOCKET=m
+CONFIG_NFT_TPROXY=m
+CONFIG_NFT_TUNNEL=m
+CONFIG_NFT_XFRM=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_BRIDGE=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_DUP_IPV4=m
+CONFIG_NF_DUP_NETDEV=m
+CONFIG_NF_LOG_ARP=m
+CONFIG_NF_LOG_IPV4=m
+CONFIG_NF_LOG_SYSLOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_MASQUERADE=y
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_SIP=m
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_NF_SOCKET_IPV4=m
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_BRIDGE=m
+CONFIG_NF_TPROXY_IPV4=m
+CONFIG_NILFS2_FS=m
+CONFIG_NIU=m
+# CONFIG_NL80211_TESTMODE is not set
+CONFIG_NLMON=m
+CONFIG_NLS=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
+CONFIG_NLS_UTF8=m
+CONFIG_NOUVEAU_DEBUG=5
+CONFIG_NOUVEAU_DEBUG_DEFAULT=3
+# CONFIG_NOUVEAU_DEBUG_MMU is not set
+# CONFIG_NOUVEAU_DEBUG_PUSH is not set
+CONFIG_NOZOMI=m
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_FULL=y
+CONFIG_NR_CPUS=32
+CONFIG_NS83820=m
+CONFIG_NULL_TTY=m
+CONFIG_NVDLA=m
 CONFIG_NVMEM=y
 CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=m
+CONFIG_NVME_FABRICS=m
+CONFIG_NVME_FC=m
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_NVME_RDMA=m
+CONFIG_NVME_TARGET=m
+CONFIG_NVME_TARGET_FC=m
+CONFIG_NVME_TARGET_FCLOOP=m
+CONFIG_NVME_TARGET_LOOP=m
+CONFIG_NVME_TARGET_PASSTHRU=y
+CONFIG_NVME_TARGET_RDMA=m
+CONFIG_NVME_TARGET_TCP=m
+CONFIG_NVME_TCP=m
+CONFIG_N_GSM=m
+CONFIG_N_HDLC=m
+CONFIG_OBJAGG=m
+# CONFIG_OCFS2_DEBUG_FS is not set
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_OCFS2_FS=m
+CONFIG_OCFS2_FS_O2CB=m
+# CONFIG_OCFS2_FS_STATS is not set
+CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
 CONFIG_OF_EARLY_FLATTREE=y
 CONFIG_OF_FLATTREE=y
+CONFIG_OF_FPGA_REGION=m
 CONFIG_OF_GPIO=y
 CONFIG_OF_IRQ=y
 CONFIG_OF_KOBJ=y
 CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
 CONFIG_OID_REGISTRY=y
+CONFIG_OPENVSWITCH=m
+CONFIG_OPENVSWITCH_GENEVE=m
+CONFIG_OPENVSWITCH_GRE=m
+CONFIG_OPENVSWITCH_VXLAN=m
+CONFIG_OPT3001=m
+CONFIG_ORANGEFS_FS=m
+CONFIG_OSF_PARTITION=y
+CONFIG_OVERLAY_FS=m
+CONFIG_PA12203001=m
+CONFIG_PACKET_DIAG=m
+CONFIG_PACKING=y
 CONFIG_PADATA=y
+CONFIG_PAGE_COUNTER=y
 CONFIG_PAGE_OFFSET=0xffffffe000000000
+CONFIG_PAGE_POOL=y
 CONFIG_PAGE_REPORTING=y
-CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PANEL_CHANGE_MESSAGE is not set
+CONFIG_PARMAN=m
+CONFIG_PATA_ALI=m
+CONFIG_PATA_AMD=m
+CONFIG_PATA_ARTOP=m
+CONFIG_PATA_ATP867X=m
+CONFIG_PATA_CMD640_PCI=m
+CONFIG_PATA_CMD64X=m
+CONFIG_PATA_EFAR=m
+CONFIG_PATA_HPT366=m
+CONFIG_PATA_HPT37X=m
+CONFIG_PATA_HPT3X2N=m
+CONFIG_PATA_HPT3X3=m
+# CONFIG_PATA_HPT3X3_DMA is not set
+CONFIG_PATA_IT8213=m
+CONFIG_PATA_IT821X=m
+CONFIG_PATA_JMICRON=m
+CONFIG_PATA_MARVELL=m
+CONFIG_PATA_NETCELL=m
+CONFIG_PATA_NINJA32=m
+CONFIG_PATA_NS87410=m
+CONFIG_PATA_NS87415=m
+CONFIG_PATA_OPTI=m
+CONFIG_PATA_OPTIDMA=m
+CONFIG_PATA_PDC2027X=m
+CONFIG_PATA_PDC_OLD=m
+CONFIG_PATA_SERVERWORKS=m
+CONFIG_PATA_SIL680=m
+CONFIG_PATA_SIS=m
+CONFIG_PATA_TIMINGS=y
+CONFIG_PATA_VIA=m
+CONFIG_PATA_WINBOND=m
 CONFIG_PA_BITS=56
+CONFIG_PCCARD=y
 CONFIG_PCI=y
 CONFIG_PCIEAER=y
 CONFIG_PCIEAER_INJECT=m
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
 CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_CADENCE=y
+CONFIG_PCIE_CADENCE_HOST=y
 CONFIG_PCIE_DPC=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
 CONFIG_PCIE_ECRC=y
-CONFIG_PCIE_FU740=y
+# CONFIG_PCIE_FU740 is not set
 CONFIG_PCIE_PTM=y
 CONFIG_PCIE_XILINX=y
-CONFIG_PCI_DEBUG=y
+CONFIG_PCIPCWATCHDOG=m
+CONFIG_PCI_ATS=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_DOMAINS_GENERIC=y
 CONFIG_PCI_ECAM=y
 CONFIG_PCI_HOST_COMMON=y
 CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_J721E=y
+CONFIG_PCI_J721E_HOST=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_SW_SWITCHTEC=y
+CONFIG_PCI_PASID=y
+CONFIG_PCI_PF_STUB=m
+CONFIG_PCI_PRI=y
+CONFIG_PCI_STUB=y
+CONFIG_PCI_SW_SWITCHTEC=m
+CONFIG_PCMCIA_XIRCOM=m
+CONFIG_PCNET32=m
+CONFIG_PCS_XPCS=y
+CONFIG_PDC_ADMA=m
+CONFIG_PERSISTENT_KEYRINGS=y
 CONFIG_PGTABLE_LEVELS=3
 CONFIG_PHYLIB=y
 CONFIG_PHYLINK=y
 CONFIG_PHYS_ADDR_T_64BIT=y
 # CONFIG_PHYS_RAM_BASE_FIXED is not set
-CONFIG_PID_NS=y
+CONFIG_PHY_CADENCE_SALVO=m
+CONFIG_PHY_CADENCE_SIERRA=m
+CONFIG_PHY_CADENCE_TORRENT=m
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_STARFIVE=y
 CONFIG_PKCS7_MESSAGE_PARSER=y
-# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+# CONFIG_PKCS7_TEST_KEY is not set
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_PLDMFW=y
+CONFIG_PMBUS=m
+CONFIG_PMS7003=m
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_OPP=y
+CONFIG_PNFS_BLOCK=m
+CONFIG_PNFS_FILE_LAYOUT=m
+CONFIG_PNFS_FLEXFILE_LAYOUT=m
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWERCAP=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_POWER_RESET_GPIO_RESTART=y
 CONFIG_POWER_RESET_RESTART=y
 CONFIG_POWER_RESET_SYSCON=y
 CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_PPS=y
+CONFIG_POWER_RESET_TPS65086=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12
 CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PROFILING=y
+CONFIG_PSAMPLE=m
+CONFIG_PSI=y
+# CONFIG_PSI_DEFAULT_DISABLED is not set
+CONFIG_PSTORE=y
+CONFIG_PSTORE_842_COMPRESS=y
+# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
+CONFIG_PSTORE_COMPRESS=y
+CONFIG_PSTORE_COMPRESS_DEFAULT="lzo"
+CONFIG_PSTORE_LZ4HC_COMPRESS=m
+# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
+CONFIG_PSTORE_LZ4_COMPRESS=m
+# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
+CONFIG_PSTORE_LZO_COMPRESS=m
+CONFIG_PSTORE_LZO_COMPRESS_DEFAULT=y
+CONFIG_PSTORE_RAM=m
+CONFIG_PTDUMP_CORE=y
 CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PVPANIC=y
+# CONFIG_PVPANIC_MMIO is not set
+# CONFIG_PVPANIC_PCI is not set
 CONFIG_PWM=y
 CONFIG_PWM_SIFIVE=y
+CONFIG_PWM_SIFIVE_PTC=y
 CONFIG_PWM_SYSFS=y
-CONFIG_R8169=y
+CONFIG_PWRSEQ_SD8787=m
+CONFIG_PWRSEQ_SIMPLE=m
+CONFIG_QED=m
+CONFIG_QEDE=m
+CONFIG_QEDF=m
+CONFIG_QEDI=m
+CONFIG_QED_FCOE=y
+CONFIG_QED_ISCSI=y
+CONFIG_QED_LL2=y
+CONFIG_QED_OOO=y
+CONFIG_QED_RDMA=y
+CONFIG_QED_SRIOV=y
+CONFIG_QFMT_V2=y
+CONFIG_QLA3XXX=m
+CONFIG_QLCNIC=m
+CONFIG_QLCNIC_DCB=y
+CONFIG_QLCNIC_HWMON=y
+CONFIG_QLCNIC_SRIOV=y
+CONFIG_QLGE=m
+CONFIG_QSEMI_PHY=m
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QUOTA_TREE=y
+CONFIG_R6040=m
+CONFIG_R8169=m
+CONFIG_RAID6_PQ=y
+CONFIG_RAID_ATTRS=m
+CONFIG_RAPIDIO=m
+CONFIG_RAPIDIO_CHMAN=m
+CONFIG_RAPIDIO_CPS_GEN2=m
+CONFIG_RAPIDIO_CPS_XX=m
+# CONFIG_RAPIDIO_DEBUG is not set
+CONFIG_RAPIDIO_DISC_TIMEOUT=30
+CONFIG_RAPIDIO_DMA_ENGINE=y
+# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set
+CONFIG_RAPIDIO_ENUM_BASIC=m
+CONFIG_RAPIDIO_MPORT_CDEV=m
+CONFIG_RAPIDIO_RXS_GEN3=m
+CONFIG_RAPIDIO_TSI568=m
+CONFIG_RAPIDIO_TSI57X=m
+CONFIG_RAPIDIO_TSI721=m
 CONFIG_RAS=y
 CONFIG_RATIONAL=y
-CONFIG_RCU_TRACE=y
-CONFIG_RD_GZIP=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_NOCB_CPU=y
+CONFIG_RCU_TORTURE_TEST=m
+CONFIG_RDMA_RXE=m
+CONFIG_RDMA_SIW=m
+CONFIG_RDS=m
+# CONFIG_RDS_DEBUG is not set
+CONFIG_RDS_RDMA=m
+CONFIG_RDS_TCP=m
 CONFIG_REALTEK_PHY=y
+CONFIG_REBOOT_MODE=y
+CONFIG_REED_SOLOMON=m
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_I2C=y
 CONFIG_REGMAP_IRQ=y
 CONFIG_REGMAP_MMIO=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_REGMAP_SOUNDWIRE=m
+CONFIG_REGMAP_SPI=m
+CONFIG_REGMAP_SPI_AVMM=m
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_BD9571MWV=m
+CONFIG_REGULATOR_FIXED_VOLTAGE=m
+CONFIG_REGULATOR_MAX77650=m
+CONFIG_REGULATOR_MP5416=m
+CONFIG_REGULATOR_MP886X=m
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RT4801=m
+CONFIG_REGULATOR_RTMV20=m
+# CONFIG_REGULATOR_TPS65086 is not set
+CONFIG_REGULATOR_VCTRL=m
+CONFIG_REISERFS_FS=m
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REMOTEPROC=y
+# CONFIG_REMOTEPROC_CDEV is not set
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RESET_SIMPLE=y
 CONFIG_RESET_STARFIVE_JH7100=y
+CONFIG_RESET_STARFIVE_JH7100_AUDIO=y
 CONFIG_RFS_ACCEL=y
+CONFIG_RIONET=m
+CONFIG_RIONET_RX_SIZE=128
+CONFIG_RIONET_TX_SIZE=128
 CONFIG_RISCV=y
+CONFIG_RISCV_DMA_NONCOHERENT=y
 CONFIG_RISCV_ERRATA_ALTERNATIVE=y
 CONFIG_RISCV_INTC=y
 CONFIG_RISCV_ISA_C=y
 CONFIG_RISCV_SBI=y
 CONFIG_RISCV_SBI_V01=y
 CONFIG_RISCV_TIMER=y
+CONFIG_RISCV_UNCACHED_OFFSET=0xF80000000
+CONFIG_ROCKER=m
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+CONFIG_ROMFS_FS=m
+CONFIG_ROMFS_ON_BLOCK=y
+CONFIG_ROSE=m
+CONFIG_RPMSG=m
+CONFIG_RPMSG_CHAR=m
+CONFIG_RPMSG_NS=m
+CONFIG_RPMSG_VIRTIO=m
+CONFIG_RPR0521=m
 CONFIG_RPS=y
 CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DA9063=y
-# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_DRV_ABEOZ9=m
+CONFIG_RTC_DRV_ABX80X=m
+CONFIG_RTC_DRV_BQ32K=m
+CONFIG_RTC_DRV_BQ4802=m
+CONFIG_RTC_DRV_DS1286=m
+CONFIG_RTC_DRV_DS1305=m
+CONFIG_RTC_DRV_DS1307=m
+CONFIG_RTC_DRV_DS1343=m
+CONFIG_RTC_DRV_DS1347=m
+CONFIG_RTC_DRV_DS1374=m
+CONFIG_RTC_DRV_DS1374_WDT=y
+CONFIG_RTC_DRV_DS1390=m
+CONFIG_RTC_DRV_DS1511=m
+CONFIG_RTC_DRV_DS1553=m
+CONFIG_RTC_DRV_DS1672=m
+CONFIG_RTC_DRV_DS1685=y
+CONFIG_RTC_DRV_DS1685_FAMILY=m
+# CONFIG_RTC_DRV_DS1689 is not set
+# CONFIG_RTC_DRV_DS17285 is not set
+CONFIG_RTC_DRV_DS1742=m
+# CONFIG_RTC_DRV_DS17485 is not set
+# CONFIG_RTC_DRV_DS17885 is not set
+CONFIG_RTC_DRV_DS2404=m
+CONFIG_RTC_DRV_DS3232=m
+# CONFIG_RTC_DRV_DS3232_HWMON is not set
+CONFIG_RTC_DRV_EM3027=m
+CONFIG_RTC_DRV_FM3130=m
 CONFIG_RTC_DRV_GOLDFISH=y
+CONFIG_RTC_DRV_ISL12022=m
+CONFIG_RTC_DRV_ISL12026=m
+CONFIG_RTC_DRV_ISL1208=m
+CONFIG_RTC_DRV_M41T80=m
+CONFIG_RTC_DRV_M41T80_WDT=y
+CONFIG_RTC_DRV_M41T93=m
+CONFIG_RTC_DRV_M41T94=m
+CONFIG_RTC_DRV_M48T35=m
+CONFIG_RTC_DRV_M48T59=m
+CONFIG_RTC_DRV_MAX6900=m
+CONFIG_RTC_DRV_MAX6902=m
+CONFIG_RTC_DRV_MAX6916=m
+CONFIG_RTC_DRV_MCP795=m
+CONFIG_RTC_DRV_MSM6242=m
+CONFIG_RTC_DRV_PCF2123=m
+CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_PCF85063=m
+CONFIG_RTC_DRV_PCF8523=m
+CONFIG_RTC_DRV_PCF8563=m
+CONFIG_RTC_DRV_PCF8583=m
+CONFIG_RTC_DRV_R7301=m
+CONFIG_RTC_DRV_R9701=m
+CONFIG_RTC_DRV_RP5C01=m
+CONFIG_RTC_DRV_RS5C348=m
+CONFIG_RTC_DRV_RS5C372=m
+CONFIG_RTC_DRV_RV3028=m
+CONFIG_RTC_DRV_RV3029C2=m
+CONFIG_RTC_DRV_RV3029_HWMON=y
+CONFIG_RTC_DRV_RV3032=m
+CONFIG_RTC_DRV_RX4581=m
+CONFIG_RTC_DRV_RX8010=m
+CONFIG_RTC_DRV_RX8025=m
+CONFIG_RTC_DRV_RX8581=m
+CONFIG_RTC_DRV_SD3078=m
+CONFIG_RTC_DRV_STK17TA8=m
+CONFIG_RTC_DRV_V3020=m
+CONFIG_RTC_DRV_X1205=m
 CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RTC_SYSTOHC is not set
+CONFIG_RTL8192E=m
+CONFIG_RTL8723BS=m
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+# CONFIG_RT_GROUP_SCHED is not set
 CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_DEBUG=y
+CONFIG_S2IO=m
+CONFIG_SATA_ACARD_AHCI=m
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_SATA_HOST=y
+CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MOBILE_LPM_POLICY=3
+CONFIG_SATA_MV=m
+CONFIG_SATA_NV=m
+CONFIG_SATA_PROMISE=m
+CONFIG_SATA_QSTOR=m
+CONFIG_SATA_SIL=m
+CONFIG_SATA_SIL24=m
+CONFIG_SATA_SIS=m
+CONFIG_SATA_SVW=m
+CONFIG_SATA_SX4=m
+CONFIG_SATA_ULI=m
+CONFIG_SATA_VIA=m
+CONFIG_SATA_VITESSE=m
+CONFIG_SBP_TARGET=m
+CONFIG_SC92031=m
+CONFIG_SCD30_CORE=m
+CONFIG_SCD30_I2C=m
+CONFIG_SCD30_SERIAL=m
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_INFO=y
 CONFIG_SCSI=y
+CONFIG_SCSI_3W_9XXX=m
+CONFIG_SCSI_3W_SAS=m
+CONFIG_SCSI_AACRAID=m
+CONFIG_SCSI_ACARD=m
+CONFIG_SCSI_AIC79XX=m
+CONFIG_SCSI_AIC7XXX=m
+CONFIG_SCSI_AM53C974=m
+CONFIG_SCSI_ARCMSR=m
+CONFIG_SCSI_BFA_FC=m
+CONFIG_SCSI_BNX2X_FCOE=m
+CONFIG_SCSI_BNX2_ISCSI=m
+CONFIG_SCSI_CHELSIO_FCOE=m
 CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_CXGB3_ISCSI=m
+CONFIG_SCSI_CXGB4_ISCSI=m
+CONFIG_SCSI_DC395x=m
+CONFIG_SCSI_DEBUG=m
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_DH_ALUA=m
+CONFIG_SCSI_DH_EMC=m
+CONFIG_SCSI_DH_HP_SW=m
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DMX3191D=m
+# CONFIG_SCSI_EFCT is not set
+CONFIG_SCSI_ENCLOSURE=m
+CONFIG_SCSI_ESAS2R=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_FDOMAIN=m
+CONFIG_SCSI_FDOMAIN_PCI=m
+CONFIG_SCSI_HPSA=m
+CONFIG_SCSI_HPTIOP=m
+CONFIG_SCSI_INIA100=m
+CONFIG_SCSI_INITIO=m
+CONFIG_SCSI_IPR=m
+CONFIG_SCSI_IPR_DUMP=y
+CONFIG_SCSI_IPR_TRACE=y
+CONFIG_SCSI_IPS=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_MPT2SAS=m
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+CONFIG_SCSI_MVSAS=m
+CONFIG_SCSI_MVSAS_TASKLET=y
+CONFIG_SCSI_MVUMI=m
+CONFIG_SCSI_MYRB=m
+CONFIG_SCSI_MYRS=m
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PM8001=m
+CONFIG_SCSI_PMCRAID=m
+CONFIG_SCSI_QLA_FC=m
+CONFIG_SCSI_QLA_ISCSI=m
+CONFIG_SCSI_QLOGIC_1280=m
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_SMARTPQI=m
+CONFIG_SCSI_SNIC=m
+# CONFIG_SCSI_SNIC_DEBUG_FS is not set
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_STEX=m
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+CONFIG_SCSI_VIRTIO=m
+CONFIG_SCSI_WD719X=m
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
+CONFIG_SDIO_UART=m
+CONFIG_SECONDARY_TRUSTED_KEYRING=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_INFINIBAND=y
+CONFIG_SECURITY_LOCKDOWN_LSM=y
+CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_NETWORK_XFRM=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
+CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
+CONFIG_SECURITY_YAMA=y
+CONFIG_SENSORS_AD7314=m
+CONFIG_SENSORS_AD7414=m
+CONFIG_SENSORS_AD7418=m
+CONFIG_SENSORS_ADC128D818=m
+CONFIG_SENSORS_ADCXX=m
+CONFIG_SENSORS_ADM1021=m
+CONFIG_SENSORS_ADM1025=m
+CONFIG_SENSORS_ADM1026=m
+CONFIG_SENSORS_ADM1029=m
+CONFIG_SENSORS_ADM1031=m
+CONFIG_SENSORS_ADM1266=m
+CONFIG_SENSORS_ADM1275=m
+CONFIG_SENSORS_ADM9240=m
+CONFIG_SENSORS_ADS7828=m
+CONFIG_SENSORS_ADS7871=m
+CONFIG_SENSORS_ADT7310=m
+CONFIG_SENSORS_ADT7410=m
+CONFIG_SENSORS_ADT7411=m
+CONFIG_SENSORS_ADT7462=m
+CONFIG_SENSORS_ADT7470=m
+CONFIG_SENSORS_ADT7475=m
+CONFIG_SENSORS_ADT7X10=m
+CONFIG_SENSORS_AMC6821=m
+CONFIG_SENSORS_APDS990X=m
+CONFIG_SENSORS_ASC7621=m
+CONFIG_SENSORS_ASPEED=m
+CONFIG_SENSORS_ATXP1=m
+CONFIG_SENSORS_AXI_FAN_CONTROL=m
+CONFIG_SENSORS_BEL_PFE=m
+CONFIG_SENSORS_BH1770=m
+CONFIG_SENSORS_DME1737=m
+CONFIG_SENSORS_DRIVETEMP=m
+CONFIG_SENSORS_DS1621=m
+CONFIG_SENSORS_DS620=m
+CONFIG_SENSORS_EMC1403=m
+CONFIG_SENSORS_EMC6W201=m
+CONFIG_SENSORS_F71805F=m
+CONFIG_SENSORS_F71882FG=m
+CONFIG_SENSORS_F75375S=m
+CONFIG_SENSORS_FTSTEUTATES=m
+CONFIG_SENSORS_G760A=m
+CONFIG_SENSORS_G762=m
+CONFIG_SENSORS_GL518SM=m
+CONFIG_SENSORS_GL520SM=m
+CONFIG_SENSORS_IBMAEM=m
+CONFIG_SENSORS_IBMPEX=m
+CONFIG_SENSORS_INA209=m
+CONFIG_SENSORS_INA2XX=m
+CONFIG_SENSORS_INA3221=m
+CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
+CONFIG_SENSORS_IT87=m
+CONFIG_SENSORS_JC42=m
+CONFIG_SENSORS_LINEAGE=m
+CONFIG_SENSORS_LM25066=m
+CONFIG_SENSORS_LM63=m
+CONFIG_SENSORS_LM70=m
+CONFIG_SENSORS_LM73=m
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM77=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM80=m
+CONFIG_SENSORS_LM83=m
+CONFIG_SENSORS_LM85=m
+CONFIG_SENSORS_LM87=m
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_LM92=m
+CONFIG_SENSORS_LM93=m
+CONFIG_SENSORS_LM95234=m
+CONFIG_SENSORS_LM95241=m
+CONFIG_SENSORS_LM95245=m
+CONFIG_SENSORS_LTC2945=m
+CONFIG_SENSORS_LTC2947=m
+CONFIG_SENSORS_LTC2947_I2C=m
+CONFIG_SENSORS_LTC2947_SPI=m
+CONFIG_SENSORS_LTC2978=m
+# CONFIG_SENSORS_LTC2978_REGULATOR is not set
+CONFIG_SENSORS_LTC2990=m
+CONFIG_SENSORS_LTC3815=m
+CONFIG_SENSORS_LTC4151=m
+CONFIG_SENSORS_LTC4215=m
+CONFIG_SENSORS_LTC4222=m
+CONFIG_SENSORS_LTC4245=m
+CONFIG_SENSORS_LTC4260=m
+CONFIG_SENSORS_LTC4261=m
+CONFIG_SENSORS_MAX1111=m
+CONFIG_SENSORS_MAX16064=m
+CONFIG_SENSORS_MAX16065=m
+CONFIG_SENSORS_MAX1619=m
+CONFIG_SENSORS_MAX1668=m
+CONFIG_SENSORS_MAX197=m
+CONFIG_SENSORS_MAX20751=m
+CONFIG_SENSORS_MAX31722=m
+CONFIG_SENSORS_MAX31790=m
+CONFIG_SENSORS_MAX34440=m
+CONFIG_SENSORS_MAX6639=m
+CONFIG_SENSORS_MAX6642=m
+CONFIG_SENSORS_MAX6650=m
+CONFIG_SENSORS_MAX6697=m
+CONFIG_SENSORS_MAX8688=m
+CONFIG_SENSORS_MCP3021=m
+CONFIG_SENSORS_MP2975=m
+CONFIG_SENSORS_MR75203=m
+CONFIG_SENSORS_NCT6683=m
+CONFIG_SENSORS_NCT6775=m
+CONFIG_SENSORS_NCT7802=m
+CONFIG_SENSORS_NCT7904=m
+CONFIG_SENSORS_NPCM7XX=m
+CONFIG_SENSORS_NTC_THERMISTOR=m
+CONFIG_SENSORS_PC87360=m
+CONFIG_SENSORS_PC87427=m
+CONFIG_SENSORS_PCF8591=m
+CONFIG_SENSORS_POWR1220=m
+CONFIG_SENSORS_PWM_FAN=m
+CONFIG_SENSORS_RM3100=m
+CONFIG_SENSORS_RM3100_I2C=m
+CONFIG_SENSORS_RM3100_SPI=m
+CONFIG_SENSORS_SCH5627=m
+CONFIG_SENSORS_SCH5636=m
+CONFIG_SENSORS_SCH56XX_COMMON=m
+CONFIG_SENSORS_SFCTEMP=m
+CONFIG_SENSORS_SHT15=m
+CONFIG_SENSORS_SHT21=m
+CONFIG_SENSORS_SHT3x=m
+CONFIG_SENSORS_SHTC1=m
+CONFIG_SENSORS_SIS5595=m
+CONFIG_SENSORS_SMSC47B397=m
+CONFIG_SENSORS_SMSC47M1=m
+CONFIG_SENSORS_SMSC47M192=m
+CONFIG_SENSORS_TC654=m
+CONFIG_SENSORS_TC74=m
+CONFIG_SENSORS_THMC50=m
+CONFIG_SENSORS_TMP102=m
+CONFIG_SENSORS_TMP103=m
+CONFIG_SENSORS_TMP108=m
+CONFIG_SENSORS_TMP401=m
+CONFIG_SENSORS_TMP421=m
+CONFIG_SENSORS_TMP513=m
+CONFIG_SENSORS_TPS40422=m
+CONFIG_SENSORS_TPS53679=m
+CONFIG_SENSORS_TSL2550=m
+CONFIG_SENSORS_UCD9000=m
+CONFIG_SENSORS_UCD9200=m
+CONFIG_SENSORS_VIA686A=m
+CONFIG_SENSORS_VT1211=m
+CONFIG_SENSORS_VT8231=m
+CONFIG_SENSORS_W83627EHF=m
+CONFIG_SENSORS_W83627HF=m
+CONFIG_SENSORS_W83773G=m
+CONFIG_SENSORS_W83781D=m
+CONFIG_SENSORS_W83791D=m
+CONFIG_SENSORS_W83792D=m
+CONFIG_SENSORS_W83793=m
+CONFIG_SENSORS_W83795=m
+# CONFIG_SENSORS_W83795_FANCTRL is not set
+CONFIG_SENSORS_W83L785TS=m
+CONFIG_SENSORS_W83L786NG=m
+CONFIG_SENSORS_ZL6100=m
+# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=32
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_ARC=m
+CONFIG_SERIAL_ARC_NR_PORTS=1
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
 CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_SERIAL_JSM=m
 CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_NONSTANDARD=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SC16IS7XX=m
+CONFIG_SERIAL_SC16IS7XX_CORE=m
+# CONFIG_SERIAL_SC16IS7XX_I2C is not set
+CONFIG_SERIAL_SC16IS7XX_SPI=y
 CONFIG_SERIAL_SIFIVE=y
 CONFIG_SERIAL_SIFIVE_CONSOLE=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
+CONFIG_SFP=m
+CONFIG_SF_PDMA=y
+CONFIG_SGI_PARTITION=y
+CONFIG_SGL_ALLOC=y
 CONFIG_SG_POOL=y
+CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
 CONFIG_SIFIVE_L2=y
+CONFIG_SIFIVE_L2_FLUSH=y
+CONFIG_SIFIVE_L2_FLUSH_SIZE=0x800000000
+CONFIG_SIFIVE_L2_FLUSH_START=0x80000000
+CONFIG_SIFIVE_L2_IRQ_DISABLE=y
 CONFIG_SIFIVE_PLIC=y
-CONFIG_SLUB_DEBUG=y
+CONFIG_SIGNED_PE_FILE_VERIFICATION=y
+CONFIG_SIS190=m
+CONFIG_SIS900=m
+CONFIG_SKB_EXTENSIONS=y
+CONFIG_SKGE=m
+# CONFIG_SKGE_DEBUG is not set
+CONFIG_SKGE_GENESIS=y
+CONFIG_SKY2=m
+CONFIG_SLAB_FREELIST_HARDENED=y
+CONFIG_SLAB_FREELIST_RANDOM=y
+CONFIG_SLHC=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+# CONFIG_SLIP_MODE_SLIP6 is not set
+CONFIG_SLIP_SMART=y
+CONFIG_SMBFS_COMMON=m
+CONFIG_SMC=m
+CONFIG_SMC_DIAG=m
 CONFIG_SMP=y
+CONFIG_SMSC911X=m
+CONFIG_SMSC9420=m
+CONFIG_SMSC_PHY=m
+CONFIG_SMS_SDIO_DRV=m
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SND=m
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
+CONFIG_SND_AD1889=m
+CONFIG_SND_ALOOP=m
+CONFIG_SND_ATIIXP=m
+CONFIG_SND_ATIIXP_MODEM=m
+CONFIG_SND_AU8810=m
+CONFIG_SND_AU8820=m
+CONFIG_SND_AU8830=m
+CONFIG_SND_BT87X=m
+# CONFIG_SND_BT87X_OVERCLOCK is not set
+CONFIG_SND_CA0106=m
+CONFIG_SND_CMIPCI=m
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_CS46XX_NEW_DSP=y
+CONFIG_SND_CTL_LED=m
+CONFIG_SND_CTXFI=m
+CONFIG_SND_DARLA20=m
+CONFIG_SND_DARLA24=m
+CONFIG_SND_DESIGNWARE_I2S=m
+CONFIG_SND_DESIGNWARE_PCM=y
+CONFIG_SND_DMAENGINE_PCM=m
+CONFIG_SND_DUMMY=m
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_ECHO3G=m
+CONFIG_SND_ENS1370=m
+CONFIG_SND_ENS1371=m
+CONFIG_SND_FM801=m
+CONFIG_SND_GINA20=m
+CONFIG_SND_GINA24=m
+CONFIG_SND_HDA=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_CA0110=m
+CONFIG_SND_HDA_CODEC_CA0132=m
+CONFIG_SND_HDA_CODEC_CA0132_DSP=y
+CONFIG_SND_HDA_CODEC_CIRRUS=m
+CONFIG_SND_HDA_CODEC_CMEDIA=m
+CONFIG_SND_HDA_CODEC_CONEXANT=m
+CONFIG_SND_HDA_CODEC_HDMI=m
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_SI3054=m
+CONFIG_SND_HDA_CODEC_SIGMATEL=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_COMPONENT=y
+CONFIG_SND_HDA_CORE=m
+CONFIG_SND_HDA_DSP_LOADER=y
+CONFIG_SND_HDA_GENERIC=m
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_PREALLOC_SIZE=4096
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDSP=m
+CONFIG_SND_HDSPM=m
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_I2S_HI6210_I2S=m
+CONFIG_SND_ICE1724=m
+CONFIG_SND_INDIGO=m
+CONFIG_SND_INDIGODJ=m
+CONFIG_SND_INDIGODJX=m
+CONFIG_SND_INDIGOIO=m
+CONFIG_SND_INDIGOIOX=m
+CONFIG_SND_INTEL_DSP_CONFIG=m
+CONFIG_SND_JACK=y
+CONFIG_SND_KORG1212=m
+CONFIG_SND_LAYLA20=m
+CONFIG_SND_LAYLA24=m
+CONFIG_SND_LOLA=m
+CONFIG_SND_LX6464ES=m
+CONFIG_SND_MIA=m
+CONFIG_SND_MIXART=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_MONA=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_NM256=m
+CONFIG_SND_OPL3_LIB=m
+CONFIG_SND_OPL3_LIB_SEQ=m
+CONFIG_SND_OXYGEN=m
+CONFIG_SND_OXYGEN_LIB=m
+CONFIG_SND_PCM=m
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCXHR=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_RIPTIDE=m
+CONFIG_SND_RME32=m
+CONFIG_SND_RME96=m
+CONFIG_SND_RME9652=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQ_MIDI_EMUL=m
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_VIRMIDI=m
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=m
+CONFIG_SND_SOC_ADAU1761=m
+CONFIG_SND_SOC_ADAU1761_I2C=m
+CONFIG_SND_SOC_ADAU1761_SPI=m
+CONFIG_SND_SOC_ADAU17X1=m
+CONFIG_SND_SOC_ADAU7002=m
+CONFIG_SND_SOC_ADAU7118=m
+CONFIG_SND_SOC_ADAU7118_HW=m
+CONFIG_SND_SOC_ADAU7118_I2C=m
+CONFIG_SND_SOC_ADAU_UTILS=m
+CONFIG_SND_SOC_AK5558=m
+CONFIG_SND_SOC_AMD_ACP=m
+CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
+CONFIG_SND_SOC_BD28623=m
+CONFIG_SND_SOC_CS35L34=m
+CONFIG_SND_SOC_CS35L35=m
+CONFIG_SND_SOC_CS35L36=m
+CONFIG_SND_SOC_CS4234=m
+CONFIG_SND_SOC_CS42L42=m
+CONFIG_SND_SOC_CS43130=m
+CONFIG_SND_SOC_CX2072X=m
+CONFIG_SND_SOC_DA7213=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_ES7134=m
+CONFIG_SND_SOC_ES8328=m
+CONFIG_SND_SOC_ES8328_I2C=m
+CONFIG_SND_SOC_ES8328_SPI=m
+# CONFIG_SND_SOC_FSL_RPMSG is not set
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_HDMI_CODEC=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+CONFIG_SND_SOC_MAX9759=m
+CONFIG_SND_SOC_MAX98088=m
+CONFIG_SND_SOC_MAX98357A=m
+CONFIG_SND_SOC_MAX98373=m
+CONFIG_SND_SOC_MAX98373_I2C=m
+CONFIG_SND_SOC_MAX98373_SDW=m
+CONFIG_SND_SOC_MAX98390=m
+CONFIG_SND_SOC_MAX9867=m
+CONFIG_SND_SOC_MAX98927=m
+CONFIG_SND_SOC_NAU8824=m
+CONFIG_SND_SOC_PCM1789=m
+CONFIG_SND_SOC_PCM1789_I2C=m
+CONFIG_SND_SOC_PCM186X=m
+CONFIG_SND_SOC_PCM186X_I2C=m
+CONFIG_SND_SOC_PCM186X_SPI=m
+CONFIG_SND_SOC_PCM3060=m
+CONFIG_SND_SOC_PCM3060_I2C=m
+CONFIG_SND_SOC_PCM3060_SPI=m
+CONFIG_SND_SOC_RL6231=m
+CONFIG_SND_SOC_RT1308_SDW=m
+# CONFIG_SND_SOC_RT1316_SDW is not set
+CONFIG_SND_SOC_RT5645=m
+CONFIG_SND_SOC_RT5682=m
+CONFIG_SND_SOC_RT5682_SDW=m
+CONFIG_SND_SOC_RT700=m
+CONFIG_SND_SOC_RT700_SDW=m
+CONFIG_SND_SOC_RT711=m
+# CONFIG_SND_SOC_RT711_SDCA_SDW is not set
+CONFIG_SND_SOC_RT711_SDW=m
+CONFIG_SND_SOC_RT715=m
+# CONFIG_SND_SOC_RT715_SDCA_SDW is not set
+CONFIG_SND_SOC_RT715_SDW=m
+# CONFIG_SND_SOC_SDW_MOCKUP is not set
+CONFIG_SND_SOC_SIGMADSP=m
+CONFIG_SND_SOC_SIGMADSP_REGMAP=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+# CONFIG_SND_SOC_SOF_DEBUG_PROBES is not set
+# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set
+# CONFIG_SND_SOC_SOF_OF is not set
+CONFIG_SND_SOC_SOF_PCI=m
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_SND_SOC_TAS2562=m
+CONFIG_SND_SOC_TAS2764=m
+CONFIG_SND_SOC_TAS2770=m
+CONFIG_SND_SOC_TAS6424=m
+CONFIG_SND_SOC_TDA7419=m
+CONFIG_SND_SOC_TLV320ADCX140=m
+CONFIG_SND_SOC_TLV320AIC32X4=m
+CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
+CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
+CONFIG_SND_SOC_TSCS42XX=m
+# CONFIG_SND_SOC_WCD938X_SDW is not set
+CONFIG_SND_SOC_WM8524=m
+# CONFIG_SND_SOC_WSA881X is not set
+CONFIG_SND_SOC_ZL38060=m
+# CONFIG_SND_STARFIVE_I2SVAD is not set
+# CONFIG_SND_STARFIVE_PDM is not set
+CONFIG_SND_STARFIVE_PWMDAC=m
+# CONFIG_SND_STARFIVE_PWMDAC_PCM is not set
+# CONFIG_SND_STARFIVE_SPDIF is not set
+CONFIG_SND_TIMER=m
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_VIRTUOSO=m
+CONFIG_SND_VMASTER=y
+CONFIG_SND_VX222=m
+CONFIG_SND_VX_LIB=m
+CONFIG_SND_YMFPCI=m
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_SOCK_DIAG=y
 CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOCK_VALIDATE_XMIT=y
 # CONFIG_SOC_MICROCHIP_POLARFIRE is not set
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_SOC_VIRT=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_SOFT_WATCHDOG=m
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_SOUND=m
+CONFIG_SOUNDWIRE=y
+# CONFIG_SOUNDWIRE_QCOM is not set
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
 CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
 CONFIG_SPARSE_IRQ=y
 CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_ALTERA_DFL is not set
+CONFIG_SPI_CADENCE_QUADSPI=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_DMA=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_DW_PCI=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_FSI=m
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
+CONFIG_SPI_MUX=m
 CONFIG_SPI_SIFIVE=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZSTD=y
 CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
+CONFIG_SSB=m
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+CONFIG_SSB_SPROM=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_STARFIVE_WATCHDOG=m
+CONFIG_STE10XP=m
+CONFIG_STK3310=m
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PCI=y
+CONFIG_STP=m
+CONFIG_STREAM_PARSER=y
+CONFIG_ST_UVIS25=m
+CONFIG_ST_UVIS25_I2C=m
+CONFIG_ST_UVIS25_SPI=m
+CONFIG_SUNDANCE=m
+# CONFIG_SUNDANCE_MMIO is not set
+CONFIG_SUNGEM=m
+CONFIG_SUNGEM_PHY=m
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_SUNRPC_DEBUG=y
+CONFIG_SUNRPC_GSS=m
+CONFIG_SUNRPC_SWAP=y
+CONFIG_SUNRPC_XPRT_RDMA=m
+CONFIG_SUN_PARTITION=y
 CONFIG_SWIOTLB=y
 CONFIG_SWPHY=y
+CONFIG_SX9310=m
+CONFIG_SYNCLINK_GT=m
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCON_REBOOT_MODE=y
 CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFB=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
+CONFIG_SYSTEM_BLACKLIST_KEYRING=y
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
+CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096
+# CONFIG_SYSTEM_REVOCATION_LIST is not set
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSV_FS=m
+CONFIG_TAP=m
+CONFIG_TARGET_CORE=m
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASK_XACCT=y
+CONFIG_TCM_FC=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_PSCSI=m
+CONFIG_TCM_QLA2XXX=m
+# CONFIG_TCM_QLA2XXX_DEBUG is not set
+CONFIG_TCM_USER2=m
+CONFIG_TCP_CONG_BBR=m
+CONFIG_TCP_CONG_CDG=m
+CONFIG_TCP_CONG_DCTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_NV=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_MD5SIG=y
+CONFIG_TEHUTI=m
+CONFIG_TERANETICS_PHY=m
+CONFIG_TEST_KSTRTOX=y
+# CONFIG_TEST_OBJAGG is not set
+# CONFIG_TEST_PARMAN is not set
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_TEXTSEARCH_KMP=m
 CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIFM_7XX1=m
+CONFIG_TIFM_CORE=m
+CONFIG_TIGON3=m
+CONFIG_TIGON3_HWMON=y
 CONFIG_TIMER_OF=y
 CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_CLOCK=y
+CONFIG_TINYDRM_ILI9486=m
+CONFIG_TIPC=m
+CONFIG_TIPC_CRYPTO=y
+CONFIG_TIPC_DIAG=m
+# CONFIG_TIPC_MEDIA_IB is not set
+CONFIG_TIPC_MEDIA_UDP=y
+CONFIG_TI_ADC128S052=m
+CONFIG_TI_ADS1015=m
+CONFIG_TI_ADS8344=m
+CONFIG_TI_DAC7311=m
+CONFIG_TLAN=m
+CONFIG_TLS=m
+CONFIG_TLS_DEVICE=y
+# CONFIG_TLS_TOE is not set
+CONFIG_TMPFS_INODE64=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TORTURE_TEST=m
 CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
+CONFIG_TSL2772=m
+CONFIG_TTPCI_EEPROM=m
+CONFIG_TULIP=m
+CONFIG_TULIP_MMIO=y
+# CONFIG_TULIP_MWI is not set
+# CONFIG_TULIP_NAPI is not set
+CONFIG_TUN=m
 CONFIG_TUNE_GENERIC=y
-CONFIG_UCS2_STRING=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_HID=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PCI=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-# CONFIG_USER_NS is not set
-CONFIG_UTS_NS=y
+CONFIG_TYPHOON=m
+CONFIG_UACCE=m
+# CONFIG_UAPI_HEADER_TEST is not set
+CONFIG_UBIFS_ATIME_SUPPORT=y
+CONFIG_UBIFS_FS=m
+CONFIG_UBIFS_FS_AUTHENTICATION=y
+CONFIG_UDF_FS=m
+CONFIG_UDMABUF=y
+# CONFIG_UFS_DEBUG is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_UIO=m
+CONFIG_UIO_AEC=m
+CONFIG_UIO_CIF=m
+# CONFIG_UIO_DFL is not set
+# CONFIG_UIO_DMEM_GENIRQ is not set
+# CONFIG_UIO_MF624 is not set
+# CONFIG_UIO_NETX is not set
+CONFIG_UIO_PCI_GENERIC=m
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_PRUSS is not set
+CONFIG_UIO_SERCOS3=m
+CONFIG_ULI526X=m
+CONFIG_UNICODE=y
+# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_UNIX_DIAG=m
+CONFIG_USB4=y
+# CONFIG_USB4_DEBUGFS_WRITE is not set
+# CONFIG_USB4_DMA_TEST is not set
+CONFIG_USB4_NET=m
+CONFIG_USERFAULTFD=y
+CONFIG_USER_NS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VALIDATE_FS_PARSER=y
 CONFIG_VA_BITS=39
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VCNL3020=m
+CONFIG_VCNL4035=m
+CONFIG_VDPA=m
+CONFIG_VDPA_SIM=m
+# CONFIG_VDPA_SIM_BLOCK is not set
+# CONFIG_VDPA_SIM_NET is not set
+# CONFIG_VDPA_USER is not set
+CONFIG_VEML6030=m
+CONFIG_VETH=m
+CONFIG_VFAT_FS=m
+CONFIG_VFIO=m
+CONFIG_VFIO_MDEV=m
+# CONFIG_VFIO_NOIOMMU is not set
+CONFIG_VFIO_PCI=m
+CONFIG_VFIO_PCI_CORE=m
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_VIRQFD=m
+CONFIG_VHOST=m
+CONFIG_VHOST_IOTLB=m
+CONFIG_VHOST_NET=m
+CONFIG_VHOST_RING=m
+CONFIG_VHOST_SCSI=m
+CONFIG_VHOST_VDPA=m
+CONFIG_VHOST_VSOCK=m
+CONFIG_VIA_RHINE=m
+CONFIG_VIA_RHINE_MMIO=y
+CONFIG_VIA_VELOCITY=m
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_SAA7146=m
 CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_BLK=m
+CONFIG_VIRTIO_CONSOLE=m
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
+CONFIG_VIRTIO_FS=m
+CONFIG_VIRTIO_MMIO=m
+CONFIG_VIRTIO_NET=m
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_VDPA=m
+CONFIG_VIRTIO_VSOCKETS=m
+CONFIG_VIRTIO_VSOCKETS_COMMON=m
+CONFIG_VIRT_CPU_ACCOUNTING=y
+CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_VIRT_WIFI=m
+CONFIG_VITESSE_PHY=m
+CONFIG_VL53L0X_I2C=m
+CONFIG_VL6180=m
 CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_VORTEX=m
+# CONFIG_VP_VDPA is not set
+CONFIG_VSOCKETS=m
+CONFIG_VSOCKETS_LOOPBACK=m
+CONFIG_VSOCKMON=m
+CONFIG_VXGE=m
+# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
+CONFIG_VXLAN=m
+CONFIG_W1=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_SLAVE_DS2405=m
+CONFIG_W1_SLAVE_DS2406=m
+CONFIG_W1_SLAVE_DS2408=m
+# CONFIG_W1_SLAVE_DS2408_READBACK is not set
+CONFIG_W1_SLAVE_DS2413=m
+CONFIG_W1_SLAVE_DS2423=m
+CONFIG_W1_SLAVE_DS2430=m
+CONFIG_W1_SLAVE_DS2431=m
+CONFIG_W1_SLAVE_DS2433=m
+CONFIG_W1_SLAVE_DS2433_CRC=y
+CONFIG_W1_SLAVE_DS2438=m
+CONFIG_W1_SLAVE_DS2780=m
+CONFIG_W1_SLAVE_DS2781=m
+CONFIG_W1_SLAVE_DS2805=m
+CONFIG_W1_SLAVE_DS28E04=m
+CONFIG_W1_SLAVE_SMEM=m
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_WANT_DEV_COREDUMP=y
 CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_WATCH_QUEUE=y
+CONFIG_WDTPCI=m
+# CONFIG_WFX is not set
+CONFIG_WINBOND_840=m
+CONFIG_WIREGUARD=m
+# CONFIG_WIREGUARD_DEBUG is not set
+CONFIG_WIZNET_BUS_ANY=y
+# CONFIG_WIZNET_BUS_DIRECT is not set
+# CONFIG_WIZNET_BUS_INDIRECT is not set
+CONFIG_WIZNET_W5100=m
+CONFIG_WIZNET_W5100_SPI=m
+CONFIG_WIZNET_W5300=m
 CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_XDP_SOCKETS=y
+CONFIG_XDP_SOCKETS_DIAG=m
+CONFIG_XFRM_AH=m
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_ESP=m
+CONFIG_XFRM_ESPINTCP=y
+CONFIG_XFRM_IPCOMP=m
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XFRM_OFFLOAD=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_USER=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_ONLINE_REPAIR is not set
+CONFIG_XFS_ONLINE_SCRUB=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_QUOTA=y
+CONFIG_XILINX_GMII2RGMII=m
+CONFIG_XILINX_LL_TEMAC=m
+CONFIG_XILINX_PR_DECOUPLER=m
+CONFIG_XILINX_VCU=m
+CONFIG_XILLYBUS=m
+CONFIG_XILLYBUS_CLASS=m
+# CONFIG_XILLYBUS_OF is not set
+CONFIG_XILLYBUS_PCIE=m
+CONFIG_XOR_BLOCKS=y
 CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_YAM=m
+CONFIG_YELLOWFIN=m
+CONFIG_YENTA=m
+CONFIG_Z3FOLD=y
+CONFIG_ZBUD=y
+CONFIG_ZISOFS=y
+CONFIG_ZLIB_DEFLATE=y
 CONFIG_ZLIB_INFLATE=y
+# CONFIG_ZONEFS_FS is not set
 CONFIG_ZONE_DMA32=y
+CONFIG_ZOPT2201=m
+CONFIG_ZPOOL=y
+CONFIG_ZRAM=m
+CONFIG_ZRAM_DEF_COMP="lzo-rle"
+# CONFIG_ZRAM_DEF_COMP_842 is not set
+# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
+CONFIG_ZRAM_DEF_COMP_LZORLE=y
+# CONFIG_ZRAM_WRITEBACK is not set
+CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC_STAT is not set
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_ZSWAP=y
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo"
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set
+# CONFIG_ZSWAP_DEFAULT_ON is not set
+CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
+CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set

diff --git a/target/linux/visionfive/patches-5.15/0001-RISC-V-Add-StarFive-SoC-Kconfig-option.patch b/target/linux/visionfive/patches-5.15/0001-RISC-V-Add-StarFive-SoC-Kconfig-option.patch
deleted file mode 100644 (file)
index b2e81ce..0000000
--- a/target/linux/visionfive/patches-5.15/0001-RISC-V-Add-StarFive-SoC-Kconfig-option.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 3d24568b01c5a7a9e88f73f917477b60edb35bfe Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sun, 10 Oct 2021 16:10:32 +0200
-Subject: [PATCH 01/16] RISC-V: Add StarFive SoC Kconfig option
-
-Add StarFive Kconfig option to select SoC specific and common drivers
-required for these SoCs. Select subsystems required to boot so the
-required drivers gets enabled by default.
-
-Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- arch/riscv/Kconfig.socs | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/riscv/Kconfig.socs
-+++ b/arch/riscv/Kconfig.socs
-@@ -19,6 +19,14 @@ config SOC_SIFIVE
-       help
-         This enables support for SiFive SoC platform hardware.
- 
-+config SOC_STARFIVE
-+      bool "StarFive SoCs"
-+      select PINCTRL
-+      select RESET_CONTROLLER
-+      select SIFIVE_PLIC
-+      help
-+        This enables support for StarFive SoC platform hardware.
-+
- config SOC_VIRT
-       bool "QEMU Virt Machine"
-       select CLINT_TIMER if RISCV_M_MODE

diff --git a/target/linux/visionfive/patches-5.15/0001-serial-8250_lpss-Extract-dw8250_do_set_termios-for-c.patch b/target/linux/visionfive/patches-5.15/0001-serial-8250_lpss-Extract-dw8250_do_set_termios-for-c.patch
new file mode 100644 (file)
index 0000000..2b62fa3
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0001-serial-8250_lpss-Extract-dw8250_do_set_termios-for-c.patch
@@ -0,0 +1,79 @@
+From c356e653cf7664c303a70ba0829ab3582494135c Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Tue, 5 Oct 2021 16:30:25 +0300
+Subject: [PATCH 01/84] serial: 8250_lpss: Extract dw8250_do_set_termios() for
+ common use
+
+commit 7c4fc082f50431cc0814b47595ec9f9cca285993 upstream.
+
+Some of the code currently used in dw8250_set_termios(), byt_set_termios()
+may be reused by other methods in the future. Extract it to a common helper
+function.
+
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Link: https://lore.kernel.org/r/20211005133026.21488-1-andriy.shevchenko@linux.intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/serial/8250/8250_dw.c    |  6 +-----
+ drivers/tty/serial/8250/8250_dwlib.c | 10 ++++++++++
+ drivers/tty/serial/8250/8250_dwlib.h |  1 +
+ drivers/tty/serial/8250/8250_lpss.c  |  6 +-----
+ 4 files changed, 13 insertions(+), 10 deletions(-)
+
+--- a/drivers/tty/serial/8250/8250_dw.c
++++ b/drivers/tty/serial/8250/8250_dw.c
+@@ -350,11 +350,7 @@ static void dw8250_set_termios(struct ua
+       }
+       clk_prepare_enable(d->clk);
+ 
+-      p->status &= ~UPSTAT_AUTOCTS;
+-      if (termios->c_cflag & CRTSCTS)
+-              p->status |= UPSTAT_AUTOCTS;
+-
+-      serial8250_do_set_termios(p, termios, old);
++      dw8250_do_set_termios(p, termios, old);
+ }
+ 
+ static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
+--- a/drivers/tty/serial/8250/8250_dwlib.c
++++ b/drivers/tty/serial/8250/8250_dwlib.c
+@@ -77,6 +77,16 @@ static void dw8250_set_divisor(struct ua
+       serial8250_do_set_divisor(p, baud, quot, quot_frac);
+ }
+ 
++void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old)
++{
++      p->status &= ~UPSTAT_AUTOCTS;
++      if (termios->c_cflag & CRTSCTS)
++              p->status |= UPSTAT_AUTOCTS;
++
++      serial8250_do_set_termios(p, termios, old);
++}
++EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
++
+ void dw8250_setup_port(struct uart_port *p)
+ {
+       struct uart_8250_port *up = up_to_u8250p(p);
+--- a/drivers/tty/serial/8250/8250_dwlib.h
++++ b/drivers/tty/serial/8250/8250_dwlib.h
+@@ -16,4 +16,5 @@ struct dw8250_port_data {
+       u8                      dlf_size;
+ };
+ 
++void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old);
+ void dw8250_setup_port(struct uart_port *p);
+--- a/drivers/tty/serial/8250/8250_lpss.c
++++ b/drivers/tty/serial/8250/8250_lpss.c
+@@ -100,11 +100,7 @@ static void byt_set_termios(struct uart_
+       reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
+       writel(reg, p->membase + BYT_PRV_CLK);
+ 
+-      p->status &= ~UPSTAT_AUTOCTS;
+-      if (termios->c_cflag & CRTSCTS)
+-              p->status |= UPSTAT_AUTOCTS;
+-
+-      serial8250_do_set_termios(p, termios, old);
++      dw8250_do_set_termios(p, termios, old);
+ }
+ 
+ static unsigned int byt_get_mctrl(struct uart_port *port)

diff --git a/target/linux/visionfive/patches-5.15/0002-dmaengine-dw-axi-dmac-support-DMAX_NUM_CHANNELS-8.patch b/target/linux/visionfive/patches-5.15/0002-dmaengine-dw-axi-dmac-support-DMAX_NUM_CHANNELS-8.patch
new file mode 100644 (file)
index 0000000..339a31e
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0002-dmaengine-dw-axi-dmac-support-DMAX_NUM_CHANNELS-8.patch
@@ -0,0 +1,298 @@
+From c0b35303260c1a8be2ec32919896e0600bf69b06 Mon Sep 17 00:00:00 2001
+From: Pandith N <pandith.n@intel.com>
+Date: Fri, 1 Oct 2021 19:38:10 +0530
+Subject: [PATCH 02/84] dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8
+
+commit 824351668a413af7d6d88e4ee2c9bee7c60daad2 upstream.
+
+Added support for DMA controller with more than 8 channels.
+DMAC register map changes based on number of channels.
+
+Enabling DMAC channel:
+DMAC_CHENREG has to be used when number of channels <= 8
+DMAC_CHENREG2 has to be used when number of channels > 8
+
+Configuring DMA channel:
+CHx_CFG has to be used when number of channels <= 8
+CHx_CFG2 has to be used when number of channels > 8
+
+Suspending and resuming channel:
+DMAC_CHENREG has to be used when number of channels <= 8 DMAC_CHSUSPREG
+has to be used for suspending a channel > 8
+
+Signed-off-by: Pandith N <pandith.n@intel.com>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+Link: https://lore.kernel.org/r/20211001140812.24977-2-pandith.n@intel.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 105 +++++++++++++-----
+ drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  35 +++++-
+ 2 files changed, 109 insertions(+), 31 deletions(-)
+
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+@@ -79,6 +79,32 @@ axi_chan_iowrite64(struct axi_dma_chan *
+       iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4);
+ }
+ 
++static inline void axi_chan_config_write(struct axi_dma_chan *chan,
++                                       struct axi_dma_chan_config *config)
++{
++      u32 cfg_lo, cfg_hi;
++
++      cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
++                config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
++      if (chan->chip->dw->hdata->reg_map_8_channels) {
++              cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
++                       config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
++                       config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
++                       config->src_per << CH_CFG_H_SRC_PER_POS |
++                       config->dst_per << CH_CFG_H_DST_PER_POS |
++                       config->prior << CH_CFG_H_PRIORITY_POS;
++      } else {
++              cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS |
++                        config->dst_per << CH_CFG2_L_DST_PER_POS;
++              cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS |
++                       config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS |
++                       config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS |
++                       config->prior << CH_CFG2_H_PRIORITY_POS;
++      }
++      axi_chan_iowrite32(chan, CH_CFG_L, cfg_lo);
++      axi_chan_iowrite32(chan, CH_CFG_H, cfg_hi);
++}
++
+ static inline void axi_dma_disable(struct axi_dma_chip *chip)
+ {
+       u32 val;
+@@ -154,7 +180,10 @@ static inline void axi_chan_disable(stru
+ 
+       val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
+       val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT);
+-      val |=   BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
++      if (chan->chip->dw->hdata->reg_map_8_channels)
++              val |=   BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
++      else
++              val |=   BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
+       axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
+ }
+ 
+@@ -163,8 +192,12 @@ static inline void axi_chan_enable(struc
+       u32 val;
+ 
+       val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
+-      val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
+-             BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
++      if (chan->chip->dw->hdata->reg_map_8_channels)
++              val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
++                      BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
++      else
++              val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
++                      BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
+       axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
+ }
+ 
+@@ -336,7 +369,8 @@ static void axi_chan_block_xfer_start(st
+                                     struct axi_dma_desc *first)
+ {
+       u32 priority = chan->chip->dw->hdata->priority[chan->id];
+-      u32 reg, irq_mask;
++      struct axi_dma_chan_config config;
++      u32 irq_mask;
+       u8 lms = 0; /* Select AXI0 master for LLI fetching */
+ 
+       if (unlikely(axi_chan_is_hw_enable(chan))) {
+@@ -348,36 +382,32 @@ static void axi_chan_block_xfer_start(st
+ 
+       axi_dma_enable(chan->chip);
+ 
+-      reg = (DWAXIDMAC_MBLK_TYPE_LL << CH_CFG_L_DST_MULTBLK_TYPE_POS |
+-             DWAXIDMAC_MBLK_TYPE_LL << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
+-      axi_chan_iowrite32(chan, CH_CFG_L, reg);
+-
+-      reg = (DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC << CH_CFG_H_TT_FC_POS |
+-             priority << CH_CFG_H_PRIORITY_POS |
+-             DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS |
+-             DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
++      config.dst_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
++      config.src_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
++      config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC;
++      config.prior = priority;
++      config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW;
++      config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW;
+       switch (chan->direction) {
+       case DMA_MEM_TO_DEV:
+               dw_axi_dma_set_byte_halfword(chan, true);
+-              reg |= (chan->config.device_fc ?
+-                      DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
+-                      DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
+-                      << CH_CFG_H_TT_FC_POS;
++              config.tt_fc = chan->config.device_fc ?
++                              DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
++                              DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC;
+               if (chan->chip->apb_regs)
+-                      reg |= (chan->id << CH_CFG_H_DST_PER_POS);
++                      config.dst_per = chan->id;
+               break;
+       case DMA_DEV_TO_MEM:
+-              reg |= (chan->config.device_fc ?
+-                      DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
+-                      DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
+-                      << CH_CFG_H_TT_FC_POS;
++              config.tt_fc = chan->config.device_fc ?
++                              DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
++                              DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC;
+               if (chan->chip->apb_regs)
+-                      reg |= (chan->id << CH_CFG_H_SRC_PER_POS);
++                      config.src_per = chan->id;
+               break;
+       default:
+               break;
+       }
+-      axi_chan_iowrite32(chan, CH_CFG_H, reg);
++      axi_chan_config_write(chan, &config);
+ 
+       write_chan_llp(chan, first->hw_desc[0].llp | lms);
+ 
+@@ -1120,10 +1150,17 @@ static int dma_chan_pause(struct dma_cha
+ 
+       spin_lock_irqsave(&chan->vc.lock, flags);
+ 
+-      val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
+-      val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |
+-             BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
+-      axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
++      if (chan->chip->dw->hdata->reg_map_8_channels) {
++              val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
++              val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |
++                      BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
++              axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
++      } else {
++              val = 0;
++              val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
++                      BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
++              axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
++      }
+ 
+       do  {
+               if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED)
+@@ -1147,9 +1184,15 @@ static inline void axi_chan_resume(struc
+       u32 val;
+ 
+       val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
+-      val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
+-      val |=  (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
+-      axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
++      if (chan->chip->dw->hdata->reg_map_8_channels) {
++              val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
++              val |=  (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
++              axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
++      } else {
++              val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT);
++              val |=  (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT);
++              axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
++      }
+ 
+       chan->is_paused = false;
+ }
+@@ -1241,6 +1284,8 @@ static int parse_device_properties(struc
+               return -EINVAL;
+ 
+       chip->dw->hdata->nr_channels = tmp;
++      if (tmp <= DMA_REG_MAP_CH_REF)
++              chip->dw->hdata->reg_map_8_channels = true;
+ 
+       ret = device_property_read_u32(dev, "snps,dma-masters", &tmp);
+       if (ret)
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+@@ -18,7 +18,7 @@
+ 
+ #include "../virt-dma.h"
+ 
+-#define DMAC_MAX_CHANNELS     8
++#define DMAC_MAX_CHANNELS     16
+ #define DMAC_MAX_MASTERS      2
+ #define DMAC_MAX_BLK_SIZE     0x200000
+ 
+@@ -30,6 +30,8 @@ struct dw_axi_dma_hcfg {
+       u32     priority[DMAC_MAX_CHANNELS];
+       /* maximum supported axi burst length */
+       u32     axi_rw_burst_len;
++      /* Register map for DMAX_NUM_CHANNELS <= 8 */
++      bool    reg_map_8_channels;
+       bool    restrict_axi_burst_len;
+ };
+ 
+@@ -103,6 +105,17 @@ struct axi_dma_desc {
+       u32                             period_len;
+ };
+ 
++struct axi_dma_chan_config {
++      u8 dst_multblk_type;
++      u8 src_multblk_type;
++      u8 dst_per;
++      u8 src_per;
++      u8 tt_fc;
++      u8 prior;
++      u8 hs_sel_dst;
++      u8 hs_sel_src;
++};
++
+ static inline struct device *dchan2dev(struct dma_chan *dchan)
+ {
+       return &dchan->dev->device;
+@@ -139,6 +152,8 @@ static inline struct axi_dma_chan *dchan
+ #define DMAC_CHEN             0x018 /* R/W DMAC Channel Enable */
+ #define DMAC_CHEN_L           0x018 /* R/W DMAC Channel Enable 00-31 */
+ #define DMAC_CHEN_H           0x01C /* R/W DMAC Channel Enable 32-63 */
++#define DMAC_CHSUSPREG                0x020 /* R/W DMAC Channel Suspend */
++#define DMAC_CHABORTREG               0x028 /* R/W DMAC Channel Abort */
+ #define DMAC_INTSTATUS                0x030 /* R DMAC Interrupt Status */
+ #define DMAC_COMMON_INTCLEAR  0x038 /* W DMAC Interrupt Clear */
+ #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
+@@ -187,6 +202,7 @@ static inline struct axi_dma_chan *dchan
+ #define DMA_APB_HS_SEL_BIT_SIZE       0x08 /* HW handshake bits per channel */
+ #define DMA_APB_HS_SEL_MASK   0xFF /* HW handshake select masks */
+ #define MAX_BLOCK_SIZE                0x1000 /* 1024 blocks * 4 bytes data width */
++#define DMA_REG_MAP_CH_REF    0x08 /* Channel count to choose register map */
+ 
+ /* DMAC_CFG */
+ #define DMAC_EN_POS                   0
+@@ -195,12 +211,20 @@ static inline struct axi_dma_chan *dchan
+ #define INT_EN_POS                    1
+ #define INT_EN_MASK                   BIT(INT_EN_POS)
+ 
++/* DMAC_CHEN */
+ #define DMAC_CHAN_EN_SHIFT            0
+ #define DMAC_CHAN_EN_WE_SHIFT         8
+ 
+ #define DMAC_CHAN_SUSP_SHIFT          16
+ #define DMAC_CHAN_SUSP_WE_SHIFT               24
+ 
++/* DMAC_CHEN2 */
++#define DMAC_CHAN_EN2_WE_SHIFT                16
++
++/* DMAC_CHSUSP */
++#define DMAC_CHAN_SUSP2_SHIFT         0
++#define DMAC_CHAN_SUSP2_WE_SHIFT      16
++
+ /* CH_CTL_H */
+ #define CH_CTL_H_ARLEN_EN             BIT(6)
+ #define CH_CTL_H_ARLEN_POS            7
+@@ -289,6 +313,15 @@ enum {
+       DWAXIDMAC_MBLK_TYPE_LL
+ };
+ 
++/* CH_CFG2 */
++#define CH_CFG2_L_SRC_PER_POS         4
++#define CH_CFG2_L_DST_PER_POS         11
++
++#define CH_CFG2_H_TT_FC_POS           0
++#define CH_CFG2_H_HS_SEL_SRC_POS      3
++#define CH_CFG2_H_HS_SEL_DST_POS      4
++#define CH_CFG2_H_PRIORITY_POS                20
++
+ /**
+  * DW AXI DMA channel interrupts
+  *

diff --git a/target/linux/visionfive/patches-5.15/0002-dt-bindings-timer-Add-StarFive-JH7100-clint.patch b/target/linux/visionfive/patches-5.15/0002-dt-bindings-timer-Add-StarFive-JH7100-clint.patch
deleted file mode 100644 (file)
index 32efa91..0000000
--- a/target/linux/visionfive/patches-5.15/0002-dt-bindings-timer-Add-StarFive-JH7100-clint.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From 3234d3a1374308615c0cde5e83e52f6b644eaf53 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sun, 10 Oct 2021 16:48:27 +0200
-Subject: [PATCH 02/16] dt-bindings: timer: Add StarFive JH7100 clint
-
-Add compatible string for the StarFive JH7100 clint.
-
-Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
-+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
-@@ -25,6 +25,7 @@ properties:
-     items:
-       - enum:
-           - sifive,fu540-c000-clint
-+          - starfive,jh7100-clint
-           - canaan,k210-clint
-       - const: sifive,clint0
- 

diff --git a/target/linux/visionfive/patches-5.15/0003-dmaengine-dw-axi-dmac-Hardware-handshake-configurati.patch b/target/linux/visionfive/patches-5.15/0003-dmaengine-dw-axi-dmac-Hardware-handshake-configurati.patch
new file mode 100644 (file)
index 0000000..08156b9
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0003-dmaengine-dw-axi-dmac-Hardware-handshake-configurati.patch
@@ -0,0 +1,41 @@
+From 4798cbff53d2643971e2eee16391778b96368408 Mon Sep 17 00:00:00 2001
+From: Pandith N <pandith.n@intel.com>
+Date: Fri, 1 Oct 2021 19:38:11 +0530
+Subject: [PATCH 03/84] dmaengine: dw-axi-dmac: Hardware handshake
+ configuration
+
+commit 93a7d32e9f4b8bad722a8c8c83c579a2f6a5aec3 upstream.
+
+Added hardware handshake selection in channel config,
+for mem2per and per2mem case.
+The peripheral specific handshake interface needs to be
+programmed in src_per, dst_per bits of CHx_CFG register.
+
+Signed-off-by: Pandith N <pandith.n@intel.com>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Link: https://lore.kernel.org/r/20211001140812.24977-3-pandith.n@intel.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+@@ -396,6 +396,8 @@ static void axi_chan_block_xfer_start(st
+                               DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC;
+               if (chan->chip->apb_regs)
+                       config.dst_per = chan->id;
++              else
++                      config.dst_per = chan->hw_handshake_num;
+               break;
+       case DMA_DEV_TO_MEM:
+               config.tt_fc = chan->config.device_fc ?
+@@ -403,6 +405,8 @@ static void axi_chan_block_xfer_start(st
+                               DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC;
+               if (chan->chip->apb_regs)
+                       config.src_per = chan->id;
++              else
++                      config.src_per = chan->hw_handshake_num;
+               break;
+       default:
+               break;

diff --git a/target/linux/visionfive/patches-5.15/0003-dt-bindings-interrupt-controller-Add-StarFive-JH7100.patch b/target/linux/visionfive/patches-5.15/0003-dt-bindings-interrupt-controller-Add-StarFive-JH7100.patch
deleted file mode 100644 (file)
index 538a0e0..0000000
--- a/target/linux/visionfive/patches-5.15/0003-dt-bindings-interrupt-controller-Add-StarFive-JH7100.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 9ac16169b4d4359d3832669bf06aab9e51184828 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sun, 10 Oct 2021 16:48:27 +0200
-Subject: [PATCH 03/16] dt-bindings: interrupt-controller: Add StarFive JH7100
- plic
-
-Add compatible string for StarFive JH7100 plic.
-
-Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
-+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
-@@ -45,6 +45,7 @@ properties:
-     items:
-       - enum:
-           - sifive,fu540-c000-plic
-+          - starfive,jh7100-plic
-           - canaan,k210-plic
-       - const: sifive,plic-1.0.0
- 

diff --git a/target/linux/visionfive/patches-5.15/0004-dmaengine-dw-axi-dmac-set-coherent-mask.patch b/target/linux/visionfive/patches-5.15/0004-dmaengine-dw-axi-dmac-set-coherent-mask.patch
new file mode 100644 (file)
index 0000000..e449342
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0004-dmaengine-dw-axi-dmac-set-coherent-mask.patch
@@ -0,0 +1,37 @@
+From 9bb19d196865ac213d14b79bbacf7aed0d6d2304 Mon Sep 17 00:00:00 2001
+From: Pandith N <pandith.n@intel.com>
+Date: Fri, 1 Oct 2021 19:38:12 +0530
+Subject: [PATCH 04/84] dmaengine: dw-axi-dmac: set coherent mask
+
+commit 2d0f07f888f52532588730aae0241af5c5df393d upstream.
+
+Add support for setting dma coherent mask, dma mask is set to 64 bit
+
+Signed-off-by: Pandith N <pandith.n@intel.com>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+Link: https://lore.kernel.org/r/20211001140812.24977-4-pandith.n@intel.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+@@ -212,12 +212,16 @@ static inline bool axi_chan_is_hw_enable
+ 
+ static void axi_dma_hw_init(struct axi_dma_chip *chip)
+ {
++      int ret;
+       u32 i;
+ 
+       for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
+               axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
+               axi_chan_disable(&chip->dw->chan[i]);
+       }
++      ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
++      if (ret)
++              dev_warn(chip->dev, "Unable to set coherent mask\n");
+ }
+ 
+ static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src,

diff --git a/target/linux/visionfive/patches-5.15/0004-dt-bindings-clock-starfive-Add-JH7100-clock-definiti.patch b/target/linux/visionfive/patches-5.15/0004-dt-bindings-clock-starfive-Add-JH7100-clock-definiti.patch
deleted file mode 100644 (file)
index bc5f773..0000000
--- a/target/linux/visionfive/patches-5.15/0004-dt-bindings-clock-starfive-Add-JH7100-clock-definiti.patch
+++ /dev/null
@@ -1,225 +0,0 @@
-From 38bb8a7264daf0ff5bb3024ae94bc465de78203d Mon Sep 17 00:00:00 2001
-From: Geert Uytterhoeven <geert@linux-m68k.org>
-Date: Fri, 25 Jun 2021 11:29:51 +0200
-Subject: [PATCH 04/16] dt-bindings: clock: starfive: Add JH7100 clock
- definitions
-
-Add all clock outputs for the StarFive JH7100 clock generator.
-
-Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
-to all definitions.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- include/dt-bindings/clock/starfive-jh7100.h | 202 ++++++++++++++++++++
- 1 file changed, 202 insertions(+)
- create mode 100644 include/dt-bindings/clock/starfive-jh7100.h
-
---- /dev/null
-+++ b/include/dt-bindings/clock/starfive-jh7100.h
-@@ -0,0 +1,202 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
-+ */
-+
-+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
-+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
-+
-+#define JH7100_CLK_CPUNDBUS_ROOT      0
-+#define JH7100_CLK_DLA_ROOT           1
-+#define JH7100_CLK_DSP_ROOT           2
-+#define JH7100_CLK_GMACUSB_ROOT               3
-+#define JH7100_CLK_PERH0_ROOT         4
-+#define JH7100_CLK_PERH1_ROOT         5
-+#define JH7100_CLK_VIN_ROOT           6
-+#define JH7100_CLK_VOUT_ROOT          7
-+#define JH7100_CLK_AUDIO_ROOT         8
-+#define JH7100_CLK_CDECHIFI4_ROOT     9
-+#define JH7100_CLK_CDEC_ROOT          10
-+#define JH7100_CLK_VOUTBUS_ROOT               11
-+#define JH7100_CLK_CPUNBUS_ROOT_DIV   12
-+#define JH7100_CLK_DSP_ROOT_DIV               13
-+#define JH7100_CLK_PERH0_SRC          14
-+#define JH7100_CLK_PERH1_SRC          15
-+#define JH7100_CLK_PLL0_TESTOUT               16
-+#define JH7100_CLK_PLL1_TESTOUT               17
-+#define JH7100_CLK_PLL2_TESTOUT               18
-+#define JH7100_CLK_PLL2_REF           19
-+#define JH7100_CLK_CPU_CORE           20
-+#define JH7100_CLK_CPU_AXI            21
-+#define JH7100_CLK_AHB_BUS            22
-+#define JH7100_CLK_APB1_BUS           23
-+#define JH7100_CLK_APB2_BUS           24
-+#define JH7100_CLK_DOM3AHB_BUS                25
-+#define JH7100_CLK_DOM7AHB_BUS                26
-+#define JH7100_CLK_U74_CORE0          27
-+#define JH7100_CLK_U74_CORE1          28
-+#define JH7100_CLK_U74_AXI            29
-+#define JH7100_CLK_U74RTC_TOGGLE      30
-+#define JH7100_CLK_SGDMA2P_AXI                31
-+#define JH7100_CLK_DMA2PNOC_AXI               32
-+#define JH7100_CLK_SGDMA2P_AHB                33
-+#define JH7100_CLK_DLA_BUS            34
-+#define JH7100_CLK_DLA_AXI            35
-+#define JH7100_CLK_DLANOC_AXI         36
-+#define JH7100_CLK_DLA_APB            37
-+#define JH7100_CLK_VP6_CORE           38
-+#define JH7100_CLK_VP6BUS_SRC         39
-+#define JH7100_CLK_VP6_AXI            40
-+#define JH7100_CLK_VCDECBUS_SRC               41
-+#define JH7100_CLK_VDEC_BUS           42
-+#define JH7100_CLK_VDEC_AXI           43
-+#define JH7100_CLK_VDECBRG_MAIN               44
-+#define JH7100_CLK_VDEC_BCLK          45
-+#define JH7100_CLK_VDEC_CCLK          46
-+#define JH7100_CLK_VDEC_APB           47
-+#define JH7100_CLK_JPEG_AXI           48
-+#define JH7100_CLK_JPEG_CCLK          49
-+#define JH7100_CLK_JPEG_APB           50
-+#define JH7100_CLK_GC300_2X           51
-+#define JH7100_CLK_GC300_AHB          52
-+#define JH7100_CLK_JPCGC300_AXIBUS    53
-+#define JH7100_CLK_GC300_AXI          54
-+#define JH7100_CLK_JPCGC300_MAIN      55
-+#define JH7100_CLK_VENC_BUS           56
-+#define JH7100_CLK_VENC_AXI           57
-+#define JH7100_CLK_VENCBRG_MAIN               58
-+#define JH7100_CLK_VENC_BCLK          59
-+#define JH7100_CLK_VENC_CCLK          60
-+#define JH7100_CLK_VENC_APB           61
-+#define JH7100_CLK_DDRPLL_DIV2                62
-+#define JH7100_CLK_DDRPLL_DIV4                63
-+#define JH7100_CLK_DDRPLL_DIV8                64
-+#define JH7100_CLK_DDROSC_DIV2                65
-+#define JH7100_CLK_DDRC0              66
-+#define JH7100_CLK_DDRC1              67
-+#define JH7100_CLK_DDRPHY_APB         68
-+#define JH7100_CLK_NOC_ROB            69
-+#define JH7100_CLK_NOC_COG            70
-+#define JH7100_CLK_NNE_AHB            71
-+#define JH7100_CLK_NNEBUS_SRC1                72
-+#define JH7100_CLK_NNE_BUS            73
-+#define JH7100_CLK_NNE_AXI            74
-+#define JH7100_CLK_NNENOC_AXI         75
-+#define JH7100_CLK_DLASLV_AXI         76
-+#define JH7100_CLK_DSPX2C_AXI         77
-+#define JH7100_CLK_HIFI4_SRC          78
-+#define JH7100_CLK_HIFI4_COREFREE     79
-+#define JH7100_CLK_HIFI4_CORE         80
-+#define JH7100_CLK_HIFI4_BUS          81
-+#define JH7100_CLK_HIFI4_AXI          82
-+#define JH7100_CLK_HIFI4NOC_AXI               83
-+#define JH7100_CLK_SGDMA1P_BUS                84
-+#define JH7100_CLK_SGDMA1P_AXI                85
-+#define JH7100_CLK_DMA1P_AXI          86
-+#define JH7100_CLK_X2C_AXI            87
-+#define JH7100_CLK_USB_BUS            88
-+#define JH7100_CLK_USB_AXI            89
-+#define JH7100_CLK_USBNOC_AXI         90
-+#define JH7100_CLK_USBPHY_ROOTDIV     91
-+#define JH7100_CLK_USBPHY_125M                92
-+#define JH7100_CLK_USBPHY_PLLDIV25M   93
-+#define JH7100_CLK_USBPHY_25M         94
-+#define JH7100_CLK_AUDIO_DIV          95
-+#define JH7100_CLK_AUDIO_SRC          96
-+#define JH7100_CLK_AUDIO_12288                97
-+#define JH7100_CLK_VIN_SRC            98
-+#define JH7100_CLK_ISP0_BUS           99
-+#define JH7100_CLK_ISP0_AXI           100
-+#define JH7100_CLK_ISP0NOC_AXI                101
-+#define JH7100_CLK_ISPSLV_AXI         102
-+#define JH7100_CLK_ISP1_BUS           103
-+#define JH7100_CLK_ISP1_AXI           104
-+#define JH7100_CLK_ISP1NOC_AXI                105
-+#define JH7100_CLK_VIN_BUS            106
-+#define JH7100_CLK_VIN_AXI            107
-+#define JH7100_CLK_VINNOC_AXI         108
-+#define JH7100_CLK_VOUT_SRC           109
-+#define JH7100_CLK_DISPBUS_SRC                110
-+#define JH7100_CLK_DISP_BUS           111
-+#define JH7100_CLK_DISP_AXI           112
-+#define JH7100_CLK_DISPNOC_AXI                113
-+#define JH7100_CLK_SDIO0_AHB          114
-+#define JH7100_CLK_SDIO0_CCLKINT      115
-+#define JH7100_CLK_SDIO0_CCLKINT_INV  116
-+#define JH7100_CLK_SDIO1_AHB          117
-+#define JH7100_CLK_SDIO1_CCLKINT      118
-+#define JH7100_CLK_SDIO1_CCLKINT_INV  119
-+#define JH7100_CLK_GMAC_AHB           120
-+#define JH7100_CLK_GMAC_ROOT_DIV      121
-+#define JH7100_CLK_GMAC_PTP_REF               122
-+#define JH7100_CLK_GMAC_GTX           123
-+#define JH7100_CLK_GMAC_RMII_TX               124
-+#define JH7100_CLK_GMAC_RMII_RX               125
-+#define JH7100_CLK_GMAC_TX            126
-+#define JH7100_CLK_GMAC_TX_INV                127
-+#define JH7100_CLK_GMAC_RX_PRE                128
-+#define JH7100_CLK_GMAC_RX_INV                129
-+#define JH7100_CLK_GMAC_RMII          130
-+#define JH7100_CLK_GMAC_TOPHYREF      131
-+#define JH7100_CLK_SPI2AHB_AHB                132
-+#define JH7100_CLK_SPI2AHB_CORE               133
-+#define JH7100_CLK_EZMASTER_AHB               134
-+#define JH7100_CLK_E24_AHB            135
-+#define JH7100_CLK_E24RTC_TOGGLE      136
-+#define JH7100_CLK_QSPI_AHB           137
-+#define JH7100_CLK_QSPI_APB           138
-+#define JH7100_CLK_QSPI_REF           139
-+#define JH7100_CLK_SEC_AHB            140
-+#define JH7100_CLK_AES                        141
-+#define JH7100_CLK_SHA                        142
-+#define JH7100_CLK_PKA                        143
-+#define JH7100_CLK_TRNG_APB           144
-+#define JH7100_CLK_OTP_APB            145
-+#define JH7100_CLK_UART0_APB          146
-+#define JH7100_CLK_UART0_CORE         147
-+#define JH7100_CLK_UART1_APB          148
-+#define JH7100_CLK_UART1_CORE         149
-+#define JH7100_CLK_SPI0_APB           150
-+#define JH7100_CLK_SPI0_CORE          151
-+#define JH7100_CLK_SPI1_APB           152
-+#define JH7100_CLK_SPI1_CORE          153
-+#define JH7100_CLK_I2C0_APB           154
-+#define JH7100_CLK_I2C0_CORE          155
-+#define JH7100_CLK_I2C1_APB           156
-+#define JH7100_CLK_I2C1_CORE          157
-+#define JH7100_CLK_GPIO_APB           158
-+#define JH7100_CLK_UART2_APB          159
-+#define JH7100_CLK_UART2_CORE         160
-+#define JH7100_CLK_UART3_APB          161
-+#define JH7100_CLK_UART3_CORE         162
-+#define JH7100_CLK_SPI2_APB           163
-+#define JH7100_CLK_SPI2_CORE          164
-+#define JH7100_CLK_SPI3_APB           165
-+#define JH7100_CLK_SPI3_CORE          166
-+#define JH7100_CLK_I2C2_APB           167
-+#define JH7100_CLK_I2C2_CORE          168
-+#define JH7100_CLK_I2C3_APB           169
-+#define JH7100_CLK_I2C3_CORE          170
-+#define JH7100_CLK_WDTIMER_APB                171
-+#define JH7100_CLK_WDT_CORE           172
-+#define JH7100_CLK_TIMER0_CORE                173
-+#define JH7100_CLK_TIMER1_CORE                174
-+#define JH7100_CLK_TIMER2_CORE                175
-+#define JH7100_CLK_TIMER3_CORE                176
-+#define JH7100_CLK_TIMER4_CORE                177
-+#define JH7100_CLK_TIMER5_CORE                178
-+#define JH7100_CLK_TIMER6_CORE                179
-+#define JH7100_CLK_VP6INTC_APB                180
-+#define JH7100_CLK_PWM_APB            181
-+#define JH7100_CLK_MSI_APB            182
-+#define JH7100_CLK_TEMP_APB           183
-+#define JH7100_CLK_TEMP_SENSE         184
-+#define JH7100_CLK_SYSERR_APB         185
-+
-+#define JH7100_CLK_PLL0_OUT           186
-+#define JH7100_CLK_PLL1_OUT           187
-+#define JH7100_CLK_PLL2_OUT           188
-+
-+#define JH7100_CLK_END                        189
-+
-+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */

diff --git a/target/linux/visionfive/patches-5.15/0005-dmaengine-dw-axi-dmac-Simplify-assignment-in-dma_cha.patch b/target/linux/visionfive/patches-5.15/0005-dmaengine-dw-axi-dmac-Simplify-assignment-in-dma_cha.patch
new file mode 100644 (file)
index 0000000..c739857
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0005-dmaengine-dw-axi-dmac-Simplify-assignment-in-dma_cha.patch
@@ -0,0 +1,32 @@
+From bcc0159d4fc6183f2dbf1132895fff9ec9982841 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Tue, 26 Oct 2021 17:56:07 +0200
+Subject: [PATCH 05/84] dmaengine: dw-axi-dmac: Simplify assignment in
+ dma_chan_pause()
+
+commit 2f23355e96b4a5896de2032176197fa0c5c444dd upstream.
+
+Simplify assigning zero and performing a logical OR to a single
+assignment.
+
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Link: https://lore.kernel.org/r/2abd0da35608c14689a919d47dd45898a8ab4297.1635263478.git.geert@linux-m68k.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+@@ -1164,9 +1164,8 @@ static int dma_chan_pause(struct dma_cha
+                       BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
+               axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
+       } else {
+-              val = 0;
+-              val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
+-                      BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
++              val = BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
++                    BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
+               axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
+       }
+ 

diff --git a/target/linux/visionfive/patches-5.15/0005-dt-bindings-clock-starfive-Add-JH7100-bindings.patch b/target/linux/visionfive/patches-5.15/0005-dt-bindings-clock-starfive-Add-JH7100-bindings.patch
deleted file mode 100644 (file)
index 2f40211..0000000
--- a/target/linux/visionfive/patches-5.15/0005-dt-bindings-clock-starfive-Add-JH7100-bindings.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From af35098f4fcd1f9bfc58dc37479e0786a4d85e96 Mon Sep 17 00:00:00 2001
-From: Geert Uytterhoeven <geert@linux-m68k.org>
-Date: Tue, 1 Jun 2021 16:02:23 +0200
-Subject: [PATCH 05/16] dt-bindings: clock: starfive: Add JH7100 bindings
-
-Add bindings for the clock generator on the JH7100 RISC-V SoC by
-StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
-
-Reviewed-by: Rob Herring <robh@kernel.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- .../clock/starfive,jh7100-clkgen.yaml         | 56 +++++++++++++++++++
- 1 file changed, 56 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
-@@ -0,0 +1,56 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: StarFive JH7100 Clock Generator
-+
-+maintainers:
-+  - Geert Uytterhoeven <geert@linux-m68k.org>
-+  - Emil Renner Berthing <kernel@esmil.dk>
-+
-+properties:
-+  compatible:
-+    const: starfive,jh7100-clkgen
-+
-+  reg:
-+    maxItems: 1
-+
-+  clocks:
-+    items:
-+      - description: Main clock source (25 MHz)
-+      - description: Application-specific clock source (12-27 MHz)
-+      - description: RMII reference clock (50 MHz)
-+      - description: RGMII RX clock (125 MHz)
-+
-+  clock-names:
-+    items:
-+      - const: osc_sys
-+      - const: osc_aud
-+      - const: gmac_rmii_ref
-+      - const: gmac_gr_mii_rxclk
-+
-+  '#clock-cells':
-+    const: 1
-+    description:
-+      See <dt-bindings/clock/starfive-jh7100.h> for valid indices.
-+
-+required:
-+  - compatible
-+  - reg
-+  - clocks
-+  - clock-names
-+  - '#clock-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    clock-controller@11800000 {
-+            compatible = "starfive,jh7100-clkgen";
-+            reg = <0x11800000 0x10000>;
-+            clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
-+            clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
-+            #clock-cells = <1>;
-+    };

diff --git a/target/linux/visionfive/patches-5.15/0006-clk-starfive-Add-JH7100-clock-generator-driver.patch b/target/linux/visionfive/patches-5.15/0006-clk-starfive-Add-JH7100-clock-generator-driver.patch
deleted file mode 100644 (file)
index 06f6137..0000000
--- a/target/linux/visionfive/patches-5.15/0006-clk-starfive-Add-JH7100-clock-generator-driver.patch
+++ /dev/null
@@ -1,770 +0,0 @@
-From 4210be668a09ee20e4e1c7adf61b47d33d05c480 Mon Sep 17 00:00:00 2001
-From: Geert Uytterhoeven <geert@linux-m68k.org>
-Date: Tue, 1 Jun 2021 15:57:52 +0200
-Subject: [PATCH 06/16] clk: starfive: Add JH7100 clock generator driver
-
-Add a driver for the StarFive JH7100 clock generator.
-
-Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- MAINTAINERS                                |   7 +
- drivers/clk/Kconfig                        |   1 +
- drivers/clk/Makefile                       |   1 +
- drivers/clk/starfive/Kconfig               |   9 +
- drivers/clk/starfive/Makefile              |   3 +
- drivers/clk/starfive/clk-starfive-jh7100.c | 689 +++++++++++++++++++++
- 6 files changed, 710 insertions(+)
- create mode 100644 drivers/clk/starfive/Kconfig
- create mode 100644 drivers/clk/starfive/Makefile
- create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -17860,6 +17860,13 @@ M:    Ion Badulescu <ionut@badula.org>
- S:    Odd Fixes
- F:    drivers/net/ethernet/adaptec/starfire*
- 
-+STARFIVE JH7100 CLOCK DRIVER
-+M:    Emil Renner Berthing <kernel@esmil.dk>
-+S:    Maintained
-+F:    Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
-+F:    drivers/clk/starfive/clk-starfive-jh7100.c
-+F:    include/dt-bindings/clock/starfive-jh7100.h
-+
- STATIC BRANCH/CALL
- M:    Peter Zijlstra <peterz@infradead.org>
- M:    Josh Poimboeuf <jpoimboe@redhat.com>
---- a/drivers/clk/Kconfig
-+++ b/drivers/clk/Kconfig
-@@ -412,6 +412,7 @@ source "drivers/clk/samsung/Kconfig"
- source "drivers/clk/sifive/Kconfig"
- source "drivers/clk/socfpga/Kconfig"
- source "drivers/clk/sprd/Kconfig"
-+source "drivers/clk/starfive/Kconfig"
- source "drivers/clk/sunxi/Kconfig"
- source "drivers/clk/sunxi-ng/Kconfig"
- source "drivers/clk/tegra/Kconfig"
---- a/drivers/clk/Makefile
-+++ b/drivers/clk/Makefile
-@@ -109,6 +109,7 @@ obj-y                                      += socfpga/
- obj-$(CONFIG_PLAT_SPEAR)              += spear/
- obj-y                                 += sprd/
- obj-$(CONFIG_ARCH_STI)                        += st/
-+obj-$(CONFIG_SOC_STARFIVE)            += starfive/
- obj-$(CONFIG_ARCH_SUNXI)              += sunxi/
- obj-$(CONFIG_SUNXI_CCU)                       += sunxi-ng/
- obj-$(CONFIG_ARCH_TEGRA)              += tegra/
---- /dev/null
-+++ b/drivers/clk/starfive/Kconfig
-@@ -0,0 +1,9 @@
-+# SPDX-License-Identifier: GPL-2.0
-+
-+config CLK_STARFIVE_JH7100
-+      bool "StarFive JH7100 clock support"
-+      depends on SOC_STARFIVE || COMPILE_TEST
-+      default SOC_STARFIVE
-+      help
-+        Say yes here to support the clock controller on the StarFive JH7100
-+        SoC.
---- /dev/null
-+++ b/drivers/clk/starfive/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier: GPL-2.0
-+# StarFive Clock
-+obj-$(CONFIG_CLK_STARFIVE_JH7100)     += clk-starfive-jh7100.o
---- /dev/null
-+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
-@@ -0,0 +1,689 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * StarFive JH7100 Clock Generator Driver
-+ *
-+ * Copyright 2021 Ahmad Fatoum, Pengutronix
-+ * Copyright (C) 2021 Glider bv
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+#include <linux/bits.h>
-+#include <linux/clk-provider.h>
-+#include <linux/debugfs.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <dt-bindings/clock/starfive-jh7100.h>
-+
-+/* external clocks */
-+#define JH7100_CLK_OSC_SYS            (JH7100_CLK_END + 0)
-+#define JH7100_CLK_OSC_AUD            (JH7100_CLK_END + 1)
-+#define JH7100_CLK_GMAC_RMII_REF      (JH7100_CLK_END + 2)
-+#define JH7100_CLK_GMAC_GR_MII_RX     (JH7100_CLK_END + 3)
-+
-+/* register fields */
-+#define JH7100_CLK_ENABLE     BIT(31)
-+#define JH7100_CLK_INVERT     BIT(30)
-+#define JH7100_CLK_MUX_MASK   GENMASK(27, 24)
-+#define JH7100_CLK_MUX_SHIFT  24
-+#define JH7100_CLK_DIV_MASK   GENMASK(23, 0)
-+
-+/* clock data */
-+#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = {          \
-+      .name = _name,                                                  \
-+      .flags = CLK_SET_RATE_PARENT | (_flags),                        \
-+      .max = JH7100_CLK_ENABLE,                                       \
-+      .parents = { [0] = _parent },                                   \
-+}
-+
-+#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = {            \
-+      .name = _name,                                                  \
-+      .flags = 0,                                                     \
-+      .max = _max,                                                    \
-+      .parents = { [0] = _parent },                                   \
-+}
-+
-+#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = {    \
-+      .name = _name,                                                  \
-+      .flags = _flags,                                                \
-+      .max = JH7100_CLK_ENABLE | (_max),                              \
-+      .parents = { [0] = _parent },                                   \
-+}
-+
-+#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = {           \
-+      .name = _name,                                                  \
-+      .flags = 0,                                                     \
-+      .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT,               \
-+      .parents = { __VA_ARGS__ },                                     \
-+}
-+
-+#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = {   \
-+      .name = _name,                                                  \
-+      .flags = _flags,                                                \
-+      .max = JH7100_CLK_ENABLE |                                      \
-+              (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT),            \
-+      .parents = { __VA_ARGS__ },                                     \
-+}
-+
-+#define JH7100__INV(_idx, _name, _parent) [_idx] = {                  \
-+      .name = _name,                                                  \
-+      .flags = CLK_SET_RATE_PARENT,                                   \
-+      .max = JH7100_CLK_INVERT,                                       \
-+      .parents = { [0] = _parent },                                   \
-+}
-+
-+static const struct {
-+      const char *name;
-+      unsigned long flags;
-+      u32 max;
-+      u8 parents[4];
-+} jh7100_clk_data[] __initconst = {
-+      JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_PLL0_OUT,
-+                  JH7100_CLK_PLL1_OUT,
-+                  JH7100_CLK_PLL2_OUT),
-+      JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_PLL1_OUT,
-+                  JH7100_CLK_PLL2_OUT),
-+      JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_PLL0_OUT,
-+                  JH7100_CLK_PLL1_OUT,
-+                  JH7100_CLK_PLL2_OUT),
-+      JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_PLL0_OUT,
-+                  JH7100_CLK_PLL2_OUT),
-+      JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_PLL0_OUT),
-+      JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_PLL2_OUT),
-+      JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_PLL1_OUT,
-+                  JH7100_CLK_PLL2_OUT),
-+      JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
-+                  JH7100_CLK_OSC_AUD,
-+                  JH7100_CLK_PLL0_OUT,
-+                  JH7100_CLK_PLL2_OUT),
-+      JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
-+      JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_PLL1_OUT,
-+                  JH7100_CLK_PLL2_OUT),
-+      JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_PLL0_OUT,
-+                  JH7100_CLK_PLL1_OUT),
-+      JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
-+                  JH7100_CLK_OSC_AUD,
-+                  JH7100_CLK_PLL0_OUT,
-+                  JH7100_CLK_PLL2_OUT),
-+      JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
-+      JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
-+      JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
-+      JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
-+      JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
-+      JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
-+      JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
-+      JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_OSC_AUD),
-+      JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-+      JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
-+      JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-+      JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
-+      JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
-+      JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
-+      JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
-+      JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
-+      JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
-+      JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
-+      JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
-+      JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
-+      JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
-+      JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
-+      JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
-+      JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
-+      JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
-+      JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
-+      JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
-+      JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
-+      JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
-+      JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
-+      JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
-+      JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
-+      JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
-+      JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-+      JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-+      JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
-+      JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
-+      JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
-+      JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
-+      JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
-+      JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
-+      JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
-+      JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
-+      JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
-+      JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
-+      JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
-+      JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
-+      JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
-+      JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
-+                  JH7100_CLK_DDROSC_DIV2,
-+                  JH7100_CLK_DDRPLL_DIV2,
-+                  JH7100_CLK_DDRPLL_DIV4,
-+                  JH7100_CLK_DDRPLL_DIV8),
-+      JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
-+                  JH7100_CLK_DDROSC_DIV2,
-+                  JH7100_CLK_DDRPLL_DIV2,
-+                  JH7100_CLK_DDRPLL_DIV4,
-+                  JH7100_CLK_DDRPLL_DIV8),
-+      JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-+      JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
-+      JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
-+      JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
-+                  JH7100_CLK_CPU_AXI,
-+                  JH7100_CLK_NNEBUS_SRC1),
-+      JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
-+      JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
-+      JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
-+      JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
-+      JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
-+      JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
-+      JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
-+      JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
-+      JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
-+      JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
-+      JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-+      JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
-+      JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
-+      JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-+      JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-+      JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
-+      JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
-+      JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
-+      JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
-+      JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
-+      JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
-+                  JH7100_CLK_OSC_SYS,
-+                  JH7100_CLK_USBPHY_PLLDIV25M),
-+      JH7100__DIV(JH7100_CLK_AUDIO_DIV, "audio_div", 131072, JH7100_CLK_AUDIO_ROOT),
-+      JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
-+      JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
-+      JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
-+      JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
-+      JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
-+      JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
-+      JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
-+      JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
-+      JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
-+      JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
-+      JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
-+      JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
-+      JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
-+      JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
-+      JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
-+      JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
-+      JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
-+      JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
-+      JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
-+      JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
-+      JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
-+      JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
-+      JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
-+      JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
-+      JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
-+      JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
-+      JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
-+      JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
-+                  JH7100_CLK_GMAC_GTX,
-+                  JH7100_CLK_GMAC_TX_INV,
-+                  JH7100_CLK_GMAC_RMII_TX),
-+      JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
-+      JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
-+                  JH7100_CLK_GMAC_GR_MII_RX,
-+                  JH7100_CLK_GMAC_RMII_RX),
-+      JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
-+      JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
-+      JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
-+      JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
-+      JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
-+      JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
-+      JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
-+      JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
-+      JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
-+      JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
-+      JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
-+      JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
-+      JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
-+      JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
-+      JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
-+      JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
-+      JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
-+      JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-+      JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
-+      JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
-+      JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
-+};
-+
-+struct jh7100_clk {
-+      struct clk_hw hw;
-+      unsigned int idx;
-+      unsigned int max_div;
-+};
-+
-+struct jh7100_clk_priv {
-+      /* protect clk enable and set rate/parent from happening at the same time */
-+      spinlock_t rmw_lock;
-+      struct device *dev;
-+      void __iomem *base;
-+      struct clk_hw *pll[3];
-+      struct jh7100_clk reg[JH7100_CLK_PLL0_OUT];
-+};
-+
-+static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
-+{
-+      return container_of(hw, struct jh7100_clk, hw);
-+}
-+
-+static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
-+{
-+      return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
-+}
-+
-+static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
-+{
-+      struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
-+      void __iomem *reg = priv->base + 4 * clk->idx;
-+
-+      return readl_relaxed(reg);
-+}
-+
-+static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
-+{
-+      struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
-+      void __iomem *reg = priv->base + 4 * clk->idx;
-+      unsigned long flags;
-+
-+      spin_lock_irqsave(&priv->rmw_lock, flags);
-+      value |= readl_relaxed(reg) & ~mask;
-+      writel_relaxed(value, reg);
-+      spin_unlock_irqrestore(&priv->rmw_lock, flags);
-+}
-+
-+static int jh7100_clk_enable(struct clk_hw *hw)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+
-+      jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
-+      return 0;
-+}
-+
-+static void jh7100_clk_disable(struct clk_hw *hw)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+
-+      jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
-+}
-+
-+static int jh7100_clk_is_enabled(struct clk_hw *hw)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+
-+      return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
-+}
-+
-+static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
-+                                          unsigned long parent_rate)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+      u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
-+
-+      return div ? parent_rate / div : 0;
-+}
-+
-+static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk,
-+                                      unsigned long rate, unsigned long parent)
-+{
-+      unsigned long max = clk->max_div;
-+      unsigned long div = DIV_ROUND_UP(parent, rate);
-+
-+      return min(div, max);
-+}
-+
-+static int jh7100_clk_determine_rate(struct clk_hw *hw,
-+                                   struct clk_rate_request *req)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+      unsigned long parent = req->best_parent_rate;
-+      unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
-+      unsigned long div = jh7100_clk_bestdiv(clk, rate, parent);
-+      unsigned long result = parent / div;
-+
-+      /*
-+       * we want the result clamped by min_rate and max_rate if possible:
-+       * case 1: div hits the max divider value, which means it's less than
-+       * parent / rate, so the result is greater than rate and min_rate in
-+       * particular. we can't do anything about result > max_rate because the
-+       * divider doesn't go any further.
-+       * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
-+       * always lower or equal to rate and max_rate. however the result may
-+       * turn out lower than min_rate, but then the next higher rate is fine:
-+       *   div - 1 = ceil(parent / rate) - 1 < parent / rate
-+       * and thus
-+       *   min_rate <= rate < parent / (div - 1)
-+       */
-+      if (result < req->min_rate && div > 1)
-+              result = parent / (div - 1);
-+
-+      req->rate = result;
-+      return 0;
-+}
-+
-+static int jh7100_clk_set_rate(struct clk_hw *hw,
-+                             unsigned long rate,
-+                             unsigned long parent_rate)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+      unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate);
-+
-+      jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
-+      return 0;
-+}
-+
-+static u8 jh7100_clk_get_parent(struct clk_hw *hw)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+      u32 value = jh7100_clk_reg_get(clk);
-+
-+      return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
-+}
-+
-+static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+      u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
-+
-+      jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
-+      return 0;
-+}
-+
-+static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
-+                                       struct clk_rate_request *req)
-+{
-+      return clk_mux_determine_rate_flags(hw, req, 0);
-+}
-+
-+static int jh7100_clk_get_phase(struct clk_hw *hw)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+      u32 value = jh7100_clk_reg_get(clk);
-+
-+      return (value & JH7100_CLK_INVERT) ? 180 : 0;
-+}
-+
-+static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
-+{
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+      u32 value;
-+
-+      if (degrees == 0)
-+              value = 0;
-+      else if (degrees == 180)
-+              value = JH7100_CLK_INVERT;
-+      else
-+              return -EINVAL;
-+
-+      jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
-+      return 0;
-+}
-+
-+#ifdef CONFIG_DEBUG_FS
-+static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
-+{
-+      static const struct debugfs_reg32 jh7100_clk_reg = {
-+              .name = "CTRL",
-+              .offset = 0,
-+      };
-+      struct jh7100_clk *clk = jh7100_clk_from(hw);
-+      struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
-+      struct debugfs_regset32 *regset;
-+
-+      regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
-+      if (!regset)
-+              return;
-+
-+      regset->regs = &jh7100_clk_reg;
-+      regset->nregs = 1;
-+      regset->base = priv->base + 4 * clk->idx;
-+
-+      debugfs_create_regset32("registers", 0400, dentry, regset);
-+}
-+#else
-+#define jh7100_clk_debug_init NULL
-+#endif
-+
-+static const struct clk_ops jh7100_clk_gate_ops = {
-+      .enable = jh7100_clk_enable,
-+      .disable = jh7100_clk_disable,
-+      .is_enabled = jh7100_clk_is_enabled,
-+      .debug_init = jh7100_clk_debug_init,
-+};
-+
-+static const struct clk_ops jh7100_clk_div_ops = {
-+      .recalc_rate = jh7100_clk_recalc_rate,
-+      .determine_rate = jh7100_clk_determine_rate,
-+      .set_rate = jh7100_clk_set_rate,
-+      .debug_init = jh7100_clk_debug_init,
-+};
-+
-+static const struct clk_ops jh7100_clk_gdiv_ops = {
-+      .enable = jh7100_clk_enable,
-+      .disable = jh7100_clk_disable,
-+      .is_enabled = jh7100_clk_is_enabled,
-+      .recalc_rate = jh7100_clk_recalc_rate,
-+      .determine_rate = jh7100_clk_determine_rate,
-+      .set_rate = jh7100_clk_set_rate,
-+      .debug_init = jh7100_clk_debug_init,
-+};
-+
-+static const struct clk_ops jh7100_clk_mux_ops = {
-+      .determine_rate = jh7100_clk_mux_determine_rate,
-+      .set_parent = jh7100_clk_set_parent,
-+      .get_parent = jh7100_clk_get_parent,
-+      .debug_init = jh7100_clk_debug_init,
-+};
-+
-+static const struct clk_ops jh7100_clk_gmux_ops = {
-+      .enable = jh7100_clk_enable,
-+      .disable = jh7100_clk_disable,
-+      .is_enabled = jh7100_clk_is_enabled,
-+      .determine_rate = jh7100_clk_mux_determine_rate,
-+      .set_parent = jh7100_clk_set_parent,
-+      .get_parent = jh7100_clk_get_parent,
-+      .debug_init = jh7100_clk_debug_init,
-+};
-+
-+static const struct clk_ops jh7100_clk_inv_ops = {
-+      .get_phase = jh7100_clk_get_phase,
-+      .set_phase = jh7100_clk_set_phase,
-+      .debug_init = jh7100_clk_debug_init,
-+};
-+
-+static const struct clk_ops *__init jh7100_clk_ops(u32 max)
-+{
-+      if (max & JH7100_CLK_DIV_MASK) {
-+              if (max & JH7100_CLK_ENABLE)
-+                      return &jh7100_clk_gdiv_ops;
-+              return &jh7100_clk_div_ops;
-+      }
-+
-+      if (max & JH7100_CLK_MUX_MASK) {
-+              if (max & JH7100_CLK_ENABLE)
-+                      return &jh7100_clk_gmux_ops;
-+              return &jh7100_clk_mux_ops;
-+      }
-+
-+      if (max & JH7100_CLK_ENABLE)
-+              return &jh7100_clk_gate_ops;
-+
-+      return &jh7100_clk_inv_ops;
-+}
-+
-+static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
-+{
-+      struct jh7100_clk_priv *priv = data;
-+      unsigned int idx = clkspec->args[0];
-+
-+      if (idx < JH7100_CLK_PLL0_OUT)
-+              return &priv->reg[idx].hw;
-+
-+      if (idx < JH7100_CLK_END)
-+              return priv->pll[idx - JH7100_CLK_PLL0_OUT];
-+
-+      return ERR_PTR(-EINVAL);
-+}
-+
-+static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
-+{
-+      struct jh7100_clk_priv *priv;
-+      unsigned int idx;
-+      int ret;
-+
-+      priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+      if (!priv)
-+              return -ENOMEM;
-+
-+      spin_lock_init(&priv->rmw_lock);
-+      priv->dev = &pdev->dev;
-+      priv->base = devm_platform_ioremap_resource(pdev, 0);
-+      if (IS_ERR(priv->base))
-+              return PTR_ERR(priv->base);
-+
-+      priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
-+                                                       "osc_sys", 0, 40, 1);
-+      if (IS_ERR(priv->pll[0]))
-+              return PTR_ERR(priv->pll[0]);
-+
-+      priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
-+                                                       "osc_sys", 0, 64, 1);
-+      if (IS_ERR(priv->pll[1]))
-+              return PTR_ERR(priv->pll[1]);
-+
-+      priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
-+                                                       "pll2_refclk", 0, 55, 1);
-+      if (IS_ERR(priv->pll[2]))
-+              return PTR_ERR(priv->pll[2]);
-+
-+      for (idx = 0; idx < JH7100_CLK_PLL0_OUT; idx++) {
-+              u32 max = jh7100_clk_data[idx].max;
-+              struct clk_parent_data parents[4] = {};
-+              struct clk_init_data init = {
-+                      .name = jh7100_clk_data[idx].name,
-+                      .ops = jh7100_clk_ops(max),
-+                      .parent_data = parents,
-+                      .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
-+                      .flags = jh7100_clk_data[idx].flags,
-+              };
-+              struct jh7100_clk *clk = &priv->reg[idx];
-+              unsigned int i;
-+
-+              for (i = 0; i < init.num_parents; i++) {
-+                      unsigned int pidx = jh7100_clk_data[idx].parents[i];
-+
-+                      if (pidx < JH7100_CLK_PLL0_OUT)
-+                              parents[i].hw = &priv->reg[pidx].hw;
-+                      else if (pidx < JH7100_CLK_END)
-+                              parents[i].hw = priv->pll[pidx - JH7100_CLK_PLL0_OUT];
-+                      else if (pidx == JH7100_CLK_OSC_SYS)
-+                              parents[i].fw_name = "osc_sys";
-+                      else if (pidx == JH7100_CLK_OSC_AUD)
-+                              parents[i].fw_name = "osc_aud";
-+                      else if (pidx == JH7100_CLK_GMAC_RMII_REF)
-+                              parents[i].fw_name = "gmac_rmii_ref";
-+                      else if (pidx == JH7100_CLK_GMAC_GR_MII_RX)
-+                              parents[i].fw_name = "gmac_gr_mii_rxclk";
-+              }
-+
-+              clk->hw.init = &init;
-+              clk->idx = idx;
-+              clk->max_div = max & JH7100_CLK_DIV_MASK;
-+
-+              ret = devm_clk_hw_register(priv->dev, &clk->hw);
-+              if (ret)
-+                      return ret;
-+      }
-+
-+      return devm_of_clk_add_hw_provider(priv->dev, jh7100_clk_get, priv);
-+}
-+
-+static const struct of_device_id clk_starfive_jh7100_match[] = {
-+      { .compatible = "starfive,jh7100-clkgen" },
-+      { /* sentinel */ }
-+};
-+
-+static struct platform_driver clk_starfive_jh7100_driver = {
-+      .driver = {
-+              .name = "clk-starfive-jh7100",
-+              .of_match_table = clk_starfive_jh7100_match,
-+              .suppress_bind_attrs = true,
-+      },
-+};
-+builtin_platform_driver_probe(clk_starfive_jh7100_driver, clk_starfive_jh7100_probe);

diff --git a/target/linux/visionfive/patches-5.15/0006-dmaengine-dw-axi-dmac-Fix-uninitialized-variable-in-.patch b/target/linux/visionfive/patches-5.15/0006-dmaengine-dw-axi-dmac-Fix-uninitialized-variable-in-.patch
new file mode 100644 (file)
index 0000000..283f88a
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0006-dmaengine-dw-axi-dmac-Fix-uninitialized-variable-in-.patch
@@ -0,0 +1,51 @@
+From 851a492a509a6ff8cf64d8a4f0148f7db4e7d8fd Mon Sep 17 00:00:00 2001
+From: Tim Gardner <tim.gardner@canonical.com>
+Date: Mon, 25 Oct 2021 12:16:56 -0600
+Subject: [PATCH 06/84] dmaengine: dw-axi-dmac: Fix uninitialized variable in
+ axi_chan_block_xfer_start()
+
+commit 885633075847f475f26a29249d772cc0da85d8cd upstream.
+
+Coverity complains of an uninitialized variable:
+
+5. uninit_use_in_call: Using uninitialized value config.dst_per when calling axi_chan_config_write. [show details]
+6. uninit_use_in_call: Using uninitialized value config.hs_sel_src when calling axi_chan_config_write. [show details]
+CID 121164 (#1-3 of 3): Uninitialized scalar variable (UNINIT)
+7. uninit_use_in_call: Using uninitialized value config.src_per when calling axi_chan_config_write. [show details]
+418        axi_chan_config_write(chan, &config);
+
+Fix this by initializing the structure to 0 which should at least be benign in axi_chan_config_write(). Also fix
+what looks like a cut-n-paste error when initializing config.hs_sel_dst.
+
+Fixes: 824351668a413 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8")
+Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+Cc: Vinod Koul <vkoul@kernel.org>
+Cc: dmaengine@vger.kernel.org
+Cc: linux-kernel@vger.kernel.org
+Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
+Link: https://lore.kernel.org/r/20211025181656.31658-1-tim.gardner@canonical.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+@@ -373,7 +373,7 @@ static void axi_chan_block_xfer_start(st
+                                     struct axi_dma_desc *first)
+ {
+       u32 priority = chan->chip->dw->hdata->priority[chan->id];
+-      struct axi_dma_chan_config config;
++      struct axi_dma_chan_config config = {};
+       u32 irq_mask;
+       u8 lms = 0; /* Select AXI0 master for LLI fetching */
+ 
+@@ -391,7 +391,7 @@ static void axi_chan_block_xfer_start(st
+       config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC;
+       config.prior = priority;
+       config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW;
+-      config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW;
++      config.hs_sel_src = DWAXIDMAC_HS_SEL_HW;
+       switch (chan->direction) {
+       case DMA_MEM_TO_DEV:
+               dw_axi_dma_set_byte_halfword(chan, true);

diff --git a/target/linux/visionfive/patches-5.15/0007-RISC-V-Add-StarFive-SoC-Kconfig-option.patch b/target/linux/visionfive/patches-5.15/0007-RISC-V-Add-StarFive-SoC-Kconfig-option.patch
new file mode 100644 (file)
index 0000000..482514c
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0007-RISC-V-Add-StarFive-SoC-Kconfig-option.patch
@@ -0,0 +1,35 @@
+From 7938cac5884184d441d9a469cb085a7122c04922 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 16:10:32 +0200
+Subject: [PATCH 07/84] RISC-V: Add StarFive SoC Kconfig option
+
+commit 3d24568b01c5a7a9e88f73f917477b60edb35bfe upstream.
+
+Add StarFive Kconfig option to select SoC specific and common drivers
+required for these SoCs. Select subsystems required to boot so the
+required drivers gets enabled by default.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/Kconfig.socs | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/riscv/Kconfig.socs
++++ b/arch/riscv/Kconfig.socs
+@@ -19,6 +19,14 @@ config SOC_SIFIVE
+       help
+         This enables support for SiFive SoC platform hardware.
+ 
++config SOC_STARFIVE
++      bool "StarFive SoCs"
++      select PINCTRL
++      select RESET_CONTROLLER
++      select SIFIVE_PLIC
++      help
++        This enables support for StarFive SoC platform hardware.
++
+ config SOC_VIRT
+       bool "QEMU Virt Machine"
+       select CLINT_TIMER if RISCV_M_MODE

diff --git a/target/linux/visionfive/patches-5.15/0007-dt-bindings-reset-Add-StarFive-JH7100-reset-definiti.patch b/target/linux/visionfive/patches-5.15/0007-dt-bindings-reset-Add-StarFive-JH7100-reset-definiti.patch
deleted file mode 100644 (file)
index e9691fd..0000000
--- a/target/linux/visionfive/patches-5.15/0007-dt-bindings-reset-Add-StarFive-JH7100-reset-definiti.patch
+++ /dev/null
@@ -1,148 +0,0 @@
-From 810e287e83b69ff8563bde15cae9120c802ac5d7 Mon Sep 17 00:00:00 2001
-From: Geert Uytterhoeven <geert@linux-m68k.org>
-Date: Fri, 25 Jun 2021 11:30:00 +0200
-Subject: [PATCH 07/16] dt-bindings: reset: Add StarFive JH7100 reset
- definitions
-
-Add all resets for the StarFive JH7100 reset controller.
-
-Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
-to all definitions.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- include/dt-bindings/reset/starfive-jh7100.h | 126 ++++++++++++++++++++
- 1 file changed, 126 insertions(+)
- create mode 100644 include/dt-bindings/reset/starfive-jh7100.h
-
---- /dev/null
-+++ b/include/dt-bindings/reset/starfive-jh7100.h
-@@ -0,0 +1,126 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
-+ */
-+
-+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
-+#define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
-+
-+#define JH7100_RSTN_DOM3AHB_BUS               0
-+#define JH7100_RSTN_DOM7AHB_BUS               1
-+#define JH7100_RST_U74                        2
-+#define JH7100_RSTN_U74_AXI           3
-+#define JH7100_RSTN_SGDMA2P_AHB               4
-+#define JH7100_RSTN_SGDMA2P_AXI               5
-+#define JH7100_RSTN_DMA2PNOC_AXI      6
-+#define JH7100_RSTN_DLA_AXI           7
-+#define JH7100_RSTN_DLANOC_AXI                8
-+#define JH7100_RSTN_DLA_APB           9
-+#define JH7100_RST_VP6_DRESET         10
-+#define JH7100_RST_VP6_BRESET         11
-+#define JH7100_RSTN_VP6_AXI           12
-+#define JH7100_RSTN_VDECBRG_MAIN      13
-+#define JH7100_RSTN_VDEC_AXI          14
-+#define JH7100_RSTN_VDEC_BCLK         15
-+#define JH7100_RSTN_VDEC_CCLK         16
-+#define JH7100_RSTN_VDEC_APB          17
-+#define JH7100_RSTN_JPEG_AXI          18
-+#define JH7100_RSTN_JPEG_CCLK         19
-+#define JH7100_RSTN_JPEG_APB          20
-+#define JH7100_RSTN_JPCGC300_MAIN     21
-+#define JH7100_RSTN_GC300_2X          22
-+#define JH7100_RSTN_GC300_AXI         23
-+#define JH7100_RSTN_GC300_AHB         24
-+#define JH7100_RSTN_VENC_AXI          25
-+#define JH7100_RSTN_VENCBRG_MAIN      26
-+#define JH7100_RSTN_VENC_BCLK         27
-+#define JH7100_RSTN_VENC_CCLK         28
-+#define JH7100_RSTN_VENC_APB          29
-+#define JH7100_RSTN_DDRPHY_APB                30
-+#define JH7100_RSTN_NOC_ROB           31
-+#define JH7100_RSTN_NOC_COG           32
-+#define JH7100_RSTN_HIFI4_AXI         33
-+#define JH7100_RSTN_HIFI4NOC_AXI      34
-+#define JH7100_RST_HIFI4_DRESET               35
-+#define JH7100_RST_HIFI4_BRESET               36
-+#define JH7100_RSTN_USB_AXI           37
-+#define JH7100_RSTN_USBNOC_AXI                38
-+#define JH7100_RSTN_SGDMA1P_AXI               39
-+#define JH7100_RSTN_DMA1P_AXI         40
-+#define JH7100_RSTN_X2C_AXI           41
-+#define JH7100_RSTN_NNE_AHB           42
-+#define JH7100_RSTN_NNE_AXI           43
-+#define JH7100_RSTN_NNENOC_AXI                44
-+#define JH7100_RSTN_DLASLV_AXI                45
-+#define JH7100_RSTN_DSPX2C_AXI                46
-+#define JH7100_RSTN_VIN_SRC           47
-+#define JH7100_RSTN_ISPSLV_AXI                48
-+#define JH7100_RSTN_VIN_AXI           49
-+#define JH7100_RSTN_VINNOC_AXI                50
-+#define JH7100_RSTN_ISP0_AXI          51
-+#define JH7100_RSTN_ISP0NOC_AXI               52
-+#define JH7100_RSTN_ISP1_AXI          53
-+#define JH7100_RSTN_ISP1NOC_AXI               54
-+#define JH7100_RSTN_VOUT_SRC          55
-+#define JH7100_RSTN_DISP_AXI          56
-+#define JH7100_RSTN_DISPNOC_AXI               57
-+#define JH7100_RSTN_SDIO0_AHB         58
-+#define JH7100_RSTN_SDIO1_AHB         59
-+#define JH7100_RSTN_GMAC_AHB          60
-+#define JH7100_RSTN_SPI2AHB_AHB               61
-+#define JH7100_RSTN_SPI2AHB_CORE      62
-+#define JH7100_RSTN_EZMASTER_AHB      63
-+#define JH7100_RST_E24                        64
-+#define JH7100_RSTN_QSPI_AHB          65
-+#define JH7100_RSTN_QSPI_CORE         66
-+#define JH7100_RSTN_QSPI_APB          67
-+#define JH7100_RSTN_SEC_AHB           68
-+#define JH7100_RSTN_AES                       69
-+#define JH7100_RSTN_PKA                       70
-+#define JH7100_RSTN_SHA                       71
-+#define JH7100_RSTN_TRNG_APB          72
-+#define JH7100_RSTN_OTP_APB           73
-+#define JH7100_RSTN_UART0_APB         74
-+#define JH7100_RSTN_UART0_CORE                75
-+#define JH7100_RSTN_UART1_APB         76
-+#define JH7100_RSTN_UART1_CORE                77
-+#define JH7100_RSTN_SPI0_APB          78
-+#define JH7100_RSTN_SPI0_CORE         79
-+#define JH7100_RSTN_SPI1_APB          80
-+#define JH7100_RSTN_SPI1_CORE         81
-+#define JH7100_RSTN_I2C0_APB          82
-+#define JH7100_RSTN_I2C0_CORE         83
-+#define JH7100_RSTN_I2C1_APB          84
-+#define JH7100_RSTN_I2C1_CORE         85
-+#define JH7100_RSTN_GPIO_APB          86
-+#define JH7100_RSTN_UART2_APB         87
-+#define JH7100_RSTN_UART2_CORE                88
-+#define JH7100_RSTN_UART3_APB         89
-+#define JH7100_RSTN_UART3_CORE                90
-+#define JH7100_RSTN_SPI2_APB          91
-+#define JH7100_RSTN_SPI2_CORE         92
-+#define JH7100_RSTN_SPI3_APB          93
-+#define JH7100_RSTN_SPI3_CORE         94
-+#define JH7100_RSTN_I2C2_APB          95
-+#define JH7100_RSTN_I2C2_CORE         96
-+#define JH7100_RSTN_I2C3_APB          97
-+#define JH7100_RSTN_I2C3_CORE         98
-+#define JH7100_RSTN_WDTIMER_APB               99
-+#define JH7100_RSTN_WDT                       100
-+#define JH7100_RSTN_TIMER0            101
-+#define JH7100_RSTN_TIMER1            102
-+#define JH7100_RSTN_TIMER2            103
-+#define JH7100_RSTN_TIMER3            104
-+#define JH7100_RSTN_TIMER4            105
-+#define JH7100_RSTN_TIMER5            106
-+#define JH7100_RSTN_TIMER6            107
-+#define JH7100_RSTN_VP6INTC_APB               108
-+#define JH7100_RSTN_PWM_APB           109
-+#define JH7100_RSTN_MSI_APB           110
-+#define JH7100_RSTN_TEMP_APB          111
-+#define JH7100_RSTN_TEMP_SENSE                112
-+#define JH7100_RSTN_SYSERR_APB                113
-+
-+#define JH7100_RSTN_END                       114
-+
-+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */

diff --git a/target/linux/visionfive/patches-5.15/0008-dt-bindings-reset-Add-Starfive-JH7100-reset-bindings.patch b/target/linux/visionfive/patches-5.15/0008-dt-bindings-reset-Add-Starfive-JH7100-reset-bindings.patch
deleted file mode 100644 (file)
index f607652..0000000
--- a/target/linux/visionfive/patches-5.15/0008-dt-bindings-reset-Add-Starfive-JH7100-reset-bindings.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From d7d456a5201d2e707318bbdc4fb69a3407eed29e Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sun, 19 Sep 2021 14:34:34 +0200
-Subject: [PATCH 08/16] dt-bindings: reset: Add Starfive JH7100 reset bindings
-
-Add bindings for the reset controller on the JH7100 RISC-V SoC by
-StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
-
-Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- .../bindings/reset/starfive,jh7100-reset.yaml | 38 +++++++++++++++++++
- 1 file changed, 38 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
-@@ -0,0 +1,38 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: StarFive JH7100 SoC Reset Controller Device Tree Bindings
-+
-+maintainers:
-+  - Emil Renner Berthing <kernel@esmil.dk>
-+
-+properties:
-+  compatible:
-+    enum:
-+      - starfive,jh7100-reset
-+
-+  reg:
-+    maxItems: 1
-+
-+  "#reset-cells":
-+    const: 1
-+
-+required:
-+  - compatible
-+  - reg
-+  - "#reset-cells"
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    reset-controller@11840000 {
-+        compatible = "starfive,jh7100-reset";
-+        reg = <0x11840000 0x10000>;
-+        #reset-cells = <1>;
-+    };
-+
-+...

diff --git a/target/linux/visionfive/patches-5.15/0008-dt-bindings-timer-Add-StarFive-JH7100-clint.patch b/target/linux/visionfive/patches-5.15/0008-dt-bindings-timer-Add-StarFive-JH7100-clint.patch
new file mode 100644 (file)
index 0000000..f9d3f99
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0008-dt-bindings-timer-Add-StarFive-JH7100-clint.patch
@@ -0,0 +1,26 @@
+From 22af1072a98f163008d8084c35425cddb6069372 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 16:48:27 +0200
+Subject: [PATCH 08/84] dt-bindings: timer: Add StarFive JH7100 clint
+
+commit 3234d3a1374308615c0cde5e83e52f6b644eaf53 upstream.
+
+Add compatible string for the StarFive JH7100 clint.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
++++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+@@ -25,6 +25,7 @@ properties:
+     items:
+       - enum:
+           - sifive,fu540-c000-clint
++          - starfive,jh7100-clint
+           - canaan,k210-clint
+       - const: sifive,clint0
+ 

diff --git a/target/linux/visionfive/patches-5.15/0009-dt-bindings-interrupt-controller-Add-StarFive-JH7100.patch b/target/linux/visionfive/patches-5.15/0009-dt-bindings-interrupt-controller-Add-StarFive-JH7100.patch
new file mode 100644 (file)
index 0000000..4e96758
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0009-dt-bindings-interrupt-controller-Add-StarFive-JH7100.patch
@@ -0,0 +1,27 @@
+From d9a77deebb3620428ddbf97738275ce74cee22ee Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 16:48:27 +0200
+Subject: [PATCH 09/84] dt-bindings: interrupt-controller: Add StarFive JH7100
+ plic
+
+commit 9ac16169b4d4359d3832669bf06aab9e51184828 upstream.
+
+Add compatible string for StarFive JH7100 plic.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
++++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+@@ -45,6 +45,7 @@ properties:
+     items:
+       - enum:
+           - sifive,fu540-c000-plic
++          - starfive,jh7100-plic
+           - canaan,k210-plic
+       - const: sifive,plic-1.0.0
+ 

diff --git a/target/linux/visionfive/patches-5.15/0009-reset-starfive-jh7100-Add-StarFive-JH7100-reset-driv.patch b/target/linux/visionfive/patches-5.15/0009-reset-starfive-jh7100-Add-StarFive-JH7100-reset-driv.patch
deleted file mode 100644 (file)
index c130683..0000000
--- a/target/linux/visionfive/patches-5.15/0009-reset-starfive-jh7100-Add-StarFive-JH7100-reset-driv.patch
+++ /dev/null
@@ -1,235 +0,0 @@
-From 0be3a1595bf8c7f39153be02c9aae61dd2108576 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sun, 19 Sep 2021 14:21:05 +0200
-Subject: [PATCH 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset
- driver
-
-Add a driver for the StarFive JH7100 reset controller.
-
-Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- MAINTAINERS                           |   7 ++
- drivers/reset/Kconfig                 |   7 ++
- drivers/reset/Makefile                |   1 +
- drivers/reset/reset-starfive-jh7100.c | 172 ++++++++++++++++++++++++++
- 4 files changed, 187 insertions(+)
- create mode 100644 drivers/reset/reset-starfive-jh7100.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -17867,6 +17867,13 @@ F:    Documentation/devicetree/bindings/clo
- F:    drivers/clk/starfive/clk-starfive-jh7100.c
- F:    include/dt-bindings/clock/starfive-jh7100.h
- 
-+STARFIVE JH7100 RESET CONTROLLER DRIVER
-+M:    Emil Renner Berthing <kernel@esmil.dk>
-+S:    Maintained
-+F:    Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
-+F:    drivers/reset/reset-starfive-jh7100.c
-+F:    include/dt-bindings/reset/starfive-jh7100.h
-+
- STATIC BRANCH/CALL
- M:    Peter Zijlstra <peterz@infradead.org>
- M:    Josh Poimboeuf <jpoimboe@redhat.com>
---- a/drivers/reset/Kconfig
-+++ b/drivers/reset/Kconfig
-@@ -224,6 +224,13 @@ config RESET_SOCFPGA
-         This enables the reset driver for the SoCFPGA ARMv7 platforms. This
-         driver gets initialized early during platform init calls.
- 
-+config RESET_STARFIVE_JH7100
-+      bool "StarFive JH7100 Reset Driver"
-+      depends on SOC_STARFIVE || COMPILE_TEST
-+      default SOC_STARFIVE
-+      help
-+        This enables the reset controller driver for the StarFive JH7100 SoC.
-+
- config RESET_SUNXI
-       bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
-       default ARCH_SUNXI
---- a/drivers/reset/Makefile
-+++ b/drivers/reset/Makefile
-@@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) +=
- obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
- obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
- obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
-+obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
- obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
- obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
- obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
---- /dev/null
-+++ b/drivers/reset/reset-starfive-jh7100.c
-@@ -0,0 +1,172 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later
-+/*
-+ * Reset driver for the StarFive JH7100 SoC
-+ *
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+#include <linux/bitmap.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset-controller.h>
-+#include <linux/spinlock.h>
-+
-+#include <dt-bindings/reset/starfive-jh7100.h>
-+
-+/* register offsets */
-+#define JH7100_RESET_ASSERT0  0x00
-+#define JH7100_RESET_ASSERT1  0x04
-+#define JH7100_RESET_ASSERT2  0x08
-+#define JH7100_RESET_ASSERT3  0x0c
-+#define JH7100_RESET_STATUS0  0x10
-+#define JH7100_RESET_STATUS1  0x14
-+#define JH7100_RESET_STATUS2  0x18
-+#define JH7100_RESET_STATUS3  0x1c
-+
-+/*
-+ * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
-+ * line 32m + n, and writing a 0 deasserts the same line.
-+ * Most reset lines have their status inverted so a 0 bit in the STATUS
-+ * register means the line is asserted and a 1 means it's deasserted. A few
-+ * lines don't though, so store the expected value of the status registers when
-+ * all lines are asserted.
-+ */
-+static const u64 jh7100_reset_asserted[2] = {
-+      /* STATUS0 */
-+      BIT_ULL_MASK(JH7100_RST_U74) |
-+      BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
-+      BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
-+      /* STATUS1 */
-+      BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
-+      BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
-+      /* STATUS2 */
-+      BIT_ULL_MASK(JH7100_RST_E24) |
-+      /* STATUS3 */
-+      0,
-+};
-+
-+struct jh7100_reset {
-+      struct reset_controller_dev rcdev;
-+      /* protect registers against concurrent read-modify-write */
-+      spinlock_t lock;
-+      void __iomem *base;
-+};
-+
-+static inline struct jh7100_reset *
-+jh7100_reset_from(struct reset_controller_dev *rcdev)
-+{
-+      return container_of(rcdev, struct jh7100_reset, rcdev);
-+}
-+
-+static int jh7100_reset_update(struct reset_controller_dev *rcdev,
-+                             unsigned long id, bool assert)
-+{
-+      struct jh7100_reset *data = jh7100_reset_from(rcdev);
-+      unsigned long offset = BIT_ULL_WORD(id);
-+      u64 mask = BIT_ULL_MASK(id);
-+      void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
-+      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
-+      u64 done = jh7100_reset_asserted[offset] & mask;
-+      u64 value;
-+      unsigned long flags;
-+      int ret;
-+
-+      if (!assert)
-+              done ^= mask;
-+
-+      spin_lock_irqsave(&data->lock, flags);
-+
-+      value = readq(reg_assert);
-+      if (assert)
-+              value |= mask;
-+      else
-+              value &= ~mask;
-+      writeq(value, reg_assert);
-+
-+      /* if the associated clock is gated, deasserting might otherwise hang forever */
-+      ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
-+
-+      spin_unlock_irqrestore(&data->lock, flags);
-+      return ret;
-+}
-+
-+static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
-+                             unsigned long id)
-+{
-+      return jh7100_reset_update(rcdev, id, true);
-+}
-+
-+static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
-+                               unsigned long id)
-+{
-+      return jh7100_reset_update(rcdev, id, false);
-+}
-+
-+static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
-+                            unsigned long id)
-+{
-+      int ret;
-+
-+      ret = jh7100_reset_assert(rcdev, id);
-+      if (ret)
-+              return ret;
-+
-+      return jh7100_reset_deassert(rcdev, id);
-+}
-+
-+static int jh7100_reset_status(struct reset_controller_dev *rcdev,
-+                             unsigned long id)
-+{
-+      struct jh7100_reset *data = jh7100_reset_from(rcdev);
-+      unsigned long offset = BIT_ULL_WORD(id);
-+      u64 mask = BIT_ULL_MASK(id);
-+      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
-+      u64 value = readq(reg_status);
-+
-+      return !((value ^ jh7100_reset_asserted[offset]) & mask);
-+}
-+
-+static const struct reset_control_ops jh7100_reset_ops = {
-+      .assert         = jh7100_reset_assert,
-+      .deassert       = jh7100_reset_deassert,
-+      .reset          = jh7100_reset_reset,
-+      .status         = jh7100_reset_status,
-+};
-+
-+static int __init jh7100_reset_probe(struct platform_device *pdev)
-+{
-+      struct jh7100_reset *data;
-+
-+      data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
-+      if (!data)
-+              return -ENOMEM;
-+
-+      data->base = devm_platform_ioremap_resource(pdev, 0);
-+      if (IS_ERR(data->base))
-+              return PTR_ERR(data->base);
-+
-+      data->rcdev.ops = &jh7100_reset_ops;
-+      data->rcdev.owner = THIS_MODULE;
-+      data->rcdev.nr_resets = JH7100_RSTN_END;
-+      data->rcdev.dev = &pdev->dev;
-+      data->rcdev.of_node = pdev->dev.of_node;
-+      spin_lock_init(&data->lock);
-+
-+      return devm_reset_controller_register(&pdev->dev, &data->rcdev);
-+}
-+
-+static const struct of_device_id jh7100_reset_dt_ids[] = {
-+      { .compatible = "starfive,jh7100-reset" },
-+      { /* sentinel */ }
-+};
-+
-+static struct platform_driver jh7100_reset_driver = {
-+      .driver = {
-+              .name = "jh7100-reset",
-+              .of_match_table = jh7100_reset_dt_ids,
-+              .suppress_bind_attrs = true,
-+      },
-+};
-+builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);

diff --git a/target/linux/visionfive/patches-5.15/0010-dt-bindings-clock-starfive-Add-JH7100-clock-definiti.patch b/target/linux/visionfive/patches-5.15/0010-dt-bindings-clock-starfive-Add-JH7100-clock-definiti.patch
new file mode 100644 (file)
index 0000000..6d80f0a
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0010-dt-bindings-clock-starfive-Add-JH7100-clock-definiti.patch
@@ -0,0 +1,227 @@
+From f08d090b11b517dc82189a69bcb805ade1abf2cc Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Fri, 25 Jun 2021 11:29:51 +0200
+Subject: [PATCH 10/84] dt-bindings: clock: starfive: Add JH7100 clock
+ definitions
+
+commit 38bb8a7264daf0ff5bb3024ae94bc465de78203d upstream.
+
+Add all clock outputs for the StarFive JH7100 clock generator.
+
+Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
+to all definitions.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ include/dt-bindings/clock/starfive-jh7100.h | 202 ++++++++++++++++++++
+ 1 file changed, 202 insertions(+)
+ create mode 100644 include/dt-bindings/clock/starfive-jh7100.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/starfive-jh7100.h
+@@ -0,0 +1,202 @@
++/* SPDX-License-Identifier: GPL-2.0 OR MIT */
++/*
++ * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
++ */
++
++#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
++#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
++
++#define JH7100_CLK_CPUNDBUS_ROOT      0
++#define JH7100_CLK_DLA_ROOT           1
++#define JH7100_CLK_DSP_ROOT           2
++#define JH7100_CLK_GMACUSB_ROOT               3
++#define JH7100_CLK_PERH0_ROOT         4
++#define JH7100_CLK_PERH1_ROOT         5
++#define JH7100_CLK_VIN_ROOT           6
++#define JH7100_CLK_VOUT_ROOT          7
++#define JH7100_CLK_AUDIO_ROOT         8
++#define JH7100_CLK_CDECHIFI4_ROOT     9
++#define JH7100_CLK_CDEC_ROOT          10
++#define JH7100_CLK_VOUTBUS_ROOT               11
++#define JH7100_CLK_CPUNBUS_ROOT_DIV   12
++#define JH7100_CLK_DSP_ROOT_DIV               13
++#define JH7100_CLK_PERH0_SRC          14
++#define JH7100_CLK_PERH1_SRC          15
++#define JH7100_CLK_PLL0_TESTOUT               16
++#define JH7100_CLK_PLL1_TESTOUT               17
++#define JH7100_CLK_PLL2_TESTOUT               18
++#define JH7100_CLK_PLL2_REF           19
++#define JH7100_CLK_CPU_CORE           20
++#define JH7100_CLK_CPU_AXI            21
++#define JH7100_CLK_AHB_BUS            22
++#define JH7100_CLK_APB1_BUS           23
++#define JH7100_CLK_APB2_BUS           24
++#define JH7100_CLK_DOM3AHB_BUS                25
++#define JH7100_CLK_DOM7AHB_BUS                26
++#define JH7100_CLK_U74_CORE0          27
++#define JH7100_CLK_U74_CORE1          28
++#define JH7100_CLK_U74_AXI            29
++#define JH7100_CLK_U74RTC_TOGGLE      30
++#define JH7100_CLK_SGDMA2P_AXI                31
++#define JH7100_CLK_DMA2PNOC_AXI               32
++#define JH7100_CLK_SGDMA2P_AHB                33
++#define JH7100_CLK_DLA_BUS            34
++#define JH7100_CLK_DLA_AXI            35
++#define JH7100_CLK_DLANOC_AXI         36
++#define JH7100_CLK_DLA_APB            37
++#define JH7100_CLK_VP6_CORE           38
++#define JH7100_CLK_VP6BUS_SRC         39
++#define JH7100_CLK_VP6_AXI            40
++#define JH7100_CLK_VCDECBUS_SRC               41
++#define JH7100_CLK_VDEC_BUS           42
++#define JH7100_CLK_VDEC_AXI           43
++#define JH7100_CLK_VDECBRG_MAIN               44
++#define JH7100_CLK_VDEC_BCLK          45
++#define JH7100_CLK_VDEC_CCLK          46
++#define JH7100_CLK_VDEC_APB           47
++#define JH7100_CLK_JPEG_AXI           48
++#define JH7100_CLK_JPEG_CCLK          49
++#define JH7100_CLK_JPEG_APB           50
++#define JH7100_CLK_GC300_2X           51
++#define JH7100_CLK_GC300_AHB          52
++#define JH7100_CLK_JPCGC300_AXIBUS    53
++#define JH7100_CLK_GC300_AXI          54
++#define JH7100_CLK_JPCGC300_MAIN      55
++#define JH7100_CLK_VENC_BUS           56
++#define JH7100_CLK_VENC_AXI           57
++#define JH7100_CLK_VENCBRG_MAIN               58
++#define JH7100_CLK_VENC_BCLK          59
++#define JH7100_CLK_VENC_CCLK          60
++#define JH7100_CLK_VENC_APB           61
++#define JH7100_CLK_DDRPLL_DIV2                62
++#define JH7100_CLK_DDRPLL_DIV4                63
++#define JH7100_CLK_DDRPLL_DIV8                64
++#define JH7100_CLK_DDROSC_DIV2                65
++#define JH7100_CLK_DDRC0              66
++#define JH7100_CLK_DDRC1              67
++#define JH7100_CLK_DDRPHY_APB         68
++#define JH7100_CLK_NOC_ROB            69
++#define JH7100_CLK_NOC_COG            70
++#define JH7100_CLK_NNE_AHB            71
++#define JH7100_CLK_NNEBUS_SRC1                72
++#define JH7100_CLK_NNE_BUS            73
++#define JH7100_CLK_NNE_AXI            74
++#define JH7100_CLK_NNENOC_AXI         75
++#define JH7100_CLK_DLASLV_AXI         76
++#define JH7100_CLK_DSPX2C_AXI         77
++#define JH7100_CLK_HIFI4_SRC          78
++#define JH7100_CLK_HIFI4_COREFREE     79
++#define JH7100_CLK_HIFI4_CORE         80
++#define JH7100_CLK_HIFI4_BUS          81
++#define JH7100_CLK_HIFI4_AXI          82
++#define JH7100_CLK_HIFI4NOC_AXI               83
++#define JH7100_CLK_SGDMA1P_BUS                84
++#define JH7100_CLK_SGDMA1P_AXI                85
++#define JH7100_CLK_DMA1P_AXI          86
++#define JH7100_CLK_X2C_AXI            87
++#define JH7100_CLK_USB_BUS            88
++#define JH7100_CLK_USB_AXI            89
++#define JH7100_CLK_USBNOC_AXI         90
++#define JH7100_CLK_USBPHY_ROOTDIV     91
++#define JH7100_CLK_USBPHY_125M                92
++#define JH7100_CLK_USBPHY_PLLDIV25M   93
++#define JH7100_CLK_USBPHY_25M         94
++#define JH7100_CLK_AUDIO_DIV          95
++#define JH7100_CLK_AUDIO_SRC          96
++#define JH7100_CLK_AUDIO_12288                97
++#define JH7100_CLK_VIN_SRC            98
++#define JH7100_CLK_ISP0_BUS           99
++#define JH7100_CLK_ISP0_AXI           100
++#define JH7100_CLK_ISP0NOC_AXI                101
++#define JH7100_CLK_ISPSLV_AXI         102
++#define JH7100_CLK_ISP1_BUS           103
++#define JH7100_CLK_ISP1_AXI           104
++#define JH7100_CLK_ISP1NOC_AXI                105
++#define JH7100_CLK_VIN_BUS            106
++#define JH7100_CLK_VIN_AXI            107
++#define JH7100_CLK_VINNOC_AXI         108
++#define JH7100_CLK_VOUT_SRC           109
++#define JH7100_CLK_DISPBUS_SRC                110
++#define JH7100_CLK_DISP_BUS           111
++#define JH7100_CLK_DISP_AXI           112
++#define JH7100_CLK_DISPNOC_AXI                113
++#define JH7100_CLK_SDIO0_AHB          114
++#define JH7100_CLK_SDIO0_CCLKINT      115
++#define JH7100_CLK_SDIO0_CCLKINT_INV  116
++#define JH7100_CLK_SDIO1_AHB          117
++#define JH7100_CLK_SDIO1_CCLKINT      118
++#define JH7100_CLK_SDIO1_CCLKINT_INV  119
++#define JH7100_CLK_GMAC_AHB           120
++#define JH7100_CLK_GMAC_ROOT_DIV      121
++#define JH7100_CLK_GMAC_PTP_REF               122
++#define JH7100_CLK_GMAC_GTX           123
++#define JH7100_CLK_GMAC_RMII_TX               124
++#define JH7100_CLK_GMAC_RMII_RX               125
++#define JH7100_CLK_GMAC_TX            126
++#define JH7100_CLK_GMAC_TX_INV                127
++#define JH7100_CLK_GMAC_RX_PRE                128
++#define JH7100_CLK_GMAC_RX_INV                129
++#define JH7100_CLK_GMAC_RMII          130
++#define JH7100_CLK_GMAC_TOPHYREF      131
++#define JH7100_CLK_SPI2AHB_AHB                132
++#define JH7100_CLK_SPI2AHB_CORE               133
++#define JH7100_CLK_EZMASTER_AHB               134
++#define JH7100_CLK_E24_AHB            135
++#define JH7100_CLK_E24RTC_TOGGLE      136
++#define JH7100_CLK_QSPI_AHB           137
++#define JH7100_CLK_QSPI_APB           138
++#define JH7100_CLK_QSPI_REF           139
++#define JH7100_CLK_SEC_AHB            140
++#define JH7100_CLK_AES                        141
++#define JH7100_CLK_SHA                        142
++#define JH7100_CLK_PKA                        143
++#define JH7100_CLK_TRNG_APB           144
++#define JH7100_CLK_OTP_APB            145
++#define JH7100_CLK_UART0_APB          146
++#define JH7100_CLK_UART0_CORE         147
++#define JH7100_CLK_UART1_APB          148
++#define JH7100_CLK_UART1_CORE         149
++#define JH7100_CLK_SPI0_APB           150
++#define JH7100_CLK_SPI0_CORE          151
++#define JH7100_CLK_SPI1_APB           152
++#define JH7100_CLK_SPI1_CORE          153
++#define JH7100_CLK_I2C0_APB           154
++#define JH7100_CLK_I2C0_CORE          155
++#define JH7100_CLK_I2C1_APB           156
++#define JH7100_CLK_I2C1_CORE          157
++#define JH7100_CLK_GPIO_APB           158
++#define JH7100_CLK_UART2_APB          159
++#define JH7100_CLK_UART2_CORE         160
++#define JH7100_CLK_UART3_APB          161
++#define JH7100_CLK_UART3_CORE         162
++#define JH7100_CLK_SPI2_APB           163
++#define JH7100_CLK_SPI2_CORE          164
++#define JH7100_CLK_SPI3_APB           165
++#define JH7100_CLK_SPI3_CORE          166
++#define JH7100_CLK_I2C2_APB           167
++#define JH7100_CLK_I2C2_CORE          168
++#define JH7100_CLK_I2C3_APB           169
++#define JH7100_CLK_I2C3_CORE          170
++#define JH7100_CLK_WDTIMER_APB                171
++#define JH7100_CLK_WDT_CORE           172
++#define JH7100_CLK_TIMER0_CORE                173
++#define JH7100_CLK_TIMER1_CORE                174
++#define JH7100_CLK_TIMER2_CORE                175
++#define JH7100_CLK_TIMER3_CORE                176
++#define JH7100_CLK_TIMER4_CORE                177
++#define JH7100_CLK_TIMER5_CORE                178
++#define JH7100_CLK_TIMER6_CORE                179
++#define JH7100_CLK_VP6INTC_APB                180
++#define JH7100_CLK_PWM_APB            181
++#define JH7100_CLK_MSI_APB            182
++#define JH7100_CLK_TEMP_APB           183
++#define JH7100_CLK_TEMP_SENSE         184
++#define JH7100_CLK_SYSERR_APB         185
++
++#define JH7100_CLK_PLL0_OUT           186
++#define JH7100_CLK_PLL1_OUT           187
++#define JH7100_CLK_PLL2_OUT           188
++
++#define JH7100_CLK_END                        189
++
++#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */

diff --git a/target/linux/visionfive/patches-5.15/0010-dt-bindings-pinctrl-Add-StarFive-pinctrl-definitions.patch b/target/linux/visionfive/patches-5.15/0010-dt-bindings-pinctrl-Add-StarFive-pinctrl-definitions.patch
deleted file mode 100644 (file)
index 1f93fd1..0000000
--- a/target/linux/visionfive/patches-5.15/0010-dt-bindings-pinctrl-Add-StarFive-pinctrl-definitions.patch
+++ /dev/null
@@ -1,293 +0,0 @@
-From 3021114b3d172cf80c074c81425741f9e26c6679 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Tue, 6 Jul 2021 20:19:06 +0200
-Subject: [PATCH 10/16] dt-bindings: pinctrl: Add StarFive pinctrl definitions
-
-Add definitons for pins and GPIO input, output and output enable
-signals on the StarFive JH7100 SoC.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- .../dt-bindings/pinctrl/pinctrl-starfive.h    | 275 ++++++++++++++++++
- 1 file changed, 275 insertions(+)
- create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive.h
-
---- /dev/null
-+++ b/include/dt-bindings/pinctrl/pinctrl-starfive.h
-@@ -0,0 +1,275 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_H__
-+#define __DT_BINDINGS_PINCTRL_STARFIVE_H__
-+
-+#define PAD_GPIO_OFFSET               0
-+#define PAD_FUNC_SHARE_OFFSET 64
-+#define PAD_GPIO(x)           (PAD_GPIO_OFFSET + (x))
-+#define PAD_FUNC_SHARE(x)     (PAD_FUNC_SHARE_OFFSET + (x))
-+
-+/*
-+ * GPIOMUX bits:
-+ *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
-+ *  |  dout   |  doen   |  din   | dout rev | doen rev | gpio nr |
-+ *
-+ * dout:     output signal
-+ * doen:     output enable signal
-+ * din:      optional input signal, 0xff = none
-+ * dout rev: output signal reverse bit
-+ * doen rev: output enable signal reverse bit
-+ * gpio nr:  gpio number, 0 - 63
-+ */
-+#define GPIOMUX(n, dout, doen, din) ( \
-+              (((dout) & 0x80000000) >> (31 - 7)) | (((dout) & 0xff) << 24) | \
-+              (((doen) & 0x80000000) >> (31 - 6)) | (((doen) & 0xff) << 16) | \
-+              (((din) & 0xff) << 8) | \
-+              ((n) & 0x3f))
-+
-+#define GPO_REVERSE                           0x80000000
-+
-+#define GPO_LOW                                       0
-+#define GPO_HIGH                              1
-+#define GPO_ENABLE                            0
-+#define GPO_DISABLE                           1
-+#define GPO_CLK_GMAC_PAPHYREF                 2
-+#define GPO_JTAG_TDO                          3
-+#define GPO_JTAG_TDO_OEN                      4
-+#define GPO_DMIC_CLK_OUT                      5
-+#define GPO_DSP_JTDOEN_PAD                    6
-+#define GPO_DSP_JTDO_PAD                      7
-+#define GPO_I2C0_PAD_SCK_OE                   8
-+#define GPO_I2C0_PAD_SCK_OEN                  (GPO_I2C0_PAD_SCK_OE | GPO_REVERSE)
-+#define GPO_I2C0_PAD_SDA_OE                   9
-+#define GPO_I2C0_PAD_SDA_OEN                  (GPO_I2C0_PAD_SDA_OE | GPO_REVERSE)
-+#define GPO_I2C1_PAD_SCK_OE                   10
-+#define GPO_I2C1_PAD_SCK_OEN                  (GPO_I2C1_PAD_SCK_OE | GPO_REVERSE)
-+#define GPO_I2C1_PAD_SDA_OE                   11
-+#define GPO_I2C1_PAD_SDA_OEN                  (GPO_I2C1_PAD_SDA_OE | GPO_REVERSE)
-+#define GPO_I2C2_PAD_SCK_OE                   12
-+#define GPO_I2C2_PAD_SCK_OEN                  (GPO_I2C2_PAD_SCK_OE | GPO_REVERSE)
-+#define GPO_I2C2_PAD_SDA_OE                   13
-+#define GPO_I2C2_PAD_SDA_OEN                  (GPO_I2C2_PAD_SDA_OE | GPO_REVERSE)
-+#define GPO_I2C3_PAD_SCK_OE                   14
-+#define GPO_I2C3_PAD_SCK_OEN                  (GPO_I2C3_PAD_SCK_OE | GPO_REVERSE)
-+#define GPO_I2C3_PAD_SDA_OE                   15
-+#define GPO_I2C3_PAD_SDA_OEN                  (GPO_I2C3_PAD_SDA_OE | GPO_REVERSE)
-+#define GPO_I2SRX_BCLK_OUT                    16
-+#define GPO_I2SRX_BCLK_OUT_OEN                        17
-+#define GPO_I2SRX_LRCK_OUT                    18
-+#define GPO_I2SRX_LRCK_OUT_OEN                        19
-+#define GPO_I2SRX_MCLK_OUT                    20
-+#define GPO_I2STX_BCLK_OUT                    21
-+#define GPO_I2STX_BCLK_OUT_OEN                        22
-+#define GPO_I2STX_LRCK_OUT                    23
-+#define GPO_I2STX_LRCK_OUT_OEN                        24
-+#define GPO_I2STX_MCLK_OUT                    25
-+#define GPO_I2STX_SDOUT0                      26
-+#define GPO_I2STX_SDOUT1                      27
-+#define GPO_LCD_PAD_CSM_N                     28
-+#define GPO_PWM_PAD_OE_N_BIT0                 29
-+#define GPO_PWM_PAD_OE_N_BIT1                 30
-+#define GPO_PWM_PAD_OE_N_BIT2                 31
-+#define GPO_PWM_PAD_OE_N_BIT3                 32
-+#define GPO_PWM_PAD_OE_N_BIT4                 33
-+#define GPO_PWM_PAD_OE_N_BIT5                 34
-+#define GPO_PWM_PAD_OE_N_BIT6                 35
-+#define GPO_PWM_PAD_OE_N_BIT7                 36
-+#define GPO_PWM_PAD_OUT_BIT0                  37
-+#define GPO_PWM_PAD_OUT_BIT1                  38
-+#define GPO_PWM_PAD_OUT_BIT2                  39
-+#define GPO_PWM_PAD_OUT_BIT3                  40
-+#define GPO_PWM_PAD_OUT_BIT4                  41
-+#define GPO_PWM_PAD_OUT_BIT5                  42
-+#define GPO_PWM_PAD_OUT_BIT6                  43
-+#define GPO_PWM_PAD_OUT_BIT7                  44
-+#define GPO_PWMDAC_LEFT_OUT                   45
-+#define GPO_PWMDAC_RIGHT_OUT                  46
-+#define GPO_QSPI_CSN1_OUT                     47
-+#define GPO_QSPI_CSN2_OUT                     48
-+#define GPO_QSPI_CSN3_OUT                     49
-+#define GPO_REGISTER23_SCFG_CMSENSOR_RST0     50
-+#define GPO_REGISTER23_SCFG_CMSENSOR_RST1     51
-+#define GPO_REGISTER32_SCFG_GMAC_PHY_RSTN     52
-+#define GPO_SDIO0_PAD_CARD_POWER_EN           53
-+#define GPO_SDIO0_PAD_CCLK_OUT                        54
-+#define GPO_SDIO0_PAD_CCMD_OE                 55
-+#define GPO_SDIO0_PAD_CCMD_OEN                        (GPO_SDIO0_PAD_CCMD_OE | GPO_REVERSE)
-+#define GPO_SDIO0_PAD_CCMD_OUT                        56
-+#define GPO_SDIO0_PAD_CDATA_OE_BIT0           57
-+#define GPO_SDIO0_PAD_CDATA_OEN_BIT0          (GPO_SDIO0_PAD_CDATA_OE_BIT0 | GPO_REVERSE)
-+#define GPO_SDIO0_PAD_CDATA_OE_BIT1           58
-+#define GPO_SDIO0_PAD_CDATA_OEN_BIT1          (GPO_SDIO0_PAD_CDATA_OE_BIT1 | GPO_REVERSE)
-+#define GPO_SDIO0_PAD_CDATA_OE_BIT2           59
-+#define GPO_SDIO0_PAD_CDATA_OEN_BIT2          (GPO_SDIO0_PAD_CDATA_OE_BIT2 | GPO_REVERSE)
-+#define GPO_SDIO0_PAD_CDATA_OE_BIT3           60
-+#define GPO_SDIO0_PAD_CDATA_OEN_BIT3          (GPO_SDIO0_PAD_CDATA_OE_BIT3 | GPO_REVERSE)
-+#define GPO_SDIO0_PAD_CDATA_OE_BIT4           61
-+#define GPO_SDIO0_PAD_CDATA_OEN_BIT4          (GPO_SDIO0_PAD_CDATA_OE_BIT4 | GPO_REVERSE)
-+#define GPO_SDIO0_PAD_CDATA_OE_BIT5           62
-+#define GPO_SDIO0_PAD_CDATA_OEN_BIT5          (GPO_SDIO0_PAD_CDATA_OE_BIT5 | GPO_REVERSE)
-+#define GPO_SDIO0_PAD_CDATA_OE_BIT6           63
-+#define GPO_SDIO0_PAD_CDATA_OEN_BIT6          (GPO_SDIO0_PAD_CDATA_OE_BIT6 | GPO_REVERSE)
-+#define GPO_SDIO0_PAD_CDATA_OE_BIT7           64
-+#define GPO_SDIO0_PAD_CDATA_OEN_BIT7          (GPO_SDIO0_PAD_CDATA_OE_BIT7 | GPO_REVERSE)
-+#define GPO_SDIO0_PAD_CDATA_OUT_BIT0          65
-+#define GPO_SDIO0_PAD_CDATA_OUT_BIT1          66
-+#define GPO_SDIO0_PAD_CDATA_OUT_BIT2          67
-+#define GPO_SDIO0_PAD_CDATA_OUT_BIT3          68
-+#define GPO_SDIO0_PAD_CDATA_OUT_BIT4          69
-+#define GPO_SDIO0_PAD_CDATA_OUT_BIT5          70
-+#define GPO_SDIO0_PAD_CDATA_OUT_BIT6          71
-+#define GPO_SDIO0_PAD_CDATA_OUT_BIT7          72
-+#define GPO_SDIO0_PAD_RST_N                   73
-+#define GPO_SDIO1_PAD_CARD_POWER_EN           74
-+#define GPO_SDIO1_PAD_CCLK_OUT                        75
-+#define GPO_SDIO1_PAD_CCMD_OE                 76
-+#define GPO_SDIO1_PAD_CCMD_OEN                        (GPO_SDIO1_PAD_CCMD_OE | GPO_REVERSE)
-+#define GPO_SDIO1_PAD_CCMD_OUT                        77
-+#define GPO_SDIO1_PAD_CDATA_OE_BIT0           78
-+#define GPO_SDIO1_PAD_CDATA_OEN_BIT0          (GPO_SDIO1_PAD_CDATA_OE_BIT0 | GPO_REVERSE)
-+#define GPO_SDIO1_PAD_CDATA_OE_BIT1           79
-+#define GPO_SDIO1_PAD_CDATA_OEN_BIT1          (GPO_SDIO1_PAD_CDATA_OE_BIT1 | GPO_REVERSE)
-+#define GPO_SDIO1_PAD_CDATA_OE_BIT2           80
-+#define GPO_SDIO1_PAD_CDATA_OEN_BIT2          (GPO_SDIO1_PAD_CDATA_OE_BIT2 | GPO_REVERSE)
-+#define GPO_SDIO1_PAD_CDATA_OE_BIT3           81
-+#define GPO_SDIO1_PAD_CDATA_OEN_BIT3          (GPO_SDIO1_PAD_CDATA_OE_BIT3 | GPO_REVERSE)
-+#define GPO_SDIO1_PAD_CDATA_OE_BIT4           82
-+#define GPO_SDIO1_PAD_CDATA_OEN_BIT4          (GPO_SDIO1_PAD_CDATA_OE_BIT4 | GPO_REVERSE)
-+#define GPO_SDIO1_PAD_CDATA_OE_BIT5           83
-+#define GPO_SDIO1_PAD_CDATA_OEN_BIT5          (GPO_SDIO1_PAD_CDATA_OE_BIT5 | GPO_REVERSE)
-+#define GPO_SDIO1_PAD_CDATA_OE_BIT6           84
-+#define GPO_SDIO1_PAD_CDATA_OEN_BIT6          (GPO_SDIO1_PAD_CDATA_OE_BIT6 | GPO_REVERSE)
-+#define GPO_SDIO1_PAD_CDATA_OE_BIT7           85
-+#define GPO_SDIO1_PAD_CDATA_OEN_BIT7          (GPO_SDIO1_PAD_CDATA_OE_BIT7 | GPO_REVERSE)
-+#define GPO_SDIO1_PAD_CDATA_OUT_BIT0          86
-+#define GPO_SDIO1_PAD_CDATA_OUT_BIT1          87
-+#define GPO_SDIO1_PAD_CDATA_OUT_BIT2          88
-+#define GPO_SDIO1_PAD_CDATA_OUT_BIT3          89
-+#define GPO_SDIO1_PAD_CDATA_OUT_BIT4          90
-+#define GPO_SDIO1_PAD_CDATA_OUT_BIT5          91
-+#define GPO_SDIO1_PAD_CDATA_OUT_BIT6          92
-+#define GPO_SDIO1_PAD_CDATA_OUT_BIT7          93
-+#define GPO_SDIO1_PAD_RST_N                   94
-+#define GPO_SPDIF_TX_SDOUT                    95
-+#define GPO_SPDIF_TX_SDOUT_OEN                        96
-+#define GPO_SPI0_PAD_OE_N                     97
-+#define GPO_SPI0_PAD_SCK_OUT                  98
-+#define GPO_SPI0_PAD_SS_0_N                   99
-+#define GPO_SPI0_PAD_SS_1_N                   100
-+#define GPO_SPI0_PAD_TXD                      101
-+#define GPO_SPI1_PAD_OE_N                     102
-+#define GPO_SPI1_PAD_SCK_OUT                  103
-+#define GPO_SPI1_PAD_SS_0_N                   104
-+#define GPO_SPI1_PAD_SS_1_N                   105
-+#define GPO_SPI1_PAD_TXD                      106
-+#define GPO_SPI2_PAD_OE_N                     107
-+#define GPO_SPI2_PAD_SCK_OUT                  108
-+#define GPO_SPI2_PAD_SS_0_N                   109
-+#define GPO_SPI2_PAD_SS_1_N                   110
-+#define GPO_SPI2_PAD_TXD                      111
-+#define GPO_SPI2AHB_PAD_OE_N_BIT0             112
-+#define GPO_SPI2AHB_PAD_OE_N_BIT1             113
-+#define GPO_SPI2AHB_PAD_OE_N_BIT2             114
-+#define GPO_SPI2AHB_PAD_OE_N_BIT3             115
-+#define GPO_SPI2AHB_PAD_TXD_BIT0              116
-+#define GPO_SPI2AHB_PAD_TXD_BIT1              117
-+#define GPO_SPI2AHB_PAD_TXD_BIT2              118
-+#define GPO_SPI2AHB_PAD_TXD_BIT3              119
-+#define GPO_SPI3_PAD_OE_N                     120
-+#define GPO_SPI3_PAD_SCK_OUT                  121
-+#define GPO_SPI3_PAD_SS_0_N                   122
-+#define GPO_SPI3_PAD_SS_1_N                   123
-+#define GPO_SPI3_PAD_TXD                      124
-+#define GPO_UART0_PAD_DTRN                    125
-+#define GPO_UART0_PAD_RTSN                    126
-+#define GPO_UART0_PAD_SOUT                    127
-+#define GPO_UART1_PAD_SOUT                    128
-+#define GPO_UART2_PAD_DTR_N                   129
-+#define GPO_UART2_PAD_RTS_N                   130
-+#define GPO_UART2_PAD_SOUT                    131
-+#define GPO_UART3_PAD_SOUT                    132
-+#define GPO_USB_DRV_BUS                               133
-+
-+#define GPI_CPU_JTAG_TCK                      0
-+#define GPI_CPU_JTAG_TDI                      1
-+#define GPI_CPU_JTAG_TMS                      2
-+#define GPI_CPU_JTAG_TRST                     3
-+#define GPI_DMIC_SDIN_BIT0                    4
-+#define GPI_DMIC_SDIN_BIT1                    5
-+#define GPI_DSP_JTCK_PAD                      6
-+#define GPI_DSP_JTDI_PAD                      7
-+#define GPI_DSP_JTMS_PAD                      8
-+#define GPI_DSP_TRST_PAD                      9
-+#define GPI_I2C0_PAD_SCK_IN                   10
-+#define GPI_I2C0_PAD_SDA_IN                   11
-+#define GPI_I2C1_PAD_SCK_IN                   12
-+#define GPI_I2C1_PAD_SDA_IN                   13
-+#define GPI_I2C2_PAD_SCK_IN                   14
-+#define GPI_I2C2_PAD_SDA_IN                   15
-+#define GPI_I2C3_PAD_SCK_IN                   16
-+#define GPI_I2C3_PAD_SDA_IN                   17
-+#define GPI_I2SRX_BCLK_IN                     18
-+#define GPI_I2SRX_LRCK_IN                     19
-+#define GPI_I2SRX_SDIN_BIT0                   20
-+#define GPI_I2SRX_SDIN_BIT1                   21
-+#define GPI_I2SRX_SDIN_BIT2                   22
-+#define GPI_I2STX_BCLK_IN                     23
-+#define GPI_I2STX_LRCK_IN                     24
-+#define GPI_SDIO0_PAD_CARD_DETECT_N           25
-+#define GPI_SDIO0_PAD_CARD_WRITE_PRT          26
-+#define GPI_SDIO0_PAD_CCMD_IN                 27
-+#define GPI_SDIO0_PAD_CDATA_IN_BIT0           28
-+#define GPI_SDIO0_PAD_CDATA_IN_BIT1           29
-+#define GPI_SDIO0_PAD_CDATA_IN_BIT2           30
-+#define GPI_SDIO0_PAD_CDATA_IN_BIT3           31
-+#define GPI_SDIO0_PAD_CDATA_IN_BIT4           32
-+#define GPI_SDIO0_PAD_CDATA_IN_BIT5           33
-+#define GPI_SDIO0_PAD_CDATA_IN_BIT6           34
-+#define GPI_SDIO0_PAD_CDATA_IN_BIT7           35
-+#define GPI_SDIO1_PAD_CARD_DETECT_N           36
-+#define GPI_SDIO1_PAD_CARD_WRITE_PRT          37
-+#define GPI_SDIO1_PAD_CCMD_IN                 38
-+#define GPI_SDIO1_PAD_CDATA_IN_BIT0           39
-+#define GPI_SDIO1_PAD_CDATA_IN_BIT1           40
-+#define GPI_SDIO1_PAD_CDATA_IN_BIT2           41
-+#define GPI_SDIO1_PAD_CDATA_IN_BIT3           42
-+#define GPI_SDIO1_PAD_CDATA_IN_BIT4           43
-+#define GPI_SDIO1_PAD_CDATA_IN_BIT5           44
-+#define GPI_SDIO1_PAD_CDATA_IN_BIT6           45
-+#define GPI_SDIO1_PAD_CDATA_IN_BIT7           46
-+#define GPI_SPDIF_RX_SDIN                     47
-+#define GPI_SPI0_PAD_RXD                      48
-+#define GPI_SPI0_PAD_SS_IN_N                  49
-+#define GPI_SPI1_PAD_RXD                      50
-+#define GPI_SPI1_PAD_SS_IN_N                  51
-+#define GPI_SPI2_PAD_RXD                      52
-+#define GPI_SPI2_PAD_SS_IN_N                  53
-+#define GPI_SPI2AHB_PAD_RXD_BIT0              54
-+#define GPI_SPI2AHB_PAD_RXD_BIT1              55
-+#define GPI_SPI2AHB_PAD_RXD_BIT2              56
-+#define GPI_SPI2AHB_PAD_RXD_BIT3              57
-+#define GPI_SPI2AHB_PAD_SS_N                  58
-+#define GPI_SPI2AHB_SLV_SCLKIN                        59
-+#define GPI_SPI3_PAD_RXD                      60
-+#define GPI_SPI3_PAD_SS_IN_N                  61
-+#define GPI_UART0_PAD_CTSN                    62
-+#define GPI_UART0_PAD_DCDN                    63
-+#define GPI_UART0_PAD_DSRN                    64
-+#define GPI_UART0_PAD_RIN                     65
-+#define GPI_UART0_PAD_SIN                     66
-+#define GPI_UART1_PAD_SIN                     67
-+#define GPI_UART2_PAD_CTS_N                   68
-+#define GPI_UART2_PAD_DCD_N                   69
-+#define GPI_UART2_PAD_DSR_N                   70
-+#define GPI_UART2_PAD_RI_N                    71
-+#define GPI_UART2_PAD_SIN                     72
-+#define GPI_UART3_PAD_SIN                     73
-+#define GPI_USB_OVER_CURRENT                  74
-+
-+#define GPI_NONE                              0xff
-+
-+#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_H__ */

diff --git a/target/linux/visionfive/patches-5.15/0011-dt-bindings-clock-starfive-Add-JH7100-bindings.patch b/target/linux/visionfive/patches-5.15/0011-dt-bindings-clock-starfive-Add-JH7100-bindings.patch
new file mode 100644 (file)
index 0000000..86b8854
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0011-dt-bindings-clock-starfive-Add-JH7100-bindings.patch
@@ -0,0 +1,78 @@
+From d17a37a986f6c112048988a10a355c17cee14424 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Tue, 1 Jun 2021 16:02:23 +0200
+Subject: [PATCH 11/84] dt-bindings: clock: starfive: Add JH7100 bindings
+
+commit af35098f4fcd1f9bfc58dc37479e0786a4d85e96 upstream.
+
+Add bindings for the clock generator on the JH7100 RISC-V SoC by
+StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../clock/starfive,jh7100-clkgen.yaml         | 56 +++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
+@@ -0,0 +1,56 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7100 Clock Generator
++
++maintainers:
++  - Geert Uytterhoeven <geert@linux-m68k.org>
++  - Emil Renner Berthing <kernel@esmil.dk>
++
++properties:
++  compatible:
++    const: starfive,jh7100-clkgen
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: Main clock source (25 MHz)
++      - description: Application-specific clock source (12-27 MHz)
++      - description: RMII reference clock (50 MHz)
++      - description: RGMII RX clock (125 MHz)
++
++  clock-names:
++    items:
++      - const: osc_sys
++      - const: osc_aud
++      - const: gmac_rmii_ref
++      - const: gmac_gr_mii_rxclk
++
++  '#clock-cells':
++    const: 1
++    description:
++      See <dt-bindings/clock/starfive-jh7100.h> for valid indices.
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    clock-controller@11800000 {
++            compatible = "starfive,jh7100-clkgen";
++            reg = <0x11800000 0x10000>;
++            clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
++            clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
++            #clock-cells = <1>;
++    };

diff --git a/target/linux/visionfive/patches-5.15/0011-dt-bindings-pinctrl-Add-StarFive-JH7100-bindings.patch b/target/linux/visionfive/patches-5.15/0011-dt-bindings-pinctrl-Add-StarFive-JH7100-bindings.patch
deleted file mode 100644 (file)
index 75e57e8..0000000
--- a/target/linux/visionfive/patches-5.15/0011-dt-bindings-pinctrl-Add-StarFive-JH7100-bindings.patch
+++ /dev/null
@@ -1,326 +0,0 @@
-From 7431b391df95f5b8d08fd0f9fa1a75cc038ee290 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Tue, 27 Jul 2021 14:34:33 +0200
-Subject: [PATCH 11/16] dt-bindings: pinctrl: Add StarFive JH7100 bindings
-
-Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by
-StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
-
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- .../pinctrl/starfive,jh7100-pinctrl.yaml      | 307 ++++++++++++++++++
- 1 file changed, 307 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
-@@ -0,0 +1,307 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: StarFive JH7100 Pin Controller Device Tree Bindings
-+
-+description: |
-+  Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
-+
-+  Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
-+  and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
-+  configurable bias, drive strength, schmitt trigger etc. The SoC has an
-+  interesting 2-layered approach to pin muxing best illustrated by the diagram
-+  below.
-+
-+                          Signal group 0, 1, ... or 6
-+                                 ___|___
-+                                |       |
-+    LCD output -----------------|       |
-+    CMOS Camera interface ------|       |--- PAD_GPIO[0]
-+    Ethernet PHY interface -----|  MUX  |--- PAD_GPIO[1]
-+      ...                       |       |      ...
-+                                |       |--- PAD_GPIO[63]
-+     -------- GPIO0 ------------|       |
-+    |  -------|-- GPIO1 --------|       |--- PAD_FUNC_SHARE[0]
-+    | |       |   |             |       |--- PAD_FUNC_SHARE[1]
-+    | |       |   |  ...        |       |       ...
-+    | |       |   |             |       |--- PAD_FUNC_SHARE[141]
-+    | |  -----|---|-- GPIO63 ---|       |
-+    | | |     |   |   |          -------
-+    UART0     UART1 --
-+
-+
-+  The big MUX in the diagram only has 7 different ways of mapping peripherals
-+  on the left to pins on the right. StarFive calls the 7 configurations "signal
-+  groups".
-+  However some peripherals have their I/O go through the 64 "GPIOs". The
-+  diagram only shows UART0 and UART1, but this also includes a number of other
-+  UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
-+  GPIOs such that any GPIO can be set up to be controlled by any of the
-+  peripherals.
-+  Note that signal group 0 doesn't map any of the GPIOs to pins, and only
-+  signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].
-+
-+maintainers:
-+  - Emil Renner Berthing <kernel@esmil.dk>
-+  - Drew Fustini <drew@beagleboard.org>
-+
-+properties:
-+  compatible:
-+    const: starfive,jh7100-pinctrl
-+
-+  reg:
-+    minItems: 2
-+    maxItems: 2
-+
-+  reg-names:
-+    items:
-+      - const: gpio
-+      - const: padctl
-+
-+  clocks:
-+    maxItems: 1
-+
-+  resets:
-+    maxItems: 1
-+
-+  gpio-controller: true
-+
-+  "#gpio-cells":
-+    const: 2
-+
-+  interrupts:
-+    maxItems: 1
-+    description: The GPIO parent interrupt.
-+
-+  interrupt-controller: true
-+
-+  "#interrupt-cells":
-+    const: 2
-+
-+  starfive,signal-group:
-+    description: |
-+      Select one of the 7 signal groups. If this property is not set it
-+      defaults to the configuration already chosen by the earlier boot stages.
-+    $ref: /schemas/types.yaml#/definitions/uint32
-+    enum: [0, 1, 2, 3, 4, 5, 6]
-+
-+required:
-+  - compatible
-+  - reg
-+  - reg-names
-+  - clocks
-+  - gpio-controller
-+  - "#gpio-cells"
-+  - interrupts
-+  - interrupt-controller
-+  - "#interrupt-cells"
-+
-+patternProperties:
-+  '-[0-9]+$':
-+    type: object
-+    patternProperties:
-+      '-pins$':
-+        type: object
-+        description: |
-+          A pinctrl node should contain at least one subnode representing the
-+          pinctrl groups available on the machine. Each subnode will list the
-+          pins it needs, and how they should be configured, with regard to
-+          muxer configuration, bias, input enable/disable, input schmitt
-+          trigger enable/disable, slew-rate and drive strength.
-+        $ref: "/schemas/pinctrl/pincfg-node.yaml"
-+
-+        properties:
-+          pins:
-+            description: |
-+              The list of pin identifiers that properties in the node apply to.
-+              This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
-+              macros.
-+              Either this or "pinmux" has to be specified, but not both.
-+            $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins"
-+
-+          pinmux:
-+            description: |
-+              The list of GPIOs and their mux settings that properties in the
-+              node apply to. This should be set using the GPIOMUX macro.
-+              Either this or "pins" has to be specified, but not both.
-+            $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"
-+
-+          bias-disable: true
-+
-+          bias-pull-up:
-+            type: boolean
-+
-+          bias-pull-down:
-+            type: boolean
-+
-+          drive-strength:
-+            enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]
-+
-+          input-enable: true
-+
-+          input-disable: true
-+
-+          input-schmitt-enable: true
-+
-+          input-schmitt-disable: true
-+
-+          slew-rate:
-+            maximum: 7
-+
-+          starfive,strong-pull-up:
-+            description: enable strong pull-up.
-+            type: boolean
-+
-+        additionalProperties: false
-+
-+    additionalProperties: false
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/clock/starfive-jh7100.h>
-+    #include <dt-bindings/reset/starfive-jh7100.h>
-+    #include <dt-bindings/pinctrl/pinctrl-starfive.h>
-+
-+    soc {
-+        #address-cells = <2>;
-+        #size-cells = <2>;
-+
-+        pinctrl@11910000 {
-+            compatible = "starfive,jh7100-pinctrl";
-+            reg = <0x0 0x11910000 0x0 0x10000>,
-+                  <0x0 0x11858000 0x0 0x1000>;
-+            reg-names = "gpio", "padctl";
-+            clocks = <&clkgen JH7100_CLK_GPIO_APB>;
-+            resets = <&clkgen JH7100_RSTN_GPIO_APB>;
-+            interrupts = <32>;
-+            gpio-controller;
-+            #gpio-cells = <2>;
-+            interrupt-controller;
-+            #interrupt-cells = <2>;
-+            starfive,signal-group = <6>;
-+
-+            gmac_pins_default: gmac-0 {
-+                gtxclk-pins {
-+                    pins = <PAD_FUNC_SHARE(115)>;
-+                    bias-pull-up;
-+                    drive-strength = <35>;
-+                    input-enable;
-+                    input-schmitt-enable;
-+                    slew-rate = <0>;
-+                };
-+                miitxclk-pins {
-+                    pins = <PAD_FUNC_SHARE(116)>;
-+                    bias-pull-up;
-+                    drive-strength = <14>;
-+                    input-enable;
-+                    input-schmitt-disable;
-+                    slew-rate = <0>;
-+                };
-+                tx-pins {
-+                    pins = <PAD_FUNC_SHARE(117)>,
-+                           <PAD_FUNC_SHARE(119)>,
-+                           <PAD_FUNC_SHARE(120)>,
-+                           <PAD_FUNC_SHARE(121)>,
-+                           <PAD_FUNC_SHARE(122)>,
-+                           <PAD_FUNC_SHARE(123)>,
-+                           <PAD_FUNC_SHARE(124)>,
-+                           <PAD_FUNC_SHARE(125)>,
-+                           <PAD_FUNC_SHARE(126)>;
-+                    bias-disable;
-+                    drive-strength = <35>;
-+                    input-disable;
-+                    input-schmitt-disable;
-+                    slew-rate = <0>;
-+                };
-+                rxclk-pins {
-+                    pins = <PAD_FUNC_SHARE(127)>;
-+                    bias-pull-up;
-+                    drive-strength = <14>;
-+                    input-enable;
-+                    input-schmitt-disable;
-+                    slew-rate = <6>;
-+                };
-+                rxer-pins {
-+                    pins = <PAD_FUNC_SHARE(129)>;
-+                    bias-pull-up;
-+                    drive-strength = <14>;
-+                    input-enable;
-+                    input-schmitt-disable;
-+                    slew-rate = <0>;
-+                };
-+                rx-pins {
-+                    pins = <PAD_FUNC_SHARE(128)>,
-+                           <PAD_FUNC_SHARE(130)>,
-+                           <PAD_FUNC_SHARE(131)>,
-+                           <PAD_FUNC_SHARE(132)>,
-+                           <PAD_FUNC_SHARE(133)>,
-+                           <PAD_FUNC_SHARE(134)>,
-+                           <PAD_FUNC_SHARE(135)>,
-+                           <PAD_FUNC_SHARE(136)>,
-+                           <PAD_FUNC_SHARE(137)>,
-+                           <PAD_FUNC_SHARE(138)>,
-+                           <PAD_FUNC_SHARE(139)>,
-+                           <PAD_FUNC_SHARE(140)>,
-+                           <PAD_FUNC_SHARE(141)>;
-+                    bias-pull-up;
-+                    drive-strength = <14>;
-+                    input-enable;
-+                    input-schmitt-enable;
-+                    slew-rate = <0>;
-+                };
-+            };
-+
-+            i2c0_pins_default: i2c0-0 {
-+                i2c-pins {
-+                    pinmux = <GPIOMUX(62, GPO_LOW,
-+                              GPO_I2C0_PAD_SCK_OEN,
-+                              GPI_I2C0_PAD_SCK_IN)>,
-+                             <GPIOMUX(61, GPO_LOW,
-+                              GPO_I2C0_PAD_SDA_OEN,
-+                              GPI_I2C0_PAD_SDA_IN)>;
-+                    bias-disable; /* external pull-up */
-+                    input-enable;
-+                    input-schmitt-enable;
-+                };
-+            };
-+
-+            uart3_pins_default: uart3-0 {
-+                rx-pins {
-+                    pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
-+                              GPI_UART3_PAD_SIN)>;
-+                    bias-pull-up;
-+                    input-enable;
-+                    input-schmitt-enable;
-+                };
-+                tx-pins {
-+                    pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
-+                              GPO_ENABLE, GPI_NONE)>;
-+                    bias-disable;
-+                    input-disable;
-+                    input-schmitt-disable;
-+                };
-+            };
-+        };
-+
-+        gmac {
-+            pinctrl-0 = <&gmac_pins_default>;
-+            pinctrl-names = "default";
-+        };
-+
-+        i2c0 {
-+            pinctrl-0 = <&i2c0_pins_default>;
-+            pinctrl-names = "default";
-+        };
-+
-+        uart3 {
-+            pinctrl-0 = <&uart3_pins_default>;
-+            pinctrl-names = "default";
-+        };
-+    };
-+
-+...

diff --git a/target/linux/visionfive/patches-5.15/0012-clk-starfive-Add-JH7100-clock-generator-driver.patch b/target/linux/visionfive/patches-5.15/0012-clk-starfive-Add-JH7100-clock-generator-driver.patch
new file mode 100644 (file)
index 0000000..6eb1b41
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0012-clk-starfive-Add-JH7100-clock-generator-driver.patch
@@ -0,0 +1,772 @@
+From f052303d49564c2f83aebe588c5ae148a47ba054 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Tue, 1 Jun 2021 15:57:52 +0200
+Subject: [PATCH 12/84] clk: starfive: Add JH7100 clock generator driver
+
+commit 4210be668a09ee20e4e1c7adf61b47d33d05c480 upstream.
+
+Add a driver for the StarFive JH7100 clock generator.
+
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ MAINTAINERS                                |   7 +
+ drivers/clk/Kconfig                        |   1 +
+ drivers/clk/Makefile                       |   1 +
+ drivers/clk/starfive/Kconfig               |   9 +
+ drivers/clk/starfive/Makefile              |   3 +
+ drivers/clk/starfive/clk-starfive-jh7100.c | 689 +++++++++++++++++++++
+ 6 files changed, 710 insertions(+)
+ create mode 100644 drivers/clk/starfive/Kconfig
+ create mode 100644 drivers/clk/starfive/Makefile
+ create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -17860,6 +17860,13 @@ M:    Ion Badulescu <ionut@badula.org>
+ S:    Odd Fixes
+ F:    drivers/net/ethernet/adaptec/starfire*
+ 
++STARFIVE JH7100 CLOCK DRIVER
++M:    Emil Renner Berthing <kernel@esmil.dk>
++S:    Maintained
++F:    Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
++F:    drivers/clk/starfive/clk-starfive-jh7100.c
++F:    include/dt-bindings/clock/starfive-jh7100.h
++
+ STATIC BRANCH/CALL
+ M:    Peter Zijlstra <peterz@infradead.org>
+ M:    Josh Poimboeuf <jpoimboe@redhat.com>
+--- a/drivers/clk/Kconfig
++++ b/drivers/clk/Kconfig
+@@ -412,6 +412,7 @@ source "drivers/clk/samsung/Kconfig"
+ source "drivers/clk/sifive/Kconfig"
+ source "drivers/clk/socfpga/Kconfig"
+ source "drivers/clk/sprd/Kconfig"
++source "drivers/clk/starfive/Kconfig"
+ source "drivers/clk/sunxi/Kconfig"
+ source "drivers/clk/sunxi-ng/Kconfig"
+ source "drivers/clk/tegra/Kconfig"
+--- a/drivers/clk/Makefile
++++ b/drivers/clk/Makefile
+@@ -109,6 +109,7 @@ obj-y                                      += socfpga/
+ obj-$(CONFIG_PLAT_SPEAR)              += spear/
+ obj-y                                 += sprd/
+ obj-$(CONFIG_ARCH_STI)                        += st/
++obj-$(CONFIG_SOC_STARFIVE)            += starfive/
+ obj-$(CONFIG_ARCH_SUNXI)              += sunxi/
+ obj-$(CONFIG_SUNXI_CCU)                       += sunxi-ng/
+ obj-$(CONFIG_ARCH_TEGRA)              += tegra/
+--- /dev/null
++++ b/drivers/clk/starfive/Kconfig
+@@ -0,0 +1,9 @@
++# SPDX-License-Identifier: GPL-2.0
++
++config CLK_STARFIVE_JH7100
++      bool "StarFive JH7100 clock support"
++      depends on SOC_STARFIVE || COMPILE_TEST
++      default SOC_STARFIVE
++      help
++        Say yes here to support the clock controller on the StarFive JH7100
++        SoC.
+--- /dev/null
++++ b/drivers/clk/starfive/Makefile
+@@ -0,0 +1,3 @@
++# SPDX-License-Identifier: GPL-2.0
++# StarFive Clock
++obj-$(CONFIG_CLK_STARFIVE_JH7100)     += clk-starfive-jh7100.o
+--- /dev/null
++++ b/drivers/clk/starfive/clk-starfive-jh7100.c
+@@ -0,0 +1,689 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * StarFive JH7100 Clock Generator Driver
++ *
++ * Copyright 2021 Ahmad Fatoum, Pengutronix
++ * Copyright (C) 2021 Glider bv
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#include <linux/bits.h>
++#include <linux/clk-provider.h>
++#include <linux/debugfs.h>
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/mod_devicetable.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <dt-bindings/clock/starfive-jh7100.h>
++
++/* external clocks */
++#define JH7100_CLK_OSC_SYS            (JH7100_CLK_END + 0)
++#define JH7100_CLK_OSC_AUD            (JH7100_CLK_END + 1)
++#define JH7100_CLK_GMAC_RMII_REF      (JH7100_CLK_END + 2)
++#define JH7100_CLK_GMAC_GR_MII_RX     (JH7100_CLK_END + 3)
++
++/* register fields */
++#define JH7100_CLK_ENABLE     BIT(31)
++#define JH7100_CLK_INVERT     BIT(30)
++#define JH7100_CLK_MUX_MASK   GENMASK(27, 24)
++#define JH7100_CLK_MUX_SHIFT  24
++#define JH7100_CLK_DIV_MASK   GENMASK(23, 0)
++
++/* clock data */
++#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = {          \
++      .name = _name,                                                  \
++      .flags = CLK_SET_RATE_PARENT | (_flags),                        \
++      .max = JH7100_CLK_ENABLE,                                       \
++      .parents = { [0] = _parent },                                   \
++}
++
++#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = {            \
++      .name = _name,                                                  \
++      .flags = 0,                                                     \
++      .max = _max,                                                    \
++      .parents = { [0] = _parent },                                   \
++}
++
++#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = {    \
++      .name = _name,                                                  \
++      .flags = _flags,                                                \
++      .max = JH7100_CLK_ENABLE | (_max),                              \
++      .parents = { [0] = _parent },                                   \
++}
++
++#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = {           \
++      .name = _name,                                                  \
++      .flags = 0,                                                     \
++      .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT,               \
++      .parents = { __VA_ARGS__ },                                     \
++}
++
++#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = {   \
++      .name = _name,                                                  \
++      .flags = _flags,                                                \
++      .max = JH7100_CLK_ENABLE |                                      \
++              (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT),            \
++      .parents = { __VA_ARGS__ },                                     \
++}
++
++#define JH7100__INV(_idx, _name, _parent) [_idx] = {                  \
++      .name = _name,                                                  \
++      .flags = CLK_SET_RATE_PARENT,                                   \
++      .max = JH7100_CLK_INVERT,                                       \
++      .parents = { [0] = _parent },                                   \
++}
++
++static const struct {
++      const char *name;
++      unsigned long flags;
++      u32 max;
++      u8 parents[4];
++} jh7100_clk_data[] __initconst = {
++      JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_PLL0_OUT,
++                  JH7100_CLK_PLL1_OUT,
++                  JH7100_CLK_PLL2_OUT),
++      JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_PLL1_OUT,
++                  JH7100_CLK_PLL2_OUT),
++      JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_PLL0_OUT,
++                  JH7100_CLK_PLL1_OUT,
++                  JH7100_CLK_PLL2_OUT),
++      JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_PLL0_OUT,
++                  JH7100_CLK_PLL2_OUT),
++      JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_PLL0_OUT),
++      JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_PLL2_OUT),
++      JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_PLL1_OUT,
++                  JH7100_CLK_PLL2_OUT),
++      JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
++                  JH7100_CLK_OSC_AUD,
++                  JH7100_CLK_PLL0_OUT,
++                  JH7100_CLK_PLL2_OUT),
++      JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
++      JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_PLL1_OUT,
++                  JH7100_CLK_PLL2_OUT),
++      JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_PLL0_OUT,
++                  JH7100_CLK_PLL1_OUT),
++      JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
++                  JH7100_CLK_OSC_AUD,
++                  JH7100_CLK_PLL0_OUT,
++                  JH7100_CLK_PLL2_OUT),
++      JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
++      JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
++      JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
++      JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
++      JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
++      JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
++      JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
++      JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_OSC_AUD),
++      JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++      JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
++      JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++      JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
++      JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
++      JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
++      JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
++      JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
++      JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
++      JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
++      JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
++      JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
++      JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
++      JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
++      JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
++      JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
++      JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
++      JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
++      JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
++      JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
++      JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
++      JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
++      JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
++      JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
++      JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
++      JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++      JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++      JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
++      JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
++      JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
++      JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
++      JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
++      JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
++      JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
++      JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
++      JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
++      JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
++      JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
++      JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
++      JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
++      JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
++                  JH7100_CLK_DDROSC_DIV2,
++                  JH7100_CLK_DDRPLL_DIV2,
++                  JH7100_CLK_DDRPLL_DIV4,
++                  JH7100_CLK_DDRPLL_DIV8),
++      JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
++                  JH7100_CLK_DDROSC_DIV2,
++                  JH7100_CLK_DDRPLL_DIV2,
++                  JH7100_CLK_DDRPLL_DIV4,
++                  JH7100_CLK_DDRPLL_DIV8),
++      JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++      JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
++      JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
++      JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
++                  JH7100_CLK_CPU_AXI,
++                  JH7100_CLK_NNEBUS_SRC1),
++      JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
++      JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
++      JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
++      JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
++      JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
++      JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
++      JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
++      JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
++      JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
++      JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
++      JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++      JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
++      JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
++      JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++      JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++      JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
++      JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
++      JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
++      JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
++      JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
++      JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
++                  JH7100_CLK_OSC_SYS,
++                  JH7100_CLK_USBPHY_PLLDIV25M),
++      JH7100__DIV(JH7100_CLK_AUDIO_DIV, "audio_div", 131072, JH7100_CLK_AUDIO_ROOT),
++      JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
++      JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
++      JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
++      JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
++      JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
++      JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
++      JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
++      JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
++      JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
++      JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
++      JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
++      JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
++      JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
++      JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
++      JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
++      JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
++      JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
++      JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
++      JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
++      JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
++      JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
++      JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
++      JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
++      JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
++      JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
++      JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
++      JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
++      JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
++                  JH7100_CLK_GMAC_GTX,
++                  JH7100_CLK_GMAC_TX_INV,
++                  JH7100_CLK_GMAC_RMII_TX),
++      JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
++      JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
++                  JH7100_CLK_GMAC_GR_MII_RX,
++                  JH7100_CLK_GMAC_RMII_RX),
++      JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
++      JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
++      JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
++      JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
++      JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
++      JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
++      JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
++      JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
++      JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
++      JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
++      JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
++      JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
++      JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
++      JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
++      JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
++      JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++      JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
++      JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
++};
++
++struct jh7100_clk {
++      struct clk_hw hw;
++      unsigned int idx;
++      unsigned int max_div;
++};
++
++struct jh7100_clk_priv {
++      /* protect clk enable and set rate/parent from happening at the same time */
++      spinlock_t rmw_lock;
++      struct device *dev;
++      void __iomem *base;
++      struct clk_hw *pll[3];
++      struct jh7100_clk reg[JH7100_CLK_PLL0_OUT];
++};
++
++static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
++{
++      return container_of(hw, struct jh7100_clk, hw);
++}
++
++static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
++{
++      return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
++}
++
++static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
++{
++      struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
++      void __iomem *reg = priv->base + 4 * clk->idx;
++
++      return readl_relaxed(reg);
++}
++
++static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
++{
++      struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
++      void __iomem *reg = priv->base + 4 * clk->idx;
++      unsigned long flags;
++
++      spin_lock_irqsave(&priv->rmw_lock, flags);
++      value |= readl_relaxed(reg) & ~mask;
++      writel_relaxed(value, reg);
++      spin_unlock_irqrestore(&priv->rmw_lock, flags);
++}
++
++static int jh7100_clk_enable(struct clk_hw *hw)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++
++      jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
++      return 0;
++}
++
++static void jh7100_clk_disable(struct clk_hw *hw)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++
++      jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
++}
++
++static int jh7100_clk_is_enabled(struct clk_hw *hw)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++
++      return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
++}
++
++static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
++                                          unsigned long parent_rate)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
++
++      return div ? parent_rate / div : 0;
++}
++
++static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk,
++                                      unsigned long rate, unsigned long parent)
++{
++      unsigned long max = clk->max_div;
++      unsigned long div = DIV_ROUND_UP(parent, rate);
++
++      return min(div, max);
++}
++
++static int jh7100_clk_determine_rate(struct clk_hw *hw,
++                                   struct clk_rate_request *req)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      unsigned long parent = req->best_parent_rate;
++      unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
++      unsigned long div = jh7100_clk_bestdiv(clk, rate, parent);
++      unsigned long result = parent / div;
++
++      /*
++       * we want the result clamped by min_rate and max_rate if possible:
++       * case 1: div hits the max divider value, which means it's less than
++       * parent / rate, so the result is greater than rate and min_rate in
++       * particular. we can't do anything about result > max_rate because the
++       * divider doesn't go any further.
++       * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
++       * always lower or equal to rate and max_rate. however the result may
++       * turn out lower than min_rate, but then the next higher rate is fine:
++       *   div - 1 = ceil(parent / rate) - 1 < parent / rate
++       * and thus
++       *   min_rate <= rate < parent / (div - 1)
++       */
++      if (result < req->min_rate && div > 1)
++              result = parent / (div - 1);
++
++      req->rate = result;
++      return 0;
++}
++
++static int jh7100_clk_set_rate(struct clk_hw *hw,
++                             unsigned long rate,
++                             unsigned long parent_rate)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate);
++
++      jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
++      return 0;
++}
++
++static u8 jh7100_clk_get_parent(struct clk_hw *hw)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      u32 value = jh7100_clk_reg_get(clk);
++
++      return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
++}
++
++static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
++
++      jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
++      return 0;
++}
++
++static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
++                                       struct clk_rate_request *req)
++{
++      return clk_mux_determine_rate_flags(hw, req, 0);
++}
++
++static int jh7100_clk_get_phase(struct clk_hw *hw)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      u32 value = jh7100_clk_reg_get(clk);
++
++      return (value & JH7100_CLK_INVERT) ? 180 : 0;
++}
++
++static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      u32 value;
++
++      if (degrees == 0)
++              value = 0;
++      else if (degrees == 180)
++              value = JH7100_CLK_INVERT;
++      else
++              return -EINVAL;
++
++      jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
++      return 0;
++}
++
++#ifdef CONFIG_DEBUG_FS
++static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
++{
++      static const struct debugfs_reg32 jh7100_clk_reg = {
++              .name = "CTRL",
++              .offset = 0,
++      };
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
++      struct debugfs_regset32 *regset;
++
++      regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
++      if (!regset)
++              return;
++
++      regset->regs = &jh7100_clk_reg;
++      regset->nregs = 1;
++      regset->base = priv->base + 4 * clk->idx;
++
++      debugfs_create_regset32("registers", 0400, dentry, regset);
++}
++#else
++#define jh7100_clk_debug_init NULL
++#endif
++
++static const struct clk_ops jh7100_clk_gate_ops = {
++      .enable = jh7100_clk_enable,
++      .disable = jh7100_clk_disable,
++      .is_enabled = jh7100_clk_is_enabled,
++      .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_div_ops = {
++      .recalc_rate = jh7100_clk_recalc_rate,
++      .determine_rate = jh7100_clk_determine_rate,
++      .set_rate = jh7100_clk_set_rate,
++      .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_gdiv_ops = {
++      .enable = jh7100_clk_enable,
++      .disable = jh7100_clk_disable,
++      .is_enabled = jh7100_clk_is_enabled,
++      .recalc_rate = jh7100_clk_recalc_rate,
++      .determine_rate = jh7100_clk_determine_rate,
++      .set_rate = jh7100_clk_set_rate,
++      .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_mux_ops = {
++      .determine_rate = jh7100_clk_mux_determine_rate,
++      .set_parent = jh7100_clk_set_parent,
++      .get_parent = jh7100_clk_get_parent,
++      .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_gmux_ops = {
++      .enable = jh7100_clk_enable,
++      .disable = jh7100_clk_disable,
++      .is_enabled = jh7100_clk_is_enabled,
++      .determine_rate = jh7100_clk_mux_determine_rate,
++      .set_parent = jh7100_clk_set_parent,
++      .get_parent = jh7100_clk_get_parent,
++      .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_inv_ops = {
++      .get_phase = jh7100_clk_get_phase,
++      .set_phase = jh7100_clk_set_phase,
++      .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops *__init jh7100_clk_ops(u32 max)
++{
++      if (max & JH7100_CLK_DIV_MASK) {
++              if (max & JH7100_CLK_ENABLE)
++                      return &jh7100_clk_gdiv_ops;
++              return &jh7100_clk_div_ops;
++      }
++
++      if (max & JH7100_CLK_MUX_MASK) {
++              if (max & JH7100_CLK_ENABLE)
++                      return &jh7100_clk_gmux_ops;
++              return &jh7100_clk_mux_ops;
++      }
++
++      if (max & JH7100_CLK_ENABLE)
++              return &jh7100_clk_gate_ops;
++
++      return &jh7100_clk_inv_ops;
++}
++
++static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct jh7100_clk_priv *priv = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx < JH7100_CLK_PLL0_OUT)
++              return &priv->reg[idx].hw;
++
++      if (idx < JH7100_CLK_END)
++              return priv->pll[idx - JH7100_CLK_PLL0_OUT];
++
++      return ERR_PTR(-EINVAL);
++}
++
++static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
++{
++      struct jh7100_clk_priv *priv;
++      unsigned int idx;
++      int ret;
++
++      priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++      if (!priv)
++              return -ENOMEM;
++
++      spin_lock_init(&priv->rmw_lock);
++      priv->dev = &pdev->dev;
++      priv->base = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(priv->base))
++              return PTR_ERR(priv->base);
++
++      priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
++                                                       "osc_sys", 0, 40, 1);
++      if (IS_ERR(priv->pll[0]))
++              return PTR_ERR(priv->pll[0]);
++
++      priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
++                                                       "osc_sys", 0, 64, 1);
++      if (IS_ERR(priv->pll[1]))
++              return PTR_ERR(priv->pll[1]);
++
++      priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
++                                                       "pll2_refclk", 0, 55, 1);
++      if (IS_ERR(priv->pll[2]))
++              return PTR_ERR(priv->pll[2]);
++
++      for (idx = 0; idx < JH7100_CLK_PLL0_OUT; idx++) {
++              u32 max = jh7100_clk_data[idx].max;
++              struct clk_parent_data parents[4] = {};
++              struct clk_init_data init = {
++                      .name = jh7100_clk_data[idx].name,
++                      .ops = jh7100_clk_ops(max),
++                      .parent_data = parents,
++                      .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
++                      .flags = jh7100_clk_data[idx].flags,
++              };
++              struct jh7100_clk *clk = &priv->reg[idx];
++              unsigned int i;
++
++              for (i = 0; i < init.num_parents; i++) {
++                      unsigned int pidx = jh7100_clk_data[idx].parents[i];
++
++                      if (pidx < JH7100_CLK_PLL0_OUT)
++                              parents[i].hw = &priv->reg[pidx].hw;
++                      else if (pidx < JH7100_CLK_END)
++                              parents[i].hw = priv->pll[pidx - JH7100_CLK_PLL0_OUT];
++                      else if (pidx == JH7100_CLK_OSC_SYS)
++                              parents[i].fw_name = "osc_sys";
++                      else if (pidx == JH7100_CLK_OSC_AUD)
++                              parents[i].fw_name = "osc_aud";
++                      else if (pidx == JH7100_CLK_GMAC_RMII_REF)
++                              parents[i].fw_name = "gmac_rmii_ref";
++                      else if (pidx == JH7100_CLK_GMAC_GR_MII_RX)
++                              parents[i].fw_name = "gmac_gr_mii_rxclk";
++              }
++
++              clk->hw.init = &init;
++              clk->idx = idx;
++              clk->max_div = max & JH7100_CLK_DIV_MASK;
++
++              ret = devm_clk_hw_register(priv->dev, &clk->hw);
++              if (ret)
++                      return ret;
++      }
++
++      return devm_of_clk_add_hw_provider(priv->dev, jh7100_clk_get, priv);
++}
++
++static const struct of_device_id clk_starfive_jh7100_match[] = {
++      { .compatible = "starfive,jh7100-clkgen" },
++      { /* sentinel */ }
++};
++
++static struct platform_driver clk_starfive_jh7100_driver = {
++      .driver = {
++              .name = "clk-starfive-jh7100",
++              .of_match_table = clk_starfive_jh7100_match,
++              .suppress_bind_attrs = true,
++      },
++};
++builtin_platform_driver_probe(clk_starfive_jh7100_driver, clk_starfive_jh7100_probe);

diff --git a/target/linux/visionfive/patches-5.15/0012-pinctrl-starfive-Add-pinctrl-driver-for-StarFive-SoC.patch b/target/linux/visionfive/patches-5.15/0012-pinctrl-starfive-Add-pinctrl-driver-for-StarFive-SoC.patch
deleted file mode 100644 (file)
index 04ea59f..0000000
--- a/target/linux/visionfive/patches-5.15/0012-pinctrl-starfive-Add-pinctrl-driver-for-StarFive-SoC.patch
+++ /dev/null
@@ -1,1447 +0,0 @@
-From ec648f6b7686b716424e8e73eebb4c11ae199187 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Tue, 6 Jul 2021 20:19:06 +0200
-Subject: [PATCH 12/16] pinctrl: starfive: Add pinctrl driver for StarFive SoCs
-
-Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
-StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
-is said to feature only minor changes to these pinctrl/GPIO parts.
-
-For each "GPIO" there are two registers for configuring the output and
-output enable signals which may come from other peripherals. Among these
-are two special signals that are constant 0 and constant 1 respectively.
-Controlling the GPIOs from software is done by choosing one of these
-signals. In other words the same registers are used for both pin muxing
-and controlling the GPIOs, which makes it easier to combine the pinctrl
-and GPIO driver in one.
-
-I wrote the pinconf and pinmux parts, but the GPIO part of the code is
-based on the GPIO driver in the vendor tree written by Huan Feng with
-cleanups and fixes by Drew and me.
-
-Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
-Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
-Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
-Co-developed-by: Drew Fustini <drew@beagleboard.org>
-Signed-off-by: Drew Fustini <drew@beagleboard.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- MAINTAINERS                        |    8 +
- drivers/pinctrl/Kconfig            |   17 +
- drivers/pinctrl/Makefile           |    1 +
- drivers/pinctrl/pinctrl-starfive.c | 1354 ++++++++++++++++++++++++++++
- 4 files changed, 1380 insertions(+)
- create mode 100644 drivers/pinctrl/pinctrl-starfive.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -17867,6 +17867,14 @@ F:    Documentation/devicetree/bindings/clo
- F:    drivers/clk/starfive/clk-starfive-jh7100.c
- F:    include/dt-bindings/clock/starfive-jh7100.h
- 
-+STARFIVE JH7100 PINCTRL DRIVER
-+M:    Emil Renner Berthing <kernel@esmil.dk>
-+L:    linux-gpio@vger.kernel.org
-+S:    Maintained
-+F:    Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
-+F:    drivers/pinctrl/pinctrl-starfive.c
-+F:    include/dt-bindings/pinctrl/pinctrl-starfive.h
-+
- STARFIVE JH7100 RESET CONTROLLER DRIVER
- M:    Emil Renner Berthing <kernel@esmil.dk>
- S:    Maintained
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -265,6 +265,23 @@ config PINCTRL_ST
-       select PINCONF
-       select GPIOLIB_IRQCHIP
- 
-+config PINCTRL_STARFIVE
-+      tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
-+      depends on SOC_STARFIVE || COMPILE_TEST
-+      depends on OF
-+      default SOC_STARFIVE
-+      select GENERIC_PINCTRL_GROUPS
-+      select GENERIC_PINMUX_FUNCTIONS
-+      select GENERIC_PINCONF
-+      select GPIOLIB
-+      select GPIOLIB_IRQCHIP
-+      select OF_GPIO
-+      help
-+        Say yes here to support pin control on the StarFive JH7100 SoC.
-+        This also provides an interface to the GPIO pins not used by other
-+        peripherals supporting inputs, outputs, configuring pull-up/pull-down
-+        and interrupts on input changes.
-+
- config PINCTRL_STMFX
-       tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
-       depends on I2C
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -38,6 +38,7 @@ obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-
- obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
- obj-$(CONFIG_PINCTRL_TB10X)   += pinctrl-tb10x.o
- obj-$(CONFIG_PINCTRL_ST)      += pinctrl-st.o
-+obj-$(CONFIG_PINCTRL_STARFIVE)        += pinctrl-starfive.o
- obj-$(CONFIG_PINCTRL_STMFX)   += pinctrl-stmfx.o
- obj-$(CONFIG_PINCTRL_ZYNQ)    += pinctrl-zynq.o
- obj-$(CONFIG_PINCTRL_ZYNQMP)  += pinctrl-zynqmp.o
---- /dev/null
-+++ b/drivers/pinctrl/pinctrl-starfive.c
-@@ -0,0 +1,1354 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Pinctrl / GPIO driver for StarFive JH7100 SoC
-+ *
-+ * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+#include <linux/bits.h>
-+#include <linux/clk.h>
-+#include <linux/gpio/driver.h>
-+#include <linux/io.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+#include <linux/spinlock.h>
-+
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinmux.h>
-+
-+#include <dt-bindings/pinctrl/pinctrl-starfive.h>
-+
-+#include "core.h"
-+#include "pinctrl-utils.h"
-+#include "pinmux.h"
-+#include "pinconf.h"
-+
-+#define DRIVER_NAME "pinctrl-starfive"
-+
-+/*
-+ * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
-+ * https://github.com/starfive-tech/JH7100_Docs
-+ */
-+#define NR_GPIOS      64
-+
-+/*
-+ * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
-+ * are enabled. If set to 0 the GPIO interrupts are disabled.
-+ */
-+#define GPIOEN                0x000
-+
-+/*
-+ * The following 32-bit registers come in pairs, but only the offset of the
-+ * first register is defined. The first controls (interrupts for) GPIO 0-31 and
-+ * the second GPIO 32-63.
-+ */
-+
-+/*
-+ * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
-+ * interrupt is level-triggered.
-+ */
-+#define GPIOIS                0x010
-+
-+/*
-+ * Edge-Trigger Interrupt Type.  If set to 1 the interrupt gets triggered on
-+ * both positive and negative edges. If set to 0 the interrupt is triggered by a
-+ * single edge.
-+ */
-+#define GPIOIBE               0x018
-+
-+/*
-+ * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
-+ * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
-+ * interrupt is triggered on a falling edge (edge-triggered) or low level
-+ * (level-triggered).
-+ */
-+#define GPIOIEV               0x020
-+
-+/*
-+ * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0
-+ * the interrupt is disabled (masked). Note that the current documentation is
-+ * wrong and says the exct opposite of this.
-+ */
-+#define GPIOIE                0x028
-+
-+/*
-+ * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
-+ * interrupt.
-+ */
-+#define GPIOIC                0x030
-+
-+/*
-+ * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
-+ */
-+#define GPIORIS               0x038
-+
-+/*
-+ * Interrupt Status after Masking. A 1 means the configured edge or level was
-+ * detected and not masked.
-+ */
-+#define GPIOMIS               0x040
-+
-+/*
-+ * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
-+ * a digital 1 and if 0 the pin is a digital 0.
-+ */
-+#define GPIODIN               0x048
-+
-+/*
-+ * From the data sheet section 12.2, there are 64 32-bit output data registers
-+ * and 64 output enable registers. Output data and output enable registers for
-+ * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
-+ * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c.  The stride
-+ * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
-+ * and GPOn_DOEN_CFG is 0x54 + 8n.
-+ */
-+#define GPON_DOUT_CFG 0x050
-+#define GPON_DOEN_CFG 0x054
-+
-+/*
-+ * From Section 12.3, there are 75 input signal configuration registers which
-+ * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with
-+ * GPI_USB_OVER_CURRENT_CFG 0x378
-+ */
-+#define GPI_CFG_OFFSET        0x250
-+
-+/*
-+ * Pad Control Bits. There are 16 pad control bits for each pin located in 103
-+ * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
-+ * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16
-+ * bit of each register.
-+ */
-+#define PAD_SLEW_RATE_MASK            GENMASK(11, 9)
-+#define PAD_SLEW_RATE_POS             9
-+#define PAD_BIAS_STRONG_PULL_UP               BIT(8)
-+#define PAD_INPUT_ENABLE              BIT(7)
-+#define PAD_INPUT_SCHMITT_ENABLE      BIT(6)
-+#define PAD_BIAS_DISABLE              BIT(5)
-+#define PAD_BIAS_PULL_DOWN            BIT(4)
-+#define PAD_BIAS_MASK \
-+      (PAD_BIAS_STRONG_PULL_UP | \
-+       PAD_BIAS_DISABLE | \
-+       PAD_BIAS_PULL_DOWN)
-+#define PAD_DRIVE_STRENGTH_MASK               GENMASK(3, 0)
-+#define PAD_DRIVE_STRENGTH_POS                0
-+
-+/*
-+ * From Section 11, the IO_PADSHARE_SEL register can be programmed to select
-+ * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
-+ * PAD_GPIO pads. This is a global setting.
-+ */
-+#define IO_PADSHARE_SEL                       0x1a0
-+
-+/*
-+ * This just needs to be some number such that when
-+ * sfp->gpio.pin_base = PAD_INVALID_GPIO then
-+ * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
-+ * That is it should underflow and return something >= NR_GPIOS.
-+ */
-+#define PAD_INVALID_GPIO              0x10000
-+
-+/*
-+ * The packed pinmux values from the device tree look like this:
-+ *
-+ *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
-+ *  |  dout   |  doen   |  din   | dout rev | doen rev | gpio nr |
-+ *
-+ * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this:
-+ *
-+ *  |      31       | 30 - 8 |   7 - 0   |
-+ *  | dout/doen rev | unused | dout/doen |
-+ */
-+static unsigned int starfive_pinmux_to_gpio(u32 v)
-+{
-+      return v & (NR_GPIOS - 1);
-+}
-+
-+static u32 starfive_pinmux_to_dout(u32 v)
-+{
-+      return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));
-+}
-+
-+static u32 starfive_pinmux_to_doen(u32 v)
-+{
-+      return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));
-+}
-+
-+static u32 starfive_pinmux_to_din(u32 v)
-+{
-+      return (v >> 8) & GENMASK(7, 0);
-+}
-+
-+/*
-+ * The maximum GPIO output current depends on the chosen drive strength:
-+ *
-+ *  DS:   0     1     2     3     4     5     6     7
-+ *  mA:  14.2  21.2  28.2  35.2  42.2  49.1  56.0  62.8
-+ *
-+ * After rounding that is 7*DS + 14 mA
-+ */
-+static u32 starfive_drive_strength_to_max_mA(u16 ds)
-+{
-+      return 7 * ds + 14;
-+}
-+
-+static u16 starfive_drive_strength_from_max_mA(u32 i)
-+{
-+      return (clamp(i, 14U, 63U) - 14) / 7;
-+}
-+
-+struct starfive_pinctrl {
-+      struct gpio_chip gc;
-+      struct pinctrl_gpio_range gpios;
-+      raw_spinlock_t lock;
-+      void __iomem *base;
-+      void __iomem *padctl;
-+      struct pinctrl_dev *pctl;
-+};
-+
-+static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
-+                                              unsigned int pin)
-+{
-+      return pin - sfp->gpios.pin_base;
-+}
-+
-+static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,
-+                                              unsigned int gpio)
-+{
-+      return sfp->gpios.pin_base + gpio;
-+}
-+
-+static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
-+{
-+      struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-+
-+      return container_of(gc, struct starfive_pinctrl, gc);
-+}
-+
-+static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
-+{
-+      struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-+
-+      return container_of(gc, struct starfive_pinctrl, gc);
-+}
-+
-+static const struct pinctrl_pin_desc starfive_pins[] = {
-+      PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),
-+      PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),
-+      PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),
-+      PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),
-+      PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),
-+      PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),
-+      PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),
-+      PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),
-+      PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),
-+      PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),
-+      PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),
-+      PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),
-+      PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),
-+      PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),
-+      PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),
-+      PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),
-+      PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),
-+      PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),
-+      PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),
-+      PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),
-+      PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),
-+      PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),
-+      PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),
-+      PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),
-+      PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),
-+      PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),
-+      PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),
-+      PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),
-+      PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),
-+      PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),
-+      PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),
-+      PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),
-+      PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),
-+      PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),
-+      PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),
-+      PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),
-+      PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),
-+      PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),
-+      PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),
-+      PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),
-+      PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),
-+      PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),
-+      PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),
-+      PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),
-+      PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),
-+      PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),
-+      PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),
-+      PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),
-+      PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),
-+      PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),
-+      PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),
-+      PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),
-+      PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),
-+      PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),
-+      PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),
-+      PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),
-+      PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),
-+      PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),
-+      PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),
-+      PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),
-+      PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),
-+      PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),
-+      PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),
-+      PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"),
-+      PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"),
-+};
-+
-+#ifdef CONFIG_DEBUG_FS
-+static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
-+                                struct seq_file *s,
-+                                unsigned int pin)
-+{
-+      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
-+      unsigned int gpio = starfive_pin_to_gpio(sfp, pin);
-+      void __iomem *reg;
-+      u32 dout, doen;
-+
-+      if (gpio >= NR_GPIOS)
-+              return;
-+
-+      reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;
-+      dout = readl_relaxed(reg + 0x000);
-+      doen = readl_relaxed(reg + 0x004);
-+
-+      seq_printf(s, "dout=%lu%s doen=%lu%s",
-+                 dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",
-+                 doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");
-+}
-+#else
-+#define starfive_pin_dbg_show NULL
-+#endif
-+
-+static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
-+                                 struct device_node *np,
-+                                 struct pinctrl_map **maps,
-+                                 unsigned int *num_maps)
-+{
-+      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
-+      struct device *dev = sfp->gc.parent;
-+      struct device_node *child;
-+      struct pinctrl_map *map;
-+      const char **pgnames;
-+      const char *grpname;
-+      u32 *pinmux;
-+      int ngroups;
-+      int *pins;
-+      int nmaps;
-+      int ret;
-+
-+      nmaps = 0;
-+      ngroups = 0;
-+      for_each_child_of_node(np, child) {
-+              int npinmux = of_property_count_u32_elems(child, "pinmux");
-+              int npins   = of_property_count_u32_elems(child, "pins");
-+
-+              if (npinmux > 0 && npins > 0) {
-+                      dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
-+                              np, child);
-+                      of_node_put(child);
-+                      return -EINVAL;
-+              }
-+              if (npinmux == 0 && npins == 0) {
-+                      dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
-+                              np, child);
-+                      of_node_put(child);
-+                      return -EINVAL;
-+              }
-+
-+              if (npinmux > 0)
-+                      nmaps += 2;
-+              else
-+                      nmaps += 1;
-+              ngroups += 1;
-+      }
-+
-+      pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
-+      if (!pgnames)
-+              return -ENOMEM;
-+
-+      map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
-+      if (!map)
-+              return -ENOMEM;
-+
-+      nmaps = 0;
-+      ngroups = 0;
-+      for_each_child_of_node(np, child) {
-+              int npins;
-+              int i;
-+
-+              grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
-+              if (!grpname) {
-+                      ret = -ENOMEM;
-+                      goto put_child;
-+              }
-+
-+              pgnames[ngroups++] = grpname;
-+
-+              if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) {
-+                      pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
-+                      if (!pins) {
-+                              ret = -ENOMEM;
-+                              goto put_child;
-+                      }
-+
-+                      pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
-+                      if (!pinmux) {
-+                              ret = -ENOMEM;
-+                              goto put_child;
-+                      }
-+
-+                      ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
-+                      if (ret)
-+                              goto put_child;
-+
-+                      for (i = 0; i < npins; i++) {
-+                              unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
-+
-+                              pins[i] = starfive_gpio_to_pin(sfp, gpio);
-+                      }
-+
-+                      map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
-+                      map[nmaps].data.mux.function = np->name;
-+                      map[nmaps].data.mux.group = grpname;
-+                      nmaps += 1;
-+              } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) {
-+                      pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
-+                      if (!pins) {
-+                              ret = -ENOMEM;
-+                              goto put_child;
-+                      }
-+
-+                      pinmux = NULL;
-+
-+                      for (i = 0; i < npins; i++) {
-+                              u32 v;
-+
-+                              ret = of_property_read_u32_index(child, "pins", i, &v);
-+                              if (ret)
-+                                      goto put_child;
-+                              pins[i] = v;
-+                      }
-+              } else {
-+                      ret = -EINVAL;
-+                      goto put_child;
-+              }
-+
-+              ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
-+              if (ret < 0) {
-+                      dev_err(dev, "error adding group %s: %d\n", grpname, ret);
-+                      goto put_child;
-+              }
-+
-+              ret = pinconf_generic_parse_dt_config(child, pctldev,
-+                                                    &map[nmaps].data.configs.configs,
-+                                                    &map[nmaps].data.configs.num_configs);
-+              if (ret) {
-+                      dev_err(dev, "error parsing pin config of group %s: %d\n",
-+                              grpname, ret);
-+                      goto put_child;
-+              }
-+
-+              /* don't create a map if there are no pinconf settings */
-+              if (map[nmaps].data.configs.num_configs == 0)
-+                      continue;
-+
-+              map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
-+              map[nmaps].data.configs.group_or_pin = grpname;
-+              nmaps += 1;
-+      }
-+
-+      ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
-+      if (ret < 0) {
-+              dev_err(dev, "error adding function %s: %d\n", np->name, ret);
-+              goto free_map;
-+      }
-+
-+      *maps = map;
-+      *num_maps = nmaps;
-+      return 0;
-+
-+put_child:
-+      of_node_put(child);
-+free_map:
-+      pinctrl_utils_free_map(pctldev, map, nmaps);
-+      return ret;
-+}
-+
-+static const struct pinctrl_ops starfive_pinctrl_ops = {
-+      .get_groups_count = pinctrl_generic_get_group_count,
-+      .get_group_name = pinctrl_generic_get_group_name,
-+      .get_group_pins = pinctrl_generic_get_group_pins,
-+      .pin_dbg_show = starfive_pin_dbg_show,
-+      .dt_node_to_map = starfive_dt_node_to_map,
-+      .dt_free_map = pinctrl_utils_free_map,
-+};
-+
-+static int starfive_set_mux(struct pinctrl_dev *pctldev,
-+                          unsigned int fsel, unsigned int gsel)
-+{
-+      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
-+      struct device *dev = sfp->gc.parent;
-+      const struct group_desc *group;
-+      const u32 *pinmux;
-+      unsigned int i;
-+
-+      group = pinctrl_generic_get_group(pctldev, gsel);
-+      if (!group)
-+              return -EINVAL;
-+
-+      pinmux = group->data;
-+      for (i = 0; i < group->num_pins; i++) {
-+              u32 v = pinmux[i];
-+              unsigned int gpio = starfive_pinmux_to_gpio(v);
-+              u32 dout = starfive_pinmux_to_dout(v);
-+              u32 doen = starfive_pinmux_to_doen(v);
-+              u32 din = starfive_pinmux_to_din(v);
-+              void __iomem *reg_dout;
-+              void __iomem *reg_doen;
-+              void __iomem *reg_din;
-+              unsigned long flags;
-+
-+              dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n",
-+                      gpio, dout, doen, din);
-+
-+              reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
-+              reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
-+              if (din != GPI_NONE)
-+                      reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;
-+              else
-+                      reg_din = NULL;
-+
-+              raw_spin_lock_irqsave(&sfp->lock, flags);
-+              writel_relaxed(dout, reg_dout);
-+              writel_relaxed(doen, reg_doen);
-+              if (reg_din)
-+                      writel_relaxed(gpio + 2, reg_din);
-+              raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+      }
-+
-+      return 0;
-+}
-+
-+static const struct pinmux_ops starfive_pinmux_ops = {
-+      .get_functions_count = pinmux_generic_get_function_count,
-+      .get_function_name = pinmux_generic_get_function_name,
-+      .get_function_groups = pinmux_generic_get_function_groups,
-+      .set_mux = starfive_set_mux,
-+      .strict = true,
-+};
-+
-+static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,
-+                             unsigned int pin)
-+{
-+      void __iomem *reg = sfp->padctl + 4 * (pin / 2);
-+      int shift = 16 * (pin % 2);
-+
-+      return readl_relaxed(reg) >> shift;
-+}
-+
-+static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,
-+                              unsigned int pin,
-+                              u16 _mask, u16 _value)
-+{
-+      void __iomem *reg = sfp->padctl + 4 * (pin / 2);
-+      int shift = 16 * (pin % 2);
-+      u32 mask = (u32)_mask << shift;
-+      u32 value = (u32)_value << shift;
-+      unsigned long flags;
-+
-+      dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);
-+
-+      raw_spin_lock_irqsave(&sfp->lock, flags);
-+      value |= readl_relaxed(reg) & ~mask;
-+      writel_relaxed(value, reg);
-+      raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+}
-+
-+#define PIN_CONFIG_STARFIVE_STRONG_PULL_UP    (PIN_CONFIG_END + 1)
-+
-+static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {
-+      { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
-+};
-+
-+#ifdef CONFIG_DEBUG_FS
-+static const struct pin_config_item starfive_pinconf_custom_conf_items[] = {
-+      PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
-+};
-+
-+static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) ==
-+            ARRAY_SIZE(starfive_pinconf_custom_params));
-+#else
-+#define starfive_pinconf_custom_conf_items NULL
-+#endif
-+
-+static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
-+                              unsigned int pin, unsigned long *config)
-+{
-+      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
-+      int param = pinconf_to_config_param(*config);
-+      u16 value = starfive_padctl_get(sfp, pin);
-+      bool enabled;
-+      u32 arg;
-+
-+      switch (param) {
-+      case PIN_CONFIG_BIAS_DISABLE:
-+              enabled = value & PAD_BIAS_DISABLE;
-+              arg = 0;
-+              break;
-+      case PIN_CONFIG_BIAS_PULL_DOWN:
-+              enabled = value & PAD_BIAS_PULL_DOWN;
-+              arg = 1;
-+              break;
-+      case PIN_CONFIG_BIAS_PULL_UP:
-+              enabled = !(value & PAD_BIAS_MASK);
-+              arg = 1;
-+              break;
-+      case PIN_CONFIG_DRIVE_STRENGTH:
-+              enabled = value & PAD_DRIVE_STRENGTH_MASK;
-+              arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK);
-+              break;
-+      case PIN_CONFIG_INPUT_ENABLE:
-+              enabled = value & PAD_INPUT_ENABLE;
-+              arg = enabled;
-+              break;
-+      case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
-+              enabled = value & PAD_INPUT_SCHMITT_ENABLE;
-+              arg = enabled;
-+              break;
-+      case PIN_CONFIG_SLEW_RATE:
-+              enabled = value & PAD_SLEW_RATE_MASK;
-+              arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS;
-+              break;
-+      case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
-+              enabled = value & PAD_BIAS_STRONG_PULL_UP;
-+              arg = enabled;
-+              break;
-+      default:
-+              return -ENOTSUPP;
-+      }
-+
-+      *config = pinconf_to_config_packed(param, arg);
-+      return enabled ? 0 : -EINVAL;
-+}
-+
-+static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
-+                                    unsigned int gsel, unsigned long *config)
-+{
-+      const struct group_desc *group;
-+
-+      group = pinctrl_generic_get_group(pctldev, gsel);
-+      if (!group)
-+              return -EINVAL;
-+
-+      return starfive_pinconf_get(pctldev, group->pins[0], config);
-+}
-+
-+static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
-+                                    unsigned int gsel,
-+                                    unsigned long *configs,
-+                                    unsigned int num_configs)
-+{
-+      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
-+      const struct group_desc *group;
-+      u16 mask, value;
-+      int i;
-+
-+      group = pinctrl_generic_get_group(pctldev, gsel);
-+      if (!group)
-+              return -EINVAL;
-+
-+      mask = 0;
-+      value = 0;
-+      for (i = 0; i < num_configs; i++) {
-+              int param = pinconf_to_config_param(configs[i]);
-+              u32 arg = pinconf_to_config_argument(configs[i]);
-+
-+              switch (param) {
-+              case PIN_CONFIG_BIAS_DISABLE:
-+                      mask |= PAD_BIAS_MASK;
-+                      value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE;
-+                      break;
-+              case PIN_CONFIG_BIAS_PULL_DOWN:
-+                      if (arg == 0)
-+                              return -ENOTSUPP;
-+                      mask |= PAD_BIAS_MASK;
-+                      value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN;
-+                      break;
-+              case PIN_CONFIG_BIAS_PULL_UP:
-+                      if (arg == 0)
-+                              return -ENOTSUPP;
-+                      mask |= PAD_BIAS_MASK;
-+                      value = value & ~PAD_BIAS_MASK;
-+                      break;
-+              case PIN_CONFIG_DRIVE_STRENGTH:
-+                      mask |= PAD_DRIVE_STRENGTH_MASK;
-+                      value = (value & ~PAD_DRIVE_STRENGTH_MASK) |
-+                              starfive_drive_strength_from_max_mA(arg);
-+                      break;
-+              case PIN_CONFIG_INPUT_ENABLE:
-+                      mask |= PAD_INPUT_ENABLE;
-+                      if (arg)
-+                              value |= PAD_INPUT_ENABLE;
-+                      else
-+                              value &= ~PAD_INPUT_ENABLE;
-+                      break;
-+              case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
-+                      mask |= PAD_INPUT_SCHMITT_ENABLE;
-+                      if (arg)
-+                              value |= PAD_INPUT_SCHMITT_ENABLE;
-+                      else
-+                              value &= ~PAD_INPUT_SCHMITT_ENABLE;
-+                      break;
-+              case PIN_CONFIG_SLEW_RATE:
-+                      mask |= PAD_SLEW_RATE_MASK;
-+                      value = (value & ~PAD_SLEW_RATE_MASK) |
-+                              ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK);
-+                      break;
-+              case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
-+                      if (arg) {
-+                              mask |= PAD_BIAS_MASK;
-+                              value = (value & ~PAD_BIAS_MASK) |
-+                                      PAD_BIAS_STRONG_PULL_UP;
-+                      } else {
-+                              mask |= PAD_BIAS_STRONG_PULL_UP;
-+                              value = value & ~PAD_BIAS_STRONG_PULL_UP;
-+                      }
-+                      break;
-+              default:
-+                      return -ENOTSUPP;
-+              }
-+      }
-+
-+      for (i = 0; i < group->num_pins; i++)
-+              starfive_padctl_rmw(sfp, group->pins[i], mask, value);
-+
-+      return 0;
-+}
-+
-+#ifdef CONFIG_DEBUG_FS
-+static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
-+                                    struct seq_file *s, unsigned int pin)
-+{
-+      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
-+      u16 value = starfive_padctl_get(sfp, pin);
-+
-+      seq_printf(s, " (0x%03x)", value);
-+}
-+#else
-+#define starfive_pinconf_dbg_show NULL
-+#endif
-+
-+static const struct pinconf_ops starfive_pinconf_ops = {
-+      .pin_config_get = starfive_pinconf_get,
-+      .pin_config_group_get = starfive_pinconf_group_get,
-+      .pin_config_group_set = starfive_pinconf_group_set,
-+      .pin_config_dbg_show = starfive_pinconf_dbg_show,
-+      .is_generic = true,
-+};
-+
-+static struct pinctrl_desc starfive_desc = {
-+      .name = DRIVER_NAME,
-+      .pins = starfive_pins,
-+      .npins = ARRAY_SIZE(starfive_pins),
-+      .pctlops = &starfive_pinctrl_ops,
-+      .pmxops = &starfive_pinmux_ops,
-+      .confops = &starfive_pinconf_ops,
-+      .owner = THIS_MODULE,
-+      .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params),
-+      .custom_params = starfive_pinconf_custom_params,
-+      .custom_conf_items = starfive_pinconf_custom_conf_items,
-+};
-+
-+static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio)
-+{
-+      return pinctrl_gpio_request(gc->base + gpio);
-+}
-+
-+static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio)
-+{
-+      pinctrl_gpio_free(gc->base + gpio);
-+}
-+
-+static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
-+{
-+      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
-+      void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
-+
-+      if (readl_relaxed(doen) == GPO_ENABLE)
-+              return GPIO_LINE_DIRECTION_OUT;
-+
-+      return GPIO_LINE_DIRECTION_IN;
-+}
-+
-+static int starfive_gpio_direction_input(struct gpio_chip *gc,
-+                                       unsigned int gpio)
-+{
-+      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
-+      void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
-+      unsigned long flags;
-+
-+      /* enable input and schmitt trigger */
-+      starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
-+                          PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
-+                          PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE);
-+
-+      raw_spin_lock_irqsave(&sfp->lock, flags);
-+      writel_relaxed(GPO_DISABLE, doen);
-+      raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+      return 0;
-+}
-+
-+static int starfive_gpio_direction_output(struct gpio_chip *gc,
-+                                        unsigned int gpio, int value)
-+{
-+      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
-+      void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
-+      void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
-+      unsigned long flags;
-+
-+      raw_spin_lock_irqsave(&sfp->lock, flags);
-+      writel_relaxed(value, dout);
-+      writel_relaxed(GPO_ENABLE, doen);
-+      raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+
-+      /* disable input, schmitt trigger and bias */
-+      starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
-+                          PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
-+                          PAD_BIAS_DISABLE);
-+
-+      return 0;
-+}
-+
-+static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)
-+{
-+      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
-+      void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);
-+
-+      return !!(readl_relaxed(din) & BIT(gpio % 32));
-+}
-+
-+static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
-+                            int value)
-+{
-+      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
-+      void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
-+      unsigned long flags;
-+
-+      raw_spin_lock_irqsave(&sfp->lock, flags);
-+      writel_relaxed(value, dout);
-+      raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+}
-+
-+static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
-+                                  unsigned long config)
-+{
-+      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
-+      u32 arg = pinconf_to_config_argument(config);
-+      u16 value;
-+      u16 mask;
-+
-+      switch (pinconf_to_config_param(config)) {
-+      case PIN_CONFIG_BIAS_DISABLE:
-+              mask  = PAD_BIAS_MASK;
-+              value = PAD_BIAS_DISABLE;
-+              break;
-+      case PIN_CONFIG_BIAS_PULL_DOWN:
-+              if (arg == 0)
-+                      return -ENOTSUPP;
-+              mask  = PAD_BIAS_MASK;
-+              value = PAD_BIAS_PULL_DOWN;
-+              break;
-+      case PIN_CONFIG_BIAS_PULL_UP:
-+              if (arg == 0)
-+                      return -ENOTSUPP;
-+              mask  = PAD_BIAS_MASK;
-+              value = 0;
-+              break;
-+      case PIN_CONFIG_DRIVE_PUSH_PULL:
-+              return 0;
-+      case PIN_CONFIG_INPUT_ENABLE:
-+              mask  = PAD_INPUT_ENABLE;
-+              value = arg ? PAD_INPUT_ENABLE : 0;
-+              break;
-+      case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
-+              mask  = PAD_INPUT_SCHMITT_ENABLE;
-+              value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0;
-+              break;
-+      default:
-+              return -ENOTSUPP;
-+      };
-+
-+      starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
-+      return 0;
-+}
-+
-+static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)
-+{
-+      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
-+
-+      sfp->gpios.name = sfp->gc.label;
-+      sfp->gpios.base = sfp->gc.base;
-+      /*
-+       * sfp->gpios.pin_base depends on the chosen signal group
-+       * and is set in starfive_probe()
-+       */
-+      sfp->gpios.npins = NR_GPIOS;
-+      sfp->gpios.gc = &sfp->gc;
-+      pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
-+      return 0;
-+}
-+
-+static void starfive_irq_ack(struct irq_data *d)
-+{
-+      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
-+      irq_hw_number_t gpio = irqd_to_hwirq(d);
-+      void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
-+      u32 mask = BIT(gpio % 32);
-+      unsigned long flags;
-+
-+      raw_spin_lock_irqsave(&sfp->lock, flags);
-+      writel_relaxed(mask, ic);
-+      raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+}
-+
-+static void starfive_irq_mask(struct irq_data *d)
-+{
-+      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
-+      irq_hw_number_t gpio = irqd_to_hwirq(d);
-+      void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
-+      u32 mask = BIT(gpio % 32);
-+      unsigned long flags;
-+      u32 value;
-+
-+      raw_spin_lock_irqsave(&sfp->lock, flags);
-+      value = readl_relaxed(ie) & ~mask;
-+      writel_relaxed(value, ie);
-+      raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+}
-+
-+static void starfive_irq_mask_ack(struct irq_data *d)
-+{
-+      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
-+      irq_hw_number_t gpio = irqd_to_hwirq(d);
-+      void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
-+      void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
-+      u32 mask = BIT(gpio % 32);
-+      unsigned long flags;
-+      u32 value;
-+
-+      raw_spin_lock_irqsave(&sfp->lock, flags);
-+      value = readl_relaxed(ie) & ~mask;
-+      writel_relaxed(value, ie);
-+      writel_relaxed(mask, ic);
-+      raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+}
-+
-+static void starfive_irq_unmask(struct irq_data *d)
-+{
-+      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
-+      irq_hw_number_t gpio = irqd_to_hwirq(d);
-+      void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
-+      u32 mask = BIT(gpio % 32);
-+      unsigned long flags;
-+      u32 value;
-+
-+      raw_spin_lock_irqsave(&sfp->lock, flags);
-+      value = readl_relaxed(ie) | mask;
-+      writel_relaxed(value, ie);
-+      raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+}
-+
-+static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
-+{
-+      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
-+      irq_hw_number_t gpio = irqd_to_hwirq(d);
-+      void __iomem *base = sfp->base + 4 * (gpio / 32);
-+      u32 mask = BIT(gpio % 32);
-+      u32 irq_type, edge_both, polarity;
-+      unsigned long flags;
-+
-+      switch (trigger) {
-+      case IRQ_TYPE_EDGE_RISING:
-+              irq_type  = mask; /* 1: edge triggered */
-+              edge_both = 0;    /* 0: single edge */
-+              polarity  = mask; /* 1: rising edge */
-+              break;
-+      case IRQ_TYPE_EDGE_FALLING:
-+              irq_type  = mask; /* 1: edge triggered */
-+              edge_both = 0;    /* 0: single edge */
-+              polarity  = 0;    /* 0: falling edge */
-+              break;
-+      case IRQ_TYPE_EDGE_BOTH:
-+              irq_type  = mask; /* 1: edge triggered */
-+              edge_both = mask; /* 1: both edges */
-+              polarity  = 0;    /* 0: ignored */
-+              break;
-+      case IRQ_TYPE_LEVEL_HIGH:
-+              irq_type  = 0;    /* 0: level triggered */
-+              edge_both = 0;    /* 0: ignored */
-+              polarity  = mask; /* 1: high level */
-+              break;
-+      case IRQ_TYPE_LEVEL_LOW:
-+              irq_type  = 0;    /* 0: level triggered */
-+              edge_both = 0;    /* 0: ignored */
-+              polarity  = 0;    /* 0: low level */
-+              break;
-+      default:
-+              return -EINVAL;
-+      }
-+
-+      if (trigger & IRQ_TYPE_EDGE_BOTH)
-+              irq_set_handler_locked(d, handle_edge_irq);
-+      else
-+              irq_set_handler_locked(d, handle_level_irq);
-+
-+      raw_spin_lock_irqsave(&sfp->lock, flags);
-+      irq_type |= readl_relaxed(base + GPIOIS) & ~mask;
-+      writel_relaxed(irq_type, base + GPIOIS);
-+      edge_both |= readl_relaxed(base + GPIOIBE) & ~mask;
-+      writel_relaxed(edge_both, base + GPIOIBE);
-+      polarity |= readl_relaxed(base + GPIOIEV) & ~mask;
-+      writel_relaxed(polarity, base + GPIOIEV);
-+      raw_spin_unlock_irqrestore(&sfp->lock, flags);
-+      return 0;
-+}
-+
-+static struct irq_chip starfive_irq_chip = {
-+      .irq_ack = starfive_irq_ack,
-+      .irq_mask = starfive_irq_mask,
-+      .irq_mask_ack = starfive_irq_mask_ack,
-+      .irq_unmask = starfive_irq_unmask,
-+      .irq_set_type = starfive_irq_set_type,
-+      .flags = IRQCHIP_SET_TYPE_MASKED,
-+};
-+
-+static void starfive_gpio_irq_handler(struct irq_desc *desc)
-+{
-+      struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
-+      struct irq_chip *chip = irq_desc_get_chip(desc);
-+      unsigned long mis;
-+      unsigned int pin;
-+
-+      chained_irq_enter(chip, desc);
-+
-+      mis = readl_relaxed(sfp->base + GPIOMIS + 0);
-+      for_each_set_bit(pin, &mis, 32)
-+              generic_handle_domain_irq(sfp->gc.irq.domain, pin);
-+
-+      mis = readl_relaxed(sfp->base + GPIOMIS + 4);
-+      for_each_set_bit(pin, &mis, 32)
-+              generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
-+
-+      chained_irq_exit(chip, desc);
-+}
-+
-+static int starfive_gpio_init_hw(struct gpio_chip *gc)
-+{
-+      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
-+
-+      /* mask all GPIO interrupts */
-+      writel(0, sfp->base + GPIOIE + 0);
-+      writel(0, sfp->base + GPIOIE + 4);
-+      /* clear edge interrupt flags */
-+      writel(~0U, sfp->base + GPIOIC + 0);
-+      writel(~0U, sfp->base + GPIOIC + 4);
-+      /* enable GPIO interrupts */
-+      writel(1, sfp->base + GPIOEN);
-+      return 0;
-+}
-+
-+static void starfive_disable_clock(void *data)
-+{
-+      clk_disable_unprepare(data);
-+}
-+
-+static int starfive_probe(struct platform_device *pdev)
-+{
-+      struct device *dev = &pdev->dev;
-+      struct starfive_pinctrl *sfp;
-+      struct reset_control *rst;
-+      struct clk *clk;
-+      u32 value;
-+      int ret;
-+
-+      sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
-+      if (!sfp)
-+              return -ENOMEM;
-+
-+      sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
-+      if (IS_ERR(sfp->base))
-+              return PTR_ERR(sfp->base);
-+
-+      sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
-+      if (IS_ERR(sfp->padctl))
-+              return PTR_ERR(sfp->padctl);
-+
-+      clk = devm_clk_get(dev, NULL);
-+      if (IS_ERR(clk))
-+              return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
-+
-+      rst = devm_reset_control_get_exclusive(dev, NULL);
-+      if (IS_ERR(rst))
-+              return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
-+
-+      ret = clk_prepare_enable(clk);
-+      if (ret)
-+              return dev_err_probe(dev, ret, "could not enable clock\n");
-+
-+      ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
-+      if (ret)
-+              return ret;
-+
-+      /*
-+       * We don't want to assert reset and risk undoing pin muxing for the
-+       * early boot serial console, but let's make sure the reset line is
-+       * deasserted in case someone runs a really minimal bootloader.
-+       */
-+      ret = reset_control_deassert(rst);
-+      if (ret)
-+              return dev_err_probe(dev, ret, "could not deassert reset\n");
-+
-+      platform_set_drvdata(pdev, sfp);
-+      sfp->gc.parent = dev;
-+      raw_spin_lock_init(&sfp->lock);
-+
-+      ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
-+      if (ret)
-+              return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
-+
-+      if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {
-+              if (value > 6)
-+                      return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
-+              writel(value, sfp->padctl + IO_PADSHARE_SEL);
-+      }
-+
-+      value = readl(sfp->padctl + IO_PADSHARE_SEL);
-+      switch (value) {
-+      case 0:
-+              sfp->gpios.pin_base = PAD_INVALID_GPIO;
-+              goto out_pinctrl_enable;
-+      case 1:
-+              sfp->gpios.pin_base = PAD_GPIO(0);
-+              break;
-+      case 2:
-+              sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
-+              break;
-+      case 3:
-+              sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
-+              break;
-+      case 4: case 5: case 6:
-+              sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
-+              break;
-+      default:
-+              return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
-+      }
-+
-+      sfp->gc.label = dev_name(dev);
-+      sfp->gc.owner = THIS_MODULE;
-+      sfp->gc.request = starfive_gpio_request;
-+      sfp->gc.free = starfive_gpio_free;
-+      sfp->gc.get_direction = starfive_gpio_get_direction;
-+      sfp->gc.direction_input = starfive_gpio_direction_input;
-+      sfp->gc.direction_output = starfive_gpio_direction_output;
-+      sfp->gc.get = starfive_gpio_get;
-+      sfp->gc.set = starfive_gpio_set;
-+      sfp->gc.set_config = starfive_gpio_set_config;
-+      sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
-+      sfp->gc.base = -1;
-+      sfp->gc.ngpio = NR_GPIOS;
-+
-+      starfive_irq_chip.parent_device = dev;
-+      starfive_irq_chip.name = sfp->gc.label;
-+
-+      sfp->gc.irq.chip = &starfive_irq_chip;
-+      sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
-+      sfp->gc.irq.num_parents = 1;
-+      sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
-+                                         sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
-+      if (!sfp->gc.irq.parents)
-+              return -ENOMEM;
-+      sfp->gc.irq.default_type = IRQ_TYPE_NONE;
-+      sfp->gc.irq.handler = handle_bad_irq;
-+      sfp->gc.irq.init_hw = starfive_gpio_init_hw;
-+
-+      ret = platform_get_irq(pdev, 0);
-+      if (ret < 0)
-+              return ret;
-+      sfp->gc.irq.parents[0] = ret;
-+
-+      ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
-+      if (ret)
-+              return dev_err_probe(dev, ret, "could not register gpiochip\n");
-+
-+out_pinctrl_enable:
-+      return pinctrl_enable(sfp->pctl);
-+}
-+
-+static const struct of_device_id starfive_of_match[] = {
-+      { .compatible = "starfive,jh7100-pinctrl" },
-+      { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, starfive_of_match);
-+
-+static struct platform_driver starfive_pinctrl_driver = {
-+      .probe = starfive_probe,
-+      .driver = {
-+              .name = DRIVER_NAME,
-+              .of_match_table = starfive_of_match,
-+      },
-+};
-+module_platform_driver(starfive_pinctrl_driver);
-+
-+MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs");
-+MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
-+MODULE_LICENSE("GPL v2");

diff --git a/target/linux/visionfive/patches-5.15/0013-dt-bindings-reset-Add-StarFive-JH7100-reset-definiti.patch b/target/linux/visionfive/patches-5.15/0013-dt-bindings-reset-Add-StarFive-JH7100-reset-definiti.patch
new file mode 100644 (file)
index 0000000..63d8ce5
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0013-dt-bindings-reset-Add-StarFive-JH7100-reset-definiti.patch
@@ -0,0 +1,150 @@
+From e891a717991186ea80470709a56426d42c1a0495 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Fri, 25 Jun 2021 11:30:00 +0200
+Subject: [PATCH 13/84] dt-bindings: reset: Add StarFive JH7100 reset
+ definitions
+
+commit 810e287e83b69ff8563bde15cae9120c802ac5d7 upstream.
+
+Add all resets for the StarFive JH7100 reset controller.
+
+Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
+to all definitions.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ include/dt-bindings/reset/starfive-jh7100.h | 126 ++++++++++++++++++++
+ 1 file changed, 126 insertions(+)
+ create mode 100644 include/dt-bindings/reset/starfive-jh7100.h
+
+--- /dev/null
++++ b/include/dt-bindings/reset/starfive-jh7100.h
+@@ -0,0 +1,126 @@
++/* SPDX-License-Identifier: GPL-2.0 OR MIT */
++/*
++ * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
++ */
++
++#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
++#define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
++
++#define JH7100_RSTN_DOM3AHB_BUS               0
++#define JH7100_RSTN_DOM7AHB_BUS               1
++#define JH7100_RST_U74                        2
++#define JH7100_RSTN_U74_AXI           3
++#define JH7100_RSTN_SGDMA2P_AHB               4
++#define JH7100_RSTN_SGDMA2P_AXI               5
++#define JH7100_RSTN_DMA2PNOC_AXI      6
++#define JH7100_RSTN_DLA_AXI           7
++#define JH7100_RSTN_DLANOC_AXI                8
++#define JH7100_RSTN_DLA_APB           9
++#define JH7100_RST_VP6_DRESET         10
++#define JH7100_RST_VP6_BRESET         11
++#define JH7100_RSTN_VP6_AXI           12
++#define JH7100_RSTN_VDECBRG_MAIN      13
++#define JH7100_RSTN_VDEC_AXI          14
++#define JH7100_RSTN_VDEC_BCLK         15
++#define JH7100_RSTN_VDEC_CCLK         16
++#define JH7100_RSTN_VDEC_APB          17
++#define JH7100_RSTN_JPEG_AXI          18
++#define JH7100_RSTN_JPEG_CCLK         19
++#define JH7100_RSTN_JPEG_APB          20
++#define JH7100_RSTN_JPCGC300_MAIN     21
++#define JH7100_RSTN_GC300_2X          22
++#define JH7100_RSTN_GC300_AXI         23
++#define JH7100_RSTN_GC300_AHB         24
++#define JH7100_RSTN_VENC_AXI          25
++#define JH7100_RSTN_VENCBRG_MAIN      26
++#define JH7100_RSTN_VENC_BCLK         27
++#define JH7100_RSTN_VENC_CCLK         28
++#define JH7100_RSTN_VENC_APB          29
++#define JH7100_RSTN_DDRPHY_APB                30
++#define JH7100_RSTN_NOC_ROB           31
++#define JH7100_RSTN_NOC_COG           32
++#define JH7100_RSTN_HIFI4_AXI         33
++#define JH7100_RSTN_HIFI4NOC_AXI      34
++#define JH7100_RST_HIFI4_DRESET               35
++#define JH7100_RST_HIFI4_BRESET               36
++#define JH7100_RSTN_USB_AXI           37
++#define JH7100_RSTN_USBNOC_AXI                38
++#define JH7100_RSTN_SGDMA1P_AXI               39
++#define JH7100_RSTN_DMA1P_AXI         40
++#define JH7100_RSTN_X2C_AXI           41
++#define JH7100_RSTN_NNE_AHB           42
++#define JH7100_RSTN_NNE_AXI           43
++#define JH7100_RSTN_NNENOC_AXI                44
++#define JH7100_RSTN_DLASLV_AXI                45
++#define JH7100_RSTN_DSPX2C_AXI                46
++#define JH7100_RSTN_VIN_SRC           47
++#define JH7100_RSTN_ISPSLV_AXI                48
++#define JH7100_RSTN_VIN_AXI           49
++#define JH7100_RSTN_VINNOC_AXI                50
++#define JH7100_RSTN_ISP0_AXI          51
++#define JH7100_RSTN_ISP0NOC_AXI               52
++#define JH7100_RSTN_ISP1_AXI          53
++#define JH7100_RSTN_ISP1NOC_AXI               54
++#define JH7100_RSTN_VOUT_SRC          55
++#define JH7100_RSTN_DISP_AXI          56
++#define JH7100_RSTN_DISPNOC_AXI               57
++#define JH7100_RSTN_SDIO0_AHB         58
++#define JH7100_RSTN_SDIO1_AHB         59
++#define JH7100_RSTN_GMAC_AHB          60
++#define JH7100_RSTN_SPI2AHB_AHB               61
++#define JH7100_RSTN_SPI2AHB_CORE      62
++#define JH7100_RSTN_EZMASTER_AHB      63
++#define JH7100_RST_E24                        64
++#define JH7100_RSTN_QSPI_AHB          65
++#define JH7100_RSTN_QSPI_CORE         66
++#define JH7100_RSTN_QSPI_APB          67
++#define JH7100_RSTN_SEC_AHB           68
++#define JH7100_RSTN_AES                       69
++#define JH7100_RSTN_PKA                       70
++#define JH7100_RSTN_SHA                       71
++#define JH7100_RSTN_TRNG_APB          72
++#define JH7100_RSTN_OTP_APB           73
++#define JH7100_RSTN_UART0_APB         74
++#define JH7100_RSTN_UART0_CORE                75
++#define JH7100_RSTN_UART1_APB         76
++#define JH7100_RSTN_UART1_CORE                77
++#define JH7100_RSTN_SPI0_APB          78
++#define JH7100_RSTN_SPI0_CORE         79
++#define JH7100_RSTN_SPI1_APB          80
++#define JH7100_RSTN_SPI1_CORE         81
++#define JH7100_RSTN_I2C0_APB          82
++#define JH7100_RSTN_I2C0_CORE         83
++#define JH7100_RSTN_I2C1_APB          84
++#define JH7100_RSTN_I2C1_CORE         85
++#define JH7100_RSTN_GPIO_APB          86
++#define JH7100_RSTN_UART2_APB         87
++#define JH7100_RSTN_UART2_CORE                88
++#define JH7100_RSTN_UART3_APB         89
++#define JH7100_RSTN_UART3_CORE                90
++#define JH7100_RSTN_SPI2_APB          91
++#define JH7100_RSTN_SPI2_CORE         92
++#define JH7100_RSTN_SPI3_APB          93
++#define JH7100_RSTN_SPI3_CORE         94
++#define JH7100_RSTN_I2C2_APB          95
++#define JH7100_RSTN_I2C2_CORE         96
++#define JH7100_RSTN_I2C3_APB          97
++#define JH7100_RSTN_I2C3_CORE         98
++#define JH7100_RSTN_WDTIMER_APB               99
++#define JH7100_RSTN_WDT                       100
++#define JH7100_RSTN_TIMER0            101
++#define JH7100_RSTN_TIMER1            102
++#define JH7100_RSTN_TIMER2            103
++#define JH7100_RSTN_TIMER3            104
++#define JH7100_RSTN_TIMER4            105
++#define JH7100_RSTN_TIMER5            106
++#define JH7100_RSTN_TIMER6            107
++#define JH7100_RSTN_VP6INTC_APB               108
++#define JH7100_RSTN_PWM_APB           109
++#define JH7100_RSTN_MSI_APB           110
++#define JH7100_RSTN_TEMP_APB          111
++#define JH7100_RSTN_TEMP_SENSE                112
++#define JH7100_RSTN_SYSERR_APB                113
++
++#define JH7100_RSTN_END                       114
++
++#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */

diff --git a/target/linux/visionfive/patches-5.15/0013-dt-bindings-serial-snps-dw-apb-uart-Add-JH7100-uarts.patch b/target/linux/visionfive/patches-5.15/0013-dt-bindings-serial-snps-dw-apb-uart-Add-JH7100-uarts.patch
deleted file mode 100644 (file)
index 0e77bf5..0000000
--- a/target/linux/visionfive/patches-5.15/0013-dt-bindings-serial-snps-dw-apb-uart-Add-JH7100-uarts.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From d0b65b1500973fef840dbc4bb9f9c237db2b761f Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Thu, 7 Oct 2021 14:24:29 +0200
-Subject: [PATCH 13/16] dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
-
-Add compatibles for the StarFive JH7100 uarts.
-
-Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- .../devicetree/bindings/serial/snps-dw-apb-uart.yaml         | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
-+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
-@@ -40,6 +40,11 @@ properties:
-               - brcm,bcm11351-dw-apb-uart
-               - brcm,bcm21664-dw-apb-uart
-           - const: snps,dw-apb-uart
-+      - items:
-+          - enum:
-+              - starfive,jh7100-hsuart
-+              - starfive,jh7100-uart
-+          - const: snps,dw-apb-uart
-       - const: snps,dw-apb-uart
- 
-   reg:

diff --git a/target/linux/visionfive/patches-5.15/0014-dt-bindings-reset-Add-Starfive-JH7100-reset-bindings.patch b/target/linux/visionfive/patches-5.15/0014-dt-bindings-reset-Add-Starfive-JH7100-reset-bindings.patch
new file mode 100644 (file)
index 0000000..fb2ea71
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0014-dt-bindings-reset-Add-Starfive-JH7100-reset-bindings.patch
@@ -0,0 +1,59 @@
+From 763e6f4b1343ac389f62ef307250eb0a5ec17cd3 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 19 Sep 2021 14:34:34 +0200
+Subject: [PATCH 14/84] dt-bindings: reset: Add Starfive JH7100 reset bindings
+
+commit d7d456a5201d2e707318bbdc4fb69a3407eed29e upstream.
+
+Add bindings for the reset controller on the JH7100 RISC-V SoC by
+StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../bindings/reset/starfive,jh7100-reset.yaml | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+@@ -0,0 +1,38 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7100 SoC Reset Controller Device Tree Bindings
++
++maintainers:
++  - Emil Renner Berthing <kernel@esmil.dk>
++
++properties:
++  compatible:
++    enum:
++      - starfive,jh7100-reset
++
++  reg:
++    maxItems: 1
++
++  "#reset-cells":
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - "#reset-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    reset-controller@11840000 {
++        compatible = "starfive,jh7100-reset";
++        reg = <0x11840000 0x10000>;
++        #reset-cells = <1>;
++    };
++
++...

diff --git a/target/linux/visionfive/patches-5.15/0014-serial-8250_dw-Add-StarFive-JH7100-quirk.patch b/target/linux/visionfive/patches-5.15/0014-serial-8250_dw-Add-StarFive-JH7100-quirk.patch
deleted file mode 100644 (file)
index a305165..0000000
--- a/target/linux/visionfive/patches-5.15/0014-serial-8250_dw-Add-StarFive-JH7100-quirk.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From b0ad20a3b64bf653a717860819691b262c0b2a2b Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Mon, 4 Oct 2021 19:40:29 +0200
-Subject: [PATCH 14/16] serial: 8250_dw: Add StarFive JH7100 quirk
-
-On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
-exactly 16 * 115200Hz and many other common bitrates. Trying this will
-only result in a higher input clock, but low enough that the UART's
-internal divisor can't come close enough to the baud rate target.
-So rather than try to set the input clock it's better to skip the
-clk_set_rate call and rely solely on the UART's internal divisor.
-
-Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
-Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- drivers/tty/serial/8250/8250_dw.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/tty/serial/8250/8250_dw.c
-+++ b/drivers/tty/serial/8250/8250_dw.c
-@@ -418,6 +418,8 @@ static void dw8250_quirks(struct uart_po
-               }
-               if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
-                       p->serial_out = dw8250_serial_out38x;
-+              if (of_device_is_compatible(np, "starfive,jh7100-uart"))
-+                      p->set_termios = dw8250_do_set_termios;
- 
-       } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
-               p->iotype = UPIO_MEM32;
-@@ -700,6 +702,7 @@ static const struct of_device_id dw8250_
-       { .compatible = "cavium,octeon-3860-uart" },
-       { .compatible = "marvell,armada-38x-uart" },
-       { .compatible = "renesas,rzn1-uart" },
-+      { .compatible = "starfive,jh7100-uart" },
-       { /* Sentinel */ }
- };
- MODULE_DEVICE_TABLE(of, dw8250_of_match);

diff --git a/target/linux/visionfive/patches-5.15/0015-RISC-V-Add-initial-StarFive-JH7100-device-tree.patch b/target/linux/visionfive/patches-5.15/0015-RISC-V-Add-initial-StarFive-JH7100-device-tree.patch
deleted file mode 100644 (file)
index a165ab3..0000000
--- a/target/linux/visionfive/patches-5.15/0015-RISC-V-Add-initial-StarFive-JH7100-device-tree.patch
+++ /dev/null
@@ -1,251 +0,0 @@
-From ec85362fb121d0297b9f3bb56816ea6282c34fda Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sun, 10 Oct 2021 16:48:27 +0200
-Subject: [PATCH 15/16] RISC-V: Add initial StarFive JH7100 device tree
-
-Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
-is a test chip for their upcoming JH7110 SoC.
-
-The CPU and cache data is based on the device tree in the vendor u-boot
-port.
-
-Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- arch/riscv/boot/dts/starfive/jh7100.dtsi | 230 +++++++++++++++++++++++
- 1 file changed, 230 insertions(+)
- create mode 100644 arch/riscv/boot/dts/starfive/jh7100.dtsi
-
---- /dev/null
-+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
-@@ -0,0 +1,230 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/clock/starfive-jh7100.h>
-+#include <dt-bindings/reset/starfive-jh7100.h>
-+
-+/ {
-+      compatible = "starfive,jh7100";
-+      #address-cells = <2>;
-+      #size-cells = <2>;
-+
-+      cpus {
-+              #address-cells = <1>;
-+              #size-cells = <0>;
-+
-+              cpu@0 {
-+                      compatible = "sifive,u74-mc", "riscv";
-+                      reg = <0>;
-+                      d-cache-block-size = <64>;
-+                      d-cache-sets = <64>;
-+                      d-cache-size = <32768>;
-+                      d-tlb-sets = <1>;
-+                      d-tlb-size = <32>;
-+                      device_type = "cpu";
-+                      i-cache-block-size = <64>;
-+                      i-cache-sets = <64>;
-+                      i-cache-size = <32768>;
-+                      i-tlb-sets = <1>;
-+                      i-tlb-size = <32>;
-+                      mmu-type = "riscv,sv39";
-+                      riscv,isa = "rv64imafdc";
-+                      tlb-split;
-+
-+                      cpu0_intc: interrupt-controller {
-+                              compatible = "riscv,cpu-intc";
-+                              interrupt-controller;
-+                              #interrupt-cells = <1>;
-+                      };
-+              };
-+
-+              cpu@1 {
-+                      compatible = "sifive,u74-mc", "riscv";
-+                      reg = <1>;
-+                      d-cache-block-size = <64>;
-+                      d-cache-sets = <64>;
-+                      d-cache-size = <32768>;
-+                      d-tlb-sets = <1>;
-+                      d-tlb-size = <32>;
-+                      device_type = "cpu";
-+                      i-cache-block-size = <64>;
-+                      i-cache-sets = <64>;
-+                      i-cache-size = <32768>;
-+                      i-tlb-sets = <1>;
-+                      i-tlb-size = <32>;
-+                      mmu-type = "riscv,sv39";
-+                      riscv,isa = "rv64imafdc";
-+                      tlb-split;
-+
-+                      cpu1_intc: interrupt-controller {
-+                              compatible = "riscv,cpu-intc";
-+                              interrupt-controller;
-+                              #interrupt-cells = <1>;
-+                      };
-+              };
-+      };
-+
-+      osc_sys: osc_sys {
-+              compatible = "fixed-clock";
-+              #clock-cells = <0>;
-+              /* This value must be overridden by the board */
-+              clock-frequency = <0>;
-+      };
-+
-+      osc_aud: osc_aud {
-+              compatible = "fixed-clock";
-+              #clock-cells = <0>;
-+              /* This value must be overridden by the board */
-+              clock-frequency = <0>;
-+      };
-+
-+      gmac_rmii_ref: gmac_rmii_ref {
-+              compatible = "fixed-clock";
-+              #clock-cells = <0>;
-+              /* Should be overridden by the board when needed */
-+              clock-frequency = <0>;
-+      };
-+
-+      gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
-+              compatible = "fixed-clock";
-+              #clock-cells = <0>;
-+              /* Should be overridden by the board when needed */
-+              clock-frequency = <0>;
-+      };
-+
-+      soc {
-+              compatible = "simple-bus";
-+              interrupt-parent = <&plic>;
-+              #address-cells = <2>;
-+              #size-cells = <2>;
-+              ranges;
-+
-+              clint: clint@2000000 {
-+                      compatible = "starfive,jh7100-clint", "sifive,clint0";
-+                      reg = <0x0 0x2000000 0x0 0x10000>;
-+                      interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
-+                                             &cpu1_intc 3 &cpu1_intc 7>;
-+              };
-+
-+              plic: interrupt-controller@c000000 {
-+                      compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
-+                      reg = <0x0 0xc000000 0x0 0x4000000>;
-+                      interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
-+                                             &cpu1_intc 11 &cpu1_intc 9>;
-+                      interrupt-controller;
-+                      #address-cells = <0>;
-+                      #interrupt-cells = <1>;
-+                      riscv,ndev = <127>;
-+              };
-+
-+              clkgen: clock-controller@11800000 {
-+                      compatible = "starfive,jh7100-clkgen";
-+                      reg = <0x0 0x11800000 0x0 0x10000>;
-+                      clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
-+                      clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
-+                      #clock-cells = <1>;
-+              };
-+
-+              rstgen: reset-controller@11840000 {
-+                      compatible = "starfive,jh7100-reset";
-+                      reg = <0x0 0x11840000 0x0 0x10000>;
-+                      #reset-cells = <1>;
-+              };
-+
-+              i2c0: i2c@118b0000 {
-+                      compatible = "snps,designware-i2c";
-+                      reg = <0x0 0x118b0000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
-+                               <&clkgen JH7100_CLK_I2C0_APB>;
-+                      clock-names = "ref", "pclk";
-+                      resets = <&rstgen JH7100_RSTN_I2C0_APB>;
-+                      interrupts = <96>;
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      status = "disabled";
-+              };
-+
-+              i2c1: i2c@118c0000 {
-+                      compatible = "snps,designware-i2c";
-+                      reg = <0x0 0x118c0000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
-+                               <&clkgen JH7100_CLK_I2C1_APB>;
-+                      clock-names = "ref", "pclk";
-+                      resets = <&rstgen JH7100_RSTN_I2C1_APB>;
-+                      interrupts = <97>;
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      status = "disabled";
-+              };
-+
-+              gpio: pinctrl@11910000 {
-+                      compatible = "starfive,jh7100-pinctrl";
-+                      reg = <0x0 0x11910000 0x0 0x10000>,
-+                            <0x0 0x11858000 0x0 0x1000>;
-+                      reg-names = "gpio", "padctl";
-+                      clocks = <&clkgen JH7100_CLK_GPIO_APB>;
-+                      resets = <&rstgen JH7100_RSTN_GPIO_APB>;
-+                      interrupts = <32>;
-+                      gpio-controller;
-+                      #gpio-cells = <2>;
-+                      interrupt-controller;
-+                      #interrupt-cells = <2>;
-+              };
-+
-+              uart2: serial@12430000 {
-+                      compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
-+                      reg = <0x0 0x12430000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_UART2_CORE>,
-+                               <&clkgen JH7100_CLK_UART2_APB>;
-+                      clock-names = "baudclk", "apb_pclk";
-+                      resets = <&rstgen JH7100_RSTN_UART2_APB>;
-+                      interrupts = <72>;
-+                      reg-io-width = <4>;
-+                      reg-shift = <2>;
-+                      status = "disabled";
-+              };
-+
-+              uart3: serial@12440000 {
-+                      compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
-+                      reg = <0x0 0x12440000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_UART3_CORE>,
-+                               <&clkgen JH7100_CLK_UART3_APB>;
-+                      clock-names = "baudclk", "apb_pclk";
-+                      resets = <&rstgen JH7100_RSTN_UART3_APB>;
-+                      interrupts = <73>;
-+                      reg-io-width = <4>;
-+                      reg-shift = <2>;
-+                      status = "disabled";
-+              };
-+
-+              i2c2: i2c@12450000 {
-+                      compatible = "snps,designware-i2c";
-+                      reg = <0x0 0x12450000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
-+                               <&clkgen JH7100_CLK_I2C2_APB>;
-+                      clock-names = "ref", "pclk";
-+                      resets = <&rstgen JH7100_RSTN_I2C2_APB>;
-+                      interrupts = <74>;
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      status = "disabled";
-+              };
-+
-+              i2c3: i2c@12460000 {
-+                      compatible = "snps,designware-i2c";
-+                      reg = <0x0 0x12460000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
-+                               <&clkgen JH7100_CLK_I2C3_APB>;
-+                      clock-names = "ref", "pclk";
-+                      resets = <&rstgen JH7100_RSTN_I2C3_APB>;
-+                      interrupts = <75>;
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      status = "disabled";
-+              };
-+      };
-+};

diff --git a/target/linux/visionfive/patches-5.15/0015-reset-starfive-jh7100-Add-StarFive-JH7100-reset-driv.patch b/target/linux/visionfive/patches-5.15/0015-reset-starfive-jh7100-Add-StarFive-JH7100-reset-driv.patch
new file mode 100644 (file)
index 0000000..85a9557
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0015-reset-starfive-jh7100-Add-StarFive-JH7100-reset-driv.patch
@@ -0,0 +1,237 @@
+From a605dceaf4682f8e72427daf688a1366cbbeb948 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 19 Sep 2021 14:21:05 +0200
+Subject: [PATCH 15/84] reset: starfive-jh7100: Add StarFive JH7100 reset
+ driver
+
+commit 0be3a1595bf8c7f39153be02c9aae61dd2108576 upstream.
+
+Add a driver for the StarFive JH7100 reset controller.
+
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ MAINTAINERS                           |   7 ++
+ drivers/reset/Kconfig                 |   7 ++
+ drivers/reset/Makefile                |   1 +
+ drivers/reset/reset-starfive-jh7100.c | 172 ++++++++++++++++++++++++++
+ 4 files changed, 187 insertions(+)
+ create mode 100644 drivers/reset/reset-starfive-jh7100.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -17867,6 +17867,13 @@ F:    Documentation/devicetree/bindings/clo
+ F:    drivers/clk/starfive/clk-starfive-jh7100.c
+ F:    include/dt-bindings/clock/starfive-jh7100.h
+ 
++STARFIVE JH7100 RESET CONTROLLER DRIVER
++M:    Emil Renner Berthing <kernel@esmil.dk>
++S:    Maintained
++F:    Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
++F:    drivers/reset/reset-starfive-jh7100.c
++F:    include/dt-bindings/reset/starfive-jh7100.h
++
+ STATIC BRANCH/CALL
+ M:    Peter Zijlstra <peterz@infradead.org>
+ M:    Josh Poimboeuf <jpoimboe@redhat.com>
+--- a/drivers/reset/Kconfig
++++ b/drivers/reset/Kconfig
+@@ -224,6 +224,13 @@ config RESET_SOCFPGA
+         This enables the reset driver for the SoCFPGA ARMv7 platforms. This
+         driver gets initialized early during platform init calls.
+ 
++config RESET_STARFIVE_JH7100
++      bool "StarFive JH7100 Reset Driver"
++      depends on SOC_STARFIVE || COMPILE_TEST
++      default SOC_STARFIVE
++      help
++        This enables the reset controller driver for the StarFive JH7100 SoC.
++
+ config RESET_SUNXI
+       bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
+       default ARCH_SUNXI
+--- a/drivers/reset/Makefile
++++ b/drivers/reset/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) +=
+ obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
+ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+ obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
++obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
+ obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
+ obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
+--- /dev/null
++++ b/drivers/reset/reset-starfive-jh7100.c
+@@ -0,0 +1,172 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Reset driver for the StarFive JH7100 SoC
++ *
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#include <linux/bitmap.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/mod_devicetable.h>
++#include <linux/platform_device.h>
++#include <linux/reset-controller.h>
++#include <linux/spinlock.h>
++
++#include <dt-bindings/reset/starfive-jh7100.h>
++
++/* register offsets */
++#define JH7100_RESET_ASSERT0  0x00
++#define JH7100_RESET_ASSERT1  0x04
++#define JH7100_RESET_ASSERT2  0x08
++#define JH7100_RESET_ASSERT3  0x0c
++#define JH7100_RESET_STATUS0  0x10
++#define JH7100_RESET_STATUS1  0x14
++#define JH7100_RESET_STATUS2  0x18
++#define JH7100_RESET_STATUS3  0x1c
++
++/*
++ * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
++ * line 32m + n, and writing a 0 deasserts the same line.
++ * Most reset lines have their status inverted so a 0 bit in the STATUS
++ * register means the line is asserted and a 1 means it's deasserted. A few
++ * lines don't though, so store the expected value of the status registers when
++ * all lines are asserted.
++ */
++static const u64 jh7100_reset_asserted[2] = {
++      /* STATUS0 */
++      BIT_ULL_MASK(JH7100_RST_U74) |
++      BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
++      BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
++      /* STATUS1 */
++      BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
++      BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
++      /* STATUS2 */
++      BIT_ULL_MASK(JH7100_RST_E24) |
++      /* STATUS3 */
++      0,
++};
++
++struct jh7100_reset {
++      struct reset_controller_dev rcdev;
++      /* protect registers against concurrent read-modify-write */
++      spinlock_t lock;
++      void __iomem *base;
++};
++
++static inline struct jh7100_reset *
++jh7100_reset_from(struct reset_controller_dev *rcdev)
++{
++      return container_of(rcdev, struct jh7100_reset, rcdev);
++}
++
++static int jh7100_reset_update(struct reset_controller_dev *rcdev,
++                             unsigned long id, bool assert)
++{
++      struct jh7100_reset *data = jh7100_reset_from(rcdev);
++      unsigned long offset = BIT_ULL_WORD(id);
++      u64 mask = BIT_ULL_MASK(id);
++      void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
++      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
++      u64 done = jh7100_reset_asserted[offset] & mask;
++      u64 value;
++      unsigned long flags;
++      int ret;
++
++      if (!assert)
++              done ^= mask;
++
++      spin_lock_irqsave(&data->lock, flags);
++
++      value = readq(reg_assert);
++      if (assert)
++              value |= mask;
++      else
++              value &= ~mask;
++      writeq(value, reg_assert);
++
++      /* if the associated clock is gated, deasserting might otherwise hang forever */
++      ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
++
++      spin_unlock_irqrestore(&data->lock, flags);
++      return ret;
++}
++
++static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
++                             unsigned long id)
++{
++      return jh7100_reset_update(rcdev, id, true);
++}
++
++static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
++                               unsigned long id)
++{
++      return jh7100_reset_update(rcdev, id, false);
++}
++
++static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
++                            unsigned long id)
++{
++      int ret;
++
++      ret = jh7100_reset_assert(rcdev, id);
++      if (ret)
++              return ret;
++
++      return jh7100_reset_deassert(rcdev, id);
++}
++
++static int jh7100_reset_status(struct reset_controller_dev *rcdev,
++                             unsigned long id)
++{
++      struct jh7100_reset *data = jh7100_reset_from(rcdev);
++      unsigned long offset = BIT_ULL_WORD(id);
++      u64 mask = BIT_ULL_MASK(id);
++      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
++      u64 value = readq(reg_status);
++
++      return !((value ^ jh7100_reset_asserted[offset]) & mask);
++}
++
++static const struct reset_control_ops jh7100_reset_ops = {
++      .assert         = jh7100_reset_assert,
++      .deassert       = jh7100_reset_deassert,
++      .reset          = jh7100_reset_reset,
++      .status         = jh7100_reset_status,
++};
++
++static int __init jh7100_reset_probe(struct platform_device *pdev)
++{
++      struct jh7100_reset *data;
++
++      data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++      if (!data)
++              return -ENOMEM;
++
++      data->base = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(data->base))
++              return PTR_ERR(data->base);
++
++      data->rcdev.ops = &jh7100_reset_ops;
++      data->rcdev.owner = THIS_MODULE;
++      data->rcdev.nr_resets = JH7100_RSTN_END;
++      data->rcdev.dev = &pdev->dev;
++      data->rcdev.of_node = pdev->dev.of_node;
++      spin_lock_init(&data->lock);
++
++      return devm_reset_controller_register(&pdev->dev, &data->rcdev);
++}
++
++static const struct of_device_id jh7100_reset_dt_ids[] = {
++      { .compatible = "starfive,jh7100-reset" },
++      { /* sentinel */ }
++};
++
++static struct platform_driver jh7100_reset_driver = {
++      .driver = {
++              .name = "jh7100-reset",
++              .of_match_table = jh7100_reset_dt_ids,
++              .suppress_bind_attrs = true,
++      },
++};
++builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);

diff --git a/target/linux/visionfive/patches-5.15/0016-RISC-V-Add-BeagleV-Starlight-Beta-device-tree.patch b/target/linux/visionfive/patches-5.15/0016-RISC-V-Add-BeagleV-Starlight-Beta-device-tree.patch
deleted file mode 100644 (file)
index 9360863..0000000
--- a/target/linux/visionfive/patches-5.15/0016-RISC-V-Add-BeagleV-Starlight-Beta-device-tree.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-From a43676272a6e0b398781bc5337ca4cc187ba923d Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sun, 10 Oct 2021 19:48:36 +0200
-Subject: [PATCH 16/16] RISC-V: Add BeagleV Starlight Beta device tree
-
-Add initial device tree for the BeagleV Starlight Beta board. About 300
-of these boards were sent out as part of a now cancelled BeagleBoard.org
-project.
-
-I2C timing data is based on the device tree in the vendor u-boot port.
-Heartbeat LED added by Geert.
-
-Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
-Co-developed-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- arch/riscv/boot/dts/Makefile                  |   1 +
- arch/riscv/boot/dts/starfive/Makefile         |   2 +
- .../dts/starfive/jh7100-beaglev-starlight.dts | 164 ++++++++++++++++++
- 3 files changed, 167 insertions(+)
- create mode 100644 arch/riscv/boot/dts/starfive/Makefile
- create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
-
---- a/arch/riscv/boot/dts/Makefile
-+++ b/arch/riscv/boot/dts/Makefile
-@@ -1,5 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
- subdir-y += sifive
-+subdir-y += starfive
- subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
- subdir-y += microchip
- 
---- /dev/null
-+++ b/arch/riscv/boot/dts/starfive/Makefile
-@@ -0,0 +1,2 @@
-+# SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
-@@ -0,0 +1,164 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+/dts-v1/;
-+#include "jh7100.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/pinctrl-starfive.h>
-+
-+/ {
-+      model = "BeagleV Starlight Beta";
-+      compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
-+
-+      aliases {
-+              serial0 = &uart3;
-+      };
-+
-+      chosen {
-+              stdout-path = "serial0:115200n8";
-+      };
-+
-+      cpus {
-+              timebase-frequency = <6250000>;
-+      };
-+
-+      memory@80000000 {
-+              device_type = "memory";
-+              reg = <0x0 0x80000000 0x2 0x0>;
-+      };
-+
-+      leds {
-+              compatible = "gpio-leds";
-+
-+              led-ack {
-+                      gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
-+                      color = <LED_COLOR_ID_GREEN>;
-+                      function = LED_FUNCTION_HEARTBEAT;
-+                      linux,default-trigger = "heartbeat";
-+                      label = "ack";
-+              };
-+      };
-+};
-+
-+&gpio {
-+      i2c0_pins: i2c0-0 {
-+              i2c-pins {
-+                      pinmux = <GPIOMUX(62, GPO_LOW,
-+                                GPO_I2C0_PAD_SCK_OEN,
-+                                GPI_I2C0_PAD_SCK_IN)>,
-+                               <GPIOMUX(61, GPO_LOW,
-+                                GPO_I2C0_PAD_SDA_OEN,
-+                                GPI_I2C0_PAD_SDA_IN)>;
-+                      bias-disable; /* external pull-up */
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+      };
-+
-+      i2c1_pins: i2c1-0 {
-+              i2c-pins {
-+                      pinmux = <GPIOMUX(47, GPO_LOW,
-+                                GPO_I2C1_PAD_SCK_OEN,
-+                                GPI_I2C1_PAD_SCK_IN)>,
-+                               <GPIOMUX(48, GPO_LOW,
-+                                GPO_I2C1_PAD_SDA_OEN,
-+                                GPI_I2C1_PAD_SDA_IN)>;
-+                      bias-pull-up;
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+      };
-+
-+      i2c2_pins: i2c2-0 {
-+              i2c-pins {
-+                      pinmux = <GPIOMUX(60, GPO_LOW,
-+                                GPO_I2C2_PAD_SCK_OEN,
-+                                GPI_I2C2_PAD_SCK_IN)>,
-+                               <GPIOMUX(59, GPO_LOW,
-+                                GPO_I2C2_PAD_SDA_OEN,
-+                                GPI_I2C2_PAD_SDA_IN)>;
-+                      bias-disable; /* external pull-up */
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+      };
-+
-+      uart3_pins: uart3-0 {
-+              rx-pins {
-+                      pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
-+                                GPI_UART3_PAD_SIN)>;
-+                      bias-pull-up;
-+                      drive-strength = <14>;
-+                      input-enable;
-+                      input-schmitt-enable;
-+                      slew-rate = <0>;
-+              };
-+              tx-pins {
-+                      pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
-+                                GPO_ENABLE, GPI_NONE)>;
-+                      bias-disable;
-+                      drive-strength = <35>;
-+                      input-disable;
-+                      input-schmitt-disable;
-+                      slew-rate = <0>;
-+              };
-+      };
-+};
-+
-+&i2c0 {
-+      clock-frequency = <100000>;
-+      i2c-sda-hold-time-ns = <300>;
-+      i2c-sda-falling-time-ns = <500>;
-+      i2c-scl-falling-time-ns = <500>;
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&i2c0_pins>;
-+      status = "okay";
-+
-+      pmic@5e {
-+              compatible = "ti,tps65086";
-+              reg = <0x5e>;
-+              gpio-controller;
-+              #gpio-cells = <2>;
-+
-+              regulators {
-+              };
-+      };
-+};
-+
-+&i2c1 {
-+      clock-frequency = <400000>;
-+      i2c-sda-hold-time-ns = <300>;
-+      i2c-sda-falling-time-ns = <100>;
-+      i2c-scl-falling-time-ns = <100>;
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&i2c1_pins>;
-+      status = "okay";
-+};
-+
-+&i2c2 {
-+      clock-frequency = <100000>;
-+      i2c-sda-hold-time-ns = <300>;
-+      i2c-sda-falling-time-ns = <500>;
-+      i2c-scl-falling-time-ns = <500>;
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&i2c2_pins>;
-+      status = "okay";
-+};
-+
-+&osc_sys {
-+      clock-frequency = <25000000>;
-+};
-+
-+&osc_aud {
-+      clock-frequency = <27000000>;
-+};
-+
-+&uart3 {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&uart3_pins>;
-+      status = "okay";
-+};

diff --git a/target/linux/visionfive/patches-5.15/0016-dt-bindings-pinctrl-Add-StarFive-pinctrl-definitions.patch b/target/linux/visionfive/patches-5.15/0016-dt-bindings-pinctrl-Add-StarFive-pinctrl-definitions.patch
new file mode 100644 (file)
index 0000000..8f78397
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0016-dt-bindings-pinctrl-Add-StarFive-pinctrl-definitions.patch
@@ -0,0 +1,295 @@
+From ea1349b616f08cd398d9c498bd4c471ed0311dae Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Tue, 6 Jul 2021 20:19:06 +0200
+Subject: [PATCH 16/84] dt-bindings: pinctrl: Add StarFive pinctrl definitions
+
+commit 3021114b3d172cf80c074c81425741f9e26c6679 upstream.
+
+Add definitons for pins and GPIO input, output and output enable
+signals on the StarFive JH7100 SoC.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../dt-bindings/pinctrl/pinctrl-starfive.h    | 275 ++++++++++++++++++
+ 1 file changed, 275 insertions(+)
+ create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive.h
+
+--- /dev/null
++++ b/include/dt-bindings/pinctrl/pinctrl-starfive.h
+@@ -0,0 +1,275 @@
++/* SPDX-License-Identifier: GPL-2.0 OR MIT */
++/*
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_H__
++#define __DT_BINDINGS_PINCTRL_STARFIVE_H__
++
++#define PAD_GPIO_OFFSET               0
++#define PAD_FUNC_SHARE_OFFSET 64
++#define PAD_GPIO(x)           (PAD_GPIO_OFFSET + (x))
++#define PAD_FUNC_SHARE(x)     (PAD_FUNC_SHARE_OFFSET + (x))
++
++/*
++ * GPIOMUX bits:
++ *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
++ *  |  dout   |  doen   |  din   | dout rev | doen rev | gpio nr |
++ *
++ * dout:     output signal
++ * doen:     output enable signal
++ * din:      optional input signal, 0xff = none
++ * dout rev: output signal reverse bit
++ * doen rev: output enable signal reverse bit
++ * gpio nr:  gpio number, 0 - 63
++ */
++#define GPIOMUX(n, dout, doen, din) ( \
++              (((dout) & 0x80000000) >> (31 - 7)) | (((dout) & 0xff) << 24) | \
++              (((doen) & 0x80000000) >> (31 - 6)) | (((doen) & 0xff) << 16) | \
++              (((din) & 0xff) << 8) | \
++              ((n) & 0x3f))
++
++#define GPO_REVERSE                           0x80000000
++
++#define GPO_LOW                                       0
++#define GPO_HIGH                              1
++#define GPO_ENABLE                            0
++#define GPO_DISABLE                           1
++#define GPO_CLK_GMAC_PAPHYREF                 2
++#define GPO_JTAG_TDO                          3
++#define GPO_JTAG_TDO_OEN                      4
++#define GPO_DMIC_CLK_OUT                      5
++#define GPO_DSP_JTDOEN_PAD                    6
++#define GPO_DSP_JTDO_PAD                      7
++#define GPO_I2C0_PAD_SCK_OE                   8
++#define GPO_I2C0_PAD_SCK_OEN                  (GPO_I2C0_PAD_SCK_OE | GPO_REVERSE)
++#define GPO_I2C0_PAD_SDA_OE                   9
++#define GPO_I2C0_PAD_SDA_OEN                  (GPO_I2C0_PAD_SDA_OE | GPO_REVERSE)
++#define GPO_I2C1_PAD_SCK_OE                   10
++#define GPO_I2C1_PAD_SCK_OEN                  (GPO_I2C1_PAD_SCK_OE | GPO_REVERSE)
++#define GPO_I2C1_PAD_SDA_OE                   11
++#define GPO_I2C1_PAD_SDA_OEN                  (GPO_I2C1_PAD_SDA_OE | GPO_REVERSE)
++#define GPO_I2C2_PAD_SCK_OE                   12
++#define GPO_I2C2_PAD_SCK_OEN                  (GPO_I2C2_PAD_SCK_OE | GPO_REVERSE)
++#define GPO_I2C2_PAD_SDA_OE                   13
++#define GPO_I2C2_PAD_SDA_OEN                  (GPO_I2C2_PAD_SDA_OE | GPO_REVERSE)
++#define GPO_I2C3_PAD_SCK_OE                   14
++#define GPO_I2C3_PAD_SCK_OEN                  (GPO_I2C3_PAD_SCK_OE | GPO_REVERSE)
++#define GPO_I2C3_PAD_SDA_OE                   15
++#define GPO_I2C3_PAD_SDA_OEN                  (GPO_I2C3_PAD_SDA_OE | GPO_REVERSE)
++#define GPO_I2SRX_BCLK_OUT                    16
++#define GPO_I2SRX_BCLK_OUT_OEN                        17
++#define GPO_I2SRX_LRCK_OUT                    18
++#define GPO_I2SRX_LRCK_OUT_OEN                        19
++#define GPO_I2SRX_MCLK_OUT                    20
++#define GPO_I2STX_BCLK_OUT                    21
++#define GPO_I2STX_BCLK_OUT_OEN                        22
++#define GPO_I2STX_LRCK_OUT                    23
++#define GPO_I2STX_LRCK_OUT_OEN                        24
++#define GPO_I2STX_MCLK_OUT                    25
++#define GPO_I2STX_SDOUT0                      26
++#define GPO_I2STX_SDOUT1                      27
++#define GPO_LCD_PAD_CSM_N                     28
++#define GPO_PWM_PAD_OE_N_BIT0                 29
++#define GPO_PWM_PAD_OE_N_BIT1                 30
++#define GPO_PWM_PAD_OE_N_BIT2                 31
++#define GPO_PWM_PAD_OE_N_BIT3                 32
++#define GPO_PWM_PAD_OE_N_BIT4                 33
++#define GPO_PWM_PAD_OE_N_BIT5                 34
++#define GPO_PWM_PAD_OE_N_BIT6                 35
++#define GPO_PWM_PAD_OE_N_BIT7                 36
++#define GPO_PWM_PAD_OUT_BIT0                  37
++#define GPO_PWM_PAD_OUT_BIT1                  38
++#define GPO_PWM_PAD_OUT_BIT2                  39
++#define GPO_PWM_PAD_OUT_BIT3                  40
++#define GPO_PWM_PAD_OUT_BIT4                  41
++#define GPO_PWM_PAD_OUT_BIT5                  42
++#define GPO_PWM_PAD_OUT_BIT6                  43
++#define GPO_PWM_PAD_OUT_BIT7                  44
++#define GPO_PWMDAC_LEFT_OUT                   45
++#define GPO_PWMDAC_RIGHT_OUT                  46
++#define GPO_QSPI_CSN1_OUT                     47
++#define GPO_QSPI_CSN2_OUT                     48
++#define GPO_QSPI_CSN3_OUT                     49
++#define GPO_REGISTER23_SCFG_CMSENSOR_RST0     50
++#define GPO_REGISTER23_SCFG_CMSENSOR_RST1     51
++#define GPO_REGISTER32_SCFG_GMAC_PHY_RSTN     52
++#define GPO_SDIO0_PAD_CARD_POWER_EN           53
++#define GPO_SDIO0_PAD_CCLK_OUT                        54
++#define GPO_SDIO0_PAD_CCMD_OE                 55
++#define GPO_SDIO0_PAD_CCMD_OEN                        (GPO_SDIO0_PAD_CCMD_OE | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CCMD_OUT                        56
++#define GPO_SDIO0_PAD_CDATA_OE_BIT0           57
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT0          (GPO_SDIO0_PAD_CDATA_OE_BIT0 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT1           58
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT1          (GPO_SDIO0_PAD_CDATA_OE_BIT1 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT2           59
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT2          (GPO_SDIO0_PAD_CDATA_OE_BIT2 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT3           60
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT3          (GPO_SDIO0_PAD_CDATA_OE_BIT3 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT4           61
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT4          (GPO_SDIO0_PAD_CDATA_OE_BIT4 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT5           62
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT5          (GPO_SDIO0_PAD_CDATA_OE_BIT5 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT6           63
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT6          (GPO_SDIO0_PAD_CDATA_OE_BIT6 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT7           64
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT7          (GPO_SDIO0_PAD_CDATA_OE_BIT7 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT0          65
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT1          66
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT2          67
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT3          68
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT4          69
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT5          70
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT6          71
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT7          72
++#define GPO_SDIO0_PAD_RST_N                   73
++#define GPO_SDIO1_PAD_CARD_POWER_EN           74
++#define GPO_SDIO1_PAD_CCLK_OUT                        75
++#define GPO_SDIO1_PAD_CCMD_OE                 76
++#define GPO_SDIO1_PAD_CCMD_OEN                        (GPO_SDIO1_PAD_CCMD_OE | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CCMD_OUT                        77
++#define GPO_SDIO1_PAD_CDATA_OE_BIT0           78
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT0          (GPO_SDIO1_PAD_CDATA_OE_BIT0 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT1           79
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT1          (GPO_SDIO1_PAD_CDATA_OE_BIT1 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT2           80
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT2          (GPO_SDIO1_PAD_CDATA_OE_BIT2 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT3           81
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT3          (GPO_SDIO1_PAD_CDATA_OE_BIT3 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT4           82
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT4          (GPO_SDIO1_PAD_CDATA_OE_BIT4 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT5           83
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT5          (GPO_SDIO1_PAD_CDATA_OE_BIT5 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT6           84
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT6          (GPO_SDIO1_PAD_CDATA_OE_BIT6 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT7           85
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT7          (GPO_SDIO1_PAD_CDATA_OE_BIT7 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT0          86
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT1          87
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT2          88
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT3          89
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT4          90
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT5          91
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT6          92
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT7          93
++#define GPO_SDIO1_PAD_RST_N                   94
++#define GPO_SPDIF_TX_SDOUT                    95
++#define GPO_SPDIF_TX_SDOUT_OEN                        96
++#define GPO_SPI0_PAD_OE_N                     97
++#define GPO_SPI0_PAD_SCK_OUT                  98
++#define GPO_SPI0_PAD_SS_0_N                   99
++#define GPO_SPI0_PAD_SS_1_N                   100
++#define GPO_SPI0_PAD_TXD                      101
++#define GPO_SPI1_PAD_OE_N                     102
++#define GPO_SPI1_PAD_SCK_OUT                  103
++#define GPO_SPI1_PAD_SS_0_N                   104
++#define GPO_SPI1_PAD_SS_1_N                   105
++#define GPO_SPI1_PAD_TXD                      106
++#define GPO_SPI2_PAD_OE_N                     107
++#define GPO_SPI2_PAD_SCK_OUT                  108
++#define GPO_SPI2_PAD_SS_0_N                   109
++#define GPO_SPI2_PAD_SS_1_N                   110
++#define GPO_SPI2_PAD_TXD                      111
++#define GPO_SPI2AHB_PAD_OE_N_BIT0             112
++#define GPO_SPI2AHB_PAD_OE_N_BIT1             113
++#define GPO_SPI2AHB_PAD_OE_N_BIT2             114
++#define GPO_SPI2AHB_PAD_OE_N_BIT3             115
++#define GPO_SPI2AHB_PAD_TXD_BIT0              116
++#define GPO_SPI2AHB_PAD_TXD_BIT1              117
++#define GPO_SPI2AHB_PAD_TXD_BIT2              118
++#define GPO_SPI2AHB_PAD_TXD_BIT3              119
++#define GPO_SPI3_PAD_OE_N                     120
++#define GPO_SPI3_PAD_SCK_OUT                  121
++#define GPO_SPI3_PAD_SS_0_N                   122
++#define GPO_SPI3_PAD_SS_1_N                   123
++#define GPO_SPI3_PAD_TXD                      124
++#define GPO_UART0_PAD_DTRN                    125
++#define GPO_UART0_PAD_RTSN                    126
++#define GPO_UART0_PAD_SOUT                    127
++#define GPO_UART1_PAD_SOUT                    128
++#define GPO_UART2_PAD_DTR_N                   129
++#define GPO_UART2_PAD_RTS_N                   130
++#define GPO_UART2_PAD_SOUT                    131
++#define GPO_UART3_PAD_SOUT                    132
++#define GPO_USB_DRV_BUS                               133
++
++#define GPI_CPU_JTAG_TCK                      0
++#define GPI_CPU_JTAG_TDI                      1
++#define GPI_CPU_JTAG_TMS                      2
++#define GPI_CPU_JTAG_TRST                     3
++#define GPI_DMIC_SDIN_BIT0                    4
++#define GPI_DMIC_SDIN_BIT1                    5
++#define GPI_DSP_JTCK_PAD                      6
++#define GPI_DSP_JTDI_PAD                      7
++#define GPI_DSP_JTMS_PAD                      8
++#define GPI_DSP_TRST_PAD                      9
++#define GPI_I2C0_PAD_SCK_IN                   10
++#define GPI_I2C0_PAD_SDA_IN                   11
++#define GPI_I2C1_PAD_SCK_IN                   12
++#define GPI_I2C1_PAD_SDA_IN                   13
++#define GPI_I2C2_PAD_SCK_IN                   14
++#define GPI_I2C2_PAD_SDA_IN                   15
++#define GPI_I2C3_PAD_SCK_IN                   16
++#define GPI_I2C3_PAD_SDA_IN                   17
++#define GPI_I2SRX_BCLK_IN                     18
++#define GPI_I2SRX_LRCK_IN                     19
++#define GPI_I2SRX_SDIN_BIT0                   20
++#define GPI_I2SRX_SDIN_BIT1                   21
++#define GPI_I2SRX_SDIN_BIT2                   22
++#define GPI_I2STX_BCLK_IN                     23
++#define GPI_I2STX_LRCK_IN                     24
++#define GPI_SDIO0_PAD_CARD_DETECT_N           25
++#define GPI_SDIO0_PAD_CARD_WRITE_PRT          26
++#define GPI_SDIO0_PAD_CCMD_IN                 27
++#define GPI_SDIO0_PAD_CDATA_IN_BIT0           28
++#define GPI_SDIO0_PAD_CDATA_IN_BIT1           29
++#define GPI_SDIO0_PAD_CDATA_IN_BIT2           30
++#define GPI_SDIO0_PAD_CDATA_IN_BIT3           31
++#define GPI_SDIO0_PAD_CDATA_IN_BIT4           32
++#define GPI_SDIO0_PAD_CDATA_IN_BIT5           33
++#define GPI_SDIO0_PAD_CDATA_IN_BIT6           34
++#define GPI_SDIO0_PAD_CDATA_IN_BIT7           35
++#define GPI_SDIO1_PAD_CARD_DETECT_N           36
++#define GPI_SDIO1_PAD_CARD_WRITE_PRT          37
++#define GPI_SDIO1_PAD_CCMD_IN                 38
++#define GPI_SDIO1_PAD_CDATA_IN_BIT0           39
++#define GPI_SDIO1_PAD_CDATA_IN_BIT1           40
++#define GPI_SDIO1_PAD_CDATA_IN_BIT2           41
++#define GPI_SDIO1_PAD_CDATA_IN_BIT3           42
++#define GPI_SDIO1_PAD_CDATA_IN_BIT4           43
++#define GPI_SDIO1_PAD_CDATA_IN_BIT5           44
++#define GPI_SDIO1_PAD_CDATA_IN_BIT6           45
++#define GPI_SDIO1_PAD_CDATA_IN_BIT7           46
++#define GPI_SPDIF_RX_SDIN                     47
++#define GPI_SPI0_PAD_RXD                      48
++#define GPI_SPI0_PAD_SS_IN_N                  49
++#define GPI_SPI1_PAD_RXD                      50
++#define GPI_SPI1_PAD_SS_IN_N                  51
++#define GPI_SPI2_PAD_RXD                      52
++#define GPI_SPI2_PAD_SS_IN_N                  53
++#define GPI_SPI2AHB_PAD_RXD_BIT0              54
++#define GPI_SPI2AHB_PAD_RXD_BIT1              55
++#define GPI_SPI2AHB_PAD_RXD_BIT2              56
++#define GPI_SPI2AHB_PAD_RXD_BIT3              57
++#define GPI_SPI2AHB_PAD_SS_N                  58
++#define GPI_SPI2AHB_SLV_SCLKIN                        59
++#define GPI_SPI3_PAD_RXD                      60
++#define GPI_SPI3_PAD_SS_IN_N                  61
++#define GPI_UART0_PAD_CTSN                    62
++#define GPI_UART0_PAD_DCDN                    63
++#define GPI_UART0_PAD_DSRN                    64
++#define GPI_UART0_PAD_RIN                     65
++#define GPI_UART0_PAD_SIN                     66
++#define GPI_UART1_PAD_SIN                     67
++#define GPI_UART2_PAD_CTS_N                   68
++#define GPI_UART2_PAD_DCD_N                   69
++#define GPI_UART2_PAD_DSR_N                   70
++#define GPI_UART2_PAD_RI_N                    71
++#define GPI_UART2_PAD_SIN                     72
++#define GPI_UART3_PAD_SIN                     73
++#define GPI_USB_OVER_CURRENT                  74
++
++#define GPI_NONE                              0xff
++
++#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_H__ */

diff --git a/target/linux/visionfive/patches-5.15/0017-dt-bindings-pinctrl-Add-StarFive-JH7100-bindings.patch b/target/linux/visionfive/patches-5.15/0017-dt-bindings-pinctrl-Add-StarFive-JH7100-bindings.patch
new file mode 100644 (file)
index 0000000..70c4a7c
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0017-dt-bindings-pinctrl-Add-StarFive-JH7100-bindings.patch
@@ -0,0 +1,328 @@
+From bd0908d1cdc8c480dea6311d1e7533a9a2a57b86 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Tue, 27 Jul 2021 14:34:33 +0200
+Subject: [PATCH 17/84] dt-bindings: pinctrl: Add StarFive JH7100 bindings
+
+commit 7431b391df95f5b8d08fd0f9fa1a75cc038ee290 upstream.
+
+Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by
+StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
+
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../pinctrl/starfive,jh7100-pinctrl.yaml      | 307 ++++++++++++++++++
+ 1 file changed, 307 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+@@ -0,0 +1,307 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7100 Pin Controller Device Tree Bindings
++
++description: |
++  Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
++
++  Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
++  and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
++  configurable bias, drive strength, schmitt trigger etc. The SoC has an
++  interesting 2-layered approach to pin muxing best illustrated by the diagram
++  below.
++
++                          Signal group 0, 1, ... or 6
++                                 ___|___
++                                |       |
++    LCD output -----------------|       |
++    CMOS Camera interface ------|       |--- PAD_GPIO[0]
++    Ethernet PHY interface -----|  MUX  |--- PAD_GPIO[1]
++      ...                       |       |      ...
++                                |       |--- PAD_GPIO[63]
++     -------- GPIO0 ------------|       |
++    |  -------|-- GPIO1 --------|       |--- PAD_FUNC_SHARE[0]
++    | |       |   |             |       |--- PAD_FUNC_SHARE[1]
++    | |       |   |  ...        |       |       ...
++    | |       |   |             |       |--- PAD_FUNC_SHARE[141]
++    | |  -----|---|-- GPIO63 ---|       |
++    | | |     |   |   |          -------
++    UART0     UART1 --
++
++
++  The big MUX in the diagram only has 7 different ways of mapping peripherals
++  on the left to pins on the right. StarFive calls the 7 configurations "signal
++  groups".
++  However some peripherals have their I/O go through the 64 "GPIOs". The
++  diagram only shows UART0 and UART1, but this also includes a number of other
++  UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
++  GPIOs such that any GPIO can be set up to be controlled by any of the
++  peripherals.
++  Note that signal group 0 doesn't map any of the GPIOs to pins, and only
++  signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].
++
++maintainers:
++  - Emil Renner Berthing <kernel@esmil.dk>
++  - Drew Fustini <drew@beagleboard.org>
++
++properties:
++  compatible:
++    const: starfive,jh7100-pinctrl
++
++  reg:
++    minItems: 2
++    maxItems: 2
++
++  reg-names:
++    items:
++      - const: gpio
++      - const: padctl
++
++  clocks:
++    maxItems: 1
++
++  resets:
++    maxItems: 1
++
++  gpio-controller: true
++
++  "#gpio-cells":
++    const: 2
++
++  interrupts:
++    maxItems: 1
++    description: The GPIO parent interrupt.
++
++  interrupt-controller: true
++
++  "#interrupt-cells":
++    const: 2
++
++  starfive,signal-group:
++    description: |
++      Select one of the 7 signal groups. If this property is not set it
++      defaults to the configuration already chosen by the earlier boot stages.
++    $ref: /schemas/types.yaml#/definitions/uint32
++    enum: [0, 1, 2, 3, 4, 5, 6]
++
++required:
++  - compatible
++  - reg
++  - reg-names
++  - clocks
++  - gpio-controller
++  - "#gpio-cells"
++  - interrupts
++  - interrupt-controller
++  - "#interrupt-cells"
++
++patternProperties:
++  '-[0-9]+$':
++    type: object
++    patternProperties:
++      '-pins$':
++        type: object
++        description: |
++          A pinctrl node should contain at least one subnode representing the
++          pinctrl groups available on the machine. Each subnode will list the
++          pins it needs, and how they should be configured, with regard to
++          muxer configuration, bias, input enable/disable, input schmitt
++          trigger enable/disable, slew-rate and drive strength.
++        $ref: "/schemas/pinctrl/pincfg-node.yaml"
++
++        properties:
++          pins:
++            description: |
++              The list of pin identifiers that properties in the node apply to.
++              This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
++              macros.
++              Either this or "pinmux" has to be specified, but not both.
++            $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins"
++
++          pinmux:
++            description: |
++              The list of GPIOs and their mux settings that properties in the
++              node apply to. This should be set using the GPIOMUX macro.
++              Either this or "pins" has to be specified, but not both.
++            $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"
++
++          bias-disable: true
++
++          bias-pull-up:
++            type: boolean
++
++          bias-pull-down:
++            type: boolean
++
++          drive-strength:
++            enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]
++
++          input-enable: true
++
++          input-disable: true
++
++          input-schmitt-enable: true
++
++          input-schmitt-disable: true
++
++          slew-rate:
++            maximum: 7
++
++          starfive,strong-pull-up:
++            description: enable strong pull-up.
++            type: boolean
++
++        additionalProperties: false
++
++    additionalProperties: false
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/starfive-jh7100.h>
++    #include <dt-bindings/reset/starfive-jh7100.h>
++    #include <dt-bindings/pinctrl/pinctrl-starfive.h>
++
++    soc {
++        #address-cells = <2>;
++        #size-cells = <2>;
++
++        pinctrl@11910000 {
++            compatible = "starfive,jh7100-pinctrl";
++            reg = <0x0 0x11910000 0x0 0x10000>,
++                  <0x0 0x11858000 0x0 0x1000>;
++            reg-names = "gpio", "padctl";
++            clocks = <&clkgen JH7100_CLK_GPIO_APB>;
++            resets = <&clkgen JH7100_RSTN_GPIO_APB>;
++            interrupts = <32>;
++            gpio-controller;
++            #gpio-cells = <2>;
++            interrupt-controller;
++            #interrupt-cells = <2>;
++            starfive,signal-group = <6>;
++
++            gmac_pins_default: gmac-0 {
++                gtxclk-pins {
++                    pins = <PAD_FUNC_SHARE(115)>;
++                    bias-pull-up;
++                    drive-strength = <35>;
++                    input-enable;
++                    input-schmitt-enable;
++                    slew-rate = <0>;
++                };
++                miitxclk-pins {
++                    pins = <PAD_FUNC_SHARE(116)>;
++                    bias-pull-up;
++                    drive-strength = <14>;
++                    input-enable;
++                    input-schmitt-disable;
++                    slew-rate = <0>;
++                };
++                tx-pins {
++                    pins = <PAD_FUNC_SHARE(117)>,
++                           <PAD_FUNC_SHARE(119)>,
++                           <PAD_FUNC_SHARE(120)>,
++                           <PAD_FUNC_SHARE(121)>,
++                           <PAD_FUNC_SHARE(122)>,
++                           <PAD_FUNC_SHARE(123)>,
++                           <PAD_FUNC_SHARE(124)>,
++                           <PAD_FUNC_SHARE(125)>,
++                           <PAD_FUNC_SHARE(126)>;
++                    bias-disable;
++                    drive-strength = <35>;
++                    input-disable;
++                    input-schmitt-disable;
++                    slew-rate = <0>;
++                };
++                rxclk-pins {
++                    pins = <PAD_FUNC_SHARE(127)>;
++                    bias-pull-up;
++                    drive-strength = <14>;
++                    input-enable;
++                    input-schmitt-disable;
++                    slew-rate = <6>;
++                };
++                rxer-pins {
++                    pins = <PAD_FUNC_SHARE(129)>;
++                    bias-pull-up;
++                    drive-strength = <14>;
++                    input-enable;
++                    input-schmitt-disable;
++                    slew-rate = <0>;
++                };
++                rx-pins {
++                    pins = <PAD_FUNC_SHARE(128)>,
++                           <PAD_FUNC_SHARE(130)>,
++                           <PAD_FUNC_SHARE(131)>,
++                           <PAD_FUNC_SHARE(132)>,
++                           <PAD_FUNC_SHARE(133)>,
++                           <PAD_FUNC_SHARE(134)>,
++                           <PAD_FUNC_SHARE(135)>,
++                           <PAD_FUNC_SHARE(136)>,
++                           <PAD_FUNC_SHARE(137)>,
++                           <PAD_FUNC_SHARE(138)>,
++                           <PAD_FUNC_SHARE(139)>,
++                           <PAD_FUNC_SHARE(140)>,
++                           <PAD_FUNC_SHARE(141)>;
++                    bias-pull-up;
++                    drive-strength = <14>;
++                    input-enable;
++                    input-schmitt-enable;
++                    slew-rate = <0>;
++                };
++            };
++
++            i2c0_pins_default: i2c0-0 {
++                i2c-pins {
++                    pinmux = <GPIOMUX(62, GPO_LOW,
++                              GPO_I2C0_PAD_SCK_OEN,
++                              GPI_I2C0_PAD_SCK_IN)>,
++                             <GPIOMUX(61, GPO_LOW,
++                              GPO_I2C0_PAD_SDA_OEN,
++                              GPI_I2C0_PAD_SDA_IN)>;
++                    bias-disable; /* external pull-up */
++                    input-enable;
++                    input-schmitt-enable;
++                };
++            };
++
++            uart3_pins_default: uart3-0 {
++                rx-pins {
++                    pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
++                              GPI_UART3_PAD_SIN)>;
++                    bias-pull-up;
++                    input-enable;
++                    input-schmitt-enable;
++                };
++                tx-pins {
++                    pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
++                              GPO_ENABLE, GPI_NONE)>;
++                    bias-disable;
++                    input-disable;
++                    input-schmitt-disable;
++                };
++            };
++        };
++
++        gmac {
++            pinctrl-0 = <&gmac_pins_default>;
++            pinctrl-names = "default";
++        };
++
++        i2c0 {
++            pinctrl-0 = <&i2c0_pins_default>;
++            pinctrl-names = "default";
++        };
++
++        uart3 {
++            pinctrl-0 = <&uart3_pins_default>;
++            pinctrl-names = "default";
++        };
++    };
++
++...

diff --git a/target/linux/visionfive/patches-5.15/0018-pinctrl-starfive-Add-pinctrl-driver-for-StarFive-SoC.patch b/target/linux/visionfive/patches-5.15/0018-pinctrl-starfive-Add-pinctrl-driver-for-StarFive-SoC.patch
new file mode 100644 (file)
index 0000000..7c771eb
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0018-pinctrl-starfive-Add-pinctrl-driver-for-StarFive-SoC.patch
@@ -0,0 +1,1449 @@
+From 5798999e72e586bf8951ccf1e5a144b923b14f5e Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Tue, 6 Jul 2021 20:19:06 +0200
+Subject: [PATCH 18/84] pinctrl: starfive: Add pinctrl driver for StarFive SoCs
+
+commit ec648f6b7686b716424e8e73eebb4c11ae199187 upstream.
+
+Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
+StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
+is said to feature only minor changes to these pinctrl/GPIO parts.
+
+For each "GPIO" there are two registers for configuring the output and
+output enable signals which may come from other peripherals. Among these
+are two special signals that are constant 0 and constant 1 respectively.
+Controlling the GPIOs from software is done by choosing one of these
+signals. In other words the same registers are used for both pin muxing
+and controlling the GPIOs, which makes it easier to combine the pinctrl
+and GPIO driver in one.
+
+I wrote the pinconf and pinmux parts, but the GPIO part of the code is
+based on the GPIO driver in the vendor tree written by Huan Feng with
+cleanups and fixes by Drew and me.
+
+Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
+Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
+Co-developed-by: Drew Fustini <drew@beagleboard.org>
+Signed-off-by: Drew Fustini <drew@beagleboard.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ MAINTAINERS                        |    8 +
+ drivers/pinctrl/Kconfig            |   17 +
+ drivers/pinctrl/Makefile           |    1 +
+ drivers/pinctrl/pinctrl-starfive.c | 1354 ++++++++++++++++++++++++++++
+ 4 files changed, 1380 insertions(+)
+ create mode 100644 drivers/pinctrl/pinctrl-starfive.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -17867,6 +17867,14 @@ F:    Documentation/devicetree/bindings/clo
+ F:    drivers/clk/starfive/clk-starfive-jh7100.c
+ F:    include/dt-bindings/clock/starfive-jh7100.h
+ 
++STARFIVE JH7100 PINCTRL DRIVER
++M:    Emil Renner Berthing <kernel@esmil.dk>
++L:    linux-gpio@vger.kernel.org
++S:    Maintained
++F:    Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
++F:    drivers/pinctrl/pinctrl-starfive.c
++F:    include/dt-bindings/pinctrl/pinctrl-starfive.h
++
+ STARFIVE JH7100 RESET CONTROLLER DRIVER
+ M:    Emil Renner Berthing <kernel@esmil.dk>
+ S:    Maintained
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -265,6 +265,23 @@ config PINCTRL_ST
+       select PINCONF
+       select GPIOLIB_IRQCHIP
+ 
++config PINCTRL_STARFIVE
++      tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
++      depends on SOC_STARFIVE || COMPILE_TEST
++      depends on OF
++      default SOC_STARFIVE
++      select GENERIC_PINCTRL_GROUPS
++      select GENERIC_PINMUX_FUNCTIONS
++      select GENERIC_PINCONF
++      select GPIOLIB
++      select GPIOLIB_IRQCHIP
++      select OF_GPIO
++      help
++        Say yes here to support pin control on the StarFive JH7100 SoC.
++        This also provides an interface to the GPIO pins not used by other
++        peripherals supporting inputs, outputs, configuring pull-up/pull-down
++        and interrupts on input changes.
++
+ config PINCTRL_STMFX
+       tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
+       depends on I2C
+--- a/drivers/pinctrl/Makefile
++++ b/drivers/pinctrl/Makefile
+@@ -38,6 +38,7 @@ obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-
+ obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
+ obj-$(CONFIG_PINCTRL_TB10X)   += pinctrl-tb10x.o
+ obj-$(CONFIG_PINCTRL_ST)      += pinctrl-st.o
++obj-$(CONFIG_PINCTRL_STARFIVE)        += pinctrl-starfive.o
+ obj-$(CONFIG_PINCTRL_STMFX)   += pinctrl-stmfx.o
+ obj-$(CONFIG_PINCTRL_ZYNQ)    += pinctrl-zynq.o
+ obj-$(CONFIG_PINCTRL_ZYNQMP)  += pinctrl-zynqmp.o
+--- /dev/null
++++ b/drivers/pinctrl/pinctrl-starfive.c
+@@ -0,0 +1,1354 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Pinctrl / GPIO driver for StarFive JH7100 SoC
++ *
++ * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#include <linux/bits.h>
++#include <linux/clk.h>
++#include <linux/gpio/driver.h>
++#include <linux/io.h>
++#include <linux/mod_devicetable.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++#include <linux/spinlock.h>
++
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinmux.h>
++
++#include <dt-bindings/pinctrl/pinctrl-starfive.h>
++
++#include "core.h"
++#include "pinctrl-utils.h"
++#include "pinmux.h"
++#include "pinconf.h"
++
++#define DRIVER_NAME "pinctrl-starfive"
++
++/*
++ * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
++ * https://github.com/starfive-tech/JH7100_Docs
++ */
++#define NR_GPIOS      64
++
++/*
++ * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
++ * are enabled. If set to 0 the GPIO interrupts are disabled.
++ */
++#define GPIOEN                0x000
++
++/*
++ * The following 32-bit registers come in pairs, but only the offset of the
++ * first register is defined. The first controls (interrupts for) GPIO 0-31 and
++ * the second GPIO 32-63.
++ */
++
++/*
++ * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
++ * interrupt is level-triggered.
++ */
++#define GPIOIS                0x010
++
++/*
++ * Edge-Trigger Interrupt Type.  If set to 1 the interrupt gets triggered on
++ * both positive and negative edges. If set to 0 the interrupt is triggered by a
++ * single edge.
++ */
++#define GPIOIBE               0x018
++
++/*
++ * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
++ * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
++ * interrupt is triggered on a falling edge (edge-triggered) or low level
++ * (level-triggered).
++ */
++#define GPIOIEV               0x020
++
++/*
++ * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0
++ * the interrupt is disabled (masked). Note that the current documentation is
++ * wrong and says the exct opposite of this.
++ */
++#define GPIOIE                0x028
++
++/*
++ * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
++ * interrupt.
++ */
++#define GPIOIC                0x030
++
++/*
++ * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
++ */
++#define GPIORIS               0x038
++
++/*
++ * Interrupt Status after Masking. A 1 means the configured edge or level was
++ * detected and not masked.
++ */
++#define GPIOMIS               0x040
++
++/*
++ * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
++ * a digital 1 and if 0 the pin is a digital 0.
++ */
++#define GPIODIN               0x048
++
++/*
++ * From the data sheet section 12.2, there are 64 32-bit output data registers
++ * and 64 output enable registers. Output data and output enable registers for
++ * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
++ * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c.  The stride
++ * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
++ * and GPOn_DOEN_CFG is 0x54 + 8n.
++ */
++#define GPON_DOUT_CFG 0x050
++#define GPON_DOEN_CFG 0x054
++
++/*
++ * From Section 12.3, there are 75 input signal configuration registers which
++ * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with
++ * GPI_USB_OVER_CURRENT_CFG 0x378
++ */
++#define GPI_CFG_OFFSET        0x250
++
++/*
++ * Pad Control Bits. There are 16 pad control bits for each pin located in 103
++ * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
++ * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16
++ * bit of each register.
++ */
++#define PAD_SLEW_RATE_MASK            GENMASK(11, 9)
++#define PAD_SLEW_RATE_POS             9
++#define PAD_BIAS_STRONG_PULL_UP               BIT(8)
++#define PAD_INPUT_ENABLE              BIT(7)
++#define PAD_INPUT_SCHMITT_ENABLE      BIT(6)
++#define PAD_BIAS_DISABLE              BIT(5)
++#define PAD_BIAS_PULL_DOWN            BIT(4)
++#define PAD_BIAS_MASK \
++      (PAD_BIAS_STRONG_PULL_UP | \
++       PAD_BIAS_DISABLE | \
++       PAD_BIAS_PULL_DOWN)
++#define PAD_DRIVE_STRENGTH_MASK               GENMASK(3, 0)
++#define PAD_DRIVE_STRENGTH_POS                0
++
++/*
++ * From Section 11, the IO_PADSHARE_SEL register can be programmed to select
++ * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
++ * PAD_GPIO pads. This is a global setting.
++ */
++#define IO_PADSHARE_SEL                       0x1a0
++
++/*
++ * This just needs to be some number such that when
++ * sfp->gpio.pin_base = PAD_INVALID_GPIO then
++ * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
++ * That is it should underflow and return something >= NR_GPIOS.
++ */
++#define PAD_INVALID_GPIO              0x10000
++
++/*
++ * The packed pinmux values from the device tree look like this:
++ *
++ *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
++ *  |  dout   |  doen   |  din   | dout rev | doen rev | gpio nr |
++ *
++ * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this:
++ *
++ *  |      31       | 30 - 8 |   7 - 0   |
++ *  | dout/doen rev | unused | dout/doen |
++ */
++static unsigned int starfive_pinmux_to_gpio(u32 v)
++{
++      return v & (NR_GPIOS - 1);
++}
++
++static u32 starfive_pinmux_to_dout(u32 v)
++{
++      return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));
++}
++
++static u32 starfive_pinmux_to_doen(u32 v)
++{
++      return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));
++}
++
++static u32 starfive_pinmux_to_din(u32 v)
++{
++      return (v >> 8) & GENMASK(7, 0);
++}
++
++/*
++ * The maximum GPIO output current depends on the chosen drive strength:
++ *
++ *  DS:   0     1     2     3     4     5     6     7
++ *  mA:  14.2  21.2  28.2  35.2  42.2  49.1  56.0  62.8
++ *
++ * After rounding that is 7*DS + 14 mA
++ */
++static u32 starfive_drive_strength_to_max_mA(u16 ds)
++{
++      return 7 * ds + 14;
++}
++
++static u16 starfive_drive_strength_from_max_mA(u32 i)
++{
++      return (clamp(i, 14U, 63U) - 14) / 7;
++}
++
++struct starfive_pinctrl {
++      struct gpio_chip gc;
++      struct pinctrl_gpio_range gpios;
++      raw_spinlock_t lock;
++      void __iomem *base;
++      void __iomem *padctl;
++      struct pinctrl_dev *pctl;
++};
++
++static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
++                                              unsigned int pin)
++{
++      return pin - sfp->gpios.pin_base;
++}
++
++static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,
++                                              unsigned int gpio)
++{
++      return sfp->gpios.pin_base + gpio;
++}
++
++static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
++{
++      struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
++
++      return container_of(gc, struct starfive_pinctrl, gc);
++}
++
++static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
++{
++      struct gpio_chip *gc = irq_desc_get_handler_data(desc);
++
++      return container_of(gc, struct starfive_pinctrl, gc);
++}
++
++static const struct pinctrl_pin_desc starfive_pins[] = {
++      PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),
++      PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),
++      PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),
++      PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),
++      PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),
++      PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),
++      PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),
++      PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),
++      PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),
++      PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),
++      PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),
++      PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),
++      PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),
++      PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),
++      PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),
++      PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),
++      PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),
++      PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),
++      PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),
++      PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),
++      PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),
++      PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),
++      PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),
++      PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),
++      PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),
++      PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),
++      PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),
++      PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),
++      PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),
++      PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),
++      PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),
++      PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),
++      PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),
++      PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),
++      PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),
++      PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),
++      PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),
++      PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),
++      PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),
++      PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),
++      PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),
++      PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),
++      PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),
++      PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),
++      PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),
++      PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),
++      PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),
++      PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),
++      PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),
++      PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),
++      PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),
++      PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),
++      PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),
++      PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),
++      PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),
++      PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),
++      PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),
++      PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),
++      PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),
++      PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),
++      PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),
++      PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),
++      PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),
++      PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"),
++      PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"),
++};
++
++#ifdef CONFIG_DEBUG_FS
++static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
++                                struct seq_file *s,
++                                unsigned int pin)
++{
++      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++      unsigned int gpio = starfive_pin_to_gpio(sfp, pin);
++      void __iomem *reg;
++      u32 dout, doen;
++
++      if (gpio >= NR_GPIOS)
++              return;
++
++      reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;
++      dout = readl_relaxed(reg + 0x000);
++      doen = readl_relaxed(reg + 0x004);
++
++      seq_printf(s, "dout=%lu%s doen=%lu%s",
++                 dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",
++                 doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");
++}
++#else
++#define starfive_pin_dbg_show NULL
++#endif
++
++static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
++                                 struct device_node *np,
++                                 struct pinctrl_map **maps,
++                                 unsigned int *num_maps)
++{
++      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++      struct device *dev = sfp->gc.parent;
++      struct device_node *child;
++      struct pinctrl_map *map;
++      const char **pgnames;
++      const char *grpname;
++      u32 *pinmux;
++      int ngroups;
++      int *pins;
++      int nmaps;
++      int ret;
++
++      nmaps = 0;
++      ngroups = 0;
++      for_each_child_of_node(np, child) {
++              int npinmux = of_property_count_u32_elems(child, "pinmux");
++              int npins   = of_property_count_u32_elems(child, "pins");
++
++              if (npinmux > 0 && npins > 0) {
++                      dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
++                              np, child);
++                      of_node_put(child);
++                      return -EINVAL;
++              }
++              if (npinmux == 0 && npins == 0) {
++                      dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
++                              np, child);
++                      of_node_put(child);
++                      return -EINVAL;
++              }
++
++              if (npinmux > 0)
++                      nmaps += 2;
++              else
++                      nmaps += 1;
++              ngroups += 1;
++      }
++
++      pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
++      if (!pgnames)
++              return -ENOMEM;
++
++      map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
++      if (!map)
++              return -ENOMEM;
++
++      nmaps = 0;
++      ngroups = 0;
++      for_each_child_of_node(np, child) {
++              int npins;
++              int i;
++
++              grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
++              if (!grpname) {
++                      ret = -ENOMEM;
++                      goto put_child;
++              }
++
++              pgnames[ngroups++] = grpname;
++
++              if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) {
++                      pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
++                      if (!pins) {
++                              ret = -ENOMEM;
++                              goto put_child;
++                      }
++
++                      pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
++                      if (!pinmux) {
++                              ret = -ENOMEM;
++                              goto put_child;
++                      }
++
++                      ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
++                      if (ret)
++                              goto put_child;
++
++                      for (i = 0; i < npins; i++) {
++                              unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
++
++                              pins[i] = starfive_gpio_to_pin(sfp, gpio);
++                      }
++
++                      map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
++                      map[nmaps].data.mux.function = np->name;
++                      map[nmaps].data.mux.group = grpname;
++                      nmaps += 1;
++              } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) {
++                      pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
++                      if (!pins) {
++                              ret = -ENOMEM;
++                              goto put_child;
++                      }
++
++                      pinmux = NULL;
++
++                      for (i = 0; i < npins; i++) {
++                              u32 v;
++
++                              ret = of_property_read_u32_index(child, "pins", i, &v);
++                              if (ret)
++                                      goto put_child;
++                              pins[i] = v;
++                      }
++              } else {
++                      ret = -EINVAL;
++                      goto put_child;
++              }
++
++              ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
++              if (ret < 0) {
++                      dev_err(dev, "error adding group %s: %d\n", grpname, ret);
++                      goto put_child;
++              }
++
++              ret = pinconf_generic_parse_dt_config(child, pctldev,
++                                                    &map[nmaps].data.configs.configs,
++                                                    &map[nmaps].data.configs.num_configs);
++              if (ret) {
++                      dev_err(dev, "error parsing pin config of group %s: %d\n",
++                              grpname, ret);
++                      goto put_child;
++              }
++
++              /* don't create a map if there are no pinconf settings */
++              if (map[nmaps].data.configs.num_configs == 0)
++                      continue;
++
++              map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
++              map[nmaps].data.configs.group_or_pin = grpname;
++              nmaps += 1;
++      }
++
++      ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
++      if (ret < 0) {
++              dev_err(dev, "error adding function %s: %d\n", np->name, ret);
++              goto free_map;
++      }
++
++      *maps = map;
++      *num_maps = nmaps;
++      return 0;
++
++put_child:
++      of_node_put(child);
++free_map:
++      pinctrl_utils_free_map(pctldev, map, nmaps);
++      return ret;
++}
++
++static const struct pinctrl_ops starfive_pinctrl_ops = {
++      .get_groups_count = pinctrl_generic_get_group_count,
++      .get_group_name = pinctrl_generic_get_group_name,
++      .get_group_pins = pinctrl_generic_get_group_pins,
++      .pin_dbg_show = starfive_pin_dbg_show,
++      .dt_node_to_map = starfive_dt_node_to_map,
++      .dt_free_map = pinctrl_utils_free_map,
++};
++
++static int starfive_set_mux(struct pinctrl_dev *pctldev,
++                          unsigned int fsel, unsigned int gsel)
++{
++      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++      struct device *dev = sfp->gc.parent;
++      const struct group_desc *group;
++      const u32 *pinmux;
++      unsigned int i;
++
++      group = pinctrl_generic_get_group(pctldev, gsel);
++      if (!group)
++              return -EINVAL;
++
++      pinmux = group->data;
++      for (i = 0; i < group->num_pins; i++) {
++              u32 v = pinmux[i];
++              unsigned int gpio = starfive_pinmux_to_gpio(v);
++              u32 dout = starfive_pinmux_to_dout(v);
++              u32 doen = starfive_pinmux_to_doen(v);
++              u32 din = starfive_pinmux_to_din(v);
++              void __iomem *reg_dout;
++              void __iomem *reg_doen;
++              void __iomem *reg_din;
++              unsigned long flags;
++
++              dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n",
++                      gpio, dout, doen, din);
++
++              reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
++              reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
++              if (din != GPI_NONE)
++                      reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;
++              else
++                      reg_din = NULL;
++
++              raw_spin_lock_irqsave(&sfp->lock, flags);
++              writel_relaxed(dout, reg_dout);
++              writel_relaxed(doen, reg_doen);
++              if (reg_din)
++                      writel_relaxed(gpio + 2, reg_din);
++              raw_spin_unlock_irqrestore(&sfp->lock, flags);
++      }
++
++      return 0;
++}
++
++static const struct pinmux_ops starfive_pinmux_ops = {
++      .get_functions_count = pinmux_generic_get_function_count,
++      .get_function_name = pinmux_generic_get_function_name,
++      .get_function_groups = pinmux_generic_get_function_groups,
++      .set_mux = starfive_set_mux,
++      .strict = true,
++};
++
++static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,
++                             unsigned int pin)
++{
++      void __iomem *reg = sfp->padctl + 4 * (pin / 2);
++      int shift = 16 * (pin % 2);
++
++      return readl_relaxed(reg) >> shift;
++}
++
++static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,
++                              unsigned int pin,
++                              u16 _mask, u16 _value)
++{
++      void __iomem *reg = sfp->padctl + 4 * (pin / 2);
++      int shift = 16 * (pin % 2);
++      u32 mask = (u32)_mask << shift;
++      u32 value = (u32)_value << shift;
++      unsigned long flags;
++
++      dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);
++
++      raw_spin_lock_irqsave(&sfp->lock, flags);
++      value |= readl_relaxed(reg) & ~mask;
++      writel_relaxed(value, reg);
++      raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++#define PIN_CONFIG_STARFIVE_STRONG_PULL_UP    (PIN_CONFIG_END + 1)
++
++static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {
++      { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
++};
++
++#ifdef CONFIG_DEBUG_FS
++static const struct pin_config_item starfive_pinconf_custom_conf_items[] = {
++      PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
++};
++
++static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) ==
++            ARRAY_SIZE(starfive_pinconf_custom_params));
++#else
++#define starfive_pinconf_custom_conf_items NULL
++#endif
++
++static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
++                              unsigned int pin, unsigned long *config)
++{
++      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++      int param = pinconf_to_config_param(*config);
++      u16 value = starfive_padctl_get(sfp, pin);
++      bool enabled;
++      u32 arg;
++
++      switch (param) {
++      case PIN_CONFIG_BIAS_DISABLE:
++              enabled = value & PAD_BIAS_DISABLE;
++              arg = 0;
++              break;
++      case PIN_CONFIG_BIAS_PULL_DOWN:
++              enabled = value & PAD_BIAS_PULL_DOWN;
++              arg = 1;
++              break;
++      case PIN_CONFIG_BIAS_PULL_UP:
++              enabled = !(value & PAD_BIAS_MASK);
++              arg = 1;
++              break;
++      case PIN_CONFIG_DRIVE_STRENGTH:
++              enabled = value & PAD_DRIVE_STRENGTH_MASK;
++              arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK);
++              break;
++      case PIN_CONFIG_INPUT_ENABLE:
++              enabled = value & PAD_INPUT_ENABLE;
++              arg = enabled;
++              break;
++      case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
++              enabled = value & PAD_INPUT_SCHMITT_ENABLE;
++              arg = enabled;
++              break;
++      case PIN_CONFIG_SLEW_RATE:
++              enabled = value & PAD_SLEW_RATE_MASK;
++              arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS;
++              break;
++      case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
++              enabled = value & PAD_BIAS_STRONG_PULL_UP;
++              arg = enabled;
++              break;
++      default:
++              return -ENOTSUPP;
++      }
++
++      *config = pinconf_to_config_packed(param, arg);
++      return enabled ? 0 : -EINVAL;
++}
++
++static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
++                                    unsigned int gsel, unsigned long *config)
++{
++      const struct group_desc *group;
++
++      group = pinctrl_generic_get_group(pctldev, gsel);
++      if (!group)
++              return -EINVAL;
++
++      return starfive_pinconf_get(pctldev, group->pins[0], config);
++}
++
++static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
++                                    unsigned int gsel,
++                                    unsigned long *configs,
++                                    unsigned int num_configs)
++{
++      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++      const struct group_desc *group;
++      u16 mask, value;
++      int i;
++
++      group = pinctrl_generic_get_group(pctldev, gsel);
++      if (!group)
++              return -EINVAL;
++
++      mask = 0;
++      value = 0;
++      for (i = 0; i < num_configs; i++) {
++              int param = pinconf_to_config_param(configs[i]);
++              u32 arg = pinconf_to_config_argument(configs[i]);
++
++              switch (param) {
++              case PIN_CONFIG_BIAS_DISABLE:
++                      mask |= PAD_BIAS_MASK;
++                      value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE;
++                      break;
++              case PIN_CONFIG_BIAS_PULL_DOWN:
++                      if (arg == 0)
++                              return -ENOTSUPP;
++                      mask |= PAD_BIAS_MASK;
++                      value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN;
++                      break;
++              case PIN_CONFIG_BIAS_PULL_UP:
++                      if (arg == 0)
++                              return -ENOTSUPP;
++                      mask |= PAD_BIAS_MASK;
++                      value = value & ~PAD_BIAS_MASK;
++                      break;
++              case PIN_CONFIG_DRIVE_STRENGTH:
++                      mask |= PAD_DRIVE_STRENGTH_MASK;
++                      value = (value & ~PAD_DRIVE_STRENGTH_MASK) |
++                              starfive_drive_strength_from_max_mA(arg);
++                      break;
++              case PIN_CONFIG_INPUT_ENABLE:
++                      mask |= PAD_INPUT_ENABLE;
++                      if (arg)
++                              value |= PAD_INPUT_ENABLE;
++                      else
++                              value &= ~PAD_INPUT_ENABLE;
++                      break;
++              case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
++                      mask |= PAD_INPUT_SCHMITT_ENABLE;
++                      if (arg)
++                              value |= PAD_INPUT_SCHMITT_ENABLE;
++                      else
++                              value &= ~PAD_INPUT_SCHMITT_ENABLE;
++                      break;
++              case PIN_CONFIG_SLEW_RATE:
++                      mask |= PAD_SLEW_RATE_MASK;
++                      value = (value & ~PAD_SLEW_RATE_MASK) |
++                              ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK);
++                      break;
++              case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
++                      if (arg) {
++                              mask |= PAD_BIAS_MASK;
++                              value = (value & ~PAD_BIAS_MASK) |
++                                      PAD_BIAS_STRONG_PULL_UP;
++                      } else {
++                              mask |= PAD_BIAS_STRONG_PULL_UP;
++                              value = value & ~PAD_BIAS_STRONG_PULL_UP;
++                      }
++                      break;
++              default:
++                      return -ENOTSUPP;
++              }
++      }
++
++      for (i = 0; i < group->num_pins; i++)
++              starfive_padctl_rmw(sfp, group->pins[i], mask, value);
++
++      return 0;
++}
++
++#ifdef CONFIG_DEBUG_FS
++static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
++                                    struct seq_file *s, unsigned int pin)
++{
++      struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++      u16 value = starfive_padctl_get(sfp, pin);
++
++      seq_printf(s, " (0x%03x)", value);
++}
++#else
++#define starfive_pinconf_dbg_show NULL
++#endif
++
++static const struct pinconf_ops starfive_pinconf_ops = {
++      .pin_config_get = starfive_pinconf_get,
++      .pin_config_group_get = starfive_pinconf_group_get,
++      .pin_config_group_set = starfive_pinconf_group_set,
++      .pin_config_dbg_show = starfive_pinconf_dbg_show,
++      .is_generic = true,
++};
++
++static struct pinctrl_desc starfive_desc = {
++      .name = DRIVER_NAME,
++      .pins = starfive_pins,
++      .npins = ARRAY_SIZE(starfive_pins),
++      .pctlops = &starfive_pinctrl_ops,
++      .pmxops = &starfive_pinmux_ops,
++      .confops = &starfive_pinconf_ops,
++      .owner = THIS_MODULE,
++      .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params),
++      .custom_params = starfive_pinconf_custom_params,
++      .custom_conf_items = starfive_pinconf_custom_conf_items,
++};
++
++static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio)
++{
++      return pinctrl_gpio_request(gc->base + gpio);
++}
++
++static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio)
++{
++      pinctrl_gpio_free(gc->base + gpio);
++}
++
++static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
++{
++      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++      void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
++
++      if (readl_relaxed(doen) == GPO_ENABLE)
++              return GPIO_LINE_DIRECTION_OUT;
++
++      return GPIO_LINE_DIRECTION_IN;
++}
++
++static int starfive_gpio_direction_input(struct gpio_chip *gc,
++                                       unsigned int gpio)
++{
++      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++      void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
++      unsigned long flags;
++
++      /* enable input and schmitt trigger */
++      starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
++                          PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
++                          PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE);
++
++      raw_spin_lock_irqsave(&sfp->lock, flags);
++      writel_relaxed(GPO_DISABLE, doen);
++      raw_spin_unlock_irqrestore(&sfp->lock, flags);
++      return 0;
++}
++
++static int starfive_gpio_direction_output(struct gpio_chip *gc,
++                                        unsigned int gpio, int value)
++{
++      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++      void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
++      void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
++      unsigned long flags;
++
++      raw_spin_lock_irqsave(&sfp->lock, flags);
++      writel_relaxed(value, dout);
++      writel_relaxed(GPO_ENABLE, doen);
++      raw_spin_unlock_irqrestore(&sfp->lock, flags);
++
++      /* disable input, schmitt trigger and bias */
++      starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
++                          PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
++                          PAD_BIAS_DISABLE);
++
++      return 0;
++}
++
++static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)
++{
++      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++      void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);
++
++      return !!(readl_relaxed(din) & BIT(gpio % 32));
++}
++
++static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
++                            int value)
++{
++      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++      void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
++      unsigned long flags;
++
++      raw_spin_lock_irqsave(&sfp->lock, flags);
++      writel_relaxed(value, dout);
++      raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
++                                  unsigned long config)
++{
++      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++      u32 arg = pinconf_to_config_argument(config);
++      u16 value;
++      u16 mask;
++
++      switch (pinconf_to_config_param(config)) {
++      case PIN_CONFIG_BIAS_DISABLE:
++              mask  = PAD_BIAS_MASK;
++              value = PAD_BIAS_DISABLE;
++              break;
++      case PIN_CONFIG_BIAS_PULL_DOWN:
++              if (arg == 0)
++                      return -ENOTSUPP;
++              mask  = PAD_BIAS_MASK;
++              value = PAD_BIAS_PULL_DOWN;
++              break;
++      case PIN_CONFIG_BIAS_PULL_UP:
++              if (arg == 0)
++                      return -ENOTSUPP;
++              mask  = PAD_BIAS_MASK;
++              value = 0;
++              break;
++      case PIN_CONFIG_DRIVE_PUSH_PULL:
++              return 0;
++      case PIN_CONFIG_INPUT_ENABLE:
++              mask  = PAD_INPUT_ENABLE;
++              value = arg ? PAD_INPUT_ENABLE : 0;
++              break;
++      case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
++              mask  = PAD_INPUT_SCHMITT_ENABLE;
++              value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0;
++              break;
++      default:
++              return -ENOTSUPP;
++      };
++
++      starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
++      return 0;
++}
++
++static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)
++{
++      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++
++      sfp->gpios.name = sfp->gc.label;
++      sfp->gpios.base = sfp->gc.base;
++      /*
++       * sfp->gpios.pin_base depends on the chosen signal group
++       * and is set in starfive_probe()
++       */
++      sfp->gpios.npins = NR_GPIOS;
++      sfp->gpios.gc = &sfp->gc;
++      pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
++      return 0;
++}
++
++static void starfive_irq_ack(struct irq_data *d)
++{
++      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++      irq_hw_number_t gpio = irqd_to_hwirq(d);
++      void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
++      u32 mask = BIT(gpio % 32);
++      unsigned long flags;
++
++      raw_spin_lock_irqsave(&sfp->lock, flags);
++      writel_relaxed(mask, ic);
++      raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static void starfive_irq_mask(struct irq_data *d)
++{
++      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++      irq_hw_number_t gpio = irqd_to_hwirq(d);
++      void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
++      u32 mask = BIT(gpio % 32);
++      unsigned long flags;
++      u32 value;
++
++      raw_spin_lock_irqsave(&sfp->lock, flags);
++      value = readl_relaxed(ie) & ~mask;
++      writel_relaxed(value, ie);
++      raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static void starfive_irq_mask_ack(struct irq_data *d)
++{
++      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++      irq_hw_number_t gpio = irqd_to_hwirq(d);
++      void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
++      void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
++      u32 mask = BIT(gpio % 32);
++      unsigned long flags;
++      u32 value;
++
++      raw_spin_lock_irqsave(&sfp->lock, flags);
++      value = readl_relaxed(ie) & ~mask;
++      writel_relaxed(value, ie);
++      writel_relaxed(mask, ic);
++      raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static void starfive_irq_unmask(struct irq_data *d)
++{
++      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++      irq_hw_number_t gpio = irqd_to_hwirq(d);
++      void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
++      u32 mask = BIT(gpio % 32);
++      unsigned long flags;
++      u32 value;
++
++      raw_spin_lock_irqsave(&sfp->lock, flags);
++      value = readl_relaxed(ie) | mask;
++      writel_relaxed(value, ie);
++      raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
++{
++      struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++      irq_hw_number_t gpio = irqd_to_hwirq(d);
++      void __iomem *base = sfp->base + 4 * (gpio / 32);
++      u32 mask = BIT(gpio % 32);
++      u32 irq_type, edge_both, polarity;
++      unsigned long flags;
++
++      switch (trigger) {
++      case IRQ_TYPE_EDGE_RISING:
++              irq_type  = mask; /* 1: edge triggered */
++              edge_both = 0;    /* 0: single edge */
++              polarity  = mask; /* 1: rising edge */
++              break;
++      case IRQ_TYPE_EDGE_FALLING:
++              irq_type  = mask; /* 1: edge triggered */
++              edge_both = 0;    /* 0: single edge */
++              polarity  = 0;    /* 0: falling edge */
++              break;
++      case IRQ_TYPE_EDGE_BOTH:
++              irq_type  = mask; /* 1: edge triggered */
++              edge_both = mask; /* 1: both edges */
++              polarity  = 0;    /* 0: ignored */
++              break;
++      case IRQ_TYPE_LEVEL_HIGH:
++              irq_type  = 0;    /* 0: level triggered */
++              edge_both = 0;    /* 0: ignored */
++              polarity  = mask; /* 1: high level */
++              break;
++      case IRQ_TYPE_LEVEL_LOW:
++              irq_type  = 0;    /* 0: level triggered */
++              edge_both = 0;    /* 0: ignored */
++              polarity  = 0;    /* 0: low level */
++              break;
++      default:
++              return -EINVAL;
++      }
++
++      if (trigger & IRQ_TYPE_EDGE_BOTH)
++              irq_set_handler_locked(d, handle_edge_irq);
++      else
++              irq_set_handler_locked(d, handle_level_irq);
++
++      raw_spin_lock_irqsave(&sfp->lock, flags);
++      irq_type |= readl_relaxed(base + GPIOIS) & ~mask;
++      writel_relaxed(irq_type, base + GPIOIS);
++      edge_both |= readl_relaxed(base + GPIOIBE) & ~mask;
++      writel_relaxed(edge_both, base + GPIOIBE);
++      polarity |= readl_relaxed(base + GPIOIEV) & ~mask;
++      writel_relaxed(polarity, base + GPIOIEV);
++      raw_spin_unlock_irqrestore(&sfp->lock, flags);
++      return 0;
++}
++
++static struct irq_chip starfive_irq_chip = {
++      .irq_ack = starfive_irq_ack,
++      .irq_mask = starfive_irq_mask,
++      .irq_mask_ack = starfive_irq_mask_ack,
++      .irq_unmask = starfive_irq_unmask,
++      .irq_set_type = starfive_irq_set_type,
++      .flags = IRQCHIP_SET_TYPE_MASKED,
++};
++
++static void starfive_gpio_irq_handler(struct irq_desc *desc)
++{
++      struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
++      struct irq_chip *chip = irq_desc_get_chip(desc);
++      unsigned long mis;
++      unsigned int pin;
++
++      chained_irq_enter(chip, desc);
++
++      mis = readl_relaxed(sfp->base + GPIOMIS + 0);
++      for_each_set_bit(pin, &mis, 32)
++              generic_handle_domain_irq(sfp->gc.irq.domain, pin);
++
++      mis = readl_relaxed(sfp->base + GPIOMIS + 4);
++      for_each_set_bit(pin, &mis, 32)
++              generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
++
++      chained_irq_exit(chip, desc);
++}
++
++static int starfive_gpio_init_hw(struct gpio_chip *gc)
++{
++      struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++
++      /* mask all GPIO interrupts */
++      writel(0, sfp->base + GPIOIE + 0);
++      writel(0, sfp->base + GPIOIE + 4);
++      /* clear edge interrupt flags */
++      writel(~0U, sfp->base + GPIOIC + 0);
++      writel(~0U, sfp->base + GPIOIC + 4);
++      /* enable GPIO interrupts */
++      writel(1, sfp->base + GPIOEN);
++      return 0;
++}
++
++static void starfive_disable_clock(void *data)
++{
++      clk_disable_unprepare(data);
++}
++
++static int starfive_probe(struct platform_device *pdev)
++{
++      struct device *dev = &pdev->dev;
++      struct starfive_pinctrl *sfp;
++      struct reset_control *rst;
++      struct clk *clk;
++      u32 value;
++      int ret;
++
++      sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
++      if (!sfp)
++              return -ENOMEM;
++
++      sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
++      if (IS_ERR(sfp->base))
++              return PTR_ERR(sfp->base);
++
++      sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
++      if (IS_ERR(sfp->padctl))
++              return PTR_ERR(sfp->padctl);
++
++      clk = devm_clk_get(dev, NULL);
++      if (IS_ERR(clk))
++              return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
++
++      rst = devm_reset_control_get_exclusive(dev, NULL);
++      if (IS_ERR(rst))
++              return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
++
++      ret = clk_prepare_enable(clk);
++      if (ret)
++              return dev_err_probe(dev, ret, "could not enable clock\n");
++
++      ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
++      if (ret)
++              return ret;
++
++      /*
++       * We don't want to assert reset and risk undoing pin muxing for the
++       * early boot serial console, but let's make sure the reset line is
++       * deasserted in case someone runs a really minimal bootloader.
++       */
++      ret = reset_control_deassert(rst);
++      if (ret)
++              return dev_err_probe(dev, ret, "could not deassert reset\n");
++
++      platform_set_drvdata(pdev, sfp);
++      sfp->gc.parent = dev;
++      raw_spin_lock_init(&sfp->lock);
++
++      ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
++      if (ret)
++              return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
++
++      if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {
++              if (value > 6)
++                      return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
++              writel(value, sfp->padctl + IO_PADSHARE_SEL);
++      }
++
++      value = readl(sfp->padctl + IO_PADSHARE_SEL);
++      switch (value) {
++      case 0:
++              sfp->gpios.pin_base = PAD_INVALID_GPIO;
++              goto out_pinctrl_enable;
++      case 1:
++              sfp->gpios.pin_base = PAD_GPIO(0);
++              break;
++      case 2:
++              sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
++              break;
++      case 3:
++              sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
++              break;
++      case 4: case 5: case 6:
++              sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
++              break;
++      default:
++              return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
++      }
++
++      sfp->gc.label = dev_name(dev);
++      sfp->gc.owner = THIS_MODULE;
++      sfp->gc.request = starfive_gpio_request;
++      sfp->gc.free = starfive_gpio_free;
++      sfp->gc.get_direction = starfive_gpio_get_direction;
++      sfp->gc.direction_input = starfive_gpio_direction_input;
++      sfp->gc.direction_output = starfive_gpio_direction_output;
++      sfp->gc.get = starfive_gpio_get;
++      sfp->gc.set = starfive_gpio_set;
++      sfp->gc.set_config = starfive_gpio_set_config;
++      sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
++      sfp->gc.base = -1;
++      sfp->gc.ngpio = NR_GPIOS;
++
++      starfive_irq_chip.parent_device = dev;
++      starfive_irq_chip.name = sfp->gc.label;
++
++      sfp->gc.irq.chip = &starfive_irq_chip;
++      sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
++      sfp->gc.irq.num_parents = 1;
++      sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
++                                         sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
++      if (!sfp->gc.irq.parents)
++              return -ENOMEM;
++      sfp->gc.irq.default_type = IRQ_TYPE_NONE;
++      sfp->gc.irq.handler = handle_bad_irq;
++      sfp->gc.irq.init_hw = starfive_gpio_init_hw;
++
++      ret = platform_get_irq(pdev, 0);
++      if (ret < 0)
++              return ret;
++      sfp->gc.irq.parents[0] = ret;
++
++      ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
++      if (ret)
++              return dev_err_probe(dev, ret, "could not register gpiochip\n");
++
++out_pinctrl_enable:
++      return pinctrl_enable(sfp->pctl);
++}
++
++static const struct of_device_id starfive_of_match[] = {
++      { .compatible = "starfive,jh7100-pinctrl" },
++      { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, starfive_of_match);
++
++static struct platform_driver starfive_pinctrl_driver = {
++      .probe = starfive_probe,
++      .driver = {
++              .name = DRIVER_NAME,
++              .of_match_table = starfive_of_match,
++      },
++};
++module_platform_driver(starfive_pinctrl_driver);
++
++MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs");
++MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
++MODULE_LICENSE("GPL v2");

diff --git a/target/linux/visionfive/patches-5.15/0019-dt-bindings-serial-snps-dw-apb-uart-Add-JH7100-uarts.patch b/target/linux/visionfive/patches-5.15/0019-dt-bindings-serial-snps-dw-apb-uart-Add-JH7100-uarts.patch
new file mode 100644 (file)
index 0000000..de51ae9
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0019-dt-bindings-serial-snps-dw-apb-uart-Add-JH7100-uarts.patch
@@ -0,0 +1,30 @@
+From dcab11c76d8545e7c97cae8e20ef3c2f589ff102 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Thu, 7 Oct 2021 14:24:29 +0200
+Subject: [PATCH 19/84] dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
+
+commit d0b65b1500973fef840dbc4bb9f9c237db2b761f upstream.
+
+Add compatibles for the StarFive JH7100 uarts.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../devicetree/bindings/serial/snps-dw-apb-uart.yaml         | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
++++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+@@ -40,6 +40,11 @@ properties:
+               - brcm,bcm11351-dw-apb-uart
+               - brcm,bcm21664-dw-apb-uart
+           - const: snps,dw-apb-uart
++      - items:
++          - enum:
++              - starfive,jh7100-hsuart
++              - starfive,jh7100-uart
++          - const: snps,dw-apb-uart
+       - const: snps,dw-apb-uart
+ 
+   reg:

diff --git a/target/linux/visionfive/patches-5.15/0020-serial-8250_dw-Add-StarFive-JH7100-quirk.patch b/target/linux/visionfive/patches-5.15/0020-serial-8250_dw-Add-StarFive-JH7100-quirk.patch
new file mode 100644 (file)
index 0000000..0dbe3ac
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0020-serial-8250_dw-Add-StarFive-JH7100-quirk.patch
@@ -0,0 +1,40 @@
+From ead8e09f1dd45dbb714783ec41e7e9a4224fce93 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Mon, 4 Oct 2021 19:40:29 +0200
+Subject: [PATCH 20/84] serial: 8250_dw: Add StarFive JH7100 quirk
+
+commit b0ad20a3b64bf653a717860819691b262c0b2a2b upstream.
+
+On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
+exactly 16 * 115200Hz and many other common bitrates. Trying this will
+only result in a higher input clock, but low enough that the UART's
+internal divisor can't come close enough to the baud rate target.
+So rather than try to set the input clock it's better to skip the
+clk_set_rate call and rely solely on the UART's internal divisor.
+
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/tty/serial/8250/8250_dw.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/tty/serial/8250/8250_dw.c
++++ b/drivers/tty/serial/8250/8250_dw.c
+@@ -414,6 +414,8 @@ static void dw8250_quirks(struct uart_po
+               }
+               if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
+                       p->serial_out = dw8250_serial_out38x;
++              if (of_device_is_compatible(np, "starfive,jh7100-uart"))
++                      p->set_termios = dw8250_do_set_termios;
+ 
+       } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
+               p->iotype = UPIO_MEM32;
+@@ -696,6 +698,7 @@ static const struct of_device_id dw8250_
+       { .compatible = "cavium,octeon-3860-uart" },
+       { .compatible = "marvell,armada-38x-uart" },
+       { .compatible = "renesas,rzn1-uart" },
++      { .compatible = "starfive,jh7100-uart" },
+       { /* Sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, dw8250_of_match);

diff --git a/target/linux/visionfive/patches-5.15/0021-RISC-V-Add-initial-StarFive-JH7100-device-tree.patch b/target/linux/visionfive/patches-5.15/0021-RISC-V-Add-initial-StarFive-JH7100-device-tree.patch
new file mode 100644 (file)
index 0000000..24befc5
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0021-RISC-V-Add-initial-StarFive-JH7100-device-tree.patch
@@ -0,0 +1,253 @@
+From 5a61f42bd05f8d081cd868a2d56500b4212f57d6 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 16:48:27 +0200
+Subject: [PATCH 21/84] RISC-V: Add initial StarFive JH7100 device tree
+
+commit ec85362fb121d0297b9f3bb56816ea6282c34fda upstream.
+
+Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
+is a test chip for their upcoming JH7110 SoC.
+
+The CPU and cache data is based on the device tree in the vendor u-boot
+port.
+
+Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 230 +++++++++++++++++++++++
+ 1 file changed, 230 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100.dtsi
+
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -0,0 +1,230 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include <dt-bindings/clock/starfive-jh7100.h>
++#include <dt-bindings/reset/starfive-jh7100.h>
++
++/ {
++      compatible = "starfive,jh7100";
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      cpus {
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              cpu@0 {
++                      compatible = "sifive,u74-mc", "riscv";
++                      reg = <0>;
++                      d-cache-block-size = <64>;
++                      d-cache-sets = <64>;
++                      d-cache-size = <32768>;
++                      d-tlb-sets = <1>;
++                      d-tlb-size = <32>;
++                      device_type = "cpu";
++                      i-cache-block-size = <64>;
++                      i-cache-sets = <64>;
++                      i-cache-size = <32768>;
++                      i-tlb-sets = <1>;
++                      i-tlb-size = <32>;
++                      mmu-type = "riscv,sv39";
++                      riscv,isa = "rv64imafdc";
++                      tlb-split;
++
++                      cpu0_intc: interrupt-controller {
++                              compatible = "riscv,cpu-intc";
++                              interrupt-controller;
++                              #interrupt-cells = <1>;
++                      };
++              };
++
++              cpu@1 {
++                      compatible = "sifive,u74-mc", "riscv";
++                      reg = <1>;
++                      d-cache-block-size = <64>;
++                      d-cache-sets = <64>;
++                      d-cache-size = <32768>;
++                      d-tlb-sets = <1>;
++                      d-tlb-size = <32>;
++                      device_type = "cpu";
++                      i-cache-block-size = <64>;
++                      i-cache-sets = <64>;
++                      i-cache-size = <32768>;
++                      i-tlb-sets = <1>;
++                      i-tlb-size = <32>;
++                      mmu-type = "riscv,sv39";
++                      riscv,isa = "rv64imafdc";
++                      tlb-split;
++
++                      cpu1_intc: interrupt-controller {
++                              compatible = "riscv,cpu-intc";
++                              interrupt-controller;
++                              #interrupt-cells = <1>;
++                      };
++              };
++      };
++
++      osc_sys: osc_sys {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              /* This value must be overridden by the board */
++              clock-frequency = <0>;
++      };
++
++      osc_aud: osc_aud {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              /* This value must be overridden by the board */
++              clock-frequency = <0>;
++      };
++
++      gmac_rmii_ref: gmac_rmii_ref {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              /* Should be overridden by the board when needed */
++              clock-frequency = <0>;
++      };
++
++      gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              /* Should be overridden by the board when needed */
++              clock-frequency = <0>;
++      };
++
++      soc {
++              compatible = "simple-bus";
++              interrupt-parent = <&plic>;
++              #address-cells = <2>;
++              #size-cells = <2>;
++              ranges;
++
++              clint: clint@2000000 {
++                      compatible = "starfive,jh7100-clint", "sifive,clint0";
++                      reg = <0x0 0x2000000 0x0 0x10000>;
++                      interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
++                                             &cpu1_intc 3 &cpu1_intc 7>;
++              };
++
++              plic: interrupt-controller@c000000 {
++                      compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
++                      reg = <0x0 0xc000000 0x0 0x4000000>;
++                      interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
++                                             &cpu1_intc 11 &cpu1_intc 9>;
++                      interrupt-controller;
++                      #address-cells = <0>;
++                      #interrupt-cells = <1>;
++                      riscv,ndev = <127>;
++              };
++
++              clkgen: clock-controller@11800000 {
++                      compatible = "starfive,jh7100-clkgen";
++                      reg = <0x0 0x11800000 0x0 0x10000>;
++                      clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
++                      clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
++                      #clock-cells = <1>;
++              };
++
++              rstgen: reset-controller@11840000 {
++                      compatible = "starfive,jh7100-reset";
++                      reg = <0x0 0x11840000 0x0 0x10000>;
++                      #reset-cells = <1>;
++              };
++
++              i2c0: i2c@118b0000 {
++                      compatible = "snps,designware-i2c";
++                      reg = <0x0 0x118b0000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
++                               <&clkgen JH7100_CLK_I2C0_APB>;
++                      clock-names = "ref", "pclk";
++                      resets = <&rstgen JH7100_RSTN_I2C0_APB>;
++                      interrupts = <96>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              i2c1: i2c@118c0000 {
++                      compatible = "snps,designware-i2c";
++                      reg = <0x0 0x118c0000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
++                               <&clkgen JH7100_CLK_I2C1_APB>;
++                      clock-names = "ref", "pclk";
++                      resets = <&rstgen JH7100_RSTN_I2C1_APB>;
++                      interrupts = <97>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              gpio: pinctrl@11910000 {
++                      compatible = "starfive,jh7100-pinctrl";
++                      reg = <0x0 0x11910000 0x0 0x10000>,
++                            <0x0 0x11858000 0x0 0x1000>;
++                      reg-names = "gpio", "padctl";
++                      clocks = <&clkgen JH7100_CLK_GPIO_APB>;
++                      resets = <&rstgen JH7100_RSTN_GPIO_APB>;
++                      interrupts = <32>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++              };
++
++              uart2: serial@12430000 {
++                      compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
++                      reg = <0x0 0x12430000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_UART2_CORE>,
++                               <&clkgen JH7100_CLK_UART2_APB>;
++                      clock-names = "baudclk", "apb_pclk";
++                      resets = <&rstgen JH7100_RSTN_UART2_APB>;
++                      interrupts = <72>;
++                      reg-io-width = <4>;
++                      reg-shift = <2>;
++                      status = "disabled";
++              };
++
++              uart3: serial@12440000 {
++                      compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
++                      reg = <0x0 0x12440000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_UART3_CORE>,
++                               <&clkgen JH7100_CLK_UART3_APB>;
++                      clock-names = "baudclk", "apb_pclk";
++                      resets = <&rstgen JH7100_RSTN_UART3_APB>;
++                      interrupts = <73>;
++                      reg-io-width = <4>;
++                      reg-shift = <2>;
++                      status = "disabled";
++              };
++
++              i2c2: i2c@12450000 {
++                      compatible = "snps,designware-i2c";
++                      reg = <0x0 0x12450000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
++                               <&clkgen JH7100_CLK_I2C2_APB>;
++                      clock-names = "ref", "pclk";
++                      resets = <&rstgen JH7100_RSTN_I2C2_APB>;
++                      interrupts = <74>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              i2c3: i2c@12460000 {
++                      compatible = "snps,designware-i2c";
++                      reg = <0x0 0x12460000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
++                               <&clkgen JH7100_CLK_I2C3_APB>;
++                      clock-names = "ref", "pclk";
++                      resets = <&rstgen JH7100_RSTN_I2C3_APB>;
++                      interrupts = <75>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++      };
++};

diff --git a/target/linux/visionfive/patches-5.15/0022-RISC-V-Add-BeagleV-Starlight-Beta-device-tree.patch b/target/linux/visionfive/patches-5.15/0022-RISC-V-Add-BeagleV-Starlight-Beta-device-tree.patch
new file mode 100644 (file)
index 0000000..f2ed10d
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0022-RISC-V-Add-BeagleV-Starlight-Beta-device-tree.patch
@@ -0,0 +1,207 @@
+From 8d48eea41d4f2b31671fdfc71d5bac50504a1ee1 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 19:48:36 +0200
+Subject: [PATCH 22/84] RISC-V: Add BeagleV Starlight Beta device tree
+
+commit a43676272a6e0b398781bc5337ca4cc187ba923d upstream.
+
+Add initial device tree for the BeagleV Starlight Beta board. About 300
+of these boards were sent out as part of a now cancelled BeagleBoard.org
+project.
+
+I2C timing data is based on the device tree in the vendor u-boot port.
+Heartbeat LED added by Geert.
+
+Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
+Co-developed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/boot/dts/Makefile                  |   1 +
+ arch/riscv/boot/dts/starfive/Makefile         |   2 +
+ .../dts/starfive/jh7100-beaglev-starlight.dts | 164 ++++++++++++++++++
+ 3 files changed, 167 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/starfive/Makefile
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+
+--- a/arch/riscv/boot/dts/Makefile
++++ b/arch/riscv/boot/dts/Makefile
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ subdir-y += sifive
++subdir-y += starfive
+ subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
+ subdir-y += microchip
+ 
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+@@ -0,0 +1,164 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include "jh7100.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/pinctrl-starfive.h>
++
++/ {
++      model = "BeagleV Starlight Beta";
++      compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
++
++      aliases {
++              serial0 = &uart3;
++      };
++
++      chosen {
++              stdout-path = "serial0:115200n8";
++      };
++
++      cpus {
++              timebase-frequency = <6250000>;
++      };
++
++      memory@80000000 {
++              device_type = "memory";
++              reg = <0x0 0x80000000 0x2 0x0>;
++      };
++
++      leds {
++              compatible = "gpio-leds";
++
++              led-ack {
++                      gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
++                      color = <LED_COLOR_ID_GREEN>;
++                      function = LED_FUNCTION_HEARTBEAT;
++                      linux,default-trigger = "heartbeat";
++                      label = "ack";
++              };
++      };
++};
++
++&gpio {
++      i2c0_pins: i2c0-0 {
++              i2c-pins {
++                      pinmux = <GPIOMUX(62, GPO_LOW,
++                                GPO_I2C0_PAD_SCK_OEN,
++                                GPI_I2C0_PAD_SCK_IN)>,
++                               <GPIOMUX(61, GPO_LOW,
++                                GPO_I2C0_PAD_SDA_OEN,
++                                GPI_I2C0_PAD_SDA_IN)>;
++                      bias-disable; /* external pull-up */
++                      input-enable;
++                      input-schmitt-enable;
++              };
++      };
++
++      i2c1_pins: i2c1-0 {
++              i2c-pins {
++                      pinmux = <GPIOMUX(47, GPO_LOW,
++                                GPO_I2C1_PAD_SCK_OEN,
++                                GPI_I2C1_PAD_SCK_IN)>,
++                               <GPIOMUX(48, GPO_LOW,
++                                GPO_I2C1_PAD_SDA_OEN,
++                                GPI_I2C1_PAD_SDA_IN)>;
++                      bias-pull-up;
++                      input-enable;
++                      input-schmitt-enable;
++              };
++      };
++
++      i2c2_pins: i2c2-0 {
++              i2c-pins {
++                      pinmux = <GPIOMUX(60, GPO_LOW,
++                                GPO_I2C2_PAD_SCK_OEN,
++                                GPI_I2C2_PAD_SCK_IN)>,
++                               <GPIOMUX(59, GPO_LOW,
++                                GPO_I2C2_PAD_SDA_OEN,
++                                GPI_I2C2_PAD_SDA_IN)>;
++                      bias-disable; /* external pull-up */
++                      input-enable;
++                      input-schmitt-enable;
++              };
++      };
++
++      uart3_pins: uart3-0 {
++              rx-pins {
++                      pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
++                                GPI_UART3_PAD_SIN)>;
++                      bias-pull-up;
++                      drive-strength = <14>;
++                      input-enable;
++                      input-schmitt-enable;
++                      slew-rate = <0>;
++              };
++              tx-pins {
++                      pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
++                                GPO_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      drive-strength = <35>;
++                      input-disable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++      };
++};
++
++&i2c0 {
++      clock-frequency = <100000>;
++      i2c-sda-hold-time-ns = <300>;
++      i2c-sda-falling-time-ns = <500>;
++      i2c-scl-falling-time-ns = <500>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&i2c0_pins>;
++      status = "okay";
++
++      pmic@5e {
++              compatible = "ti,tps65086";
++              reg = <0x5e>;
++              gpio-controller;
++              #gpio-cells = <2>;
++
++              regulators {
++              };
++      };
++};
++
++&i2c1 {
++      clock-frequency = <400000>;
++      i2c-sda-hold-time-ns = <300>;
++      i2c-sda-falling-time-ns = <100>;
++      i2c-scl-falling-time-ns = <100>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&i2c1_pins>;
++      status = "okay";
++};
++
++&i2c2 {
++      clock-frequency = <100000>;
++      i2c-sda-hold-time-ns = <300>;
++      i2c-sda-falling-time-ns = <500>;
++      i2c-scl-falling-time-ns = <500>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&i2c2_pins>;
++      status = "okay";
++};
++
++&osc_sys {
++      clock-frequency = <25000000>;
++};
++
++&osc_aud {
++      clock-frequency = <27000000>;
++};
++
++&uart3 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&uart3_pins>;
++      status = "okay";
++};

diff --git a/target/linux/visionfive/patches-5.15/0023-reset-starfive-jh7100-Fix-32bit-compilation.patch b/target/linux/visionfive/patches-5.15/0023-reset-starfive-jh7100-Fix-32bit-compilation.patch
new file mode 100644 (file)
index 0000000..3b49cdb
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0023-reset-starfive-jh7100-Fix-32bit-compilation.patch
@@ -0,0 +1,52 @@
+From 31a06b4aaea7b76da1c3d78b6387b57cbac88542 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Mon, 20 Dec 2021 13:17:59 +0100
+Subject: [PATCH 23/84] reset: starfive-jh7100: Fix 32bit compilation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+commit 299e6f788eab0b0aef97efb29ddc6971e7d0daf3 upstream.
+
+We need to include linux/io-64-nonatomic-lo-hi.h or readq/writeq won't
+be defined when compiling on 32bit architectures:
+
+On i386:
+
+../drivers/reset/reset-starfive-jh7100.c: In function ‘jh7100_reset_update’:
+../drivers/reset/reset-starfive-jh7100.c:81:10: error: implicit declaration of function ‘readq’; did you mean ‘readl’? [-Werror=implicit-function-declaration]
+  value = readq(reg_assert);
+           ^~~~~
+../drivers/reset/reset-starfive-jh7100.c:86:2: error: implicit declaration of function ‘writeq’; did you mean ‘writel’? [-Werror=implicit-function-declaration]
+  writeq(value, reg_assert);
+  ^~~~~~
+
+On m68k:
+
+drivers/reset/reset-starfive-jh7100.c:81:17: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration]
+drivers/reset/reset-starfive-jh7100.c:86:9: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
+cc1: all warnings being treated as errors
+make[3]: *** [scripts/Makefile.build:289: drivers/reset/reset-starfive-jh7100.o] Error 1
+make[2]: *** [scripts/Makefile.build:572: drivers/reset] Error 2
+make[1]: *** [Makefile:1969: drivers] Error 2
+make: *** [Makefile:226: __sub-make] Error 2
+
+Fixes: 0be3a1595bf8 ("reset: starfive-jh7100: Add StarFive JH7100 reset driver")
+Reported-by: Randy Dunlap <rdunlap@infradead.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+Link: https://lore.kernel.org/r/20211220121800.760846-1-kernel@esmil.dk'
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ drivers/reset/reset-starfive-jh7100.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/reset/reset-starfive-jh7100.c
++++ b/drivers/reset/reset-starfive-jh7100.c
+@@ -7,6 +7,7 @@
+ 
+ #include <linux/bitmap.h>
+ #include <linux/io.h>
++#include <linux/io-64-nonatomic-lo-hi.h>
+ #include <linux/iopoll.h>
+ #include <linux/mod_devicetable.h>
+ #include <linux/platform_device.h>

diff --git a/target/linux/visionfive/patches-5.15/0024-riscv-add-ARCH_DMA_MINALIGN-support.patch b/target/linux/visionfive/patches-5.15/0024-riscv-add-ARCH_DMA_MINALIGN-support.patch
new file mode 100644 (file)
index 0000000..93db3cf
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0024-riscv-add-ARCH_DMA_MINALIGN-support.patch
@@ -0,0 +1,23 @@
+From 6962e4410b6f694c8c3d6cf456b2c181adba3e7e Mon Sep 17 00:00:00 2001
+From: Xianting Tian <xianting.tian@linux.alibaba.com>
+Date: Sat, 7 Aug 2021 22:55:37 +0800
+Subject: [PATCH 24/84] riscv: add ARCH_DMA_MINALIGN support
+
+Introduce ARCH_DMA_MINALIGN to riscv arch.
+
+Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
+---
+ arch/riscv/include/asm/cache.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/riscv/include/asm/cache.h
++++ b/arch/riscv/include/asm/cache.h
+@@ -11,6 +11,8 @@
+ 
+ #define L1_CACHE_BYTES                (1 << L1_CACHE_SHIFT)
+ 
++#define ARCH_DMA_MINALIGN     L1_CACHE_BYTES
++
+ /*
+  * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
+  * the flat loader aligns it accordingly.

diff --git a/target/linux/visionfive/patches-5.15/0025-riscv-optimized-memcpy.patch b/target/linux/visionfive/patches-5.15/0025-riscv-optimized-memcpy.patch
new file mode 100644 (file)
index 0000000..2601004
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0025-riscv-optimized-memcpy.patch
@@ -0,0 +1,338 @@
+From baf7873619fedcc4a1377a56340cd733b15049ca Mon Sep 17 00:00:00 2001
+From: Matteo Croce <mcroce@microsoft.com>
+Date: Wed, 29 Sep 2021 19:22:32 +0200
+Subject: [PATCH 25/84] riscv: optimized memcpy
+
+Write a C version of memcpy() which uses the biggest data size allowed,
+without generating unaligned accesses.
+
+The procedure is made of three steps:
+First copy data one byte at time until the destination buffer is aligned
+to a long boundary.
+Then copy the data one long at time shifting the current and the next u8
+to compose a long at every cycle.
+Finally, copy the remainder one byte at time.
+
+On a BeagleV, the TCP RX throughput increased by 45%:
+
+before:
+
+$ iperf3 -c beaglev
+Connecting to host beaglev, port 5201
+[  5] local 192.168.85.6 port 44840 connected to 192.168.85.48 port 5201
+[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
+[  5]   0.00-1.00   sec  76.4 MBytes   641 Mbits/sec   27    624 KBytes
+[  5]   1.00-2.00   sec  72.5 MBytes   608 Mbits/sec    0    708 KBytes
+[  5]   2.00-3.00   sec  73.8 MBytes   619 Mbits/sec   10    451 KBytes
+[  5]   3.00-4.00   sec  72.5 MBytes   608 Mbits/sec    0    564 KBytes
+[  5]   4.00-5.00   sec  73.8 MBytes   619 Mbits/sec    0    658 KBytes
+[  5]   5.00-6.00   sec  73.8 MBytes   619 Mbits/sec   14    522 KBytes
+[  5]   6.00-7.00   sec  73.8 MBytes   619 Mbits/sec    0    621 KBytes
+[  5]   7.00-8.00   sec  72.5 MBytes   608 Mbits/sec    0    706 KBytes
+[  5]   8.00-9.00   sec  73.8 MBytes   619 Mbits/sec   20    580 KBytes
+[  5]   9.00-10.00  sec  73.8 MBytes   619 Mbits/sec    0    672 KBytes
+- - - - - - - - - - - - - - - - - - - - - - - - -
+[ ID] Interval           Transfer     Bitrate         Retr
+[  5]   0.00-10.00  sec   736 MBytes   618 Mbits/sec   71             sender
+[  5]   0.00-10.01  sec   733 MBytes   615 Mbits/sec                  receiver
+
+after:
+
+$ iperf3 -c beaglev
+Connecting to host beaglev, port 5201
+[  5] local 192.168.85.6 port 44864 connected to 192.168.85.48 port 5201
+[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
+[  5]   0.00-1.00   sec   109 MBytes   912 Mbits/sec   48    559 KBytes
+[  5]   1.00-2.00   sec   108 MBytes   902 Mbits/sec    0    690 KBytes
+[  5]   2.00-3.00   sec   106 MBytes   891 Mbits/sec   36    396 KBytes
+[  5]   3.00-4.00   sec   108 MBytes   902 Mbits/sec    0    567 KBytes
+[  5]   4.00-5.00   sec   106 MBytes   891 Mbits/sec    0    699 KBytes
+[  5]   5.00-6.00   sec   106 MBytes   891 Mbits/sec   32    414 KBytes
+[  5]   6.00-7.00   sec   106 MBytes   891 Mbits/sec    0    583 KBytes
+[  5]   7.00-8.00   sec   106 MBytes   891 Mbits/sec    0    708 KBytes
+[  5]   8.00-9.00   sec   106 MBytes   891 Mbits/sec   28    433 KBytes
+[  5]   9.00-10.00  sec   108 MBytes   902 Mbits/sec    0    591 KBytes
+- - - - - - - - - - - - - - - - - - - - - - - - -
+[ ID] Interval           Transfer     Bitrate         Retr
+[  5]   0.00-10.00  sec  1.04 GBytes   897 Mbits/sec  144             sender
+[  5]   0.00-10.01  sec  1.04 GBytes   894 Mbits/sec                  receiver
+
+And the decreased CPU time of the memcpy() is observable with perf top.
+This is the `perf top -Ue task-clock` output when doing the test:
+
+before:
+
+Overhead  Shared O  Symbol
+  42.22%  [kernel]  [k] memcpy
+  35.00%  [kernel]  [k] __asm_copy_to_user
+   3.50%  [kernel]  [k] sifive_l2_flush64_range
+   2.30%  [kernel]  [k] stmmac_napi_poll_rx
+   1.11%  [kernel]  [k] memset
+
+after:
+
+Overhead  Shared O  Symbol
+  45.69%  [kernel]  [k] __asm_copy_to_user
+  29.06%  [kernel]  [k] memcpy
+   4.09%  [kernel]  [k] sifive_l2_flush64_range
+   2.77%  [kernel]  [k] stmmac_napi_poll_rx
+   1.24%  [kernel]  [k] memset
+
+Signed-off-by: Matteo Croce <mcroce@microsoft.com>
+Reported-by: kernel test robot <lkp@intel.com>
+---
+ arch/riscv/include/asm/string.h |   8 ++-
+ arch/riscv/kernel/riscv_ksyms.c |   2 -
+ arch/riscv/lib/Makefile         |   2 +-
+ arch/riscv/lib/memcpy.S         | 108 --------------------------------
+ arch/riscv/lib/string.c         |  90 ++++++++++++++++++++++++++
+ 5 files changed, 97 insertions(+), 113 deletions(-)
+ delete mode 100644 arch/riscv/lib/memcpy.S
+ create mode 100644 arch/riscv/lib/string.c
+
+--- a/arch/riscv/include/asm/string.h
++++ b/arch/riscv/include/asm/string.h
+@@ -12,9 +12,13 @@
+ #define __HAVE_ARCH_MEMSET
+ extern asmlinkage void *memset(void *, int, size_t);
+ extern asmlinkage void *__memset(void *, int, size_t);
++
++#ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE
+ #define __HAVE_ARCH_MEMCPY
+-extern asmlinkage void *memcpy(void *, const void *, size_t);
+-extern asmlinkage void *__memcpy(void *, const void *, size_t);
++extern void *memcpy(void *dest, const void *src, size_t count);
++extern void *__memcpy(void *dest, const void *src, size_t count);
++#endif
++
+ #define __HAVE_ARCH_MEMMOVE
+ extern asmlinkage void *memmove(void *, const void *, size_t);
+ extern asmlinkage void *__memmove(void *, const void *, size_t);
+--- a/arch/riscv/kernel/riscv_ksyms.c
++++ b/arch/riscv/kernel/riscv_ksyms.c
+@@ -10,8 +10,6 @@
+  * Assembly functions that may be used (directly or indirectly) by modules
+  */
+ EXPORT_SYMBOL(memset);
+-EXPORT_SYMBOL(memcpy);
+ EXPORT_SYMBOL(memmove);
+ EXPORT_SYMBOL(__memset);
+-EXPORT_SYMBOL(__memcpy);
+ EXPORT_SYMBOL(__memmove);
+--- a/arch/riscv/lib/Makefile
++++ b/arch/riscv/lib/Makefile
+@@ -1,9 +1,9 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ lib-y                 += delay.o
+-lib-y                 += memcpy.o
+ lib-y                 += memset.o
+ lib-y                 += memmove.o
+ lib-$(CONFIG_MMU)     += uaccess.o
+ lib-$(CONFIG_64BIT)   += tishift.o
++lib-$(CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE) += string.o
+ 
+ obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o
+--- a/arch/riscv/lib/memcpy.S
++++ /dev/null
+@@ -1,108 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * Copyright (C) 2013 Regents of the University of California
+- */
+-
+-#include <linux/linkage.h>
+-#include <asm/asm.h>
+-
+-/* void *memcpy(void *, const void *, size_t) */
+-ENTRY(__memcpy)
+-WEAK(memcpy)
+-      move t6, a0  /* Preserve return value */
+-
+-      /* Defer to byte-oriented copy for small sizes */
+-      sltiu a3, a2, 128
+-      bnez a3, 4f
+-      /* Use word-oriented copy only if low-order bits match */
+-      andi a3, t6, SZREG-1
+-      andi a4, a1, SZREG-1
+-      bne a3, a4, 4f
+-
+-      beqz a3, 2f  /* Skip if already aligned */
+-      /*
+-       * Round to nearest double word-aligned address
+-       * greater than or equal to start address
+-       */
+-      andi a3, a1, ~(SZREG-1)
+-      addi a3, a3, SZREG
+-      /* Handle initial misalignment */
+-      sub a4, a3, a1
+-1:
+-      lb a5, 0(a1)
+-      addi a1, a1, 1
+-      sb a5, 0(t6)
+-      addi t6, t6, 1
+-      bltu a1, a3, 1b
+-      sub a2, a2, a4  /* Update count */
+-
+-2:
+-      andi a4, a2, ~((16*SZREG)-1)
+-      beqz a4, 4f
+-      add a3, a1, a4
+-3:
+-      REG_L a4,       0(a1)
+-      REG_L a5,   SZREG(a1)
+-      REG_L a6, 2*SZREG(a1)
+-      REG_L a7, 3*SZREG(a1)
+-      REG_L t0, 4*SZREG(a1)
+-      REG_L t1, 5*SZREG(a1)
+-      REG_L t2, 6*SZREG(a1)
+-      REG_L t3, 7*SZREG(a1)
+-      REG_L t4, 8*SZREG(a1)
+-      REG_L t5, 9*SZREG(a1)
+-      REG_S a4,       0(t6)
+-      REG_S a5,   SZREG(t6)
+-      REG_S a6, 2*SZREG(t6)
+-      REG_S a7, 3*SZREG(t6)
+-      REG_S t0, 4*SZREG(t6)
+-      REG_S t1, 5*SZREG(t6)
+-      REG_S t2, 6*SZREG(t6)
+-      REG_S t3, 7*SZREG(t6)
+-      REG_S t4, 8*SZREG(t6)
+-      REG_S t5, 9*SZREG(t6)
+-      REG_L a4, 10*SZREG(a1)
+-      REG_L a5, 11*SZREG(a1)
+-      REG_L a6, 12*SZREG(a1)
+-      REG_L a7, 13*SZREG(a1)
+-      REG_L t0, 14*SZREG(a1)
+-      REG_L t1, 15*SZREG(a1)
+-      addi a1, a1, 16*SZREG
+-      REG_S a4, 10*SZREG(t6)
+-      REG_S a5, 11*SZREG(t6)
+-      REG_S a6, 12*SZREG(t6)
+-      REG_S a7, 13*SZREG(t6)
+-      REG_S t0, 14*SZREG(t6)
+-      REG_S t1, 15*SZREG(t6)
+-      addi t6, t6, 16*SZREG
+-      bltu a1, a3, 3b
+-      andi a2, a2, (16*SZREG)-1  /* Update count */
+-
+-4:
+-      /* Handle trailing misalignment */
+-      beqz a2, 6f
+-      add a3, a1, a2
+-
+-      /* Use word-oriented copy if co-aligned to word boundary */
+-      or a5, a1, t6
+-      or a5, a5, a3
+-      andi a5, a5, 3
+-      bnez a5, 5f
+-7:
+-      lw a4, 0(a1)
+-      addi a1, a1, 4
+-      sw a4, 0(t6)
+-      addi t6, t6, 4
+-      bltu a1, a3, 7b
+-
+-      ret
+-
+-5:
+-      lb a4, 0(a1)
+-      addi a1, a1, 1
+-      sb a4, 0(t6)
+-      addi t6, t6, 1
+-      bltu a1, a3, 5b
+-6:
+-      ret
+-END(__memcpy)
+--- /dev/null
++++ b/arch/riscv/lib/string.c
+@@ -0,0 +1,90 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * String functions optimized for hardware which doesn't
++ * handle unaligned memory accesses efficiently.
++ *
++ * Copyright (C) 2021 Matteo Croce
++ */
++
++#include <linux/types.h>
++#include <linux/module.h>
++
++/* Minimum size for a word copy to be convenient */
++#define BYTES_LONG    sizeof(long)
++#define WORD_MASK     (BYTES_LONG - 1)
++#define MIN_THRESHOLD (BYTES_LONG * 2)
++
++/* convenience union to avoid cast between different pointer types */
++union types {
++      u8 *as_u8;
++      unsigned long *as_ulong;
++      uintptr_t as_uptr;
++};
++
++union const_types {
++      const u8 *as_u8;
++      unsigned long *as_ulong;
++      uintptr_t as_uptr;
++};
++
++void *__memcpy(void *dest, const void *src, size_t count)
++{
++      union const_types s = { .as_u8 = src };
++      union types d = { .as_u8 = dest };
++      int distance = 0;
++
++      if (!IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)) {
++              if (count < MIN_THRESHOLD)
++                      goto copy_remainder;
++
++              /* Copy a byte at time until destination is aligned. */
++              for (; d.as_uptr & WORD_MASK; count--)
++                      *d.as_u8++ = *s.as_u8++;
++
++              distance = s.as_uptr & WORD_MASK;
++      }
++
++      if (distance) {
++              unsigned long last, next;
++
++              /*
++               * s is distance bytes ahead of d, and d just reached
++               * the alignment boundary. Move s backward to word align it
++               * and shift data to compensate for distance, in order to do
++               * word-by-word copy.
++               */
++              s.as_u8 -= distance;
++
++              next = s.as_ulong[0];
++              for (; count >= BYTES_LONG; count -= BYTES_LONG) {
++                      last = next;
++                      next = s.as_ulong[1];
++
++                      d.as_ulong[0] = last >> (distance * 8) |
++                                      next << ((BYTES_LONG - distance) * 8);
++
++                      d.as_ulong++;
++                      s.as_ulong++;
++              }
++
++              /* Restore s with the original offset. */
++              s.as_u8 += distance;
++      } else {
++              /*
++               * If the source and dest lower bits are the same, do a simple
++               * 32/64 bit wide copy.
++               */
++              for (; count >= BYTES_LONG; count -= BYTES_LONG)
++                      *d.as_ulong++ = *s.as_ulong++;
++      }
++
++copy_remainder:
++      while (count--)
++              *d.as_u8++ = *s.as_u8++;
++
++      return dest;
++}
++EXPORT_SYMBOL(__memcpy);
++
++void *memcpy(void *dest, const void *src, size_t count) __weak __alias(__memcpy);
++EXPORT_SYMBOL(memcpy);

diff --git a/target/linux/visionfive/patches-5.15/0026-riscv-optimized-memmove.patch b/target/linux/visionfive/patches-5.15/0026-riscv-optimized-memmove.patch
new file mode 100644 (file)
index 0000000..d9f5db5
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0026-riscv-optimized-memmove.patch
@@ -0,0 +1,404 @@
+From 1fe30ee6168bf9b77b7bc7485a1ce878f866390d Mon Sep 17 00:00:00 2001
+From: Matteo Croce <mcroce@microsoft.com>
+Date: Wed, 29 Sep 2021 19:22:33 +0200
+Subject: [PATCH 26/84] riscv: optimized memmove
+
+When the destination buffer is before the source one, or when the
+buffers doesn't overlap, it's safe to use memcpy() instead, which is
+optimized to use a bigger data size possible.
+
+Signed-off-by: Matteo Croce <mcroce@microsoft.com>
+Reported-by: kernel test robot <lkp@intel.com>
+---
+ arch/riscv/include/asm/string.h |  6 ++--
+ arch/riscv/kernel/riscv_ksyms.c |  2 --
+ arch/riscv/lib/Makefile         |  1 -
+ arch/riscv/lib/memmove.S        | 64 ---------------------------------
+ arch/riscv/lib/string.c         | 23 ++++++++++++
+ 5 files changed, 26 insertions(+), 70 deletions(-)
+ delete mode 100644 arch/riscv/lib/memmove.S
+
+--- a/arch/riscv/include/asm/string.h
++++ b/arch/riscv/include/asm/string.h
+@@ -17,11 +17,11 @@ extern asmlinkage void *__memset(void *,
+ #define __HAVE_ARCH_MEMCPY
+ extern void *memcpy(void *dest, const void *src, size_t count);
+ extern void *__memcpy(void *dest, const void *src, size_t count);
++#define __HAVE_ARCH_MEMMOVE
++extern void *memmove(void *dest, const void *src, size_t count);
++extern void *__memmove(void *dest, const void *src, size_t count);
+ #endif
+ 
+-#define __HAVE_ARCH_MEMMOVE
+-extern asmlinkage void *memmove(void *, const void *, size_t);
+-extern asmlinkage void *__memmove(void *, const void *, size_t);
+ /* For those files which don't want to check by kasan. */
+ #if defined(CONFIG_KASAN) && !defined(__SANITIZE_ADDRESS__)
+ #define memcpy(dst, src, len) __memcpy(dst, src, len)
+--- a/arch/riscv/kernel/riscv_ksyms.c
++++ b/arch/riscv/kernel/riscv_ksyms.c
+@@ -10,6 +10,4 @@
+  * Assembly functions that may be used (directly or indirectly) by modules
+  */
+ EXPORT_SYMBOL(memset);
+-EXPORT_SYMBOL(memmove);
+ EXPORT_SYMBOL(__memset);
+-EXPORT_SYMBOL(__memmove);
+--- a/arch/riscv/lib/Makefile
++++ b/arch/riscv/lib/Makefile
+@@ -1,7 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ lib-y                 += delay.o
+ lib-y                 += memset.o
+-lib-y                 += memmove.o
+ lib-$(CONFIG_MMU)     += uaccess.o
+ lib-$(CONFIG_64BIT)   += tishift.o
+ lib-$(CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE) += string.o
+--- a/arch/riscv/lib/memmove.S
++++ /dev/null
+@@ -1,316 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * Copyright (C) 2022 Michael T. Kloos <michael@michaelkloos.com>
+- */
+-
+-#include <linux/linkage.h>
+-#include <asm/asm.h>
+-
+-SYM_FUNC_START(__memmove)
+-SYM_FUNC_START_WEAK(memmove)
+-      /*
+-       * Returns
+-       *   a0 - dest
+-       *
+-       * Parameters
+-       *   a0 - Inclusive first byte of dest
+-       *   a1 - Inclusive first byte of src
+-       *   a2 - Length of copy n
+-       *
+-       * Because the return matches the parameter register a0,
+-       * we will not clobber or modify that register.
+-       *
+-       * Note: This currently only works on little-endian.
+-       * To port to big-endian, reverse the direction of shifts
+-       * in the 2 misaligned fixup copy loops.
+-       */
+-
+-      /* Return if nothing to do */
+-      beq a0, a1, return_from_memmove
+-      beqz a2, return_from_memmove
+-
+-      /*
+-       * Register Uses
+-       *      Forward Copy: a1 - Index counter of src
+-       *      Reverse Copy: a4 - Index counter of src
+-       *      Forward Copy: t3 - Index counter of dest
+-       *      Reverse Copy: t4 - Index counter of dest
+-       *   Both Copy Modes: t5 - Inclusive first multibyte/aligned of dest
+-       *   Both Copy Modes: t6 - Non-Inclusive last multibyte/aligned of dest
+-       *   Both Copy Modes: t0 - Link / Temporary for load-store
+-       *   Both Copy Modes: t1 - Temporary for load-store
+-       *   Both Copy Modes: t2 - Temporary for load-store
+-       *   Both Copy Modes: a5 - dest to src alignment offset
+-       *   Both Copy Modes: a6 - Shift ammount
+-       *   Both Copy Modes: a7 - Inverse Shift ammount
+-       *   Both Copy Modes: a2 - Alternate breakpoint for unrolled loops
+-       */
+-
+-      /*
+-       * Solve for some register values now.
+-       * Byte copy does not need t5 or t6.
+-       */
+-      mv   t3, a0
+-      add  t4, a0, a2
+-      add  a4, a1, a2
+-
+-      /*
+-       * Byte copy if copying less than (2 * SZREG) bytes. This can
+-       * cause problems with the bulk copy implementation and is
+-       * small enough not to bother.
+-       */
+-      andi t0, a2, -(2 * SZREG)
+-      beqz t0, byte_copy
+-
+-      /*
+-       * Now solve for t5 and t6.
+-       */
+-      andi t5, t3, -SZREG
+-      andi t6, t4, -SZREG
+-      /*
+-       * If dest(Register t3) rounded down to the nearest naturally
+-       * aligned SZREG address, does not equal dest, then add SZREG
+-       * to find the low-bound of SZREG alignment in the dest memory
+-       * region.  Note that this could overshoot the dest memory
+-       * region if n is less than SZREG.  This is one reason why
+-       * we always byte copy if n is less than SZREG.
+-       * Otherwise, dest is already naturally aligned to SZREG.
+-       */
+-      beq  t5, t3, 1f
+-              addi t5, t5, SZREG
+-      1:
+-
+-      /*
+-       * If the dest and src are co-aligned to SZREG, then there is
+-       * no need for the full rigmarole of a full misaligned fixup copy.
+-       * Instead, do a simpler co-aligned copy.
+-       */
+-      xor  t0, a0, a1
+-      andi t1, t0, (SZREG - 1)
+-      beqz t1, coaligned_copy
+-      /* Fall through to misaligned fixup copy */
+-
+-misaligned_fixup_copy:
+-      bltu a1, a0, misaligned_fixup_copy_reverse
+-
+-misaligned_fixup_copy_forward:
+-      jal  t0, byte_copy_until_aligned_forward
+-
+-      andi a5, a1, (SZREG - 1) /* Find the alignment offset of src (a1) */
+-      slli a6, a5, 3 /* Multiply by 8 to convert that to bits to shift */
+-      sub  a5, a1, t3 /* Find the difference between src and dest */
+-      andi a1, a1, -SZREG /* Align the src pointer */
+-      addi a2, t6, SZREG /* The other breakpoint for the unrolled loop*/
+-
+-      /*
+-       * Compute The Inverse Shift
+-       * a7 = XLEN - a6 = XLEN + -a6
+-       * 2s complement negation to find the negative: -a6 = ~a6 + 1
+-       * Add that to XLEN.  XLEN = SZREG * 8.
+-       */
+-      not  a7, a6
+-      addi a7, a7, (SZREG * 8 + 1)
+-
+-      /*
+-       * Fix Misalignment Copy Loop - Forward
+-       * load_val0 = load_ptr[0];
+-       * do {
+-       *      load_val1 = load_ptr[1];
+-       *      store_ptr += 2;
+-       *      store_ptr[0 - 2] = (load_val0 >> {a6}) | (load_val1 << {a7});
+-       *
+-       *      if (store_ptr == {a2})
+-       *              break;
+-       *
+-       *      load_val0 = load_ptr[2];
+-       *      load_ptr += 2;
+-       *      store_ptr[1 - 2] = (load_val1 >> {a6}) | (load_val0 << {a7});
+-       *
+-       * } while (store_ptr != store_ptr_end);
+-       * store_ptr = store_ptr_end;
+-       */
+-
+-      REG_L t0, (0 * SZREG)(a1)
+-      1:
+-      REG_L t1, (1 * SZREG)(a1)
+-      addi  t3, t3, (2 * SZREG)
+-      srl   t0, t0, a6
+-      sll   t2, t1, a7
+-      or    t2, t0, t2
+-      REG_S t2, ((0 * SZREG) - (2 * SZREG))(t3)
+-
+-      beq   t3, a2, 2f
+-
+-      REG_L t0, (2 * SZREG)(a1)
+-      addi  a1, a1, (2 * SZREG)
+-      srl   t1, t1, a6
+-      sll   t2, t0, a7
+-      or    t2, t1, t2
+-      REG_S t2, ((1 * SZREG) - (2 * SZREG))(t3)
+-
+-      bne   t3, t6, 1b
+-      2:
+-      mv    t3, t6 /* Fix the dest pointer in case the loop was broken */
+-
+-      add  a1, t3, a5 /* Restore the src pointer */
+-      j byte_copy_forward /* Copy any remaining bytes */
+-
+-misaligned_fixup_copy_reverse:
+-      jal  t0, byte_copy_until_aligned_reverse
+-
+-      andi a5, a4, (SZREG - 1) /* Find the alignment offset of src (a4) */
+-      slli a6, a5, 3 /* Multiply by 8 to convert that to bits to shift */
+-      sub  a5, a4, t4 /* Find the difference between src and dest */
+-      andi a4, a4, -SZREG /* Align the src pointer */
+-      addi a2, t5, -SZREG /* The other breakpoint for the unrolled loop*/
+-
+-      /*
+-       * Compute The Inverse Shift
+-       * a7 = XLEN - a6 = XLEN + -a6
+-       * 2s complement negation to find the negative: -a6 = ~a6 + 1
+-       * Add that to XLEN.  XLEN = SZREG * 8.
+-       */
+-      not  a7, a6
+-      addi a7, a7, (SZREG * 8 + 1)
+-
+-      /*
+-       * Fix Misalignment Copy Loop - Reverse
+-       * load_val1 = load_ptr[0];
+-       * do {
+-       *      load_val0 = load_ptr[-1];
+-       *      store_ptr -= 2;
+-       *      store_ptr[1] = (load_val0 >> {a6}) | (load_val1 << {a7});
+-       *
+-       *      if (store_ptr == {a2})
+-       *              break;
+-       *
+-       *      load_val1 = load_ptr[-2];
+-       *      load_ptr -= 2;
+-       *      store_ptr[0] = (load_val1 >> {a6}) | (load_val0 << {a7});
+-       *
+-       * } while (store_ptr != store_ptr_end);
+-       * store_ptr = store_ptr_end;
+-       */
+-
+-      REG_L t1, ( 0 * SZREG)(a4)
+-      1:
+-      REG_L t0, (-1 * SZREG)(a4)
+-      addi  t4, t4, (-2 * SZREG)
+-      sll   t1, t1, a7
+-      srl   t2, t0, a6
+-      or    t2, t1, t2
+-      REG_S t2, ( 1 * SZREG)(t4)
+-
+-      beq   t4, a2, 2f
+-
+-      REG_L t1, (-2 * SZREG)(a4)
+-      addi  a4, a4, (-2 * SZREG)
+-      sll   t0, t0, a7
+-      srl   t2, t1, a6
+-      or    t2, t0, t2
+-      REG_S t2, ( 0 * SZREG)(t4)
+-
+-      bne   t4, t5, 1b
+-      2:
+-      mv    t4, t5 /* Fix the dest pointer in case the loop was broken */
+-
+-      add  a4, t4, a5 /* Restore the src pointer */
+-      j byte_copy_reverse /* Copy any remaining bytes */
+-
+-/*
+- * Simple copy loops for SZREG co-aligned memory locations.
+- * These also make calls to do byte copies for any unaligned
+- * data at their terminations.
+- */
+-coaligned_copy:
+-      bltu a1, a0, coaligned_copy_reverse
+-
+-coaligned_copy_forward:
+-      jal t0, byte_copy_until_aligned_forward
+-
+-      1:
+-      REG_L t1, ( 0 * SZREG)(a1)
+-      addi  a1, a1, SZREG
+-      addi  t3, t3, SZREG
+-      REG_S t1, (-1 * SZREG)(t3)
+-      bne   t3, t6, 1b
+-
+-      j byte_copy_forward /* Copy any remaining bytes */
+-
+-coaligned_copy_reverse:
+-      jal t0, byte_copy_until_aligned_reverse
+-
+-      1:
+-      REG_L t1, (-1 * SZREG)(a4)
+-      addi  a4, a4, -SZREG
+-      addi  t4, t4, -SZREG
+-      REG_S t1, ( 0 * SZREG)(t4)
+-      bne   t4, t5, 1b
+-
+-      j byte_copy_reverse /* Copy any remaining bytes */
+-
+-/*
+- * These are basically sub-functions within the function.  They
+- * are used to byte copy until the dest pointer is in alignment.
+- * At which point, a bulk copy method can be used by the
+- * calling code.  These work on the same registers as the bulk
+- * copy loops.  Therefore, the register values can be picked
+- * up from where they were left and we avoid code duplication
+- * without any overhead except the call in and return jumps.
+- */
+-byte_copy_until_aligned_forward:
+-      beq  t3, t5, 2f
+-      1:
+-      lb   t1,  0(a1)
+-      addi a1, a1, 1
+-      addi t3, t3, 1
+-      sb   t1, -1(t3)
+-      bne  t3, t5, 1b
+-      2:
+-      jalr zero, 0x0(t0) /* Return to multibyte copy loop */
+-
+-byte_copy_until_aligned_reverse:
+-      beq  t4, t6, 2f
+-      1:
+-      lb   t1, -1(a4)
+-      addi a4, a4, -1
+-      addi t4, t4, -1
+-      sb   t1,  0(t4)
+-      bne  t4, t6, 1b
+-      2:
+-      jalr zero, 0x0(t0) /* Return to multibyte copy loop */
+-
+-/*
+- * Simple byte copy loops.
+- * These will byte copy until they reach the end of data to copy.
+- * At that point, they will call to return from memmove.
+- */
+-byte_copy:
+-      bltu a1, a0, byte_copy_reverse
+-
+-byte_copy_forward:
+-      beq  t3, t4, 2f
+-      1:
+-      lb   t1,  0(a1)
+-      addi a1, a1, 1
+-      addi t3, t3, 1
+-      sb   t1, -1(t3)
+-      bne  t3, t4, 1b
+-      2:
+-      ret
+-
+-byte_copy_reverse:
+-      beq  t4, t3, 2f
+-      1:
+-      lb   t1, -1(a4)
+-      addi a4, a4, -1
+-      addi t4, t4, -1
+-      sb   t1,  0(t4)
+-      bne  t4, t3, 1b
+-      2:
+-
+-return_from_memmove:
+-      ret
+-
+-SYM_FUNC_END(memmove)
+-SYM_FUNC_END(__memmove)
+--- a/arch/riscv/lib/string.c
++++ b/arch/riscv/lib/string.c
+@@ -88,3 +88,26 @@ EXPORT_SYMBOL(__memcpy);
+ 
+ void *memcpy(void *dest, const void *src, size_t count) __weak __alias(__memcpy);
+ EXPORT_SYMBOL(memcpy);
++
++/*
++ * Simply check if the buffer overlaps an call memcpy() in case,
++ * otherwise do a simple one byte at time backward copy.
++ */
++void *__memmove(void *dest, const void *src, size_t count)
++{
++      if (dest < src || src + count <= dest)
++              return __memcpy(dest, src, count);
++
++      if (dest > src) {
++              const char *s = src + count;
++              char *tmp = dest + count;
++
++              while (count--)
++                      *--tmp = *--s;
++      }
++      return dest;
++}
++EXPORT_SYMBOL(__memmove);
++
++void *memmove(void *dest, const void *src, size_t count) __weak __alias(__memmove);
++EXPORT_SYMBOL(memmove);

diff --git a/target/linux/visionfive/patches-5.15/0027-riscv-optimized-memset.patch b/target/linux/visionfive/patches-5.15/0027-riscv-optimized-memset.patch
new file mode 100644 (file)
index 0000000..d85ef89
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0027-riscv-optimized-memset.patch
@@ -0,0 +1,242 @@
+From f18b603c2e5ced4fbf3dc4a9b0cb2a118383504b Mon Sep 17 00:00:00 2001
+From: Matteo Croce <mcroce@microsoft.com>
+Date: Wed, 29 Sep 2021 19:22:34 +0200
+Subject: [PATCH 27/84] riscv: optimized memset
+
+The generic memset is defined as a byte at time write. This is always
+safe, but it's slower than a 4 byte or even 8 byte write.
+
+Write a generic memset which fills the data one byte at time until the
+destination is aligned, then fills using the largest size allowed,
+and finally fills the remaining data one byte at time.
+
+Signed-off-by: Matteo Croce <mcroce@microsoft.com>
+---
+ arch/riscv/include/asm/string.h |  10 +--
+ arch/riscv/kernel/Makefile      |   1 -
+ arch/riscv/kernel/riscv_ksyms.c |  13 ----
+ arch/riscv/lib/Makefile         |   1 -
+ arch/riscv/lib/memset.S         | 113 --------------------------------
+ arch/riscv/lib/string.c         |  41 ++++++++++++
+ 6 files changed, 44 insertions(+), 135 deletions(-)
+ delete mode 100644 arch/riscv/kernel/riscv_ksyms.c
+ delete mode 100644 arch/riscv/lib/memset.S
+
+--- a/arch/riscv/include/asm/string.h
++++ b/arch/riscv/include/asm/string.h
+@@ -6,14 +6,10 @@
+ #ifndef _ASM_RISCV_STRING_H
+ #define _ASM_RISCV_STRING_H
+ 
+-#include <linux/types.h>
+-#include <linux/linkage.h>
+-
+-#define __HAVE_ARCH_MEMSET
+-extern asmlinkage void *memset(void *, int, size_t);
+-extern asmlinkage void *__memset(void *, int, size_t);
+-
+ #ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE
++#define __HAVE_ARCH_MEMSET
++extern void *memset(void *s, int c, size_t count);
++extern void *__memset(void *s, int c, size_t count);
+ #define __HAVE_ARCH_MEMCPY
+ extern void *memcpy(void *dest, const void *src, size_t count);
+ extern void *__memcpy(void *dest, const void *src, size_t count);
+--- a/arch/riscv/kernel/Makefile
++++ b/arch/riscv/kernel/Makefile
+@@ -31,7 +31,6 @@ obj-y        += syscall_table.o
+ obj-y += sys_riscv.o
+ obj-y += time.o
+ obj-y += traps.o
+-obj-y += riscv_ksyms.o
+ obj-y += stacktrace.o
+ obj-y += cacheinfo.o
+ obj-y += patch.o
+--- a/arch/riscv/kernel/riscv_ksyms.c
++++ /dev/null
+@@ -1,13 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-only
+-/*
+- * Copyright (C) 2017 Zihao Yu
+- */
+-
+-#include <linux/export.h>
+-#include <linux/uaccess.h>
+-
+-/*
+- * Assembly functions that may be used (directly or indirectly) by modules
+- */
+-EXPORT_SYMBOL(memset);
+-EXPORT_SYMBOL(__memset);
+--- a/arch/riscv/lib/Makefile
++++ b/arch/riscv/lib/Makefile
+@@ -1,6 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ lib-y                 += delay.o
+-lib-y                 += memset.o
+ lib-$(CONFIG_MMU)     += uaccess.o
+ lib-$(CONFIG_64BIT)   += tishift.o
+ lib-$(CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE) += string.o
+--- a/arch/riscv/lib/memset.S
++++ /dev/null
+@@ -1,113 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * Copyright (C) 2013 Regents of the University of California
+- */
+-
+-
+-#include <linux/linkage.h>
+-#include <asm/asm.h>
+-
+-/* void *memset(void *, int, size_t) */
+-ENTRY(__memset)
+-WEAK(memset)
+-      move t0, a0  /* Preserve return value */
+-
+-      /* Defer to byte-oriented fill for small sizes */
+-      sltiu a3, a2, 16
+-      bnez a3, 4f
+-
+-      /*
+-       * Round to nearest XLEN-aligned address
+-       * greater than or equal to start address
+-       */
+-      addi a3, t0, SZREG-1
+-      andi a3, a3, ~(SZREG-1)
+-      beq a3, t0, 2f  /* Skip if already aligned */
+-      /* Handle initial misalignment */
+-      sub a4, a3, t0
+-1:
+-      sb a1, 0(t0)
+-      addi t0, t0, 1
+-      bltu t0, a3, 1b
+-      sub a2, a2, a4  /* Update count */
+-
+-2: /* Duff's device with 32 XLEN stores per iteration */
+-      /* Broadcast value into all bytes */
+-      andi a1, a1, 0xff
+-      slli a3, a1, 8
+-      or a1, a3, a1
+-      slli a3, a1, 16
+-      or a1, a3, a1
+-#ifdef CONFIG_64BIT
+-      slli a3, a1, 32
+-      or a1, a3, a1
+-#endif
+-
+-      /* Calculate end address */
+-      andi a4, a2, ~(SZREG-1)
+-      add a3, t0, a4
+-
+-      andi a4, a4, 31*SZREG  /* Calculate remainder */
+-      beqz a4, 3f            /* Shortcut if no remainder */
+-      neg a4, a4
+-      addi a4, a4, 32*SZREG  /* Calculate initial offset */
+-
+-      /* Adjust start address with offset */
+-      sub t0, t0, a4
+-
+-      /* Jump into loop body */
+-      /* Assumes 32-bit instruction lengths */
+-      la a5, 3f
+-#ifdef CONFIG_64BIT
+-      srli a4, a4, 1
+-#endif
+-      add a5, a5, a4
+-      jr a5
+-3:
+-      REG_S a1,        0(t0)
+-      REG_S a1,    SZREG(t0)
+-      REG_S a1,  2*SZREG(t0)
+-      REG_S a1,  3*SZREG(t0)
+-      REG_S a1,  4*SZREG(t0)
+-      REG_S a1,  5*SZREG(t0)
+-      REG_S a1,  6*SZREG(t0)
+-      REG_S a1,  7*SZREG(t0)
+-      REG_S a1,  8*SZREG(t0)
+-      REG_S a1,  9*SZREG(t0)
+-      REG_S a1, 10*SZREG(t0)
+-      REG_S a1, 11*SZREG(t0)
+-      REG_S a1, 12*SZREG(t0)
+-      REG_S a1, 13*SZREG(t0)
+-      REG_S a1, 14*SZREG(t0)
+-      REG_S a1, 15*SZREG(t0)
+-      REG_S a1, 16*SZREG(t0)
+-      REG_S a1, 17*SZREG(t0)
+-      REG_S a1, 18*SZREG(t0)
+-      REG_S a1, 19*SZREG(t0)
+-      REG_S a1, 20*SZREG(t0)
+-      REG_S a1, 21*SZREG(t0)
+-      REG_S a1, 22*SZREG(t0)
+-      REG_S a1, 23*SZREG(t0)
+-      REG_S a1, 24*SZREG(t0)
+-      REG_S a1, 25*SZREG(t0)
+-      REG_S a1, 26*SZREG(t0)
+-      REG_S a1, 27*SZREG(t0)
+-      REG_S a1, 28*SZREG(t0)
+-      REG_S a1, 29*SZREG(t0)
+-      REG_S a1, 30*SZREG(t0)
+-      REG_S a1, 31*SZREG(t0)
+-      addi t0, t0, 32*SZREG
+-      bltu t0, a3, 3b
+-      andi a2, a2, SZREG-1  /* Update count */
+-
+-4:
+-      /* Handle trailing misalignment */
+-      beqz a2, 6f
+-      add a3, t0, a2
+-5:
+-      sb a1, 0(t0)
+-      addi t0, t0, 1
+-      bltu t0, a3, 5b
+-6:
+-      ret
+-END(__memset)
+--- a/arch/riscv/lib/string.c
++++ b/arch/riscv/lib/string.c
+@@ -111,3 +111,44 @@ EXPORT_SYMBOL(__memmove);
+ 
+ void *memmove(void *dest, const void *src, size_t count) __weak __alias(__memmove);
+ EXPORT_SYMBOL(memmove);
++
++void *__memset(void *s, int c, size_t count)
++{
++      union types dest = { .as_u8 = s };
++
++      if (count >= MIN_THRESHOLD) {
++              unsigned long cu = (unsigned long)c;
++
++              /* Compose an ulong with 'c' repeated 4/8 times */
++#ifdef CONFIG_ARCH_HAS_FAST_MULTIPLIER
++              cu *= 0x0101010101010101UL;
++#else
++              cu |= cu << 8;
++              cu |= cu << 16;
++              /* Suppress warning on 32 bit machines */
++              cu |= (cu << 16) << 16;
++#endif
++              if (!IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)) {
++                      /*
++                       * Fill the buffer one byte at time until
++                       * the destination is word aligned.
++                       */
++                      for (; count && dest.as_uptr & WORD_MASK; count--)
++                              *dest.as_u8++ = c;
++              }
++
++              /* Copy using the largest size allowed */
++              for (; count >= BYTES_LONG; count -= BYTES_LONG)
++                      *dest.as_ulong++ = cu;
++      }
++
++      /* copy the remainder */
++      while (count--)
++              *dest.as_u8++ = c;
++
++      return s;
++}
++EXPORT_SYMBOL(__memset);
++
++void *memset(void *s, int c, size_t count) __weak __alias(__memset);
++EXPORT_SYMBOL(memset);

diff --git a/target/linux/visionfive/patches-5.15/0028-riscv-Add-ffreestanding-for-string-functions.patch b/target/linux/visionfive/patches-5.15/0028-riscv-Add-ffreestanding-for-string-functions.patch
new file mode 100644 (file)
index 0000000..b98fff3
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0028-riscv-Add-ffreestanding-for-string-functions.patch
@@ -0,0 +1,29 @@
+From dbdc81084ebfb21f1bb01a711620041e498ebd10 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Mon, 6 Dec 2021 21:27:07 +0100
+Subject: [PATCH 28/84] riscv: Add -ffreestanding for string functions
+
+The string library implements memset, memcpy and other library
+functions, so tell the compiler not to optimise such code to just calls
+to themselves.
+
+This is correct for all compilers, but for some reason only Clang builds
+break without this flag.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/lib/Makefile | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/riscv/lib/Makefile
++++ b/arch/riscv/lib/Makefile
+@@ -4,4 +4,9 @@ lib-$(CONFIG_MMU)      += uaccess.o
+ lib-$(CONFIG_64BIT)   += tishift.o
+ lib-$(CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE) += string.o
+ 
++# string.o implements standard library functions like memset/memcpy etc.
++# Use -ffreestanding to ensure that the compiler does not try to "optimize"
++# them into calls to themselves.
++CFLAGS_string.o := -ffreestanding
++
+ obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o

diff --git a/target/linux/visionfive/patches-5.15/0029-clk-starfive-jh7100-Don-t-round-divisor-up-twice.patch b/target/linux/visionfive/patches-5.15/0029-clk-starfive-jh7100-Don-t-round-divisor-up-twice.patch
new file mode 100644 (file)
index 0000000..a8ce98a
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0029-clk-starfive-jh7100-Don-t-round-divisor-up-twice.patch
@@ -0,0 +1,66 @@
+From 4718594bed7bb42e154b99db8084715b11cf3bb1 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Fri, 3 Dec 2021 00:36:16 +0100
+Subject: [PATCH 29/84] clk: starfive: jh7100: Don't round divisor up twice
+
+The problem is best illustrated by an example. Suppose a consumer wants
+a 4MHz clock rate from a divider with a 10MHz parent. It would then
+call
+
+  clk_round_rate(clk, 4000000)
+
+which would call into our determine_rate() callback that correctly
+rounds up and finds that a divisor of 3 gives the highest possible
+frequency below the requested 4MHz and returns 10000000 / 3 = 3333333Hz.
+
+However the consumer would then call
+
+  clk_set_rate(clk, 3333333)
+
+but since 3333333 doesn't divide 10000000 evenly our set_rate() callback
+would again round the divisor up and set it to 4 which results in an
+unnecessarily low rate of 2.5MHz.
+
+Fix it by using DIV_ROUND_CLOSEST in the set_rate() callback.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/clk/starfive/clk-starfive-jh7100.c | 14 +++-----------
+ 1 file changed, 3 insertions(+), 11 deletions(-)
+
+--- a/drivers/clk/starfive/clk-starfive-jh7100.c
++++ b/drivers/clk/starfive/clk-starfive-jh7100.c
+@@ -399,22 +399,13 @@ static unsigned long jh7100_clk_recalc_r
+       return div ? parent_rate / div : 0;
+ }
+ 
+-static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk,
+-                                      unsigned long rate, unsigned long parent)
+-{
+-      unsigned long max = clk->max_div;
+-      unsigned long div = DIV_ROUND_UP(parent, rate);
+-
+-      return min(div, max);
+-}
+-
+ static int jh7100_clk_determine_rate(struct clk_hw *hw,
+                                    struct clk_rate_request *req)
+ {
+       struct jh7100_clk *clk = jh7100_clk_from(hw);
+       unsigned long parent = req->best_parent_rate;
+       unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
+-      unsigned long div = jh7100_clk_bestdiv(clk, rate, parent);
++      unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
+       unsigned long result = parent / div;
+ 
+       /*
+@@ -442,7 +433,8 @@ static int jh7100_clk_set_rate(struct cl
+                              unsigned long parent_rate)
+ {
+       struct jh7100_clk *clk = jh7100_clk_from(hw);
+-      unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate);
++      unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
++                                1UL, (unsigned long)clk->max_div);
+ 
+       jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
+       return 0;

diff --git a/target/linux/visionfive/patches-5.15/0030-clk-starfive-jh7100-Handle-audio_div-clock-properly.patch b/target/linux/visionfive/patches-5.15/0030-clk-starfive-jh7100-Handle-audio_div-clock-properly.patch
new file mode 100644 (file)
index 0000000..171577d
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0030-clk-starfive-jh7100-Handle-audio_div-clock-properly.patch
@@ -0,0 +1,130 @@
+From 93cf75e1135d1fdaf3135bd2af3fa0805cd65652 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 4 Dec 2021 16:37:03 +0100
+Subject: [PATCH 30/84] clk: starfive: jh7100: Handle audio_div clock properly
+
+It turns out the audio_div clock is a fractional divider where the
+lowest byte of the ctrl register is the integer part of the divider and
+the 2nd byte is the number of 100th added to the divider.
+
+The children of this clock is used by the audio peripherals for their
+sample rate clock, so round to the closest possible rate rather than
+always rounding down like regular dividers.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/clk/starfive/clk-starfive-jh7100.c | 68 +++++++++++++++++++++-
+ 1 file changed, 67 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/starfive/clk-starfive-jh7100.c
++++ b/drivers/clk/starfive/clk-starfive-jh7100.c
+@@ -32,6 +32,13 @@
+ #define JH7100_CLK_MUX_MASK   GENMASK(27, 24)
+ #define JH7100_CLK_MUX_SHIFT  24
+ #define JH7100_CLK_DIV_MASK   GENMASK(23, 0)
++#define JH7100_CLK_FRAC_MASK  GENMASK(15, 8)
++#define JH7100_CLK_FRAC_SHIFT 8
++#define JH7100_CLK_INT_MASK   GENMASK(7, 0)
++
++/* fractional divider min/max */
++#define JH7100_CLK_FRAC_MIN   100UL
++#define JH7100_CLK_FRAC_MAX   25599UL
+ 
+ /* clock data */
+ #define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = {          \
+@@ -55,6 +62,13 @@
+       .parents = { [0] = _parent },                                   \
+ }
+ 
++#define JH7100_FDIV(_idx, _name, _parent) [_idx] = {                  \
++      .name = _name,                                                  \
++      .flags = 0,                                                     \
++      .max = JH7100_CLK_FRAC_MAX,                                     \
++      .parents = { [0] = _parent },                                   \
++}
++
+ #define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = {           \
+       .name = _name,                                                  \
+       .flags = 0,                                                     \
+@@ -225,7 +239,7 @@ static const struct {
+       JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
+                   JH7100_CLK_OSC_SYS,
+                   JH7100_CLK_USBPHY_PLLDIV25M),
+-      JH7100__DIV(JH7100_CLK_AUDIO_DIV, "audio_div", 131072, JH7100_CLK_AUDIO_ROOT),
++      JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
+       JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
+       JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
+       JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
+@@ -440,6 +454,49 @@ static int jh7100_clk_set_rate(struct cl
+       return 0;
+ }
+ 
++static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
++                                               unsigned long parent_rate)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      u32 reg = jh7100_clk_reg_get(clk);
++      unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
++                             ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
++
++      return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
++}
++
++static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
++                                        struct clk_rate_request *req)
++{
++      unsigned long parent100 = 100 * req->best_parent_rate;
++      unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
++      unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
++                                   JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
++      unsigned long result = parent100 / div100;
++
++      /* clamp the result as in jh7100_clk_determine_rate() above */
++      if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
++              result = parent100 / (div100 + 1);
++      if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
++              result = parent100 / (div100 - 1);
++
++      req->rate = result;
++      return 0;
++}
++
++static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
++                                  unsigned long rate,
++                                  unsigned long parent_rate)
++{
++      struct jh7100_clk *clk = jh7100_clk_from(hw);
++      unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
++                                   JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
++      u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
++
++      jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
++      return 0;
++}
++
+ static u8 jh7100_clk_get_parent(struct clk_hw *hw)
+ {
+       struct jh7100_clk *clk = jh7100_clk_from(hw);
+@@ -526,6 +583,13 @@ static const struct clk_ops jh7100_clk_d
+       .debug_init = jh7100_clk_debug_init,
+ };
+ 
++static const struct clk_ops jh7100_clk_fdiv_ops = {
++      .recalc_rate = jh7100_clk_frac_recalc_rate,
++      .determine_rate = jh7100_clk_frac_determine_rate,
++      .set_rate = jh7100_clk_frac_set_rate,
++      .debug_init = jh7100_clk_debug_init,
++};
++
+ static const struct clk_ops jh7100_clk_gdiv_ops = {
+       .enable = jh7100_clk_enable,
+       .disable = jh7100_clk_disable,
+@@ -564,6 +628,8 @@ static const struct clk_ops *__init jh71
+       if (max & JH7100_CLK_DIV_MASK) {
+               if (max & JH7100_CLK_ENABLE)
+                       return &jh7100_clk_gdiv_ops;
++              if (max == JH7100_CLK_FRAC_MAX)
++                      return &jh7100_clk_fdiv_ops;
+               return &jh7100_clk_div_ops;
+       }
+ 

diff --git a/target/linux/visionfive/patches-5.15/0031-riscv-dts-starfive-Group-tuples-in-interrupt-propert.patch b/target/linux/visionfive/patches-5.15/0031-riscv-dts-starfive-Group-tuples-in-interrupt-propert.patch
new file mode 100644 (file)
index 0000000..a5ee172
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0031-riscv-dts-starfive-Group-tuples-in-interrupt-propert.patch
@@ -0,0 +1,40 @@
+From 3f0556f6f493b14824b1e3ea3920916a3c2b5a37 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Thu, 25 Nov 2021 14:21:18 +0100
+Subject: [PATCH 31/84] riscv: dts: starfive: Group tuples in interrupt
+ properties
+
+To improve human readability and enable automatic validation, the tuples
+in the various properties containing interrupt specifiers should be
+grouped.
+
+Fix this by grouping the tuples of "interrupts-extended" properties
+using angle brackets.
+
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -106,15 +106,15 @@
+               clint: clint@2000000 {
+                       compatible = "starfive,jh7100-clint", "sifive,clint0";
+                       reg = <0x0 0x2000000 0x0 0x10000>;
+-                      interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+-                                             &cpu1_intc 3 &cpu1_intc 7>;
++                      interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
++                                            <&cpu1_intc 3>, <&cpu1_intc 7>;
+               };
+ 
+               plic: interrupt-controller@c000000 {
+                       compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
+                       reg = <0x0 0xc000000 0x0 0x4000000>;
+-                      interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
+-                                             &cpu1_intc 11 &cpu1_intc 9>;
++                      interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
++                                            <&cpu1_intc 11>, <&cpu1_intc 9>;
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;

diff --git a/target/linux/visionfive/patches-5.15/0032-dt-bindings-clock-Add-JH7100-audio-clock-definitions.patch b/target/linux/visionfive/patches-5.15/0032-dt-bindings-clock-Add-JH7100-audio-clock-definitions.patch
new file mode 100644 (file)
index 0000000..2a6db89
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0032-dt-bindings-clock-Add-JH7100-audio-clock-definitions.patch
@@ -0,0 +1,57 @@
+From bb84d8a672d90d8d4ef16b737bc944f00dd22f24 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Wed, 24 Nov 2021 01:33:43 +0100
+Subject: [PATCH 32/84] dt-bindings: clock: Add JH7100 audio clock definitions
+
+Add all clock outputs for the StarFive JH7100 audio clock generator.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../dt-bindings/clock/starfive-jh7100-audio.h | 41 +++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+ create mode 100644 include/dt-bindings/clock/starfive-jh7100-audio.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/starfive-jh7100-audio.h
+@@ -0,0 +1,41 @@
++/* SPDX-License-Identifier: GPL-2.0 OR MIT */
++/*
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
++#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
++
++#define JH7100_AUDCLK_ADC_MCLK                0
++#define JH7100_AUDCLK_I2S1_MCLK               1
++#define JH7100_AUDCLK_I2SADC_APB      2
++#define JH7100_AUDCLK_I2SADC_BCLK     3
++#define JH7100_AUDCLK_I2SADC_BCLK_N   4
++#define JH7100_AUDCLK_I2SADC_LRCLK    5
++#define JH7100_AUDCLK_PDM_APB         6
++#define JH7100_AUDCLK_PDM_MCLK                7
++#define JH7100_AUDCLK_I2SVAD_APB      8
++#define JH7100_AUDCLK_SPDIF           9
++#define JH7100_AUDCLK_SPDIF_APB               10
++#define JH7100_AUDCLK_PWMDAC_APB      11
++#define JH7100_AUDCLK_DAC_MCLK                12
++#define JH7100_AUDCLK_I2SDAC_APB      13
++#define JH7100_AUDCLK_I2SDAC_BCLK     14
++#define JH7100_AUDCLK_I2SDAC_BCLK_N   15
++#define JH7100_AUDCLK_I2SDAC_LRCLK    16
++#define JH7100_AUDCLK_I2S1_APB                17
++#define JH7100_AUDCLK_I2S1_BCLK               18
++#define JH7100_AUDCLK_I2S1_BCLK_N     19
++#define JH7100_AUDCLK_I2S1_LRCLK      20
++#define JH7100_AUDCLK_I2SDAC16K_APB   21
++#define JH7100_AUDCLK_APB0_BUS                22
++#define JH7100_AUDCLK_DMA1P_AHB               23
++#define JH7100_AUDCLK_USB_APB         24
++#define JH7100_AUDCLK_USB_LPM         25
++#define JH7100_AUDCLK_USB_STB         26
++#define JH7100_AUDCLK_APB_EN          27
++#define JH7100_AUDCLK_VAD_MEM         28
++
++#define JH7100_AUDCLK_END             29
++
++#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ */

diff --git a/target/linux/visionfive/patches-5.15/0033-dt-bindings-clock-Add-starfive-jh7100-audclk-binding.patch b/target/linux/visionfive/patches-5.15/0033-dt-bindings-clock-Add-starfive-jh7100-audclk-binding.patch
new file mode 100644 (file)
index 0000000..54daf7c
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0033-dt-bindings-clock-Add-starfive-jh7100-audclk-binding.patch
@@ -0,0 +1,73 @@
+From 97870acb33745e6204b90a27996b2c8937e5a011 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Tue, 7 Dec 2021 21:48:38 +0100
+Subject: [PATCH 33/84] dt-bindings: clock: Add starfive,jh7100-audclk bindings
+
+Add bindings for the audio clocks on the StarFive JH7100 RISC-V SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../clock/starfive,jh7100-audclk.yaml         | 57 +++++++++++++++++++
+ 1 file changed, 57 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml
+@@ -0,0 +1,57 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7100 Audio Clock Generator
++
++maintainers:
++  - Emil Renner Berthing <kernel@esmil.dk>
++
++properties:
++  compatible:
++    const: starfive,jh7100-audclk
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: Audio source clock
++      - description: External 12.288MHz clock
++      - description: Domain 7 AHB bus clock
++
++  clock-names:
++    items:
++      - const: audio_src
++      - const: audio_12288
++      - const: dom7ahb_bus
++
++  '#clock-cells':
++    const: 1
++    description:
++      See <dt-bindings/clock/starfive-jh7100-audio.h> for valid indices.
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/starfive-jh7100.h>
++
++    clock-controller@10480000 {
++            compatible = "starfive,jh7100-audclk";
++            reg = <0x10480000 0x10000>;
++            clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
++                     <&clkgen JH7100_CLK_AUDIO_12288>,
++                     <&clkgen JH7100_CLK_DOM7AHB_BUS>;
++            clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
++            #clock-cells = <1>;
++    };

diff --git a/target/linux/visionfive/patches-5.15/0034-clk-starfive-jh7100-Make-hw-clock-implementation-reu.patch b/target/linux/visionfive/patches-5.15/0034-clk-starfive-jh7100-Make-hw-clock-implementation-reu.patch
new file mode 100644 (file)
index 0000000..babd310
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0034-clk-starfive-jh7100-Make-hw-clock-implementation-reu.patch
@@ -0,0 +1,270 @@
+From f902389e988735ff795f76c864e695f770d47740 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 17:11:59 +0100
+Subject: [PATCH 34/84] clk: starfive: jh7100: Make hw clock implementation
+ reusable
+
+The JH7100 has additional audio and video clocks at different memory
+ranges, but they use the same register layout. Add a header and export
+the starfive_jh7100_clk_ops function so the clock implementation can be
+reused by drivers handling these clocks.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/clk/starfive/clk-starfive-jh7100.c |  96 ++-----------------
+ drivers/clk/starfive/clk-starfive-jh7100.h | 103 +++++++++++++++++++++
+ 2 files changed, 110 insertions(+), 89 deletions(-)
+ create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
+
+--- a/drivers/clk/starfive/clk-starfive-jh7100.c
++++ b/drivers/clk/starfive/clk-starfive-jh7100.c
+@@ -20,83 +20,15 @@
+ 
+ #include <dt-bindings/clock/starfive-jh7100.h>
+ 
++#include "clk-starfive-jh7100.h"
++
+ /* external clocks */
+ #define JH7100_CLK_OSC_SYS            (JH7100_CLK_END + 0)
+ #define JH7100_CLK_OSC_AUD            (JH7100_CLK_END + 1)
+ #define JH7100_CLK_GMAC_RMII_REF      (JH7100_CLK_END + 2)
+ #define JH7100_CLK_GMAC_GR_MII_RX     (JH7100_CLK_END + 3)
+ 
+-/* register fields */
+-#define JH7100_CLK_ENABLE     BIT(31)
+-#define JH7100_CLK_INVERT     BIT(30)
+-#define JH7100_CLK_MUX_MASK   GENMASK(27, 24)
+-#define JH7100_CLK_MUX_SHIFT  24
+-#define JH7100_CLK_DIV_MASK   GENMASK(23, 0)
+-#define JH7100_CLK_FRAC_MASK  GENMASK(15, 8)
+-#define JH7100_CLK_FRAC_SHIFT 8
+-#define JH7100_CLK_INT_MASK   GENMASK(7, 0)
+-
+-/* fractional divider min/max */
+-#define JH7100_CLK_FRAC_MIN   100UL
+-#define JH7100_CLK_FRAC_MAX   25599UL
+-
+-/* clock data */
+-#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = {          \
+-      .name = _name,                                                  \
+-      .flags = CLK_SET_RATE_PARENT | (_flags),                        \
+-      .max = JH7100_CLK_ENABLE,                                       \
+-      .parents = { [0] = _parent },                                   \
+-}
+-
+-#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = {            \
+-      .name = _name,                                                  \
+-      .flags = 0,                                                     \
+-      .max = _max,                                                    \
+-      .parents = { [0] = _parent },                                   \
+-}
+-
+-#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = {    \
+-      .name = _name,                                                  \
+-      .flags = _flags,                                                \
+-      .max = JH7100_CLK_ENABLE | (_max),                              \
+-      .parents = { [0] = _parent },                                   \
+-}
+-
+-#define JH7100_FDIV(_idx, _name, _parent) [_idx] = {                  \
+-      .name = _name,                                                  \
+-      .flags = 0,                                                     \
+-      .max = JH7100_CLK_FRAC_MAX,                                     \
+-      .parents = { [0] = _parent },                                   \
+-}
+-
+-#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = {           \
+-      .name = _name,                                                  \
+-      .flags = 0,                                                     \
+-      .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT,               \
+-      .parents = { __VA_ARGS__ },                                     \
+-}
+-
+-#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = {   \
+-      .name = _name,                                                  \
+-      .flags = _flags,                                                \
+-      .max = JH7100_CLK_ENABLE |                                      \
+-              (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT),            \
+-      .parents = { __VA_ARGS__ },                                     \
+-}
+-
+-#define JH7100__INV(_idx, _name, _parent) [_idx] = {                  \
+-      .name = _name,                                                  \
+-      .flags = CLK_SET_RATE_PARENT,                                   \
+-      .max = JH7100_CLK_INVERT,                                       \
+-      .parents = { [0] = _parent },                                   \
+-}
+-
+-static const struct {
+-      const char *name;
+-      unsigned long flags;
+-      u32 max;
+-      u8 parents[4];
+-} jh7100_clk_data[] __initconst = {
++static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
+       JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
+                   JH7100_CLK_OSC_SYS,
+                   JH7100_CLK_PLL0_OUT,
+@@ -337,21 +269,6 @@ static const struct {
+       JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
+ };
+ 
+-struct jh7100_clk {
+-      struct clk_hw hw;
+-      unsigned int idx;
+-      unsigned int max_div;
+-};
+-
+-struct jh7100_clk_priv {
+-      /* protect clk enable and set rate/parent from happening at the same time */
+-      spinlock_t rmw_lock;
+-      struct device *dev;
+-      void __iomem *base;
+-      struct clk_hw *pll[3];
+-      struct jh7100_clk reg[JH7100_CLK_PLL0_OUT];
+-};
+-
+ static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
+ {
+       return container_of(hw, struct jh7100_clk, hw);
+@@ -623,7 +540,7 @@ static const struct clk_ops jh7100_clk_i
+       .debug_init = jh7100_clk_debug_init,
+ };
+ 
+-static const struct clk_ops *__init jh7100_clk_ops(u32 max)
++const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
+ {
+       if (max & JH7100_CLK_DIV_MASK) {
+               if (max & JH7100_CLK_ENABLE)
+@@ -644,6 +561,7 @@ static const struct clk_ops *__init jh71
+ 
+       return &jh7100_clk_inv_ops;
+ }
++EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
+ 
+ static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
+ {
+@@ -665,7 +583,7 @@ static int __init clk_starfive_jh7100_pr
+       unsigned int idx;
+       int ret;
+ 
+-      priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++      priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL);
+       if (!priv)
+               return -ENOMEM;
+ 
+@@ -695,7 +613,7 @@ static int __init clk_starfive_jh7100_pr
+               struct clk_parent_data parents[4] = {};
+               struct clk_init_data init = {
+                       .name = jh7100_clk_data[idx].name,
+-                      .ops = jh7100_clk_ops(max),
++                      .ops = starfive_jh7100_clk_ops(max),
+                       .parent_data = parents,
+                       .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
+                       .flags = jh7100_clk_data[idx].flags,
+--- /dev/null
++++ b/drivers/clk/starfive/clk-starfive-jh7100.h
+@@ -0,0 +1,103 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * StarFive JH7100 Clock Generator Driver
++ *
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#ifndef _CLK_STARFIVE_JH7100_H_
++#define _CLK_STARFIVE_JH7100_H_
++
++#include <linux/bits.h>
++#include <linux/clk-provider.h>
++
++/* register fields */
++#define JH7100_CLK_ENABLE     BIT(31)
++#define JH7100_CLK_INVERT     BIT(30)
++#define JH7100_CLK_MUX_MASK   GENMASK(27, 24)
++#define JH7100_CLK_MUX_SHIFT  24
++#define JH7100_CLK_DIV_MASK   GENMASK(23, 0)
++#define JH7100_CLK_FRAC_MASK  GENMASK(15, 8)
++#define JH7100_CLK_FRAC_SHIFT 8
++#define JH7100_CLK_INT_MASK   GENMASK(7, 0)
++
++/* fractional divider min/max */
++#define JH7100_CLK_FRAC_MIN   100UL
++#define JH7100_CLK_FRAC_MAX   25599UL
++
++/* clock data */
++struct jh7100_clk_data {
++      const char *name;
++      unsigned long flags;
++      u32 max;
++      u8 parents[4];
++};
++
++#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = {                  \
++      .name = _name,                                                          \
++      .flags = CLK_SET_RATE_PARENT | (_flags),                                \
++      .max = JH7100_CLK_ENABLE,                                               \
++      .parents = { [0] = _parent },                                           \
++}
++
++#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = {                    \
++      .name = _name,                                                          \
++      .flags = 0,                                                             \
++      .max = _max,                                                            \
++      .parents = { [0] = _parent },                                           \
++}
++
++#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = {            \
++      .name = _name,                                                          \
++      .flags = _flags,                                                        \
++      .max = JH7100_CLK_ENABLE | (_max),                                      \
++      .parents = { [0] = _parent },                                           \
++}
++
++#define JH7100_FDIV(_idx, _name, _parent) [_idx] = {                          \
++      .name = _name,                                                          \
++      .flags = 0,                                                             \
++      .max = JH7100_CLK_FRAC_MAX,                                             \
++      .parents = { [0] = _parent },                                           \
++}
++
++#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = {                   \
++      .name = _name,                                                          \
++      .flags = 0,                                                             \
++      .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT,                       \
++      .parents = { __VA_ARGS__ },                                             \
++}
++
++#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = {           \
++      .name = _name,                                                          \
++      .flags = _flags,                                                        \
++      .max = JH7100_CLK_ENABLE |                                              \
++              (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT),                    \
++      .parents = { __VA_ARGS__ },                                             \
++}
++
++#define JH7100__INV(_idx, _name, _parent) [_idx] = {                          \
++      .name = _name,                                                          \
++      .flags = CLK_SET_RATE_PARENT,                                           \
++      .max = JH7100_CLK_INVERT,                                               \
++      .parents = { [0] = _parent },                                           \
++}
++
++struct jh7100_clk {
++      struct clk_hw hw;
++      unsigned int idx;
++      unsigned int max_div;
++};
++
++struct jh7100_clk_priv {
++      /* protect clk enable and set rate/parent from happening at the same time */
++      spinlock_t rmw_lock;
++      struct device *dev;
++      void __iomem *base;
++      struct clk_hw *pll[3];
++      struct jh7100_clk reg[];
++};
++
++const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
++
++#endif

diff --git a/target/linux/visionfive/patches-5.15/0035-clk-starfive-jh7100-Support-more-clock-types.patch b/target/linux/visionfive/patches-5.15/0035-clk-starfive-jh7100-Support-more-clock-types.patch
new file mode 100644 (file)
index 0000000..8d3d8ec
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0035-clk-starfive-jh7100-Support-more-clock-types.patch
@@ -0,0 +1,81 @@
+From 4bb089fbe5b51fd81fa62727c43fffabe71c9215 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 17:12:49 +0100
+Subject: [PATCH 35/84] clk: starfive: jh7100: Support more clock types
+
+Unlike the system clocks there are audio clocks that combine both
+multiplexer/divider and gate/multiplexer/divider, so add support for
+that.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/clk/starfive/clk-starfive-jh7100.c | 26 ++++++++++++++++++++++
+ drivers/clk/starfive/clk-starfive-jh7100.h | 15 +++++++++++++
+ 2 files changed, 41 insertions(+)
+
+--- a/drivers/clk/starfive/clk-starfive-jh7100.c
++++ b/drivers/clk/starfive/clk-starfive-jh7100.c
+@@ -534,6 +534,27 @@ static const struct clk_ops jh7100_clk_g
+       .debug_init = jh7100_clk_debug_init,
+ };
+ 
++static const struct clk_ops jh7100_clk_mdiv_ops = {
++      .recalc_rate = jh7100_clk_recalc_rate,
++      .determine_rate = jh7100_clk_determine_rate,
++      .get_parent = jh7100_clk_get_parent,
++      .set_parent = jh7100_clk_set_parent,
++      .set_rate = jh7100_clk_set_rate,
++      .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_gmd_ops = {
++      .enable = jh7100_clk_enable,
++      .disable = jh7100_clk_disable,
++      .is_enabled = jh7100_clk_is_enabled,
++      .recalc_rate = jh7100_clk_recalc_rate,
++      .determine_rate = jh7100_clk_determine_rate,
++      .get_parent = jh7100_clk_get_parent,
++      .set_parent = jh7100_clk_set_parent,
++      .set_rate = jh7100_clk_set_rate,
++      .debug_init = jh7100_clk_debug_init,
++};
++
+ static const struct clk_ops jh7100_clk_inv_ops = {
+       .get_phase = jh7100_clk_get_phase,
+       .set_phase = jh7100_clk_set_phase,
+@@ -543,6 +564,11 @@ static const struct clk_ops jh7100_clk_i
+ const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
+ {
+       if (max & JH7100_CLK_DIV_MASK) {
++              if (max & JH7100_CLK_MUX_MASK) {
++                      if (max & JH7100_CLK_ENABLE)
++                              return &jh7100_clk_gmd_ops;
++                      return &jh7100_clk_mdiv_ops;
++              }
+               if (max & JH7100_CLK_ENABLE)
+                       return &jh7100_clk_gdiv_ops;
+               if (max == JH7100_CLK_FRAC_MAX)
+--- a/drivers/clk/starfive/clk-starfive-jh7100.h
++++ b/drivers/clk/starfive/clk-starfive-jh7100.h
+@@ -76,6 +76,21 @@ struct jh7100_clk_data {
+       .parents = { __VA_ARGS__ },                                             \
+ }
+ 
++#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = {             \
++      .name = _name,                                                          \
++      .flags = 0,                                                             \
++      .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max),            \
++      .parents = { __VA_ARGS__ },                                             \
++}
++
++#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = {     \
++      .name = _name,                                                          \
++      .flags = _flags,                                                        \
++      .max = JH7100_CLK_ENABLE |                                              \
++              (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max),           \
++      .parents = { __VA_ARGS__ },                                             \
++}
++
+ #define JH7100__INV(_idx, _name, _parent) [_idx] = {                          \
+       .name = _name,                                                          \
+       .flags = CLK_SET_RATE_PARENT,                                           \

diff --git a/target/linux/visionfive/patches-5.15/0036-clk-starfive-Add-JH7100-audio-clock-driver.patch b/target/linux/visionfive/patches-5.15/0036-clk-starfive-Add-JH7100-audio-clock-driver.patch
new file mode 100644 (file)
index 0000000..22f3a84
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0036-clk-starfive-Add-JH7100-audio-clock-driver.patch
@@ -0,0 +1,228 @@
+From 22a40e1c0d83d26d84a4cfc2aea04ebf5383c84f Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Wed, 24 Nov 2021 01:34:35 +0100
+Subject: [PATCH 36/84] clk: starfive: Add JH7100 audio clock driver
+
+Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ MAINTAINERS                                   |   8 +-
+ drivers/clk/starfive/Kconfig                  |   7 +
+ drivers/clk/starfive/Makefile                 |   1 +
+ .../clk/starfive/clk-starfive-jh7100-audio.c  | 170 ++++++++++++++++++
+ 4 files changed, 182 insertions(+), 4 deletions(-)
+ create mode 100644 drivers/clk/starfive/clk-starfive-jh7100-audio.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -17860,12 +17860,12 @@ M:   Ion Badulescu <ionut@badula.org>
+ S:    Odd Fixes
+ F:    drivers/net/ethernet/adaptec/starfire*
+ 
+-STARFIVE JH7100 CLOCK DRIVER
++STARFIVE JH7100 CLOCK DRIVERS
+ M:    Emil Renner Berthing <kernel@esmil.dk>
+ S:    Maintained
+-F:    Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
+-F:    drivers/clk/starfive/clk-starfive-jh7100.c
+-F:    include/dt-bindings/clock/starfive-jh7100.h
++F:    Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
++F:    drivers/clk/starfive/clk-starfive-jh7100*
++F:    include/dt-bindings/clock/starfive-jh7100*.h
+ 
+ STARFIVE JH7100 PINCTRL DRIVER
+ M:    Emil Renner Berthing <kernel@esmil.dk>
+--- a/drivers/clk/starfive/Kconfig
++++ b/drivers/clk/starfive/Kconfig
+@@ -7,3 +7,10 @@ config CLK_STARFIVE_JH7100
+       help
+         Say yes here to support the clock controller on the StarFive JH7100
+         SoC.
++
++config CLK_STARFIVE_JH7100_AUDIO
++      tristate "StarFive JH7100 audio clock support"
++      depends on CLK_STARFIVE_JH7100
++      default SOC_STARFIVE
++      help
++        Say yes here to support the audio clocks on the StarFive JH7100 SoC.
+--- a/drivers/clk/starfive/Makefile
++++ b/drivers/clk/starfive/Makefile
+@@ -1,3 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0
+ # StarFive Clock
+ obj-$(CONFIG_CLK_STARFIVE_JH7100)     += clk-starfive-jh7100.o
++obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO)       += clk-starfive-jh7100-audio.o
+--- /dev/null
++++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+@@ -0,0 +1,170 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * StarFive JH7100 Audio Clock Driver
++ *
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#include <linux/bits.h>
++#include <linux/clk-provider.h>
++#include <linux/device.h>
++#include <linux/kernel.h>
++#include <linux/mod_devicetable.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++
++#include <dt-bindings/clock/starfive-jh7100-audio.h>
++
++#include "clk-starfive-jh7100.h"
++
++/* external clocks */
++#define JH7100_AUDCLK_AUDIO_SRC                       (JH7100_AUDCLK_END + 0)
++#define JH7100_AUDCLK_AUDIO_12288             (JH7100_AUDCLK_END + 1)
++#define JH7100_AUDCLK_DOM7AHB_BUS             (JH7100_AUDCLK_END + 2)
++#define JH7100_AUDCLK_I2SADC_BCLK_IOPAD               (JH7100_AUDCLK_END + 3)
++#define JH7100_AUDCLK_I2SADC_LRCLK_IOPAD      (JH7100_AUDCLK_END + 4)
++#define JH7100_AUDCLK_I2SDAC_BCLK_IOPAD               (JH7100_AUDCLK_END + 5)
++#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD      (JH7100_AUDCLK_END + 6)
++#define JH7100_AUDCLK_VAD_INTMEM                (JH7100_AUDCLK_END + 7)
++
++static const struct jh7100_clk_data jh7100_audclk_data[] = {
++      JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
++                  JH7100_AUDCLK_AUDIO_SRC,
++                  JH7100_AUDCLK_AUDIO_12288),
++      JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
++                  JH7100_AUDCLK_AUDIO_SRC,
++                  JH7100_AUDCLK_AUDIO_12288),
++      JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
++      JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
++                  JH7100_AUDCLK_ADC_MCLK,
++                  JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
++      JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
++      JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
++                  JH7100_AUDCLK_I2SADC_BCLK_N,
++                  JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
++                  JH7100_AUDCLK_I2SADC_BCLK),
++      JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
++      JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
++                  JH7100_AUDCLK_AUDIO_SRC,
++                  JH7100_AUDCLK_AUDIO_12288),
++      JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
++      JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
++                  JH7100_AUDCLK_AUDIO_SRC,
++                  JH7100_AUDCLK_AUDIO_12288),
++      JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
++      JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
++      JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
++                  JH7100_AUDCLK_AUDIO_SRC,
++                  JH7100_AUDCLK_AUDIO_12288),
++      JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
++      JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
++                  JH7100_AUDCLK_DAC_MCLK,
++                  JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
++      JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
++      JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
++                  JH7100_AUDCLK_I2S1_MCLK,
++                  JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
++      JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
++      JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
++                  JH7100_AUDCLK_I2S1_MCLK,
++                  JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
++      JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
++      JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
++                  JH7100_AUDCLK_I2S1_BCLK_N,
++                  JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
++      JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
++      JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
++      JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
++      JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
++      JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
++      JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
++      JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
++      JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
++                  JH7100_AUDCLK_VAD_INTMEM,
++                  JH7100_AUDCLK_AUDIO_12288),
++};
++
++static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
++{
++      struct jh7100_clk_priv *priv = data;
++      unsigned int idx = clkspec->args[0];
++
++      if (idx < JH7100_AUDCLK_END)
++              return &priv->reg[idx].hw;
++
++      return ERR_PTR(-EINVAL);
++}
++
++static int jh7100_audclk_probe(struct platform_device *pdev)
++{
++      struct jh7100_clk_priv *priv;
++      unsigned int idx;
++      int ret;
++
++      priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL);
++      if (!priv)
++              return -ENOMEM;
++
++      spin_lock_init(&priv->rmw_lock);
++      priv->dev = &pdev->dev;
++      priv->base = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(priv->base))
++              return PTR_ERR(priv->base);
++
++      for (idx = 0; idx < JH7100_AUDCLK_END; idx++) {
++              u32 max = jh7100_audclk_data[idx].max;
++              struct clk_parent_data parents[4] = {};
++              struct clk_init_data init = {
++                      .name = jh7100_audclk_data[idx].name,
++                      .ops = starfive_jh7100_clk_ops(max),
++                      .parent_data = parents,
++                      .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
++                      .flags = jh7100_audclk_data[idx].flags,
++              };
++              struct jh7100_clk *clk = &priv->reg[idx];
++              unsigned int i;
++
++              for (i = 0; i < init.num_parents; i++) {
++                      unsigned int pidx = jh7100_audclk_data[idx].parents[i];
++
++                      if (pidx < JH7100_AUDCLK_END)
++                              parents[i].hw = &priv->reg[pidx].hw;
++                      else if (pidx == JH7100_AUDCLK_AUDIO_SRC)
++                              parents[i].fw_name = "audio_src";
++                      else if (pidx == JH7100_AUDCLK_AUDIO_12288)
++                              parents[i].fw_name = "audio_12288";
++                      else if (pidx == JH7100_AUDCLK_DOM7AHB_BUS)
++                              parents[i].fw_name = "dom7ahb_bus";
++              }
++
++              clk->hw.init = &init;
++              clk->idx = idx;
++              clk->max_div = max & JH7100_CLK_DIV_MASK;
++
++              ret = devm_clk_hw_register(priv->dev, &clk->hw);
++              if (ret)
++                      return ret;
++      }
++
++      return devm_of_clk_add_hw_provider(priv->dev, jh7100_audclk_get, priv);
++}
++
++static const struct of_device_id jh7100_audclk_match[] = {
++      { .compatible = "starfive,jh7100-audclk" },
++      { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, jh7100_audclk_match);
++
++static struct platform_driver jh7100_audclk_driver = {
++      .probe = jh7100_audclk_probe,
++      .driver = {
++              .name = "clk-starfive-jh7100-audio",
++              .of_match_table = jh7100_audclk_match,
++      },
++};
++module_platform_driver(jh7100_audclk_driver);
++
++MODULE_AUTHOR("Emil Renner Berthing");
++MODULE_DESCRIPTION("StarFive JH7100 audio clock driver");
++MODULE_LICENSE("GPL");

diff --git a/target/linux/visionfive/patches-5.15/0037-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch b/target/linux/visionfive/patches-5.15/0037-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch
new file mode 100644 (file)
index 0000000..51e1c35
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0037-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch
@@ -0,0 +1,32 @@
+From 078903ae6318fa71fe035c7e39285ca611d4d0b2 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 17:13:22 +0100
+Subject: [PATCH 37/84] RISC-V: Add StarFive JH7100 audio clock node
+
+Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
+SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -121,6 +121,16 @@
+                       riscv,ndev = <127>;
+               };
+ 
++              audclk: clock-controller@10480000 {
++                      compatible = "starfive,jh7100-audclk";
++                      reg = <0x0 0x10480000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
++                               <&clkgen JH7100_CLK_AUDIO_12288>,
++                               <&clkgen JH7100_CLK_DOM7AHB_BUS>;
++                      clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
++                      #clock-cells = <1>;
++              };
++
+               clkgen: clock-controller@11800000 {
+                       compatible = "starfive,jh7100-clkgen";
+                       reg = <0x0 0x11800000 0x0 0x10000>;

diff --git a/target/linux/visionfive/patches-5.15/0038-dt-bindings-reset-Add-StarFive-JH7100-audio-reset-de.patch b/target/linux/visionfive/patches-5.15/0038-dt-bindings-reset-Add-StarFive-JH7100-audio-reset-de.patch
new file mode 100644 (file)
index 0000000..c79acaf
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0038-dt-bindings-reset-Add-StarFive-JH7100-audio-reset-de.patch
@@ -0,0 +1,48 @@
+From eccf7ed89bc26de7d314fa12955933686bcdf6bb Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 19:29:25 +0100
+Subject: [PATCH 38/84] dt-bindings: reset: Add StarFive JH7100 audio reset
+ definitions
+
+Add all resets for the StarFive JH7100 audio reset controller.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../dt-bindings/reset/starfive-jh7100-audio.h | 31 +++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+ create mode 100644 include/dt-bindings/reset/starfive-jh7100-audio.h
+
+--- /dev/null
++++ b/include/dt-bindings/reset/starfive-jh7100-audio.h
+@@ -0,0 +1,31 @@
++/* SPDX-License-Identifier: GPL-2.0 OR MIT */
++/*
++ * Copyright (C) 2021 Emil Renner Berthing
++ */
++
++#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__
++#define __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__
++
++#define JH7100_AUDRSTN_APB_BUS                0
++#define JH7100_AUDRSTN_I2SADC_APB     1
++#define JH7100_AUDRSTN_I2SADC_SRST    2
++#define JH7100_AUDRSTN_PDM_APB                3
++#define JH7100_AUDRSTN_I2SVAD_APB     4
++#define JH7100_AUDRSTN_I2SVAD_SRST    5
++#define JH7100_AUDRSTN_SPDIF_APB      6
++#define JH7100_AUDRSTN_PWMDAC_APB     7
++#define JH7100_AUDRSTN_I2SDAC_APB     8
++#define JH7100_AUDRSTN_I2SDAC_SRST    9
++#define JH7100_AUDRSTN_I2S1_APB               10
++#define JH7100_AUDRSTN_I2S1_SRST      11
++#define JH7100_AUDRSTN_I2SDAC16K_APB  12
++#define JH7100_AUDRSTN_I2SDAC16K_SRST 13
++#define JH7100_AUDRSTN_DMA1P_AHB      14
++#define JH7100_AUDRSTN_USB_APB                15
++#define JH7100_AUDRST_USB_AXI         16
++#define JH7100_AUDRST_USB_PWRUP_RST_N 17
++#define JH7100_AUDRST_USB_PONRST      18
++
++#define JH7100_AUDRSTN_END            19
++
++#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__ */

diff --git a/target/linux/visionfive/patches-5.15/0039-dt-bindings-reset-Add-starfive-jh7100-audrst-binding.patch b/target/linux/visionfive/patches-5.15/0039-dt-bindings-reset-Add-starfive-jh7100-audrst-binding.patch
new file mode 100644 (file)
index 0000000..1b446ec
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0039-dt-bindings-reset-Add-starfive-jh7100-audrst-binding.patch
@@ -0,0 +1,55 @@
+From 954f0ad6b63f9e9810a2a5b5cf8696a376988275 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Tue, 7 Dec 2021 21:48:51 +0100
+Subject: [PATCH 39/84] dt-bindings: reset: Add starfive,jh7100-audrst bindings
+
+Add bindings for the audio reset controller on the StarFive JH7100
+RISC-V SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../reset/starfive,jh7100-audrst.yaml         | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7100-audrst.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-audrst.yaml
+@@ -0,0 +1,38 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/reset/starfive,jh7100-audrst.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7100 SoC Audio Reset Controller Device Tree Bindings
++
++maintainers:
++  - Emil Renner Berthing <kernel@esmil.dk>
++
++properties:
++  compatible:
++    enum:
++      - starfive,jh7100-audrst
++
++  reg:
++    maxItems: 1
++
++  "#reset-cells":
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - "#reset-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    reset-controller@10490000 {
++        compatible = "starfive,jh7100-audrst";
++        reg = <0x10490000 0x10000>;
++        #reset-cells = <1>;
++    };
++
++...

diff --git a/target/linux/visionfive/patches-5.15/0040-reset-Create-subdirectory-for-StarFive-drivers.patch b/target/linux/visionfive/patches-5.15/0040-reset-Create-subdirectory-for-StarFive-drivers.patch
new file mode 100644 (file)
index 0000000..63bac89
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0040-reset-Create-subdirectory-for-StarFive-drivers.patch
@@ -0,0 +1,442 @@
+From 9f4fe5a1e85e0067bd1016412cb4d60402479ce9 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 18:30:33 +0100
+Subject: [PATCH 40/84] reset: Create subdirectory for StarFive drivers
+
+This moves the StarFive JH7100 reset driver to a new subdirectory in
+preparation for adding more StarFive reset drivers.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ MAINTAINERS                                          | 2 +-
+ drivers/reset/Kconfig                                | 8 +-------
+ drivers/reset/Makefile                               | 2 +-
+ drivers/reset/starfive/Kconfig                       | 8 ++++++++
+ drivers/reset/starfive/Makefile                      | 2 ++
+ drivers/reset/{ => starfive}/reset-starfive-jh7100.c | 0
+ 6 files changed, 13 insertions(+), 9 deletions(-)
+ create mode 100644 drivers/reset/starfive/Kconfig
+ create mode 100644 drivers/reset/starfive/Makefile
+ rename drivers/reset/{ => starfive}/reset-starfive-jh7100.c (100%)
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -17879,7 +17879,7 @@ STARFIVE JH7100 RESET CONTROLLER DRIVER
+ M:    Emil Renner Berthing <kernel@esmil.dk>
+ S:    Maintained
+ F:    Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+-F:    drivers/reset/reset-starfive-jh7100.c
++F:    drivers/reset/starfive/reset-starfive-jh7100.c
+ F:    include/dt-bindings/reset/starfive-jh7100.h
+ 
+ STATIC BRANCH/CALL
+--- a/drivers/reset/Kconfig
++++ b/drivers/reset/Kconfig
+@@ -224,13 +224,6 @@ config RESET_SOCFPGA
+         This enables the reset driver for the SoCFPGA ARMv7 platforms. This
+         driver gets initialized early during platform init calls.
+ 
+-config RESET_STARFIVE_JH7100
+-      bool "StarFive JH7100 Reset Driver"
+-      depends on SOC_STARFIVE || COMPILE_TEST
+-      default SOC_STARFIVE
+-      help
+-        This enables the reset controller driver for the StarFive JH7100 SoC.
+-
+ config RESET_SUNXI
+       bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
+       default ARCH_SUNXI
+@@ -282,6 +275,7 @@ config RESET_ZYNQ
+       help
+         This enables the reset controller driver for Xilinx Zynq SoCs.
+ 
++source "drivers/reset/starfive/Kconfig"
+ source "drivers/reset/sti/Kconfig"
+ source "drivers/reset/hisilicon/Kconfig"
+ source "drivers/reset/tegra/Kconfig"
+--- a/drivers/reset/Makefile
++++ b/drivers/reset/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-y += core.o
+ obj-y += hisilicon/
++obj-y += starfive/
+ obj-$(CONFIG_ARCH_STI) += sti/
+ obj-$(CONFIG_ARCH_TEGRA) += tegra/
+ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
+@@ -29,7 +30,6 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) +=
+ obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
+ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+ obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
+-obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
+ obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
+ obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
+--- /dev/null
++++ b/drivers/reset/starfive/Kconfig
+@@ -0,0 +1,8 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++config RESET_STARFIVE_JH7100
++      bool "StarFive JH7100 Reset Driver"
++      depends on SOC_STARFIVE || COMPILE_TEST
++      default SOC_STARFIVE
++      help
++        This enables the reset controller driver for the StarFive JH7100 SoC.
+--- /dev/null
++++ b/drivers/reset/starfive/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_RESET_STARFIVE_JH7100)           += reset-starfive-jh7100.o
+--- a/drivers/reset/reset-starfive-jh7100.c
++++ /dev/null
+@@ -1,173 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-or-later
+-/*
+- * Reset driver for the StarFive JH7100 SoC
+- *
+- * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+- */
+-
+-#include <linux/bitmap.h>
+-#include <linux/io.h>
+-#include <linux/io-64-nonatomic-lo-hi.h>
+-#include <linux/iopoll.h>
+-#include <linux/mod_devicetable.h>
+-#include <linux/platform_device.h>
+-#include <linux/reset-controller.h>
+-#include <linux/spinlock.h>
+-
+-#include <dt-bindings/reset/starfive-jh7100.h>
+-
+-/* register offsets */
+-#define JH7100_RESET_ASSERT0  0x00
+-#define JH7100_RESET_ASSERT1  0x04
+-#define JH7100_RESET_ASSERT2  0x08
+-#define JH7100_RESET_ASSERT3  0x0c
+-#define JH7100_RESET_STATUS0  0x10
+-#define JH7100_RESET_STATUS1  0x14
+-#define JH7100_RESET_STATUS2  0x18
+-#define JH7100_RESET_STATUS3  0x1c
+-
+-/*
+- * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
+- * line 32m + n, and writing a 0 deasserts the same line.
+- * Most reset lines have their status inverted so a 0 bit in the STATUS
+- * register means the line is asserted and a 1 means it's deasserted. A few
+- * lines don't though, so store the expected value of the status registers when
+- * all lines are asserted.
+- */
+-static const u64 jh7100_reset_asserted[2] = {
+-      /* STATUS0 */
+-      BIT_ULL_MASK(JH7100_RST_U74) |
+-      BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
+-      BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
+-      /* STATUS1 */
+-      BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
+-      BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
+-      /* STATUS2 */
+-      BIT_ULL_MASK(JH7100_RST_E24) |
+-      /* STATUS3 */
+-      0,
+-};
+-
+-struct jh7100_reset {
+-      struct reset_controller_dev rcdev;
+-      /* protect registers against concurrent read-modify-write */
+-      spinlock_t lock;
+-      void __iomem *base;
+-};
+-
+-static inline struct jh7100_reset *
+-jh7100_reset_from(struct reset_controller_dev *rcdev)
+-{
+-      return container_of(rcdev, struct jh7100_reset, rcdev);
+-}
+-
+-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
+-                             unsigned long id, bool assert)
+-{
+-      struct jh7100_reset *data = jh7100_reset_from(rcdev);
+-      unsigned long offset = BIT_ULL_WORD(id);
+-      u64 mask = BIT_ULL_MASK(id);
+-      void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
+-      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
+-      u64 done = jh7100_reset_asserted[offset] & mask;
+-      u64 value;
+-      unsigned long flags;
+-      int ret;
+-
+-      if (!assert)
+-              done ^= mask;
+-
+-      spin_lock_irqsave(&data->lock, flags);
+-
+-      value = readq(reg_assert);
+-      if (assert)
+-              value |= mask;
+-      else
+-              value &= ~mask;
+-      writeq(value, reg_assert);
+-
+-      /* if the associated clock is gated, deasserting might otherwise hang forever */
+-      ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
+-
+-      spin_unlock_irqrestore(&data->lock, flags);
+-      return ret;
+-}
+-
+-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
+-                             unsigned long id)
+-{
+-      return jh7100_reset_update(rcdev, id, true);
+-}
+-
+-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
+-                               unsigned long id)
+-{
+-      return jh7100_reset_update(rcdev, id, false);
+-}
+-
+-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
+-                            unsigned long id)
+-{
+-      int ret;
+-
+-      ret = jh7100_reset_assert(rcdev, id);
+-      if (ret)
+-              return ret;
+-
+-      return jh7100_reset_deassert(rcdev, id);
+-}
+-
+-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
+-                             unsigned long id)
+-{
+-      struct jh7100_reset *data = jh7100_reset_from(rcdev);
+-      unsigned long offset = BIT_ULL_WORD(id);
+-      u64 mask = BIT_ULL_MASK(id);
+-      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
+-      u64 value = readq(reg_status);
+-
+-      return !((value ^ jh7100_reset_asserted[offset]) & mask);
+-}
+-
+-static const struct reset_control_ops jh7100_reset_ops = {
+-      .assert         = jh7100_reset_assert,
+-      .deassert       = jh7100_reset_deassert,
+-      .reset          = jh7100_reset_reset,
+-      .status         = jh7100_reset_status,
+-};
+-
+-static int __init jh7100_reset_probe(struct platform_device *pdev)
+-{
+-      struct jh7100_reset *data;
+-
+-      data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+-      if (!data)
+-              return -ENOMEM;
+-
+-      data->base = devm_platform_ioremap_resource(pdev, 0);
+-      if (IS_ERR(data->base))
+-              return PTR_ERR(data->base);
+-
+-      data->rcdev.ops = &jh7100_reset_ops;
+-      data->rcdev.owner = THIS_MODULE;
+-      data->rcdev.nr_resets = JH7100_RSTN_END;
+-      data->rcdev.dev = &pdev->dev;
+-      data->rcdev.of_node = pdev->dev.of_node;
+-      spin_lock_init(&data->lock);
+-
+-      return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+-}
+-
+-static const struct of_device_id jh7100_reset_dt_ids[] = {
+-      { .compatible = "starfive,jh7100-reset" },
+-      { /* sentinel */ }
+-};
+-
+-static struct platform_driver jh7100_reset_driver = {
+-      .driver = {
+-              .name = "jh7100-reset",
+-              .of_match_table = jh7100_reset_dt_ids,
+-              .suppress_bind_attrs = true,
+-      },
+-};
+-builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);
+--- /dev/null
++++ b/drivers/reset/starfive/reset-starfive-jh7100.c
+@@ -0,0 +1,173 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Reset driver for the StarFive JH7100 SoC
++ *
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#include <linux/bitmap.h>
++#include <linux/io.h>
++#include <linux/io-64-nonatomic-lo-hi.h>
++#include <linux/iopoll.h>
++#include <linux/mod_devicetable.h>
++#include <linux/platform_device.h>
++#include <linux/reset-controller.h>
++#include <linux/spinlock.h>
++
++#include <dt-bindings/reset/starfive-jh7100.h>
++
++/* register offsets */
++#define JH7100_RESET_ASSERT0  0x00
++#define JH7100_RESET_ASSERT1  0x04
++#define JH7100_RESET_ASSERT2  0x08
++#define JH7100_RESET_ASSERT3  0x0c
++#define JH7100_RESET_STATUS0  0x10
++#define JH7100_RESET_STATUS1  0x14
++#define JH7100_RESET_STATUS2  0x18
++#define JH7100_RESET_STATUS3  0x1c
++
++/*
++ * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
++ * line 32m + n, and writing a 0 deasserts the same line.
++ * Most reset lines have their status inverted so a 0 bit in the STATUS
++ * register means the line is asserted and a 1 means it's deasserted. A few
++ * lines don't though, so store the expected value of the status registers when
++ * all lines are asserted.
++ */
++static const u64 jh7100_reset_asserted[2] = {
++      /* STATUS0 */
++      BIT_ULL_MASK(JH7100_RST_U74) |
++      BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
++      BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
++      /* STATUS1 */
++      BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
++      BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
++      /* STATUS2 */
++      BIT_ULL_MASK(JH7100_RST_E24) |
++      /* STATUS3 */
++      0,
++};
++
++struct jh7100_reset {
++      struct reset_controller_dev rcdev;
++      /* protect registers against concurrent read-modify-write */
++      spinlock_t lock;
++      void __iomem *base;
++};
++
++static inline struct jh7100_reset *
++jh7100_reset_from(struct reset_controller_dev *rcdev)
++{
++      return container_of(rcdev, struct jh7100_reset, rcdev);
++}
++
++static int jh7100_reset_update(struct reset_controller_dev *rcdev,
++                             unsigned long id, bool assert)
++{
++      struct jh7100_reset *data = jh7100_reset_from(rcdev);
++      unsigned long offset = BIT_ULL_WORD(id);
++      u64 mask = BIT_ULL_MASK(id);
++      void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
++      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
++      u64 done = jh7100_reset_asserted[offset] & mask;
++      u64 value;
++      unsigned long flags;
++      int ret;
++
++      if (!assert)
++              done ^= mask;
++
++      spin_lock_irqsave(&data->lock, flags);
++
++      value = readq(reg_assert);
++      if (assert)
++              value |= mask;
++      else
++              value &= ~mask;
++      writeq(value, reg_assert);
++
++      /* if the associated clock is gated, deasserting might otherwise hang forever */
++      ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
++
++      spin_unlock_irqrestore(&data->lock, flags);
++      return ret;
++}
++
++static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
++                             unsigned long id)
++{
++      return jh7100_reset_update(rcdev, id, true);
++}
++
++static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
++                               unsigned long id)
++{
++      return jh7100_reset_update(rcdev, id, false);
++}
++
++static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
++                            unsigned long id)
++{
++      int ret;
++
++      ret = jh7100_reset_assert(rcdev, id);
++      if (ret)
++              return ret;
++
++      return jh7100_reset_deassert(rcdev, id);
++}
++
++static int jh7100_reset_status(struct reset_controller_dev *rcdev,
++                             unsigned long id)
++{
++      struct jh7100_reset *data = jh7100_reset_from(rcdev);
++      unsigned long offset = BIT_ULL_WORD(id);
++      u64 mask = BIT_ULL_MASK(id);
++      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
++      u64 value = readq(reg_status);
++
++      return !((value ^ jh7100_reset_asserted[offset]) & mask);
++}
++
++static const struct reset_control_ops jh7100_reset_ops = {
++      .assert         = jh7100_reset_assert,
++      .deassert       = jh7100_reset_deassert,
++      .reset          = jh7100_reset_reset,
++      .status         = jh7100_reset_status,
++};
++
++static int __init jh7100_reset_probe(struct platform_device *pdev)
++{
++      struct jh7100_reset *data;
++
++      data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++      if (!data)
++              return -ENOMEM;
++
++      data->base = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(data->base))
++              return PTR_ERR(data->base);
++
++      data->rcdev.ops = &jh7100_reset_ops;
++      data->rcdev.owner = THIS_MODULE;
++      data->rcdev.nr_resets = JH7100_RSTN_END;
++      data->rcdev.dev = &pdev->dev;
++      data->rcdev.of_node = pdev->dev.of_node;
++      spin_lock_init(&data->lock);
++
++      return devm_reset_controller_register(&pdev->dev, &data->rcdev);
++}
++
++static const struct of_device_id jh7100_reset_dt_ids[] = {
++      { .compatible = "starfive,jh7100-reset" },
++      { /* sentinel */ }
++};
++
++static struct platform_driver jh7100_reset_driver = {
++      .driver = {
++              .name = "jh7100-reset",
++              .of_match_table = jh7100_reset_dt_ids,
++              .suppress_bind_attrs = true,
++      },
++};
++builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);

diff --git a/target/linux/visionfive/patches-5.15/0041-reset-starfive-Use-32bit-I-O-on-32bit-registers.patch b/target/linux/visionfive/patches-5.15/0041-reset-starfive-Use-32bit-I-O-on-32bit-registers.patch
new file mode 100644 (file)
index 0000000..47ac740
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0041-reset-starfive-Use-32bit-I-O-on-32bit-registers.patch
@@ -0,0 +1,99 @@
+From 22ce849ad3b855ab2eb9f94662faee7f2be7f93e Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Wed, 24 Nov 2021 01:30:54 +0100
+Subject: [PATCH 41/84] reset: starfive: Use 32bit I/O on 32bit registers
+
+The driver currently uses 64bit I/O on the 32bit registers. This works
+because there are 4 assert registers and 4 status register, so they're
+only ever accessed on 64bit boundaries.
+
+There are however other reset controllers for audio and video on the SoC
+with only one status register that isn't 64bit aligned so 64bit I/O
+would result in an unaligned access exception.
+
+Switch to 32bit I/O in preparation for supporting these resets too.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../reset/starfive/reset-starfive-jh7100.c    | 40 +++++++++----------
+ 1 file changed, 20 insertions(+), 20 deletions(-)
+
+--- a/drivers/reset/starfive/reset-starfive-jh7100.c
++++ b/drivers/reset/starfive/reset-starfive-jh7100.c
+@@ -34,16 +34,16 @@
+  * lines don't though, so store the expected value of the status registers when
+  * all lines are asserted.
+  */
+-static const u64 jh7100_reset_asserted[2] = {
++static const u32 jh7100_reset_asserted[4] = {
+       /* STATUS0 */
+-      BIT_ULL_MASK(JH7100_RST_U74) |
+-      BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
+-      BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
++      BIT(JH7100_RST_U74 % 32) |
++      BIT(JH7100_RST_VP6_DRESET % 32) |
++      BIT(JH7100_RST_VP6_BRESET % 32),
+       /* STATUS1 */
+-      BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
+-      BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
++      BIT(JH7100_RST_HIFI4_DRESET % 32) |
++      BIT(JH7100_RST_HIFI4_BRESET % 32),
+       /* STATUS2 */
+-      BIT_ULL_MASK(JH7100_RST_E24) |
++      BIT(JH7100_RST_E24 % 32),
+       /* STATUS3 */
+       0,
+ };
+@@ -65,12 +65,12 @@ static int jh7100_reset_update(struct re
+                              unsigned long id, bool assert)
+ {
+       struct jh7100_reset *data = jh7100_reset_from(rcdev);
+-      unsigned long offset = BIT_ULL_WORD(id);
+-      u64 mask = BIT_ULL_MASK(id);
+-      void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
+-      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
+-      u64 done = jh7100_reset_asserted[offset] & mask;
+-      u64 value;
++      unsigned long offset = id / 32;
++      u32 mask = BIT(id % 32);
++      void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u32);
++      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
++      u32 done = jh7100_reset_asserted[offset] & mask;
++      u32 value;
+       unsigned long flags;
+       int ret;
+ 
+@@ -79,15 +79,15 @@ static int jh7100_reset_update(struct re
+ 
+       spin_lock_irqsave(&data->lock, flags);
+ 
+-      value = readq(reg_assert);
++      value = readl(reg_assert);
+       if (assert)
+               value |= mask;
+       else
+               value &= ~mask;
+-      writeq(value, reg_assert);
++      writel(value, reg_assert);
+ 
+       /* if the associated clock is gated, deasserting might otherwise hang forever */
+-      ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
++      ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
+ 
+       spin_unlock_irqrestore(&data->lock, flags);
+       return ret;
+@@ -121,10 +121,10 @@ static int jh7100_reset_status(struct re
+                              unsigned long id)
+ {
+       struct jh7100_reset *data = jh7100_reset_from(rcdev);
+-      unsigned long offset = BIT_ULL_WORD(id);
+-      u64 mask = BIT_ULL_MASK(id);
+-      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
+-      u64 value = readq(reg_status);
++      unsigned long offset = id / 32;
++      u32 mask = BIT(id % 32);
++      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
++      u32 value = readl(reg_status);
+ 
+       return !((value ^ jh7100_reset_asserted[offset]) & mask);
+ }

diff --git a/target/linux/visionfive/patches-5.15/0042-reset-starfive-Add-JH7100-audio-reset-driver.patch b/target/linux/visionfive/patches-5.15/0042-reset-starfive-Add-JH7100-audio-reset-driver.patch
new file mode 100644 (file)
index 0000000..335caf0
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0042-reset-starfive-Add-JH7100-audio-reset-driver.patch
@@ -0,0 +1,231 @@
+From 512d1a891de7ce03ebb92a9f454608592e8eec3e Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 19:30:49 +0100
+Subject: [PATCH 42/84] reset: starfive: Add JH7100 audio reset driver
+
+The audio resets are almost identical to the system resets, there are
+just fewer of them. So factor out and export a generic probe function,
+so most of the reset controller implementation can be shared.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ MAINTAINERS                                   |  8 +--
+ drivers/reset/starfive/Kconfig                |  7 +++
+ drivers/reset/starfive/Makefile               |  1 +
+ .../starfive/reset-starfive-jh7100-audio.c    | 58 +++++++++++++++++++
+ .../reset/starfive/reset-starfive-jh7100.c    | 37 ++++++++----
+ .../reset/starfive/reset-starfive-jh7100.h    | 16 +++++
+ 6 files changed, 112 insertions(+), 15 deletions(-)
+ create mode 100644 drivers/reset/starfive/reset-starfive-jh7100-audio.c
+ create mode 100644 drivers/reset/starfive/reset-starfive-jh7100.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -17875,12 +17875,12 @@ F:   Documentation/devicetree/bindings/pin
+ F:    drivers/pinctrl/pinctrl-starfive.c
+ F:    include/dt-bindings/pinctrl/pinctrl-starfive.h
+ 
+-STARFIVE JH7100 RESET CONTROLLER DRIVER
++STARFIVE JH7100 RESET CONTROLLER DRIVERS
+ M:    Emil Renner Berthing <kernel@esmil.dk>
+ S:    Maintained
+-F:    Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+-F:    drivers/reset/starfive/reset-starfive-jh7100.c
+-F:    include/dt-bindings/reset/starfive-jh7100.h
++F:    Documentation/devicetree/bindings/reset/starfive,jh7100-*.yaml
++F:    drivers/reset/starfive/reset-starfive-jh7100*
++F:    include/dt-bindings/reset/starfive-jh7100*.h
+ 
+ STATIC BRANCH/CALL
+ M:    Peter Zijlstra <peterz@infradead.org>
+--- a/drivers/reset/starfive/Kconfig
++++ b/drivers/reset/starfive/Kconfig
+@@ -6,3 +6,10 @@ config RESET_STARFIVE_JH7100
+       default SOC_STARFIVE
+       help
+         This enables the reset controller driver for the StarFive JH7100 SoC.
++
++config RESET_STARFIVE_JH7100_AUDIO
++      tristate "StarFive JH7100 Audio Reset Driver"
++      depends on RESET_STARFIVE_JH7100
++      default SOC_STARFIVE
++      help
++        This enables the audio reset driver for the StarFive JH7100 SoC.
+--- a/drivers/reset/starfive/Makefile
++++ b/drivers/reset/starfive/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_RESET_STARFIVE_JH7100)           += reset-starfive-jh7100.o
++obj-$(CONFIG_RESET_STARFIVE_JH7100_AUDIO)     += reset-starfive-jh7100-audio.o
+--- /dev/null
++++ b/drivers/reset/starfive/reset-starfive-jh7100-audio.c
+@@ -0,0 +1,58 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Audio reset driver for the StarFive JH7100 SoC
++ *
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#include <linux/mod_devicetable.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/reset-controller.h>
++
++#include <dt-bindings/reset/starfive-jh7100-audio.h>
++
++#include "reset-starfive-jh7100.h"
++
++/* register offsets */
++#define JH7100_AUDRST_ASSERT0 0x00
++#define JH7100_AUDRST_STATUS0 0x04
++
++/*
++ * Writing a 1 to the n'th bit of the ASSERT register asserts
++ * line n, and writing a 0 deasserts the same line.
++ * Most reset lines have their status inverted so a 0 bit in the STATUS
++ * register means the line is asserted and a 1 means it's deasserted. A few
++ * lines don't though, so store the expected value of the status registers when
++ * all lines are asserted.
++ */
++static const u32 jh7100_audrst_asserted[1] = {
++      BIT(JH7100_AUDRST_USB_AXI) |
++      BIT(JH7100_AUDRST_USB_PWRUP_RST_N) |
++      BIT(JH7100_AUDRST_USB_PONRST)
++};
++
++static int jh7100_audrst_probe(struct platform_device *pdev)
++{
++      return reset_starfive_jh7100_generic_probe(pdev, jh7100_audrst_asserted,
++                                                 JH7100_AUDRST_STATUS0, JH7100_AUDRSTN_END);
++}
++
++static const struct of_device_id jh7100_audrst_dt_ids[] = {
++      { .compatible = "starfive,jh7100-audrst" },
++      { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, jh7100_audrst_dt_ids);
++
++static struct platform_driver jh7100_audrst_driver = {
++      .probe = jh7100_audrst_probe,
++      .driver = {
++              .name = "jh7100-reset-audio",
++              .of_match_table = jh7100_audrst_dt_ids,
++      },
++};
++module_platform_driver(jh7100_audrst_driver);
++
++MODULE_AUTHOR("Emil Renner Berthing");
++MODULE_DESCRIPTION("StarFive JH7100 audio reset driver");
++MODULE_LICENSE("GPL");
+--- a/drivers/reset/starfive/reset-starfive-jh7100.c
++++ b/drivers/reset/starfive/reset-starfive-jh7100.c
+@@ -16,6 +16,8 @@
+ 
+ #include <dt-bindings/reset/starfive-jh7100.h>
+ 
++#include "reset-starfive-jh7100.h"
++
+ /* register offsets */
+ #define JH7100_RESET_ASSERT0  0x00
+ #define JH7100_RESET_ASSERT1  0x04
+@@ -52,7 +54,9 @@ struct jh7100_reset {
+       struct reset_controller_dev rcdev;
+       /* protect registers against concurrent read-modify-write */
+       spinlock_t lock;
+-      void __iomem *base;
++      void __iomem *assert;
++      void __iomem *status;
++      const u32 *asserted;
+ };
+ 
+ static inline struct jh7100_reset *
+@@ -67,9 +71,9 @@ static int jh7100_reset_update(struct re
+       struct jh7100_reset *data = jh7100_reset_from(rcdev);
+       unsigned long offset = id / 32;
+       u32 mask = BIT(id % 32);
+-      void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u32);
+-      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
+-      u32 done = jh7100_reset_asserted[offset] & mask;
++      void __iomem *reg_assert = data->assert + offset * sizeof(u32);
++      void __iomem *reg_status = data->status + offset * sizeof(u32);
++      u32 done = data->asserted[offset] & mask;
+       u32 value;
+       unsigned long flags;
+       int ret;
+@@ -123,10 +127,10 @@ static int jh7100_reset_status(struct re
+       struct jh7100_reset *data = jh7100_reset_from(rcdev);
+       unsigned long offset = id / 32;
+       u32 mask = BIT(id % 32);
+-      void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
++      void __iomem *reg_status = data->status + offset * sizeof(u32);
+       u32 value = readl(reg_status);
+ 
+-      return !((value ^ jh7100_reset_asserted[offset]) & mask);
++      return !((value ^ data->asserted[offset]) & mask);
+ }
+ 
+ static const struct reset_control_ops jh7100_reset_ops = {
+@@ -136,7 +140,8 @@ static const struct reset_control_ops jh
+       .status         = jh7100_reset_status,
+ };
+ 
+-static int __init jh7100_reset_probe(struct platform_device *pdev)
++int reset_starfive_jh7100_generic_probe(struct platform_device *pdev, const u32 *asserted,
++                                      unsigned int status_offset, unsigned int nr_resets)
+ {
+       struct jh7100_reset *data;
+ 
+@@ -144,19 +149,29 @@ static int __init jh7100_reset_probe(str
+       if (!data)
+               return -ENOMEM;
+ 
+-      data->base = devm_platform_ioremap_resource(pdev, 0);
+-      if (IS_ERR(data->base))
+-              return PTR_ERR(data->base);
++      data->assert = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(data->assert))
++              return PTR_ERR(data->assert);
+ 
+       data->rcdev.ops = &jh7100_reset_ops;
+       data->rcdev.owner = THIS_MODULE;
+-      data->rcdev.nr_resets = JH7100_RSTN_END;
++      data->rcdev.nr_resets = nr_resets;
+       data->rcdev.dev = &pdev->dev;
+       data->rcdev.of_node = pdev->dev.of_node;
++
+       spin_lock_init(&data->lock);
++      data->status = data->assert + status_offset;
++      data->asserted = asserted;
+ 
+       return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+ }
++EXPORT_SYMBOL_GPL(reset_starfive_jh7100_generic_probe);
++
++static int __init jh7100_reset_probe(struct platform_device *pdev)
++{
++      return reset_starfive_jh7100_generic_probe(pdev, jh7100_reset_asserted,
++                                                 JH7100_RESET_STATUS0, JH7100_RSTN_END);
++}
+ 
+ static const struct of_device_id jh7100_reset_dt_ids[] = {
+       { .compatible = "starfive,jh7100-reset" },
+--- /dev/null
++++ b/drivers/reset/starfive/reset-starfive-jh7100.h
+@@ -0,0 +1,16 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#ifndef _RESET_STARFIVE_JH7100_H_
++#define _RESET_STARFIVE_JH7100_H_
++
++#include <linux/platform_device.h>
++
++int reset_starfive_jh7100_generic_probe(struct platform_device *pdev,
++                                      const u32 *asserted,
++                                      unsigned int status_offset,
++                                      unsigned int nr_resets);
++
++#endif

diff --git a/target/linux/visionfive/patches-5.15/0043-RISC-V-Add-StarFive-JH7100-audio-reset-node.patch b/target/linux/visionfive/patches-5.15/0043-RISC-V-Add-StarFive-JH7100-audio-reset-node.patch
new file mode 100644 (file)
index 0000000..890b44b
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0043-RISC-V-Add-StarFive-JH7100-audio-reset-node.patch
@@ -0,0 +1,28 @@
+From 51787c7fd698a58bfb9604eec161e413410ff4ef Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 21:33:08 +0100
+Subject: [PATCH 43/84] RISC-V: Add StarFive JH7100 audio reset node
+
+Add device tree node for the audio resets on the StarFive JH7100 RISC-V
+SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -131,6 +131,12 @@
+                       #clock-cells = <1>;
+               };
+ 
++              audrst: reset-controller@10490000 {
++                      compatible = "starfive,jh7100-audrst";
++                      reg = <0x0 0x10490000 0x0 0x10000>;
++                      #reset-cells = <1>;
++              };
++
+               clkgen: clock-controller@11800000 {
+                       compatible = "starfive,jh7100-clkgen";
+                       reg = <0x0 0x11800000 0x0 0x10000>;

diff --git a/target/linux/visionfive/patches-5.15/0044-clk-starfive-jh7100-Keep-more-clocks-alive.patch b/target/linux/visionfive/patches-5.15/0044-clk-starfive-jh7100-Keep-more-clocks-alive.patch
new file mode 100644 (file)
index 0000000..5a491e4
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0044-clk-starfive-jh7100-Keep-more-clocks-alive.patch
@@ -0,0 +1,102 @@
+From 63610e3a293bd27dbb381f151c969eb0ec8322cf Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Thu, 14 Oct 2021 20:35:43 +0200
+Subject: [PATCH 44/84] clk: starfive: jh7100: Keep more clocks alive
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/clk/starfive/clk-starfive-jh7100.c | 38 +++++++++++-----------
+ 1 file changed, 19 insertions(+), 19 deletions(-)
+
+--- a/drivers/clk/starfive/clk-starfive-jh7100.c
++++ b/drivers/clk/starfive/clk-starfive-jh7100.c
+@@ -99,9 +99,9 @@ static const struct jh7100_clk_data jh71
+       JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
+       JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
+       JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
+-      JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
+-      JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
+-      JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", CLK_IGNORE_UNUSED, JH7100_CLK_DLA_BUS),
++      JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", CLK_IGNORE_UNUSED, JH7100_CLK_DLA_BUS),
++      JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", CLK_IGNORE_UNUSED, JH7100_CLK_APB1_BUS),
+       JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
+       JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
+       JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
+@@ -163,11 +163,11 @@ static const struct jh7100_clk_data jh71
+       JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
+       JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+       JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+-      JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
+-      JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
++      JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", CLK_IGNORE_UNUSED, JH7100_CLK_USB_BUS),
++      JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", CLK_IGNORE_UNUSED, JH7100_CLK_USB_BUS),
+       JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
+-      JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
+-      JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
++      JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", CLK_IGNORE_UNUSED, 8, JH7100_CLK_USBPHY_ROOTDIV),
++      JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", CLK_IGNORE_UNUSED, 32, JH7100_CLK_USBPHY_ROOTDIV),
+       JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
+                   JH7100_CLK_OSC_SYS,
+                   JH7100_CLK_USBPHY_PLLDIV25M),
+@@ -185,23 +185,23 @@ static const struct jh7100_clk_data jh71
+       JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
+       JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
+       JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
+-      JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
++      JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", CLK_IGNORE_UNUSED, 4, JH7100_CLK_VOUT_ROOT),
+       JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
+       JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
+-      JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
+-      JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
++      JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", CLK_IGNORE_UNUSED, JH7100_CLK_DISP_BUS),
++      JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", CLK_IGNORE_UNUSED, JH7100_CLK_DISP_BUS),
+       JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
+       JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
+       JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
+       JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
+       JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
+       JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
+-      JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
++      JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", CLK_IGNORE_UNUSED, JH7100_CLK_AHB_BUS),
+       JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
+-      JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
+-      JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
+-      JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
+-      JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
++      JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", CLK_IGNORE_UNUSED, 31, JH7100_CLK_GMAC_ROOT_DIV),
++      JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", CLK_IGNORE_UNUSED, 255, JH7100_CLK_GMAC_ROOT_DIV),
++      JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", CLK_IGNORE_UNUSED, 8, JH7100_CLK_GMAC_RMII_REF),
++      JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", CLK_IGNORE_UNUSED, 8, JH7100_CLK_GMAC_RMII_REF),
+       JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
+                   JH7100_CLK_GMAC_GTX,
+                   JH7100_CLK_GMAC_TX_INV,
+@@ -211,8 +211,8 @@ static const struct jh7100_clk_data jh71
+                   JH7100_CLK_GMAC_GR_MII_RX,
+                   JH7100_CLK_GMAC_RMII_RX),
+       JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
+-      JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
+-      JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
++      JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", CLK_IGNORE_UNUSED, JH7100_CLK_GMAC_RMII_REF),
++      JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", CLK_IGNORE_UNUSED, 127, JH7100_CLK_GMAC_ROOT_DIV),
+       JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
+       JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
+       JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
+@@ -225,7 +225,7 @@ static const struct jh7100_clk_data jh71
+       JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
+       JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
+       JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
+-      JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
++      JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", CLK_IGNORE_UNUSED, JH7100_CLK_APB1_BUS),
+       JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
+       JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
+       JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+@@ -262,7 +262,7 @@ static const struct jh7100_clk_data jh71
+       JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+       JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+       JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
+-      JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
++      JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", CLK_IGNORE_UNUSED, JH7100_CLK_APB2_BUS),
+       JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
+       JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
+       JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),

diff --git a/target/linux/visionfive/patches-5.15/0045-pinctrl-starfive-Reset-pinmux-settings.patch b/target/linux/visionfive/patches-5.15/0045-pinctrl-starfive-Reset-pinmux-settings.patch
new file mode 100644 (file)
index 0000000..e2a7f3d
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0045-pinctrl-starfive-Reset-pinmux-settings.patch
@@ -0,0 +1,127 @@
+From 80ada2a156ffb6274df040c22d371daf08d8cbe0 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 17 Jul 2021 21:50:38 +0200
+Subject: [PATCH 45/84] pinctrl: starfive: Reset pinmux settings
+
+Current u-boot doesn't seem to take into account that some GPIOs are
+configured as inputs/outputs of certain peripherals on power-up. This
+means it ends up configuring some GPIOs as inputs to more than one
+peripheral which the documentation explicitly says is illegal. Similarly
+it also ends up configuring more than one GPIO as output of the same
+peripheral. While not explicitly mentioned by the documentation this
+also seems like a bad idea.
+
+The easiest way to remedy this mess is to just disconnect all GPIOs from
+peripherals and have our pinmux configuration set everything up
+properly. This, however, means that we'd disconnect the serial console
+from its pins for a while, so add a device tree property to keep
+certain GPIOs from being reset.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../pinctrl/starfive,jh7100-pinctrl.yaml      |  4 ++
+ drivers/pinctrl/pinctrl-starfive.c            | 66 +++++++++++++++++++
+ 2 files changed, 70 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
++++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+@@ -88,6 +88,10 @@ properties:
+     $ref: /schemas/types.yaml#/definitions/uint32
+     enum: [0, 1, 2, 3, 4, 5, 6]
+ 
++  starfive,keep-gpiomux:
++    description: Keep pinmux for these GPIOs from being reset at boot.
++    $ref: /schemas/types.yaml#/definitions/uint32-array
++
+ required:
+   - compatible
+   - reg
+--- a/drivers/pinctrl/pinctrl-starfive.c
++++ b/drivers/pinctrl/pinctrl-starfive.c
+@@ -200,6 +200,10 @@ static u16 starfive_drive_strength_from_
+       return (clamp(i, 14U, 63U) - 14) / 7;
+ }
+ 
++static bool keepmux;
++module_param(keepmux, bool, 0644);
++MODULE_PARM_DESC(keepmux, "Keep pinmux settings from previous boot stage");
++
+ struct starfive_pinctrl {
+       struct gpio_chip gc;
+       struct pinctrl_gpio_range gpios;
+@@ -1212,6 +1216,65 @@ static void starfive_disable_clock(void
+       clk_disable_unprepare(data);
+ }
+ 
++#define GPI_END (GPI_USB_OVER_CURRENT + 1)
++static void starfive_pinmux_reset(struct starfive_pinctrl *sfp)
++{
++      static const DECLARE_BITMAP(defaults, GPI_END) = {
++              BIT_MASK(GPI_I2C0_PAD_SCK_IN) |
++              BIT_MASK(GPI_I2C0_PAD_SDA_IN) |
++              BIT_MASK(GPI_I2C1_PAD_SCK_IN) |
++              BIT_MASK(GPI_I2C1_PAD_SDA_IN) |
++              BIT_MASK(GPI_I2C2_PAD_SCK_IN) |
++              BIT_MASK(GPI_I2C2_PAD_SDA_IN) |
++              BIT_MASK(GPI_I2C3_PAD_SCK_IN) |
++              BIT_MASK(GPI_I2C3_PAD_SDA_IN) |
++              BIT_MASK(GPI_SDIO0_PAD_CARD_DETECT_N) |
++
++              BIT_MASK(GPI_SDIO1_PAD_CARD_DETECT_N) |
++              BIT_MASK(GPI_SPI0_PAD_SS_IN_N) |
++              BIT_MASK(GPI_SPI1_PAD_SS_IN_N) |
++              BIT_MASK(GPI_SPI2_PAD_SS_IN_N) |
++              BIT_MASK(GPI_SPI2AHB_PAD_SS_N) |
++              BIT_MASK(GPI_SPI3_PAD_SS_IN_N),
++
++              BIT_MASK(GPI_UART0_PAD_SIN) |
++              BIT_MASK(GPI_UART1_PAD_SIN) |
++              BIT_MASK(GPI_UART2_PAD_SIN) |
++              BIT_MASK(GPI_UART3_PAD_SIN) |
++              BIT_MASK(GPI_USB_OVER_CURRENT)
++      };
++      DECLARE_BITMAP(keep, NR_GPIOS) = {};
++      struct device_node *np = sfp->gc.parent->of_node;
++      int len = of_property_count_u32_elems(np, "starfive,keep-gpiomux");
++      int i;
++
++      for (i = 0; i < len; i++) {
++              u32 gpio;
++
++              of_property_read_u32_index(np, "starfive,keep-gpiomux", i, &gpio);
++              if (gpio < NR_GPIOS)
++                      set_bit(gpio, keep);
++      }
++
++      for (i = 0; i < NR_GPIOS; i++) {
++              if (test_bit(i, keep))
++                      continue;
++
++              writel_relaxed(GPO_DISABLE, sfp->base + GPON_DOEN_CFG + 8 * i);
++              writel_relaxed(GPO_LOW,     sfp->base + GPON_DOUT_CFG + 8 * i);
++      }
++
++      for (i = 0; i < GPI_END; i++) {
++              void __iomem *reg = sfp->base + GPI_CFG_OFFSET + 4 * i;
++              u32 din = readl_relaxed(reg);
++
++              if (din >= 2 && din < (NR_GPIOS + 2) && test_bit(din - 2, keep))
++                      continue;
++
++              writel_relaxed(test_bit(i, defaults), reg);
++      }
++}
++
+ static int starfive_probe(struct platform_device *pdev)
+ {
+       struct device *dev = &pdev->dev;
+@@ -1272,6 +1335,9 @@ static int starfive_probe(struct platfor
+               writel(value, sfp->padctl + IO_PADSHARE_SEL);
+       }
+ 
++      if (!keepmux)
++              starfive_pinmux_reset(sfp);
++
+       value = readl(sfp->padctl + IO_PADSHARE_SEL);
+       switch (value) {
+       case 0:

diff --git a/target/linux/visionfive/patches-5.15/0046-serial-8250_dw-Add-quirk-for-starfive-jh7100-hsuart-.patch b/target/linux/visionfive/patches-5.15/0046-serial-8250_dw-Add-quirk-for-starfive-jh7100-hsuart-.patch
new file mode 100644 (file)
index 0000000..8800171
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0046-serial-8250_dw-Add-quirk-for-starfive-jh7100-hsuart-.patch
@@ -0,0 +1,31 @@
+From 27bd0f91291de8014200b13b6f4b305f45fb3691 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Thu, 14 Oct 2021 20:56:54 +0200
+Subject: [PATCH 46/84] serial: 8250_dw: Add quirk for starfive,jh7100-hsuart
+ too
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/tty/serial/8250/8250_dw.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/8250/8250_dw.c
++++ b/drivers/tty/serial/8250/8250_dw.c
+@@ -414,7 +414,8 @@ static void dw8250_quirks(struct uart_po
+               }
+               if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
+                       p->serial_out = dw8250_serial_out38x;
+-              if (of_device_is_compatible(np, "starfive,jh7100-uart"))
++              if (of_device_is_compatible(np, "starfive,jh7100-hsuart") ||
++                              of_device_is_compatible(np, "starfive,jh7100-uart"))
+                       p->set_termios = dw8250_do_set_termios;
+ 
+       } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
+@@ -698,6 +699,7 @@ static const struct of_device_id dw8250_
+       { .compatible = "cavium,octeon-3860-uart" },
+       { .compatible = "marvell,armada-38x-uart" },
+       { .compatible = "renesas,rzn1-uart" },
++      { .compatible = "starfive,jh7100-hsuart" },
+       { .compatible = "starfive,jh7100-uart" },
+       { /* Sentinel */ }
+ };

diff --git a/target/linux/visionfive/patches-5.15/0047-dt-bindings-hwmon-add-starfive-jh7100-temp-bindings.patch b/target/linux/visionfive/patches-5.15/0047-dt-bindings-hwmon-add-starfive-jh7100-temp-bindings.patch
new file mode 100644 (file)
index 0000000..51d5642
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0047-dt-bindings-hwmon-add-starfive-jh7100-temp-bindings.patch
@@ -0,0 +1,91 @@
+From d67e8695d1092d4818f6925984056f6c4f998538 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 6 Jun 2021 22:15:22 +0200
+Subject: [PATCH 47/84] dt-bindings: hwmon: add starfive,jh7100-temp bindings
+
+Add bindings for the temperature sensor on the StarFive JH7100 SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+Reviewed-by: Rob Herring <robh@kernel.org>
+---
+ .../bindings/hwmon/starfive,jh7100-temp.yaml  | 74 +++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/hwmon/starfive,jh7100-temp.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/hwmon/starfive,jh7100-temp.yaml
+@@ -0,0 +1,74 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/hwmon/starfive,jh7100-temp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7100 Temperature Sensor
++
++maintainers:
++  - Emil Renner Berthing <kernel@esmil.dk>
++
++description: |
++  StarFive Technology Co. JH7100 embedded temperature sensor
++
++properties:
++  compatible:
++    enum:
++      - starfive,jh7100-temp
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    minItems: 2
++    maxItems: 2
++
++  clock-names:
++    items:
++      - const: "sense"
++      - const: "bus"
++
++  '#thermal-sensor-cells':
++    const: 0
++
++  interrupts:
++    maxItems: 1
++
++  resets:
++    minItems: 2
++    maxItems: 2
++
++  reset-names:
++    items:
++      - const: "sense"
++      - const: "bus"
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - interrupts
++  - resets
++  - reset-names
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/starfive-jh7100.h>
++    #include <dt-bindings/reset/starfive-jh7100.h>
++
++    tmon: tmon@124a0000 {
++        compatible = "starfive,jh7100-temp";
++        reg = <0x124a0000 0x10000>;
++        clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
++                 <&clkgen JH7100_CLK_TEMP_APB>;
++        clock-names = "sense", "bus";
++        #thermal-sensor-cells = <0>;
++        interrupts = <122>;
++        resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
++                 <&rstgen JH7100_RSTN_TEMP_APB>;
++        reset-names = "sense", "bus";
++    };

diff --git a/target/linux/visionfive/patches-5.15/0048-hwmon-sfctemp-Add-StarFive-JH7100-temperature-sensor.patch b/target/linux/visionfive/patches-5.15/0048-hwmon-sfctemp-Add-StarFive-JH7100-temperature-sensor.patch
new file mode 100644 (file)
index 0000000..d2816a2
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0048-hwmon-sfctemp-Add-StarFive-JH7100-temperature-sensor.patch
@@ -0,0 +1,464 @@
+From b93b606bb1f4b33c08ebd469ec36fe029000caf5 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 6 Jun 2021 22:31:18 +0200
+Subject: [PATCH 48/84] hwmon: (sfctemp) Add StarFive JH7100 temperature sensor
+
+Register definitions and conversion constants based on sfctemp driver by
+Samin in the StarFive 5.10 kernel.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
+---
+ Documentation/hwmon/index.rst   |   1 +
+ Documentation/hwmon/sfctemp.rst |  32 +++
+ MAINTAINERS                     |   8 +
+ drivers/hwmon/Kconfig           |  10 +
+ drivers/hwmon/Makefile          |   1 +
+ drivers/hwmon/sfctemp.c         | 349 ++++++++++++++++++++++++++++++++
+ 6 files changed, 401 insertions(+)
+ create mode 100644 Documentation/hwmon/sfctemp.rst
+ create mode 100644 drivers/hwmon/sfctemp.c
+
+--- a/Documentation/hwmon/index.rst
++++ b/Documentation/hwmon/index.rst
+@@ -166,6 +166,7 @@ Hardware Monitoring Kernel Drivers
+    sch5627
+    sch5636
+    scpi-hwmon
++   sfctemp
+    sht15
+    sht21
+    sht3x
+--- /dev/null
++++ b/Documentation/hwmon/sfctemp.rst
+@@ -0,0 +1,32 @@
++.. SPDX-License-Identifier: GPL-2.0
++
++Kernel driver sfctemp
++=====================
++
++Supported chips:
++ - StarFive JH7100
++
++Authors:
++ - Emil Renner Berthing <kernel@esmil.dk>
++
++Description
++-----------
++
++This driver adds support for reading the built-in temperature sensor on the
++JH7100 RISC-V SoC by StarFive Technology Co. Ltd.
++
++``sysfs`` interface
++-------------------
++
++The temperature sensor can be enabled, disabled and queried via the standard
++hwmon interface in sysfs under ``/sys/class/hwmon/hwmonX`` for some value of
++``X``:
++
++================ ==== =============================================
++Name             Perm Description
++================ ==== =============================================
++temp1_enable     RW   Enable or disable temperature sensor.
++                      Automatically enabled by the driver,
++                      but may be disabled to save power.
++temp1_input      RO   Temperature reading in milli-degrees Celsius.
++================ ==== =============================================
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -16942,6 +16942,14 @@ L:    netdev@vger.kernel.org
+ S:    Supported
+ F:    drivers/net/ethernet/sfc/
+ 
++SFCTEMP HWMON DRIVER
++M:    Emil Renner Berthing <kernel@esmil.dk>
++L:    linux-hwmon@vger.kernel.org
++S:    Maintained
++F:    Documentation/devicetree/bindings/hwmon/starfive,jh7100-temp.yaml
++F:    Documentation/hwmon/sfctemp.rst
++F:    drivers/hwmon/sfctemp.c
++
+ SFF/SFP/SFP+ MODULE SUPPORT
+ M:    Russell King <linux@armlinux.org.uk>
+ L:    netdev@vger.kernel.org
+--- a/drivers/hwmon/Kconfig
++++ b/drivers/hwmon/Kconfig
+@@ -1782,6 +1782,16 @@ config SENSORS_STTS751
+         This driver can also be built as a module. If so, the module
+         will be called stts751.
+ 
++config SENSORS_SFCTEMP
++      tristate "Starfive JH7100 temperature sensor"
++      depends on SOC_STARFIVE || COMPILE_TEST
++      help
++        If you say yes here you get support for temperature sensor
++        on the Starfive JH7100 SoC.
++
++        This driver can also be built as a module.  If so, the module
++        will be called sfctemp.
++
+ config SENSORS_SMM665
+       tristate "Summit Microelectronics SMM665"
+       depends on I2C
+--- a/drivers/hwmon/Makefile
++++ b/drivers/hwmon/Makefile
+@@ -168,6 +168,7 @@ obj-$(CONFIG_SENSORS_SBRMI)        += sbrmi.o
+ obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o
+ obj-$(CONFIG_SENSORS_SCH5627) += sch5627.o
+ obj-$(CONFIG_SENSORS_SCH5636) += sch5636.o
++obj-$(CONFIG_SENSORS_SFCTEMP) += sfctemp.o
+ obj-$(CONFIG_SENSORS_SL28CPLD)        += sl28cpld-hwmon.o
+ obj-$(CONFIG_SENSORS_SHT15)   += sht15.o
+ obj-$(CONFIG_SENSORS_SHT21)   += sht21.o
+--- /dev/null
++++ b/drivers/hwmon/sfctemp.c
+@@ -0,0 +1,349 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ * Copyright (C) 2021 Samin Guo <samin.guo@starfivetech.com>
++ */
++#include <linux/clk.h>
++#include <linux/completion.h>
++#include <linux/delay.h>
++#include <linux/hwmon.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++
++/*
++ * TempSensor reset. The RSTN can be de-asserted once the analog core has
++ * powered up. Trst(min 100ns)
++ * 0:reset  1:de-assert
++ */
++#define SFCTEMP_RSTN  BIT(0)
++
++/*
++ * TempSensor analog core power down. The analog core will be powered up
++ * Tpu(min 50us) after PD is de-asserted. RSTN should be held low until the
++ * analog core is powered up.
++ * 0:power up  1:power down
++ */
++#define SFCTEMP_PD    BIT(1)
++
++/*
++ * TempSensor start conversion enable.
++ * 0:disable  1:enable
++ */
++#define SFCTEMP_RUN   BIT(2)
++
++/*
++ * TempSensor conversion value output.
++ * Temp(C)=DOUT*Y/4094 - K
++ */
++#define SFCTEMP_DOUT_POS      16
++#define SFCTEMP_DOUT_MSK      GENMASK(27, 16)
++
++/* DOUT to Celcius conversion constants */
++#define SFCTEMP_Y1000 237500L
++#define SFCTEMP_Z     4094L
++#define SFCTEMP_K1000 81100L
++
++struct sfctemp {
++      /* serialize access to hardware register and enabled below */
++      struct mutex lock;
++      struct completion conversion_done;
++      void __iomem *regs;
++      struct clk *clk_sense;
++      struct clk *clk_bus;
++      struct reset_control *rst_sense;
++      struct reset_control *rst_bus;
++      bool enabled;
++};
++
++static irqreturn_t sfctemp_isr(int irq, void *data)
++{
++      struct sfctemp *sfctemp = data;
++
++      complete(&sfctemp->conversion_done);
++      return IRQ_HANDLED;
++}
++
++static void sfctemp_power_up(struct sfctemp *sfctemp)
++{
++      /* make sure we're powered down first */
++      writel(SFCTEMP_PD, sfctemp->regs);
++      udelay(1);
++
++      writel(0, sfctemp->regs);
++      /* wait t_pu(50us) + t_rst(100ns) */
++      usleep_range(60, 200);
++
++      /* de-assert reset */
++      writel(SFCTEMP_RSTN, sfctemp->regs);
++      udelay(1); /* wait t_su(500ps) */
++}
++
++static void sfctemp_power_down(struct sfctemp *sfctemp)
++{
++      writel(SFCTEMP_PD, sfctemp->regs);
++}
++
++static void sfctemp_run_single(struct sfctemp *sfctemp)
++{
++      writel(SFCTEMP_RSTN | SFCTEMP_RUN, sfctemp->regs);
++      udelay(1);
++      writel(SFCTEMP_RSTN, sfctemp->regs);
++}
++
++static int sfctemp_enable(struct sfctemp *sfctemp)
++{
++      int ret = 0;
++
++      mutex_lock(&sfctemp->lock);
++      if (sfctemp->enabled)
++              goto done;
++
++      ret = clk_prepare_enable(sfctemp->clk_bus);
++      if (ret)
++              goto err;
++      ret = reset_control_deassert(sfctemp->rst_bus);
++      if (ret)
++              goto err_disable_bus;
++
++      ret = clk_prepare_enable(sfctemp->clk_sense);
++      if (ret)
++              goto err_assert_bus;
++      ret = reset_control_deassert(sfctemp->rst_sense);
++      if (ret)
++              goto err_disable_sense;
++
++      sfctemp_power_up(sfctemp);
++      sfctemp->enabled = true;
++done:
++      mutex_unlock(&sfctemp->lock);
++      return ret;
++
++err_disable_sense:
++      clk_disable_unprepare(sfctemp->clk_sense);
++err_assert_bus:
++      reset_control_assert(sfctemp->rst_bus);
++err_disable_bus:
++      clk_disable_unprepare(sfctemp->clk_bus);
++err:
++      mutex_unlock(&sfctemp->lock);
++      return ret;
++}
++
++static int sfctemp_disable(struct sfctemp *sfctemp)
++{
++      mutex_lock(&sfctemp->lock);
++      if (!sfctemp->enabled)
++              goto done;
++
++      sfctemp_power_down(sfctemp);
++      reset_control_assert(sfctemp->rst_sense);
++      clk_disable_unprepare(sfctemp->clk_sense);
++      reset_control_assert(sfctemp->rst_bus);
++      clk_disable_unprepare(sfctemp->clk_bus);
++      sfctemp->enabled = false;
++done:
++      mutex_unlock(&sfctemp->lock);
++      return 0;
++}
++
++static void sfctemp_disable_action(void *data)
++{
++      sfctemp_disable(data);
++}
++
++static int sfctemp_convert(struct sfctemp *sfctemp, long *val)
++{
++      int ret;
++
++      mutex_lock(&sfctemp->lock);
++      if (!sfctemp->enabled) {
++              ret = -ENODATA;
++              goto out;
++      }
++
++      sfctemp_run_single(sfctemp);
++
++      ret = wait_for_completion_interruptible_timeout(&sfctemp->conversion_done,
++                                                      msecs_to_jiffies(10));
++      if (ret <= 0) {
++              if (ret == 0)
++                      ret = -ETIMEDOUT;
++              goto out;
++      }
++
++      /* calculate temperature in milli Celcius */
++      *val = (long)((readl(sfctemp->regs) & SFCTEMP_DOUT_MSK) >> SFCTEMP_DOUT_POS)
++              * SFCTEMP_Y1000 / SFCTEMP_Z - SFCTEMP_K1000;
++
++      ret = 0;
++out:
++      mutex_unlock(&sfctemp->lock);
++      return ret;
++}
++
++static umode_t sfctemp_is_visible(const void *data, enum hwmon_sensor_types type,
++                                u32 attr, int channel)
++{
++      switch (type) {
++      case hwmon_temp:
++              switch (attr) {
++              case hwmon_temp_enable:
++                      return 0644;
++              case hwmon_temp_input:
++                      return 0444;
++              }
++              return 0;
++      default:
++              return 0;
++      }
++}
++
++static int sfctemp_read(struct device *dev, enum hwmon_sensor_types type,
++                      u32 attr, int channel, long *val)
++{
++      struct sfctemp *sfctemp = dev_get_drvdata(dev);
++
++      switch (type) {
++      case hwmon_temp:
++              switch (attr) {
++              case hwmon_temp_enable:
++                      *val = sfctemp->enabled;
++                      return 0;
++              case hwmon_temp_input:
++                      return sfctemp_convert(sfctemp, val);
++              }
++              return -EINVAL;
++      default:
++              return -EINVAL;
++      }
++}
++
++static int sfctemp_write(struct device *dev, enum hwmon_sensor_types type,
++                       u32 attr, int channel, long val)
++{
++      struct sfctemp *sfctemp = dev_get_drvdata(dev);
++
++      switch (type) {
++      case hwmon_temp:
++              switch (attr) {
++              case hwmon_temp_enable:
++                      if (val == 0)
++                              return sfctemp_disable(sfctemp);
++                      if (val == 1)
++                              return sfctemp_enable(sfctemp);
++                      break;
++              }
++              return -EINVAL;
++      default:
++              return -EINVAL;
++      }
++}
++
++static const struct hwmon_channel_info *sfctemp_info[] = {
++      HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
++      HWMON_CHANNEL_INFO(temp, HWMON_T_ENABLE | HWMON_T_INPUT),
++      NULL
++};
++
++static const struct hwmon_ops sfctemp_hwmon_ops = {
++      .is_visible = sfctemp_is_visible,
++      .read = sfctemp_read,
++      .write = sfctemp_write,
++};
++
++static const struct hwmon_chip_info sfctemp_chip_info = {
++      .ops = &sfctemp_hwmon_ops,
++      .info = sfctemp_info,
++};
++
++static int sfctemp_probe(struct platform_device *pdev)
++{
++      struct device *dev = &pdev->dev;
++      struct device *hwmon_dev;
++      struct sfctemp *sfctemp;
++      int ret;
++
++      sfctemp = devm_kzalloc(dev, sizeof(*sfctemp), GFP_KERNEL);
++      if (!sfctemp)
++              return -ENOMEM;
++
++      dev_set_drvdata(dev, sfctemp);
++      mutex_init(&sfctemp->lock);
++      init_completion(&sfctemp->conversion_done);
++
++      sfctemp->regs = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(sfctemp->regs))
++              return PTR_ERR(sfctemp->regs);
++
++      sfctemp->clk_sense = devm_clk_get(dev, "sense");
++      if (IS_ERR(sfctemp->clk_sense))
++              return dev_err_probe(dev, PTR_ERR(sfctemp->clk_sense),
++                                   "error getting sense clock\n");
++
++      sfctemp->clk_bus = devm_clk_get(dev, "bus");
++      if (IS_ERR(sfctemp->clk_bus))
++              return dev_err_probe(dev, PTR_ERR(sfctemp->clk_bus),
++                                   "error getting bus clock\n");
++
++      sfctemp->rst_sense = devm_reset_control_get_exclusive(dev, "sense");
++      if (IS_ERR(sfctemp->rst_sense))
++              return dev_err_probe(dev, PTR_ERR(sfctemp->rst_sense),
++                                   "error getting sense reset\n");
++
++      sfctemp->rst_bus = devm_reset_control_get_exclusive(dev, "bus");
++      if (IS_ERR(sfctemp->rst_bus))
++              return dev_err_probe(dev, PTR_ERR(sfctemp->rst_bus),
++                                   "error getting busreset\n");
++
++      ret = reset_control_assert(sfctemp->rst_sense);
++      if (ret)
++              return dev_err_probe(dev, ret, "error asserting sense reset\n");
++
++      ret = reset_control_assert(sfctemp->rst_bus);
++      if (ret)
++              return dev_err_probe(dev, ret, "error asserting bus reset\n");
++
++      ret = platform_get_irq(pdev, 0);
++      if (ret < 0)
++              return ret;
++
++      ret = devm_request_irq(dev, ret, sfctemp_isr, 0, pdev->name, sfctemp);
++      if (ret)
++              return dev_err_probe(dev, ret, "error requesting irq\n");
++
++      ret = devm_add_action(dev, sfctemp_disable_action, sfctemp);
++      if (ret)
++              return ret;
++
++      ret = sfctemp_enable(sfctemp);
++      if (ret)
++              return dev_err_probe(dev, ret, "error enabling temperature sensor: %d\n", ret);
++
++      hwmon_dev = devm_hwmon_device_register_with_info(dev, pdev->name, sfctemp,
++                                                       &sfctemp_chip_info, NULL);
++      return PTR_ERR_OR_ZERO(hwmon_dev);
++}
++
++static const struct of_device_id sfctemp_of_match[] = {
++      { .compatible = "starfive,jh7100-temp" },
++      { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, sfctemp_of_match);
++
++static struct platform_driver sfctemp_driver = {
++      .probe  = sfctemp_probe,
++      .driver = {
++              .name = "sfctemp",
++              .of_match_table = sfctemp_of_match,
++      },
++};
++module_platform_driver(sfctemp_driver);
++
++MODULE_AUTHOR("Emil Renner Berthing");
++MODULE_DESCRIPTION("StarFive JH7100 temperature sensor driver");
++MODULE_LICENSE("GPL");

diff --git a/target/linux/visionfive/patches-5.15/0049-watchdog-Add-StarFive-SI5-watchdog-driver.patch b/target/linux/visionfive/patches-5.15/0049-watchdog-Add-StarFive-SI5-watchdog-driver.patch
new file mode 100644 (file)
index 0000000..50b677a
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0049-watchdog-Add-StarFive-SI5-watchdog-driver.patch
@@ -0,0 +1,823 @@
+From d1e24cd90dd323835084e0d0e5392b279b47e5db Mon Sep 17 00:00:00 2001
+From: Samin Guo <samin.guo@starfivetech.com>
+Date: Wed, 17 Nov 2021 11:06:25 +0800
+Subject: [PATCH 49/84] watchdog: Add StarFive SI5 watchdog driver
+
+Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
+Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
+---
+ drivers/watchdog/Kconfig        |   9 +
+ drivers/watchdog/Makefile       |   3 +
+ drivers/watchdog/starfive-wdt.c | 776 ++++++++++++++++++++++++++++++++
+ 3 files changed, 788 insertions(+)
+ create mode 100644 drivers/watchdog/starfive-wdt.c
+
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -2008,6 +2008,15 @@ config UML_WATCHDOG
+       tristate "UML watchdog"
+       depends on UML || COMPILE_TEST
+ 
++# RISCV Architecture
++
++config STARFIVE_WATCHDOG
++      tristate "StarFive Watchdog support"
++      depends on RISCV
++      select WATCHDOG_CORE
++      help
++        Say Y here to support the starfive Si5 watchdog.
++
+ #
+ # ISA-based Watchdog Cards
+ #
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -203,6 +203,9 @@ obj-$(CONFIG_WATCHDOG_SUN4V)               += sun4v_w
+ # Xen
+ obj-$(CONFIG_XEN_WDT) += xen_wdt.o
+ 
++# RISCV Architecture
++obj-$(CONFIG_STARFIVE_WATCHDOG) += starfive-wdt.o
++
+ # Architecture Independent
+ obj-$(CONFIG_BD957XMUF_WATCHDOG) += bd9576_wdt.o
+ obj-$(CONFIG_DA9052_WATCHDOG) += da9052_wdt.o
+--- /dev/null
++++ b/drivers/watchdog/starfive-wdt.c
+@@ -0,0 +1,776 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Watchdog driver for the StarFive JH7100 SoC
++ *
++ * Copyright (C) 2021 Samin Guo <samin.guo@starfivetech.com>
++ * Copyright (C) 2021 Walker Chen <walker.chen@starfivetech.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/mfd/syscon.h>
++#include <linux/io.h>
++#include <linux/interrupt.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/timer.h>
++#include <linux/uaccess.h>
++#include <linux/watchdog.h>
++
++/* JH7100 WatchDog register define */
++#define JH7100_WDGINTSTAUS    0x000
++#define JH7100_WDOGCONTROL    0x104   /* Watchdog Control Register R/W */
++#define JH7100_WDOGLOAD               0x108   /* The initial value to be loaded */
++                              /* into the counter and is also used */
++                              /* as the reload value. R/W */
++#define JH7100_WDOGEN         0x110   /* Watchdog enable Register */
++#define JH7100_WDOGRELOAD     0x114   /* Write this register to reload preset */
++                              /* value to counter. (Write 0 or 1 are both ok) */
++#define JH7100_WDOGVALUE      0x118   /* Watchdog Value Register RO */
++#define JH7100_WDOGINTCLR     0x120   /* Watchdog Clear Interrupt Register WO */
++#define JH7100_WDOGINTMSK     0x124   /* Watchdog Interrupt Mask Register */
++#define JH7100_WDOGLOCK               0x13c   /* Watchdog Lock Register  R/W */
++
++#define JH7100_UNLOCK_KEY     0x378f0765
++#define JH7100_RESEN_SHIFT    0
++#define JH7100_EN_SHIFT               0
++#define JH7100_INTCLR_AVA_SHIFT       1       /* Watchdog can clear interrupt when this bit is 0 */
++
++/* WDOGCONTROL */
++#define WDOG_INT_EN   0x0
++#define WDOG_RESET_EN 0x1
++
++/* WDOGLOCK */
++#define WDOG_LOCKED           BIT(0)
++
++#define SI5_WATCHDOG_INTCLR   0x1
++#define SI5_WATCHDOG_ENABLE   0x1
++#define SI5_WATCHDOG_ATBOOT   0x0
++#define SI5_WATCHDOG_MAXCNT   0xffffffff
++
++#define SI5_WATCHDOG_DEFAULT_TIME     (15)
++
++static bool nowayout = WATCHDOG_NOWAYOUT;
++static int tmr_margin;
++static int tmr_atboot = SI5_WATCHDOG_ATBOOT;
++static int soft_noboot;
++
++module_param(tmr_margin, int, 0);
++module_param(tmr_atboot, int, 0);
++module_param(nowayout, bool, 0);
++module_param(soft_noboot, int, 0);
++
++MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
++              __MODULE_STRING(SI5_WATCHDOG_DEFAULT_TIME) ")");
++MODULE_PARM_DESC(tmr_atboot,
++              "Watchdog is started at boot time if set to 1, default="
++                      __MODULE_STRING(SI5_WATCHDOG_ATBOOT));
++MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
++                      __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
++MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
++
++struct si5_wdt_variant_t {
++      u32 unlock_key;
++      u8 enrst_shift;
++      u8 en_shift;
++      u8 intclr_check;
++      u8 intclr_ava_shift;
++};
++
++struct si5_wdt_variant {
++      u32 control;
++      u32 load;
++      u32 enable;
++      u32 reload;
++      u32 value;
++      u32 int_clr;
++      u32 int_mask;
++      u32 unlock;
++      struct si5_wdt_variant_t *variant;
++};
++
++struct stf_si5_wdt {
++      u64 freq;
++      struct device *dev;
++      struct watchdog_device wdt_device;
++      struct clk *core_clk;
++      struct clk *apb_clk;
++      struct reset_control *rst_wdtimer_apb;
++      struct reset_control *rst_wdt;
++
++      const struct si5_wdt_variant *drv_data;
++      u32 count;      /*count of timeout*/
++      u32 reload;     /*restore the count*/
++      void __iomem *base;
++      spinlock_t lock;
++};
++
++#ifdef CONFIG_OF
++static struct si5_wdt_variant_t jh7100_variant = {
++        .unlock_key = JH7100_UNLOCK_KEY,
++        .enrst_shift = JH7100_RESEN_SHIFT,
++        .en_shift = JH7100_EN_SHIFT,
++      .intclr_check = 1,
++      .intclr_ava_shift = JH7100_INTCLR_AVA_SHIFT,
++};
++
++static const struct si5_wdt_variant drv_data_jh7100 = {
++      .control = JH7100_WDOGCONTROL,
++      .load = JH7100_WDOGLOAD,
++      .enable = JH7100_WDOGEN,
++      .reload = JH7100_WDOGRELOAD,
++      .value = JH7100_WDOGVALUE,
++      .int_clr = JH7100_WDOGINTCLR,
++      .int_mask = JH7100_WDOGINTMSK,
++      .unlock = JH7100_WDOGLOCK,
++      .variant =  &jh7100_variant,
++};
++
++static const struct of_device_id starfive_wdt_match[] = {
++      { .compatible = "starfive,si5-wdt",
++        .data = &drv_data_jh7100 },
++      {},
++};
++MODULE_DEVICE_TABLE(of, starfive_wdt_match);
++#endif
++
++static const struct platform_device_id si5wdt_ids[] = {
++      {
++              .name = "starfive-si5-wdt",
++              .driver_data = (unsigned long)&drv_data_jh7100,
++      },
++      {}
++};
++MODULE_DEVICE_TABLE(platform, si5wdt_ids);
++
++static int si5wdt_get_clock_rate(struct stf_si5_wdt *wdt)
++{
++      int ret;
++      u32 freq;
++
++      if (!IS_ERR(wdt->core_clk)) {
++              wdt->freq = clk_get_rate(wdt->core_clk);
++              return 0;
++      }
++
++      /* Next we try to get clock-frequency from dts.*/
++      ret = of_property_read_u32(wdt->dev->of_node, "clock-frequency", &freq);
++      if (!ret) {
++              wdt->freq = (u64)freq;
++              return 0;
++      }
++      else
++              dev_err(wdt->dev, "get rate failed, need clock-frequency define in dts.\n");
++
++      return -ENOENT;
++}
++
++static int si5wdt_enable_clock(struct stf_si5_wdt *wdt)
++{
++      struct reset_control_bulk_data resets[] = {
++                { .id = "wdtimer_apb" },
++                { .id = "wdt" },
++        };
++      int ret;
++
++      ret = devm_reset_control_bulk_get_exclusive(wdt->dev, ARRAY_SIZE(resets), resets);
++      if (ret) {
++              printk(KERN_INFO "faied to get watchdog reset controls\n");
++              return ret;
++      }
++
++      wdt->rst_wdtimer_apb = resets[0].rstc;
++      wdt->rst_wdt = resets[1].rstc;
++
++      wdt->apb_clk = devm_clk_get(wdt->dev, "wdtimer_apb");
++      if (!IS_ERR(wdt->apb_clk)) {
++              ret = clk_prepare_enable(wdt->apb_clk);
++              if(ret)
++                      dev_warn(wdt->dev, "enable core_clk error.\n");
++      }
++
++      wdt->core_clk = devm_clk_get(wdt->dev, "wdt_coreclk");
++      if (!IS_ERR(wdt->core_clk)) {
++              ret = clk_prepare_enable(wdt->core_clk);
++              if(ret)
++                      dev_warn(wdt->dev, "enable apb_clk error.\n");
++      }
++
++      ret = reset_control_assert(wdt->rst_wdtimer_apb);
++      if (ret) {
++              printk(KERN_INFO "failed to assert wdtimer_apb\n");
++              return ret;
++      }
++
++      ret = reset_control_assert(wdt->rst_wdt);
++      if (ret) {
++              printk(KERN_INFO "failed to assert wdt\n");
++              return ret;
++      }
++
++      ret = reset_control_deassert(wdt->rst_wdtimer_apb);
++      if (ret) {
++              printk(KERN_INFO "failed to deassert wdtimer_apb, ret=%d\n", ret);
++              return ret;
++      }
++
++      ret = reset_control_deassert(wdt->rst_wdt);
++      if (ret) {
++              printk(KERN_INFO "failed to deassert wdt\n");
++              return ret;
++      }
++
++      return 0;
++}
++
++static __maybe_unused
++u32 si5wdt_sec_to_ticks(struct stf_si5_wdt *wdt, u32 sec)
++{
++      return sec * wdt->freq;
++}
++
++static __maybe_unused
++u32 si5wdt_ticks_to_sec(struct stf_si5_wdt *wdt, u32 ticks)
++{
++      return DIV_ROUND_CLOSEST(ticks, wdt->freq);
++}
++
++/*
++ * Write unlock-key to unlock. Write other value to lock. When lock bit is 1,
++ * external accesses to other watchdog registers are ignored.
++ */
++static int si5wdt_is_locked(struct stf_si5_wdt *wdt)
++{
++      u32 val;
++
++      val = readl(wdt->base + wdt->drv_data->unlock);
++      return !!(val & WDOG_LOCKED);
++}
++
++static void si5wdt_unlock(struct stf_si5_wdt *wdt)
++{
++      if (si5wdt_is_locked(wdt))
++              writel(wdt->drv_data->variant->unlock_key,
++                      wdt->base + wdt->drv_data->unlock);
++}
++
++static void si5wdt_lock(struct stf_si5_wdt *wdt)
++{
++      if (!si5wdt_is_locked(wdt))
++              writel(~wdt->drv_data->variant->unlock_key,
++                      wdt->base + wdt->drv_data->unlock);
++}
++
++static int __maybe_unused si5wdt_is_running(struct stf_si5_wdt *wdt)
++{
++      u32 val;
++
++      si5wdt_unlock(wdt);
++      val = readl(wdt->base + wdt->drv_data->enable);
++      si5wdt_lock(wdt);
++
++      return !!(val & SI5_WATCHDOG_ENABLE <<
++              wdt->drv_data->variant->en_shift);
++}
++
++static inline void si5wdt_int_enable(struct stf_si5_wdt *wdt)
++{
++      u32 val;
++
++      if (wdt->drv_data->int_mask) {
++              val = readl(wdt->base + wdt->drv_data->int_mask);
++              val &= ~(1<<0);
++              writel(val, wdt->base + wdt->drv_data->int_mask);
++      }
++}
++
++static inline void si5wdt_int_disable(struct stf_si5_wdt *wdt)
++{
++      u32 val;
++
++      if (wdt->drv_data->int_mask) {
++              val = readl(wdt->base + wdt->drv_data->int_mask);
++              val |= (1<<0);
++              writel(val, wdt->base + wdt->drv_data->int_mask);
++      }
++}
++
++static void si5wdt_enable_reset(struct stf_si5_wdt *wdt)
++{
++      u32 val;
++
++      val = readl(wdt->base + wdt->drv_data->control);
++      val |= WDOG_RESET_EN << wdt->drv_data->variant->enrst_shift;
++      /* enable wdog interrupt to reset */
++      writel(val, wdt->base + wdt->drv_data->control);
++}
++
++static void si5wdt_disable_reset(struct stf_si5_wdt *wdt)
++{
++      u32 val;
++
++      val = readl(wdt->base + wdt->drv_data->control);
++      val &= ~(WDOG_RESET_EN << wdt->drv_data->variant->enrst_shift);
++      /*disable wdog interrupt to reset*/
++      writel(val, wdt->base + wdt->drv_data->control);
++}
++
++static void si5wdt_int_clr(struct stf_si5_wdt *wdt)
++{
++      void __iomem *addr;
++      u8 clr_check;
++      u8 clr_ava_shift;
++
++      addr = wdt->base + wdt->drv_data->int_clr;
++      clr_ava_shift = wdt->drv_data->variant->intclr_ava_shift;
++      clr_check = wdt->drv_data->variant->intclr_check;
++      if (clr_check) {
++              /* waiting interrupt can be to clearing */
++              do {
++
++              } while (readl(addr) & BIT(clr_ava_shift));
++      }
++
++      writel(SI5_WATCHDOG_INTCLR, addr);
++}
++
++static inline void si5wdt_set_count(struct stf_si5_wdt *wdt, u32 val)
++{
++      writel(val, wdt->base + wdt->drv_data->load);
++}
++
++static inline u32 si5wdt_get_count(struct stf_si5_wdt *wdt)
++{
++      return readl(wdt->base + wdt->drv_data->value);
++}
++
++static inline void si5wdt_enable(struct stf_si5_wdt *wdt)
++{
++      u32 val;
++
++      val = readl(wdt->base + wdt->drv_data->enable);
++      val |= SI5_WATCHDOG_ENABLE << wdt->drv_data->variant->en_shift;
++      writel(val, wdt->base + wdt->drv_data->enable);
++}
++
++static inline void si5wdt_disable(struct stf_si5_wdt *wdt)
++{
++      u32 val;
++
++      val = readl(wdt->base + wdt->drv_data->enable);
++      val &= ~(SI5_WATCHDOG_ENABLE << wdt->drv_data->variant->en_shift);
++      writel(val, wdt->base + wdt->drv_data->enable);
++}
++
++static inline void
++si5wdt_set_relod_count(struct stf_si5_wdt *wdt, u32 count)
++{
++      writel(count, wdt->base + wdt->drv_data->load);
++      if (wdt->drv_data->reload)
++              writel(0x1, wdt->base + wdt->drv_data->reload);
++
++}
++
++static int si5wdt_mask_and_disable_reset(struct stf_si5_wdt *wdt, bool mask)
++{
++      si5wdt_unlock(wdt);
++
++      if (mask)
++              si5wdt_disable_reset(wdt);
++      else
++              si5wdt_enable_reset(wdt);
++
++      si5wdt_lock(wdt);
++
++      return 0;
++}
++
++static unsigned int si5wdt_max_timeout(struct stf_si5_wdt *wdt)
++{
++      return DIV_ROUND_UP(SI5_WATCHDOG_MAXCNT, wdt->freq) - 1;
++}
++
++static unsigned int si5wdt_get_timeleft(struct watchdog_device *wdd)
++{
++      struct stf_si5_wdt *wdt = watchdog_get_drvdata(wdd);
++      u32 count;
++
++      si5wdt_unlock(wdt);
++      count = si5wdt_get_count(wdt);
++      si5wdt_lock(wdt);
++
++      return si5wdt_ticks_to_sec(wdt, count);
++}
++
++static int si5wdt_keepalive(struct watchdog_device *wdd)
++{
++      struct stf_si5_wdt *wdt = watchdog_get_drvdata(wdd);
++
++      spin_lock(&wdt->lock);
++
++      si5wdt_unlock(wdt);
++      si5wdt_set_relod_count(wdt, wdt->count);
++      si5wdt_lock(wdt);
++
++      spin_unlock(&wdt->lock);
++
++      return 0;
++}
++
++static irqreturn_t si5wdt_interrupt_handler(int irq, void *data)
++{
++      /*
++       * We don't clear the IRQ status. It's supposed to be done by the
++       * following ping operations.
++       */
++
++      return IRQ_HANDLED;
++}
++
++static int si5wdt_stop(struct watchdog_device *wdd)
++{
++      struct stf_si5_wdt *wdt = watchdog_get_drvdata(wdd);
++
++      spin_lock(&wdt->lock);
++
++      si5wdt_unlock(wdt);
++      si5wdt_int_disable(wdt);
++      si5wdt_int_clr(wdt);
++      si5wdt_disable(wdt);
++      si5wdt_lock(wdt);
++
++      spin_unlock(&wdt->lock);
++
++      return 0;
++}
++
++static int si5wdt_start(struct watchdog_device *wdd)
++{
++      struct stf_si5_wdt *wdt = watchdog_get_drvdata(wdd);
++
++      spin_lock(&wdt->lock);
++
++      si5wdt_unlock(wdt);
++
++      if (soft_noboot)
++              si5wdt_disable_reset(wdt);
++      else
++              si5wdt_enable_reset(wdt);
++
++      si5wdt_set_count(wdt, wdt->count);
++      si5wdt_int_enable(wdt);
++      si5wdt_enable(wdt);
++
++      si5wdt_lock(wdt);
++
++      spin_unlock(&wdt->lock);
++
++      return 0;
++}
++
++static int si5wdt_restart(struct watchdog_device *wdd, unsigned long action,
++                            void *data)
++{
++      struct stf_si5_wdt *wdt = watchdog_get_drvdata(wdd);
++
++      si5wdt_unlock(wdt);
++      /* disable watchdog, to be safe  */
++      si5wdt_disable(wdt);
++
++      if (soft_noboot)
++              si5wdt_disable_reset(wdt);
++      else
++              si5wdt_enable_reset(wdt);
++
++      /* put initial values into count and data */
++      si5wdt_set_count(wdt, wdt->count);
++
++      /* set the watchdog to go and reset... */
++      si5wdt_int_clr(wdt);
++      si5wdt_int_enable(wdt);
++      si5wdt_enable(wdt);
++
++      /* wait for reset to assert... */
++      mdelay(500);
++
++      si5wdt_lock(wdt);
++
++      return 0;
++}
++
++static int si5wdt_set_timeout(struct watchdog_device *wdd,
++                                  unsigned int timeout)
++{
++      struct stf_si5_wdt *wdt = watchdog_get_drvdata(wdd);
++
++      unsigned long freq = wdt->freq;
++      unsigned int count;
++
++      if (timeout < 1)
++              return -EINVAL;
++
++      count = timeout * freq;
++
++      if (count > SI5_WATCHDOG_MAXCNT) {
++              dev_warn(wdt->dev, "timeout %d too big,use the MAX-timeout set.\n",
++                              timeout);
++              timeout = si5wdt_max_timeout(wdt);
++              count = timeout * freq;
++      }
++
++      dev_info(wdt->dev, "Heartbeat: timeout=%d, count=%d (%08x)\n",
++              timeout, count, count);
++
++      si5wdt_unlock(wdt);
++      si5wdt_disable(wdt);
++      si5wdt_set_relod_count(wdt, count);
++      si5wdt_enable(wdt);
++      si5wdt_lock(wdt);
++
++      wdt->count = count;
++      wdd->timeout = timeout;
++
++      return 0;
++}
++
++#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
++
++static const struct watchdog_info si5_wdt_ident = {
++      .options          = OPTIONS,
++      .firmware_version = 0,
++      .identity         = "StarFive SI5 Watchdog",
++};
++
++static const struct watchdog_ops si5wdt_ops = {
++      .owner = THIS_MODULE,
++      .start = si5wdt_start,
++      .stop = si5wdt_stop,
++      .ping = si5wdt_keepalive,
++      .set_timeout = si5wdt_set_timeout,
++      .restart = si5wdt_restart,
++      .get_timeleft = si5wdt_get_timeleft,
++};
++
++static const struct watchdog_device starfive_si5_wdd = {
++      .info = &si5_wdt_ident,
++      .ops = &si5wdt_ops,
++      .timeout = SI5_WATCHDOG_DEFAULT_TIME,
++};
++
++static inline const struct si5_wdt_variant *
++si5_get_wdt_drv_data(struct platform_device *pdev)
++{
++      const struct si5_wdt_variant *variant;
++
++      variant = of_device_get_match_data(&pdev->dev);
++      if (!variant) {
++              /* Device matched by platform_device_id */
++              variant = (struct si5_wdt_variant *)
++                         platform_get_device_id(pdev)->driver_data;
++      }
++
++      return variant;
++}
++
++static int si5wdt_probe(struct platform_device *pdev)
++{
++      struct device *dev = &pdev->dev;
++      struct stf_si5_wdt *wdt;
++      struct resource *wdt_irq;
++      int started = 0;
++      int ret;
++
++      wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
++      if (!wdt)
++              return -ENOMEM;
++
++      wdt->dev = dev;
++      spin_lock_init(&wdt->lock);
++      wdt->wdt_device = starfive_si5_wdd;
++
++      wdt->drv_data = si5_get_wdt_drv_data(pdev);
++
++      wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++      if (wdt_irq == NULL) {
++              dev_err(dev, "no irq resource specified\n");
++              ret = -ENOENT;
++              goto err;
++      }
++
++      /* get the memory region for the watchdog timer */
++      wdt->base = devm_platform_ioremap_resource(pdev, 0);
++      if (IS_ERR(wdt->base)) {
++              ret = PTR_ERR(wdt->base);
++              goto err;
++      }
++
++      ret = si5wdt_enable_clock(wdt);
++      if (ret)
++              dev_warn(wdt->dev, "get & enable clk err\n");
++
++      si5wdt_get_clock_rate(wdt);
++
++      wdt->wdt_device.min_timeout = 1;
++      wdt->wdt_device.max_timeout = si5wdt_max_timeout(wdt);
++
++      watchdog_set_drvdata(&wdt->wdt_device, wdt);
++
++      /*
++       * see if we can actually set the requested timer margin,
++       * and if not, try the default value.
++       */
++      watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
++
++      ret = si5wdt_set_timeout(&wdt->wdt_device,
++                                      wdt->wdt_device.timeout);
++      if (ret) {
++              dev_info(dev, "tmr_margin value out of range, default %d used\n",
++                               SI5_WATCHDOG_DEFAULT_TIME);
++              si5wdt_set_timeout(&wdt->wdt_device,
++                              SI5_WATCHDOG_DEFAULT_TIME);
++      }
++
++      ret = devm_request_irq(dev, wdt_irq->start, si5wdt_interrupt_handler, 0,
++                              pdev->name, pdev);
++      if (ret != 0) {
++              dev_err(dev, "failed to install irq (%d)\n", ret);
++              goto err;
++      }
++
++      watchdog_set_nowayout(&wdt->wdt_device, nowayout);
++      watchdog_set_restart_priority(&wdt->wdt_device, 128);
++
++      wdt->wdt_device.parent = dev;
++
++      ret = watchdog_register_device(&wdt->wdt_device);
++      if (ret)
++              goto err;
++
++      ret = si5wdt_mask_and_disable_reset(wdt, false);
++      if (ret < 0)
++              goto err_unregister;
++
++      if (tmr_atboot && started == 0) {
++              dev_info(dev, "starting watchdog timer\n");
++              si5wdt_start(&wdt->wdt_device);
++      } else if (!tmr_atboot) {
++
++              /*
++               *if we're not enabling the watchdog, then ensure it is
++               * disabled if it has been left running from the bootloader
++               * or other source.
++               */
++              si5wdt_stop(&wdt->wdt_device);
++      }
++
++      platform_set_drvdata(pdev, wdt);
++
++      return 0;
++
++ err_unregister:
++      watchdog_unregister_device(&wdt->wdt_device);
++
++ err:
++      return ret;
++}
++
++static int si5wdt_remove(struct platform_device *dev)
++{
++      int ret;
++      struct stf_si5_wdt *wdt = platform_get_drvdata(dev);
++
++      ret = si5wdt_mask_and_disable_reset(wdt, true);
++      if (ret < 0)
++              return ret;
++
++      watchdog_unregister_device(&wdt->wdt_device);
++
++      clk_disable_unprepare(wdt->core_clk);
++
++      return 0;
++}
++
++static void si5wdt_shutdown(struct platform_device *dev)
++{
++      struct stf_si5_wdt *wdt = platform_get_drvdata(dev);
++
++      si5wdt_mask_and_disable_reset(wdt, true);
++
++      si5wdt_stop(&wdt->wdt_device);
++
++}
++
++#ifdef CONFIG_PM_SLEEP
++
++static int si5wdt_suspend(struct device *dev)
++{
++      int ret;
++      struct stf_si5_wdt *wdt = dev_get_drvdata(dev);
++
++      si5wdt_unlock(wdt);
++
++      /* Save watchdog state, and turn it off. */
++      wdt->reload = si5wdt_get_count(wdt);
++
++      ret = si5wdt_mask_and_disable_reset(wdt, true);
++      if (ret < 0)
++              return ret;
++
++      /* Note that WTCNT doesn't need to be saved. */
++      si5wdt_stop(&wdt->wdt_device);
++
++      si5wdt_lock(wdt);
++
++      return 0;
++}
++
++static int si5wdt_resume(struct device *dev)
++{
++      int ret;
++      struct stf_si5_wdt *wdt = dev_get_drvdata(dev);
++
++      si5wdt_unlock(wdt);
++
++      /* Restore watchdog state. */
++      si5wdt_set_relod_count(wdt, wdt->reload);
++
++      ret = si5wdt_mask_and_disable_reset(wdt, false);
++      if (ret < 0)
++              return ret;
++
++      si5wdt_lock(wdt);
++
++      dev_info(dev, "watchdog resume\n")
++
++      return 0;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static SIMPLE_DEV_PM_OPS(si5wdt_pm_ops, si5wdt_suspend,
++                      si5wdt_resume);
++
++static struct platform_driver starfive_si5wdt_driver = {
++      .probe          = si5wdt_probe,
++      .remove         = si5wdt_remove,
++      .shutdown       = si5wdt_shutdown,
++      .id_table       = si5wdt_ids,
++      .driver         = {
++              .name   = "starfive-si5-wdt",
++              .pm     = &si5wdt_pm_ops,
++              .of_match_table = of_match_ptr(starfive_wdt_match),
++      },
++};
++
++module_platform_driver(starfive_si5wdt_driver);
++
++MODULE_AUTHOR("samin.guo <samin.guo@starfivetech.com>");
++MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
++MODULE_DESCRIPTION("StarFive SI5 Watchdog Device Driver");
++MODULE_LICENSE("GPL v2");

diff --git a/target/linux/visionfive/patches-5.15/0050-drivers-hw_random-Add-StarFive-JH7100-Random-Number-.patch b/target/linux/visionfive/patches-5.15/0050-drivers-hw_random-Add-StarFive-JH7100-Random-Number-.patch
new file mode 100644 (file)
index 0000000..bcca48c
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0050-drivers-hw_random-Add-StarFive-JH7100-Random-Number-.patch
@@ -0,0 +1,476 @@
+From d6818e0f00111b49f435e07261674b7c9134ff71 Mon Sep 17 00:00:00 2001
+From: Huan Feng <huan.feng@starfivetech.com>
+Date: Fri, 8 Jan 2021 03:35:42 +0800
+Subject: [PATCH 50/84] drivers/hw_random: Add StarFive JH7100 Random Number
+ Generator driver
+
+---
+ drivers/char/hw_random/Kconfig            |  13 ++
+ drivers/char/hw_random/Makefile           |   1 +
+ drivers/char/hw_random/starfive-vic-rng.c | 256 ++++++++++++++++++++++
+ drivers/char/hw_random/starfive-vic-rng.h | 167 ++++++++++++++
+ 4 files changed, 437 insertions(+)
+ create mode 100644 drivers/char/hw_random/starfive-vic-rng.c
+ create mode 100644 drivers/char/hw_random/starfive-vic-rng.h
+
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -335,6 +335,19 @@ config HW_RANDOM_POWERNV
+ 
+         If unsure, say Y.
+ 
++config HW_RANDOM_STARFIVE_VIC
++      tristate "Starfive VIC Random Number Generator support"
++      depends on HW_RANDOM && (SOC_STARFIVE || COMPILE_TEST)
++      default SOC_STARFIVE
++      help
++        This driver provides kernel-side support for the Random Number
++        Generator hardware found on Starfive VIC SoC.
++
++        To compile this driver as a module, choose M here: the
++        module will be called starfive-vic-rng.
++
++        If unsure, say Y.
++
+ config HW_RANDOM_HISI
+       tristate "Hisilicon Random Number Generator support"
+       depends on HW_RANDOM && ARCH_HISI
+--- a/drivers/char/hw_random/Makefile
++++ b/drivers/char/hw_random/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon
+ obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
+ obj-$(CONFIG_HW_RANDOM_PSERIES) += pseries-rng.o
+ obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o
++obj-$(CONFIG_HW_RANDOM_STARFIVE_VIC)  += starfive-vic-rng.o
+ obj-$(CONFIG_HW_RANDOM_HISI)  += hisi-rng.o
+ obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
+ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
+--- /dev/null
++++ b/drivers/char/hw_random/starfive-vic-rng.c
+@@ -0,0 +1,256 @@
++/*
++ ******************************************************************************
++ * @file  starfive-vic-rng.c
++ * @author  StarFive Technology
++ * @version  V1.0
++ * @date  08/13/2020
++ * @brief
++ ******************************************************************************
++ * @copy
++ *
++ * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
++ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
++ * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
++ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
++ * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
++ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
++ *
++ * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
++ */
++#include <linux/err.h>
++#include <linux/kernel.h>
++#include <linux/hw_random.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/random.h>
++
++#include "starfive-vic-rng.h"
++
++#define to_vic_rng(p) container_of(p, struct vic_rng, rng)
++
++struct vic_rng {
++      struct device   *dev;
++      void __iomem    *base;
++      struct hwrng    rng;
++};
++
++static inline void vic_wait_till_idle(struct vic_rng *hrng)
++{
++      while(readl(hrng->base + VIC_STAT) & VIC_STAT_BUSY)
++              ;
++}
++
++static inline void vic_rng_irq_mask_clear(struct vic_rng *hrng)
++{
++      // clear register: ISTAT
++      u32 data = readl(hrng->base + VIC_ISTAT);
++      writel(data, hrng->base + VIC_ISTAT);
++      writel(0, hrng->base + VIC_ALARM);
++}
++
++static int vic_trng_cmd(struct vic_rng *hrng, u32 cmd) {
++      int res = 0;
++      // wait till idle
++      vic_wait_till_idle(hrng);
++      switch (cmd) {
++      case VIC_CTRL_CMD_NOP:
++      case VIC_CTRL_CMD_GEN_NOISE:
++      case VIC_CTRL_CMD_GEN_NONCE:
++      case VIC_CTRL_CMD_CREATE_STATE:
++      case VIC_CTRL_CMD_RENEW_STATE:
++      case VIC_CTRL_CMD_REFRESH_ADDIN:
++      case VIC_CTRL_CMD_GEN_RANDOM:
++      case VIC_CTRL_CMD_ADVANCE_STATE:
++      case VIC_CTRL_CMD_KAT:
++      case VIC_CTRL_CMD_ZEROIZE:
++              writel(cmd, hrng->base + VIC_CTRL);
++              break;
++      default:
++              res = -1;
++              break;
++      }
++
++      return res;
++}
++
++static int vic_rng_init(struct hwrng *rng)
++{
++      struct vic_rng *hrng = to_vic_rng(rng);
++
++      // wait till idle
++
++      // clear register: ISTAT
++      vic_rng_irq_mask_clear(hrng);
++
++      // set mission mode
++      writel(VIC_SMODE_SECURE_EN(1), hrng->base + VIC_SMODE);
++
++      vic_trng_cmd(hrng, VIC_CTRL_CMD_GEN_NOISE);
++      vic_wait_till_idle(hrng);
++
++      // set interrupt
++      writel(VIC_IE_ALL, hrng->base + VIC_IE);
++
++      // zeroize
++      vic_trng_cmd(hrng, VIC_CTRL_CMD_ZEROIZE);
++
++      vic_wait_till_idle(hrng);
++
++      return 0;
++}
++
++static irqreturn_t vic_rng_irq(int irq, void *priv)
++{
++      u32 status, val;
++      struct vic_rng *hrng = (struct vic_rng *)priv;
++
++      /*
++       * clearing the interrupt will also clear the error register
++       * read error and status before clearing
++       */
++      status = readl(hrng->base + VIC_ISTAT);
++
++      if (status & VIC_ISTAT_ALARMS) {
++              writel(VIC_ISTAT_ALARMS, hrng->base + VIC_ISTAT);
++              val = readl(hrng->base + VIC_ALARM);
++              if (val & VIC_ALARM_ILLEGAL_CMD_SEQ) {
++                      writel(VIC_ALARM_ILLEGAL_CMD_SEQ, hrng->base + VIC_ALARM);
++                      //dev_info(hrng->dev, "ILLEGAL CMD SEQ: LAST_CMD=0x%x\r\n",
++                      //VIC_STAT_LAST_CMD(readl(hrng->base + VIC_STAT)));
++              } else {
++                      dev_info(hrng->dev, "Failed test: %x\r\n", val);
++              }
++      }
++
++      if (status & VIC_ISTAT_ZEROIZE) {
++              writel(VIC_ISTAT_ZEROIZE, hrng->base + VIC_ISTAT);
++              //dev_info(hrng->dev, "zeroized\r\n");
++      }
++
++      if (status & VIC_ISTAT_KAT_COMPLETE) {
++              writel(VIC_ISTAT_KAT_COMPLETE, hrng->base + VIC_ISTAT);
++              //dev_info(hrng->dev, "kat_completed\r\n");
++      }
++
++      if (status & VIC_ISTAT_NOISE_RDY) {
++              writel(VIC_ISTAT_NOISE_RDY, hrng->base + VIC_ISTAT);
++              //dev_info(hrng->dev, "noise_rdy\r\n");
++      }
++
++      if (status & VIC_ISTAT_DONE) {
++              writel(VIC_ISTAT_DONE, hrng->base + VIC_ISTAT);
++              //dev_info(hrng->dev, "done\r\n");
++              /*
++              if (VIC_STAT_LAST_CMD(readl(hrng->base + VIC_STAT)) ==
++                  VIC_CTRL_CMD_GEN_RANDOM) {
++                      dev_info(hrng->dev, "Need Update Buffer\r\n");
++              }
++              */
++      }
++      vic_rng_irq_mask_clear(hrng);
++
++      return IRQ_HANDLED;
++}
++
++static void vic_rng_cleanup(struct hwrng *rng)
++{
++      struct vic_rng *hrng = to_vic_rng(rng);
++
++      writel(0, hrng->base + VIC_CTRL);
++}
++
++static int vic_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++      struct vic_rng *hrng = to_vic_rng(rng);
++
++      vic_trng_cmd(hrng, VIC_CTRL_CMD_ZEROIZE);
++      vic_trng_cmd(hrng, VIC_CTRL_CMD_GEN_NOISE);
++      vic_trng_cmd(hrng, VIC_CTRL_CMD_CREATE_STATE);
++
++      vic_wait_till_idle(hrng);
++      max = min_t(size_t, max, (VIC_RAND_LEN * 4));
++
++      writel(0x0, hrng->base + VIC_MODE);
++      vic_trng_cmd(hrng, VIC_CTRL_CMD_GEN_RANDOM);
++
++      vic_wait_till_idle(hrng);
++      memcpy_fromio(buf, hrng->base + VIC_RAND0, max);
++      vic_trng_cmd(hrng, VIC_CTRL_CMD_ZEROIZE);
++
++      vic_wait_till_idle(hrng);
++      return max;
++}
++
++static int vic_rng_probe(struct platform_device *pdev)
++{
++      int ret;
++      int irq;
++      struct vic_rng *rng;
++      struct resource *res;
++
++      rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
++      if (!rng){
++              return -ENOMEM;
++      }
++
++      platform_set_drvdata(pdev, rng);
++
++      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      rng->base = devm_ioremap_resource(&pdev->dev, res);
++      if (IS_ERR(rng->base)){
++              return PTR_ERR(rng->base);
++      }
++
++      irq = platform_get_irq(pdev, 0);
++      if (irq <= 0) {
++              dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
++              return irq;
++      }
++
++      ret = devm_request_irq(&pdev->dev, irq, vic_rng_irq, 0, pdev->name,
++                              (void *)rng);
++      if (ret) {
++              dev_err(&pdev->dev, "Can't get interrupt working.\n");
++              return ret;
++      }
++
++      rng->rng.name = pdev->name;
++      rng->rng.init = vic_rng_init;
++      rng->rng.cleanup = vic_rng_cleanup;
++      rng->rng.read = vic_rng_read;
++
++      rng->dev = &pdev->dev;
++
++      ret = devm_hwrng_register(&pdev->dev, &rng->rng);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to register hwrng\n");
++              return ret;
++      }
++
++      dev_info(&pdev->dev, "Initialized\n");
++
++      return 0;
++}
++
++static const struct of_device_id vic_rng_dt_ids[] = {
++      { .compatible = "starfive,vic-rng" },
++      { }
++};
++MODULE_DEVICE_TABLE(of, vic_rng_dt_ids);
++
++static struct platform_driver vic_rng_driver = {
++      .probe          = vic_rng_probe,
++      .driver         = {
++              .name           = "vic-rng",
++              .of_match_table = of_match_ptr(vic_rng_dt_ids),
++      },
++};
++
++module_platform_driver(vic_rng_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Huan Feng <huan.feng@starfivetech.com>");
++MODULE_DESCRIPTION("Starfive VIC random number generator driver");
+--- /dev/null
++++ b/drivers/char/hw_random/starfive-vic-rng.h
+@@ -0,0 +1,167 @@
++/*
++ ******************************************************************************
++ * @file  starfive-vic-rng.h
++ * @author  StarFive Technology
++ * @version  V1.0
++ * @date  08/13/2020
++ * @brief
++ ******************************************************************************
++ * @copy
++ *
++ * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
++ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
++ * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
++ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
++ * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
++ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
++ *
++ * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
++ */
++
++#define VIC_CTRL              0x00
++#define VIC_MODE              0x04
++#define VIC_SMODE             0x08
++#define VIC_STAT              0x0C
++#define VIC_IE                        0x10
++#define VIC_ISTAT             0x14
++#define VIC_ALARM             0x18
++#define VIC_BUILD_ID          0x1C
++#define VIC_FEATURES          0x20
++#define VIC_RAND0             0x24
++#define VIC_NPA_DATA0         0x34
++#define VIC_SEED0             0x74
++#define VIC_IA_RDATA          0xA4
++#define VIC_IA_WDATA          0xA8
++#define VIC_IA_ADDR           0xAC
++#define VIC_IA_CMD            0xB0
++
++/* CTRL */
++#define VIC_CTRL_CMD_NOP              0
++#define VIC_CTRL_CMD_GEN_NOISE                1
++#define VIC_CTRL_CMD_GEN_NONCE                2
++#define VIC_CTRL_CMD_CREATE_STATE     3
++#define VIC_CTRL_CMD_RENEW_STATE      4
++#define VIC_CTRL_CMD_REFRESH_ADDIN    5
++#define VIC_CTRL_CMD_GEN_RANDOM               6
++#define VIC_CTRL_CMD_ADVANCE_STATE    7
++#define VIC_CTRL_CMD_KAT              8
++#define VIC_CTRL_CMD_ZEROIZE          15
++
++/* MODE */
++#define _VIC_MODE_ADDIN_PRESENT               4
++#define _VIC_MODE_PRED_RESIST         3
++#define _VIC_MODE_KAT_SEL             2
++#define _VIC_MODE_KAT_VEC             1
++#define _VIC_MODE_SEC_ALG             0
++
++#define VIC_MODE_ADDIN_PRESENT        (1UL << _VIC_MODE_ADDIN_PRESENT)
++#define VIC_MODE_PRED_RESIST  (1UL << _VIC_MODE_PRED_RESIST)
++#define VIC_MODE_KAT_SEL      (1UL << _VIC_MODE_KAT_SEL)
++#define VIC_MODE_KAT_VEC      (1UL << _VIC_MODE_KAT_VEC)
++#define VIC_MODE_SEC_ALG      (1UL << _VIC_MODE_SEC_ALG)
++
++/* SMODE */
++#define _VIC_SMODE_MAX_REJECTS        2
++#define _VIC_SMODE_SECURE_EN  1
++#define _VIC_SMODE_NONCE      0
++
++#define VIC_SMODE_MAX_REJECTS(x)      ((x) << _VIC_SMODE_MAX_REJECTS)
++#define VIC_SMODE_SECURE_EN(x)                ((x) << _VIC_SMODE_SECURE_EN)
++#define VIC_SMODE_NONCE                       (1UL << _VIC_SMODE_NONCE)
++
++/* STAT */
++#define _VIC_STAT_BUSY                31
++#define _VIC_STAT_DRBG_STATE  7
++#define _VIC_STAT_SECURE      6
++#define _VIC_STAT_NONCE_MODE  5
++#define _VIC_STAT_SEC_ALG     4
++#define _VIC_STAT_LAST_CMD    0
++
++#define VIC_STAT_BUSY         (1UL << _VIC_STAT_BUSY)
++#define VIC_STAT_DRBG_STATE   (1UL << _VIC_STAT_DRBG_STATE)
++#define VIC_STAT_SECURE               (1UL << _VIC_STAT_SECURE)
++#define VIC_STAT_NONCE_MODE   (1UL << _VIC_STAT_NONCE_MODE)
++#define VIC_STAT_SEC_ALG      (1UL << _VIC_STAT_SEC_ALG)
++#define VIC_STAT_LAST_CMD(x)  (((x) >> _VIC_STAT_LAST_CMD) & 0xF)
++
++/* IE */
++#define _VIC_IE_GLBL          31
++#define _VIC_IE_DONE          4
++#define _VIC_IE_ALARMS                3
++#define _VIC_IE_NOISE_RDY     2
++#define _VIC_IE_KAT_COMPLETE  1
++#define _VIC_IE_ZEROIZE               0
++
++#define VIC_IE_GLBL           (1UL << _VIC_IE_GLBL)
++#define VIC_IE_DONE           (1UL << _VIC_IE_DONE)
++#define VIC_IE_ALARMS         (1UL << _VIC_IE_ALARMS)
++#define VIC_IE_NOISE_RDY      (1UL << _VIC_IE_NOISE_RDY)
++#define VIC_IE_KAT_COMPLETE   (1UL << _VIC_IE_KAT_COMPLETE)
++#define VIC_IE_ZEROIZE                (1UL << _VIC_IE_ZEROIZE)
++#define VIC_IE_ALL            (VIC_IE_GLBL | VIC_IE_DONE | VIC_IE_ALARMS | \
++                               VIC_IE_NOISE_RDY | VIC_IE_KAT_COMPLETE | VIC_IE_ZEROIZE)
++
++/* ISTAT */
++#define _VIC_ISTAT_DONE               4
++#define _VIC_ISTAT_ALARMS     3
++#define _VIC_ISTAT_NOISE_RDY  2
++#define _VIC_ISTAT_KAT_COMPLETE       1
++#define _VIC_ISTAT_ZEROIZE    0
++
++#define VIC_ISTAT_DONE                (1UL << _VIC_ISTAT_DONE)
++#define VIC_ISTAT_ALARMS      (1UL << _VIC_ISTAT_ALARMS)
++#define VIC_ISTAT_NOISE_RDY   (1UL << _VIC_ISTAT_NOISE_RDY)
++#define VIC_ISTAT_KAT_COMPLETE        (1UL << _VIC_ISTAT_KAT_COMPLETE)
++#define VIC_ISTAT_ZEROIZE     (1UL << _VIC_ISTAT_ZEROIZE)
++
++/* ALARMS */
++#define VIC_ALARM_ILLEGAL_CMD_SEQ                     (1UL << 4)
++#define VIC_ALARM_FAILED_TEST_ID_OK                   0
++#define VIC_ALARM_FAILED_TEST_ID_KAT_STAT             1
++#define VIC_ALARM_FAILED_TEST_ID_KAT                  2
++#define VIC_ALARM_FAILED_TEST_ID_MONOBIT              3
++#define VIC_ALARM_FAILED_TEST_ID_RUN                  4
++#define VIC_ALARM_FAILED_TEST_ID_LONGRUN              5
++#define VIC_ALARM_FAILED_TEST_ID_AUTOCORRELATION      6
++#define VIC_ALARM_FAILED_TEST_ID_POKER                        7
++#define VIC_ALARM_FAILED_TEST_ID_REPETITION_COUNT     8
++#define VIC_ALARM_FAILED_TEST_ID_ADAPATIVE_PROPORTION 9
++
++/* BUILD_ID */
++#define VIC_BUILD_ID_STEPPING(x)              (((x) >> 28) & 0xF)
++#define VIC_BUILD_ID_EPN(x)                   ((x) & 0xFFFF)
++
++/* FEATURES */
++#define VIC_FEATURES_AES_256(x)                       (((x) >> 9) & 1)
++#define VIC_FEATURES_EXTRA_PS_PRESENT(x)      (((x) >> 8) & 1)
++#define VIC_FEATURES_DIAG_LEVEL_NS(x)         (((x) >> 7) & 1)
++#define VIC_FEATURES_DIAG_LEVEL_CLP800(x)     (((x) >> 4) & 7)
++#define VIC_FEATURES_DIAG_LEVEL_ST_HLT(x)     (((x) >> 1) & 7)
++#define VIC_FEATURES_SECURE_RST_STATE(x)      ((x) & 1)
++
++/* IA_CMD */
++#define VIC_IA_CMD_GO                 (1UL << 31)
++#define VIC_IA_CMD_WR                 (1)
++
++#define _VIC_SMODE_MAX_REJECTS_MASK   255UL
++#define _VIC_SMODE_SECURE_EN_MASK     1UL
++#define _VIC_SMODE_NONCE_MASK         1UL
++#define _VIC_MODE_SEC_ALG_MASK                1UL
++#define _VIC_MODE_ADDIN_PRESENT_MASK  1UL
++#define _VIC_MODE_PRED_RESIST_MASK    1UL
++
++#define VIC_SMODE_SET_MAX_REJECTS(y, x)       (((y) & ~(_VIC_SMODE_MAX_REJECTS_MASK << _VIC_SMODE_MAX_REJECTS)) | ((x) << _VIC_SMODE_MAX_REJECTS))
++#define VIC_SMODE_SET_SECURE_EN(y, x) (((y) & ~(_VIC_SMODE_SECURE_EN_MASK   << _VIC_SMODE_SECURE_EN))   | ((x) << _VIC_SMODE_SECURE_EN))
++#define VIC_SMODE_SET_NONCE(y, x)     (((y) & ~(_VIC_SMODE_NONCE_MASK       << _VIC_SMODE_NONCE))       | ((x) << _VIC_SMODE_NONCE))
++#define VIC_SMODE_GET_MAX_REJECTS(x)  (((x) >> _VIC_SMODE_MAX_REJECTS) & _VIC_SMODE_MAX_REJECTS_MASK)
++#define VIC_SMODE_GET_SECURE_EN(x)    (((x) >> _VIC_SMODE_SECURE_EN)   & _VIC_SMODE_SECURE_EN_MASK)
++#define VIC_SMODE_GET_NONCE(x)                (((x) >> _VIC_SMODE_NONCE)       & _VIC_SMODE_NONCE_MASK)
++
++#define VIC_MODE_SET_SEC_ALG(y, x)    (((y) & ~(_VIC_MODE_SEC_ALG_MASK       << _VIC_MODE_SEC_ALG))   | ((x) << _VIC_MODE_SEC_ALG))
++#define VIC_MODE_SET_PRED_RESIST(y, x)        (((y) & ~(_VIC_MODE_PRED_RESIST_MASK   << _VIC_MODE_PRED_RESIST))    | ((x) << _VIC_MODE_PRED_RESIST))
++#define VIC_MODE_SET_ADDIN_PRESENT(y, x) (((y) & ~(_VIC_MODE_ADDIN_PRESENT_MASK << _VIC_MODE_ADDIN_PRESENT))  | ((x) << _VIC_MODE_ADDIN_PRESENT))
++#define VIC_MODE_GET_SEC_ALG(x)               (((x) >> _VIC_MODE_SEC_ALG)       & _VIC_MODE_SEC_ALG_MASK)
++#define VIC_MODE_GET_PRED_RESIST(x)   (((x) >> _VIC_MODE_PRED_RESIST)   & _VIC_MODE_PRED_RESIST_MASK)
++#define VIC_MODE_GET_ADDIN_PRESENT(x) (((x) >> _VIC_MODE_ADDIN_PRESENT) & _VIC_MODE_ADDIN_PRESENT_MASK)
++
++#define VIC_RAND_LEN 4

diff --git a/target/linux/visionfive/patches-5.15/0050-riscv-dts-starfive-Group-tuples-in-interrupt-propert.patch b/target/linux/visionfive/patches-5.15/0050-riscv-dts-starfive-Group-tuples-in-interrupt-propert.patch
deleted file mode 100644 (file)
index a5c68d1..0000000
--- a/target/linux/visionfive/patches-5.15/0050-riscv-dts-starfive-Group-tuples-in-interrupt-propert.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 2a88bea858254873c675dcd1bbafefd5e17a387d Mon Sep 17 00:00:00 2001
-From: Geert Uytterhoeven <geert@linux-m68k.org>
-Date: Thu, 25 Nov 2021 14:21:18 +0100
-Subject: [PATCH 50/56] riscv: dts: starfive: Group tuples in interrupt
- properties
-
-To improve human readability and enable automatic validation, the tuples
-in the various properties containing interrupt specifiers should be
-grouped.
-
-Fix this by grouping the tuples of "interrupts-extended" properties
-using angle brackets.
-
-Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
----
- arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
-index 69f22f9aad9d..d74fc29af642 100644
---- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
-+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
-@@ -106,15 +106,15 @@ soc {
-               clint: clint@2000000 {
-                       compatible = "starfive,jh7100-clint", "sifive,clint0";
-                       reg = <0x0 0x2000000 0x0 0x10000>;
--                      interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
--                                             &cpu1_intc 3 &cpu1_intc 7>;
-+                      interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
-+                                            <&cpu1_intc 3>, <&cpu1_intc 7>;
-               };
- 
-               plic: interrupt-controller@c000000 {
-                       compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
-                       reg = <0x0 0xc000000 0x0 0x4000000>;
--                      interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
--                                             &cpu1_intc 11 &cpu1_intc 9>;
-+                      interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
-+                                            <&cpu1_intc 11>, <&cpu1_intc 9>;
-                       interrupt-controller;
-                       #address-cells = <0>;
-                       #interrupt-cells = <1>;
--- 
-2.30.2
-

diff --git a/target/linux/visionfive/patches-5.15/0051-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch b/target/linux/visionfive/patches-5.15/0051-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch
deleted file mode 100644 (file)
index 263a355..0000000
--- a/target/linux/visionfive/patches-5.15/0051-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From ce4d791aa84319736eb4827b615f250f1be59274 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sat, 20 Nov 2021 17:13:22 +0100
-Subject: [PATCH 51/56] RISC-V: Add StarFive JH7100 audio clock node
-
-Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
-SoC.
-
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
-index d74fc29af642..31b4ccc282e0 100644
---- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
-+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
-@@ -121,6 +121,16 @@ plic: interrupt-controller@c000000 {
-                       riscv,ndev = <127>;
-               };
- 
-+              audclk: clock-controller@10480000 {
-+                      compatible = "starfive,jh7100-audclk";
-+                      reg = <0x0 0x10480000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
-+                               <&clkgen JH7100_CLK_AUDIO_12288>,
-+                               <&clkgen JH7100_CLK_DOM7AHB_BUS>;
-+                      clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
-+                      #clock-cells = <1>;
-+              };
-+
-               clkgen: clock-controller@11800000 {
-                       compatible = "starfive,jh7100-clkgen";
-                       reg = <0x0 0x11800000 0x0 0x10000>;
--- 
-2.30.2
-

diff --git a/target/linux/visionfive/patches-5.15/0051-sifive-sifive_l2_cache-Add-sifive_l2_flush64_range-f.patch b/target/linux/visionfive/patches-5.15/0051-sifive-sifive_l2_cache-Add-sifive_l2_flush64_range-f.patch
new file mode 100644 (file)
index 0000000..80bd536
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0051-sifive-sifive_l2_cache-Add-sifive_l2_flush64_range-f.patch
@@ -0,0 +1,110 @@
+From 6e54d45c770d8ade51d13dd3474bce256cf40cc1 Mon Sep 17 00:00:00 2001
+From: Tom <support@vamrs.com>
+Date: Fri, 8 Jan 2021 02:54:51 +0800
+Subject: [PATCH 51/84] sifive/sifive_l2_cache: Add sifive_l2_flush64_range
+ function
+
+---
+ drivers/soc/sifive/Kconfig           | 15 ++++++++++
+ drivers/soc/sifive/sifive_l2_cache.c | 41 +++++++++++++++++++++++++++-
+ include/soc/sifive/sifive_l2_cache.h |  4 +++
+ 3 files changed, 59 insertions(+), 1 deletion(-)
+
+--- a/drivers/soc/sifive/Kconfig
++++ b/drivers/soc/sifive/Kconfig
+@@ -7,4 +7,19 @@ config SIFIVE_L2
+       help
+         Support for the L2 cache controller on SiFive platforms.
+ 
++config SIFIVE_L2_FLUSH
++      bool "Support Level 2 Cache Controller Flush operation of SiFive Soc"
++
++if SIFIVE_L2_FLUSH
++
++config SIFIVE_L2_FLUSH_START
++      hex "Level 2 Cache Flush operation start"
++      default 0x80000000
++
++config SIFIVE_L2_FLUSH_SIZE
++      hex "Level 2 Cache Flush operation size"
++      default 0x800000000
++
++endif # SIFIVE_L2_FLUSH
++
+ endif
+--- a/drivers/soc/sifive/sifive_l2_cache.c
++++ b/drivers/soc/sifive/sifive_l2_cache.c
+@@ -29,13 +29,17 @@
+ #define SIFIVE_L2_DATECCFAIL_HIGH 0x164
+ #define SIFIVE_L2_DATECCFAIL_COUNT 0x168
+ 
++#define SIFIVE_L2_FLUSH64 0x200
++
+ #define SIFIVE_L2_CONFIG 0x00
+ #define SIFIVE_L2_WAYENABLE 0x08
+ #define SIFIVE_L2_ECCINJECTERR 0x40
+ 
+ #define SIFIVE_L2_MAX_ECCINTR 4
+ 
+-static void __iomem *l2_base;
++#define SIFIVE_L2_FLUSH64_LINE_LEN 64
++
++static void __iomem *l2_base = NULL;
+ static int g_irq[SIFIVE_L2_MAX_ECCINTR];
+ static struct riscv_cacheinfo_ops l2_cache_ops;
+ 
+@@ -116,6 +120,41 @@ int unregister_sifive_l2_error_notifier(
+ }
+ EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
+ 
++#ifdef CONFIG_SIFIVE_L2_FLUSH
++void sifive_l2_flush64_range(unsigned long start, unsigned long len)
++{
++      unsigned long line;
++
++      if(!l2_base) {
++              pr_warn("L2CACHE: base addr invalid, skipping flush\n");
++              return;
++      }
++
++      /* TODO: if (len == 0), skipping flush or going on? */
++      if(!len) {
++              pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start);
++              return;
++      }
++
++      /* make sure the address is in the range */
++      if(start < CONFIG_SIFIVE_L2_FLUSH_START ||
++         (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START +
++                           CONFIG_SIFIVE_L2_FLUSH_SIZE)) {
++              pr_warn("L2CACHE: flush64 out of range: %lx(%lx), skip flush\n",
++                      start, len);
++              return;
++      }
++
++      mb();   /* sync */
++      for (line = start; line < start + len;
++           line += SIFIVE_L2_FLUSH64_LINE_LEN) {
++              writeq(line, l2_base + SIFIVE_L2_FLUSH64);
++              mb();
++      }
++}
++EXPORT_SYMBOL_GPL(sifive_l2_flush64_range);
++#endif
++
+ static int l2_largest_wayenabled(void)
+ {
+       return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
+--- a/include/soc/sifive/sifive_l2_cache.h
++++ b/include/soc/sifive/sifive_l2_cache.h
+@@ -7,6 +7,10 @@
+ #ifndef __SOC_SIFIVE_L2_CACHE_H
+ #define __SOC_SIFIVE_L2_CACHE_H
+ 
++#ifdef CONFIG_SIFIVE_L2_FLUSH
++extern void sifive_l2_flush64_range(unsigned long start, unsigned long len);
++#endif
++
+ extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
+ extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
+ 

diff --git a/target/linux/visionfive/patches-5.15/0052-RISC-V-Add-StarFive-JH7100-audio-reset-node.patch b/target/linux/visionfive/patches-5.15/0052-RISC-V-Add-StarFive-JH7100-audio-reset-node.patch
deleted file mode 100644 (file)
index ab8ea53..0000000
--- a/target/linux/visionfive/patches-5.15/0052-RISC-V-Add-StarFive-JH7100-audio-reset-node.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From ecaf4b0c2e3fdd0f909f848ef2f252b021dd4d60 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sat, 20 Nov 2021 21:33:08 +0100
-Subject: [PATCH 52/56] RISC-V: Add StarFive JH7100 audio reset node
-
-Add device tree node for the audio resets on the StarFive JH7100 RISC-V
-SoC.
-
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
-index 31b4ccc282e0..d76a67098620 100644
---- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
-+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
-@@ -131,6 +131,12 @@ audclk: clock-controller@10480000 {
-                       #clock-cells = <1>;
-               };
- 
-+              audrst: reset-controller@10490000 {
-+                      compatible = "starfive,jh7100-audrst";
-+                      reg = <0x0 0x10490000 0x0 0x10000>;
-+                      #reset-cells = <1>;
-+              };
-+
-               clkgen: clock-controller@11800000 {
-                       compatible = "starfive,jh7100-clkgen";
-                       reg = <0x0 0x11800000 0x0 0x10000>;
--- 
-2.30.2
-

diff --git a/target/linux/visionfive/patches-5.15/0052-sifive-sifive_l2_cache-Add-Starfive-support.patch b/target/linux/visionfive/patches-5.15/0052-sifive-sifive_l2_cache-Add-Starfive-support.patch
new file mode 100644 (file)
index 0000000..37a2fd8
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0052-sifive-sifive_l2_cache-Add-Starfive-support.patch
@@ -0,0 +1,19 @@
+From d06f6efc2ea564c27986b9f96d2a6f2eb5869363 Mon Sep 17 00:00:00 2001
+From: Tom <support@vamrs.com>
+Date: Mon, 15 Feb 2021 23:59:46 +0800
+Subject: [PATCH 52/84] sifive/sifive_l2_cache: Add Starfive support
+
+---
+ drivers/soc/sifive/sifive_l2_cache.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/soc/sifive/sifive_l2_cache.c
++++ b/drivers/soc/sifive/sifive_l2_cache.c
+@@ -103,6 +103,7 @@ static void l2_config_read(void)
+ static const struct of_device_id sifive_l2_ids[] = {
+       { .compatible = "sifive,fu540-c000-ccache" },
+       { .compatible = "sifive,fu740-c000-ccache" },
++      { .compatible = "starfive,ccache0" },
+       { /* end of table */ },
+ };
+ 

diff --git a/target/linux/visionfive/patches-5.15/0053-riscv-dts-Add-full-JH7100-Starlight-and-VisionFive-s.patch b/target/linux/visionfive/patches-5.15/0053-riscv-dts-Add-full-JH7100-Starlight-and-VisionFive-s.patch
deleted file mode 100644 (file)
index 2c3180e..0000000
--- a/target/linux/visionfive/patches-5.15/0053-riscv-dts-Add-full-JH7100-Starlight-and-VisionFive-s.patch
+++ /dev/null
@@ -1,1534 +0,0 @@
-From e712a44441571060b1b2ad011a1d76fe84fb1506 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sun, 31 Oct 2021 17:15:58 +0100
-Subject: [PATCH 53/56] riscv: dts: Add full JH7100, Starlight and VisionFive
- support
-
-Based on the device tree in https://github.com/starfive-tech/u-boot/
-with contributions from:
-yanhong.wang <yanhong.wang@starfivetech.com>
-Huan.Feng <huan.feng@starfivetech.com>
-ke.zhu <ke.zhu@starfivetech.com>
-yiming.li <yiming.li@starfivetech.com>
-jack.zhu <jack.zhu@starfivetech.com>
-Samin Guo <samin.guo@starfivetech.com>
-Chenjieqin <Jessica.Chen@starfivetech.com>
-bo.li <bo.li@starfivetech.com>
-
-Rearranged, cleanups, fixes, pins and resets added by Emil.
-Cleanups, fixes, clocks added by Geert.
-Cleanups and GPIO fixes from Drew.
-Thermal zone added by Stephen.
-PWM pins added by Jianlong.
-
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
-Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
-Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org>
-Signed-off-by: Drew Fustini <drew@beagleboard.org>
-Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
----
- arch/riscv/boot/dts/starfive/Makefile         |   2 +-
- .../starfive/jh7100-beaglev-starlight-a1.dts  |  24 +
- .../dts/starfive/jh7100-beaglev-starlight.dts | 154 +----
- .../boot/dts/starfive/jh7100-common.dtsi      | 586 ++++++++++++++++++
- .../jh7100-starfive-visionfive-v1.dts         |  32 +
- arch/riscv/boot/dts/starfive/jh7100.dtsi      | 559 +++++++++++++++++
- 6 files changed, 1208 insertions(+), 149 deletions(-)
- create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
- create mode 100644 arch/riscv/boot/dts/starfive/jh7100-common.dtsi
- create mode 100644 arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
-
-diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
-index 0ea1bc15ab30..058ea584aae4 100644
---- a/arch/riscv/boot/dts/starfive/Makefile
-+++ b/arch/riscv/boot/dts/starfive/Makefile
-@@ -1,2 +1,2 @@
- # SPDX-License-Identifier: GPL-2.0
--dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
-+dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight-a1.dtb jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
-diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
-new file mode 100644
-index 000000000000..d307e44590f3
---- /dev/null
-+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
-@@ -0,0 +1,24 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+/dts-v1/;
-+#include "jh7100-common.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+      model = "BeagleV Starlight Beta A1";
-+      compatible = "beagle,beaglev-starlight-jh7100-a1", "starfive,jh7100";
-+
-+      gpio-restart {
-+              compatible = "gpio-restart";
-+              gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
-+              priority = <224>;
-+      };
-+};
-+
-+&gpio {
-+      /* don't reset gpio mux for serial console and reset gpio */
-+      starfive,keep-gpiomux = <13 14 63>;
-+};
-diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
-index c9af67f7a0d2..ec42effa7a0e 100644
---- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
-+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
-@@ -1,164 +1,22 @@
- // SPDX-License-Identifier: GPL-2.0 OR MIT
- /*
-- * Copyright (C) 2021 StarFive Technology Co., Ltd.
-  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-  */
- 
- /dts-v1/;
--#include "jh7100.dtsi"
-+#include "jh7100-common.dtsi"
- #include <dt-bindings/gpio/gpio.h>
--#include <dt-bindings/leds/common.h>
--#include <dt-bindings/pinctrl/pinctrl-starfive.h>
- 
- / {
-       model = "BeagleV Starlight Beta";
-       compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
--
--      aliases {
--              serial0 = &uart3;
--      };
--
--      chosen {
--              stdout-path = "serial0:115200n8";
--      };
--
--      cpus {
--              timebase-frequency = <6250000>;
--      };
--
--      memory@80000000 {
--              device_type = "memory";
--              reg = <0x0 0x80000000 0x2 0x0>;
--      };
--
--      leds {
--              compatible = "gpio-leds";
--
--              led-ack {
--                      gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
--                      color = <LED_COLOR_ID_GREEN>;
--                      function = LED_FUNCTION_HEARTBEAT;
--                      linux,default-trigger = "heartbeat";
--                      label = "ack";
--              };
--      };
- };
- 
--&gpio {
--      i2c0_pins: i2c0-0 {
--              i2c-pins {
--                      pinmux = <GPIOMUX(62, GPO_LOW,
--                                GPO_I2C0_PAD_SCK_OEN,
--                                GPI_I2C0_PAD_SCK_IN)>,
--                               <GPIOMUX(61, GPO_LOW,
--                                GPO_I2C0_PAD_SDA_OEN,
--                                GPI_I2C0_PAD_SDA_IN)>;
--                      bias-disable; /* external pull-up */
--                      input-enable;
--                      input-schmitt-enable;
--              };
--      };
--
--      i2c1_pins: i2c1-0 {
--              i2c-pins {
--                      pinmux = <GPIOMUX(47, GPO_LOW,
--                                GPO_I2C1_PAD_SCK_OEN,
--                                GPI_I2C1_PAD_SCK_IN)>,
--                               <GPIOMUX(48, GPO_LOW,
--                                GPO_I2C1_PAD_SDA_OEN,
--                                GPI_I2C1_PAD_SDA_IN)>;
--                      bias-pull-up;
--                      input-enable;
--                      input-schmitt-enable;
--              };
--      };
--
--      i2c2_pins: i2c2-0 {
--              i2c-pins {
--                      pinmux = <GPIOMUX(60, GPO_LOW,
--                                GPO_I2C2_PAD_SCK_OEN,
--                                GPI_I2C2_PAD_SCK_IN)>,
--                               <GPIOMUX(59, GPO_LOW,
--                                GPO_I2C2_PAD_SDA_OEN,
--                                GPI_I2C2_PAD_SDA_IN)>;
--                      bias-disable; /* external pull-up */
--                      input-enable;
--                      input-schmitt-enable;
--              };
--      };
--
--      uart3_pins: uart3-0 {
--              rx-pins {
--                      pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
--                                GPI_UART3_PAD_SIN)>;
--                      bias-pull-up;
--                      drive-strength = <14>;
--                      input-enable;
--                      input-schmitt-enable;
--                      slew-rate = <0>;
--              };
--              tx-pins {
--                      pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
--                                GPO_ENABLE, GPI_NONE)>;
--                      bias-disable;
--                      drive-strength = <35>;
--                      input-disable;
--                      input-schmitt-disable;
--                      slew-rate = <0>;
--              };
--      };
-+&gmac {
-+      snps,reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
- };
- 
--&i2c0 {
--      clock-frequency = <100000>;
--      i2c-sda-hold-time-ns = <300>;
--      i2c-sda-falling-time-ns = <500>;
--      i2c-scl-falling-time-ns = <500>;
--      pinctrl-names = "default";
--      pinctrl-0 = <&i2c0_pins>;
--      status = "okay";
--
--      pmic@5e {
--              compatible = "ti,tps65086";
--              reg = <0x5e>;
--              gpio-controller;
--              #gpio-cells = <2>;
--
--              regulators {
--              };
--      };
--};
--
--&i2c1 {
--      clock-frequency = <400000>;
--      i2c-sda-hold-time-ns = <300>;
--      i2c-sda-falling-time-ns = <100>;
--      i2c-scl-falling-time-ns = <100>;
--      pinctrl-names = "default";
--      pinctrl-0 = <&i2c1_pins>;
--      status = "okay";
--};
--
--&i2c2 {
--      clock-frequency = <100000>;
--      i2c-sda-hold-time-ns = <300>;
--      i2c-sda-falling-time-ns = <500>;
--      i2c-scl-falling-time-ns = <500>;
--      pinctrl-names = "default";
--      pinctrl-0 = <&i2c2_pins>;
--      status = "okay";
--};
--
--&osc_sys {
--      clock-frequency = <25000000>;
--};
--
--&osc_aud {
--      clock-frequency = <27000000>;
--};
--
--&uart3 {
--      pinctrl-names = "default";
--      pinctrl-0 = <&uart3_pins>;
--      status = "okay";
-+&gpio {
-+      /* don't reset gpio mux for serial console on uart3 */
-+      starfive,keep-gpiomux = <13 14>;
- };
-diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
-new file mode 100644
-index 000000000000..2a5c4a4c0810
---- /dev/null
-+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
-@@ -0,0 +1,586 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+/dts-v1/;
-+#include "jh7100.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/pinctrl-starfive.h>
-+
-+/ {
-+      aliases {
-+              mshc0 = &sdio0;
-+              mshc1 = &sdio1;
-+              serial0 = &uart3;
-+              serial1 = &uart0;
-+      };
-+
-+      chosen {
-+              stdout-path = "serial0:115200n8";
-+      };
-+
-+      cpus {
-+              timebase-frequency = <6250000>;
-+      };
-+
-+      memory@80000000 {
-+              device_type = "memory";
-+              reg = <0x0 0x80000000 0x2 0x0>;
-+      };
-+
-+      leds {
-+              compatible = "gpio-leds";
-+
-+              led-ack {
-+                      gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
-+                      color = <LED_COLOR_ID_GREEN>;
-+                      function = LED_FUNCTION_HEARTBEAT;
-+                      linux,default-trigger = "heartbeat";
-+                      label = "ack";
-+              };
-+      };
-+
-+      reserved-memory {
-+              #address-cells = <2>;
-+              #size-cells = <2>;
-+              ranges;
-+
-+              linux,cma {
-+                      compatible = "shared-dma-pool";
-+                      reusable;
-+                      size = <0x0 0x28000000>;
-+                      alignment = <0x0 0x1000>;
-+                      alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
-+                      linux,cma-default;
-+              };
-+
-+              jpu_reserved: framebuffer@c9000000 {
-+                      reg = <0x0 0xc9000000 0x0 0x4000000>;
-+              };
-+
-+              nvdla_reserved: framebuffer@d0000000 {
-+                      no-map;
-+                      reg = <0x0 0xd0000000 0x0 0x28000000>;
-+              };
-+
-+              vin_reserved: framebuffer@f9000000 {
-+                      compatible = "shared-dma-pool";
-+                      no-map;
-+                      reg = <0x0 0xf9000000 0x0 0x1000000>;
-+              };
-+
-+              sffb_reserved: framebuffer@fb000000 {
-+                      compatible = "shared-dma-pool";
-+                      no-map;
-+                      reg = <0x0 0xfb000000 0x0 0x2000000>;
-+              };
-+      };
-+
-+      wifi_pwrseq: wifi-pwrseq {
-+              compatible = "mmc-pwrseq-simple";
-+              reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
-+      };
-+};
-+
-+&display {
-+      memory-region = <&sffb_reserved>;
-+      status = "okay";
-+};
-+
-+&crtc {
-+      ddr-format = <4>; //<WIN_FMT_RGB565>;
-+      status = "okay";
-+
-+      port: port@0 {
-+              reg = <0>;
-+
-+              crtc_0_out: endpoint {
-+                      remote-endpoint = <&hdmi_input0>;
-+              };
-+      };
-+};
-+
-+&encoder {
-+      encoder-type = <2>; // 2-TMDS, 3-LVDS, 6-DSI, 8-DPI
-+      status = "okay";
-+
-+      ports {
-+              port@0 {
-+                      hdmi_out: endpoint {
-+                              remote-endpoint = <&tda998x_0_input>;
-+                      };
-+              };
-+
-+              port@1 {
-+                      hdmi_input0: endpoint {
-+                              remote-endpoint = <&crtc_0_out>;
-+                      };
-+              };
-+
-+      };
-+};
-+
-+&gmac {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&gmac_pins>;
-+      status = "okay";
-+};
-+
-+&gpio {
-+      gmac_pins: gmac-0 {
-+              gtxclk-pins {
-+                      pins = <PAD_FUNC_SHARE(115)>;
-+                      bias-pull-up;
-+                      drive-strength = <35>;
-+                      input-enable;
-+                      input-schmitt-enable;
-+                      slew-rate = <0>;
-+              };
-+              miitxclk-pins {
-+                      pins = <PAD_FUNC_SHARE(116)>;
-+                      bias-pull-up;
-+                      drive-strength = <14>;
-+                      input-enable;
-+                      input-schmitt-disable;
-+                      slew-rate = <0>;
-+              };
-+              tx-pins {
-+                      pins = <PAD_FUNC_SHARE(117)>,
-+                             <PAD_FUNC_SHARE(119)>,
-+                             <PAD_FUNC_SHARE(120)>,
-+                             <PAD_FUNC_SHARE(121)>,
-+                             <PAD_FUNC_SHARE(122)>,
-+                             <PAD_FUNC_SHARE(123)>,
-+                             <PAD_FUNC_SHARE(124)>,
-+                             <PAD_FUNC_SHARE(125)>,
-+                             <PAD_FUNC_SHARE(126)>;
-+                      bias-pull-up;
-+                      drive-strength = <35>;
-+                      input-disable;
-+                      input-schmitt-disable;
-+                      slew-rate = <0>;
-+              };
-+              rxclk-pins {
-+                      pins = <PAD_FUNC_SHARE(127)>;
-+                      bias-pull-up;
-+                      drive-strength = <14>;
-+                      input-enable;
-+                      input-schmitt-disable;
-+                      slew-rate = <6>;
-+              };
-+              rxer-pins {
-+                      pins = <PAD_FUNC_SHARE(129)>;
-+                      bias-pull-up;
-+                      drive-strength = <14>;
-+                      input-enable;
-+                      input-schmitt-disable;
-+                      slew-rate = <0>;
-+              };
-+              rx-pins {
-+                      pins = <PAD_FUNC_SHARE(128)>,
-+                             <PAD_FUNC_SHARE(130)>,
-+                             <PAD_FUNC_SHARE(131)>,
-+                             <PAD_FUNC_SHARE(132)>,
-+                             <PAD_FUNC_SHARE(133)>,
-+                             <PAD_FUNC_SHARE(134)>,
-+                             <PAD_FUNC_SHARE(135)>,
-+                             <PAD_FUNC_SHARE(136)>,
-+                             <PAD_FUNC_SHARE(137)>,
-+                             <PAD_FUNC_SHARE(138)>,
-+                             <PAD_FUNC_SHARE(139)>,
-+                             <PAD_FUNC_SHARE(140)>,
-+                             <PAD_FUNC_SHARE(141)>;
-+                      bias-pull-up;
-+                      drive-strength = <14>;
-+                      input-enable;
-+                      input-schmitt-enable;
-+                      slew-rate = <0>;
-+              };
-+      };
-+
-+      i2c0_pins: i2c0-0 {
-+              i2c-pins {
-+                      pinmux = <GPIOMUX(62, GPO_LOW,
-+                                GPO_I2C0_PAD_SCK_OEN,
-+                                GPI_I2C0_PAD_SCK_IN)>,
-+                               <GPIOMUX(61, GPO_LOW,
-+                                GPO_I2C0_PAD_SDA_OEN,
-+                                GPI_I2C0_PAD_SDA_IN)>;
-+                      bias-disable; /* external pull-up */
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+      };
-+
-+      i2c1_pins: i2c1-0 {
-+              i2c-pins {
-+                      pinmux = <GPIOMUX(47, GPO_LOW,
-+                                GPO_I2C1_PAD_SCK_OEN,
-+                                GPI_I2C1_PAD_SCK_IN)>,
-+                               <GPIOMUX(48, GPO_LOW,
-+                                GPO_I2C1_PAD_SDA_OEN,
-+                                GPI_I2C1_PAD_SDA_IN)>;
-+                      bias-pull-up;
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+      };
-+
-+      i2c2_pins: i2c2-0 {
-+              i2c-pins {
-+                      pinmux = <GPIOMUX(60, GPO_LOW,
-+                                GPO_I2C2_PAD_SCK_OEN,
-+                                GPI_I2C2_PAD_SCK_IN)>,
-+                               <GPIOMUX(59, GPO_LOW,
-+                                GPO_I2C2_PAD_SDA_OEN,
-+                                GPI_I2C2_PAD_SDA_IN)>;
-+                      bias-disable; /* external pull-up */
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+      };
-+
-+      pwmdac_pins: pwmdac-0 {
-+              pwmdac-pins {
-+                      pinmux = <GPIOMUX(23, GPO_PWMDAC_LEFT_OUT,
-+                                GPO_ENABLE, GPI_NONE)>,
-+                               <GPIOMUX(24, GPO_PWMDAC_RIGHT_OUT,
-+                                GPO_ENABLE, GPI_NONE)>;
-+                      bias-disable;
-+                      drive-strength = <35>;
-+                      input-disable;
-+                      input-schmitt-disable;
-+                      slew-rate = <0>;
-+              };
-+      };
-+
-+      pwm_pins: pwm-0 {
-+              pwm-pins {
-+                      pinmux = <GPIOMUX(7,
-+                                GPO_PWM_PAD_OUT_BIT0,
-+                                GPO_PWM_PAD_OE_N_BIT0,
-+                                GPI_NONE)>,
-+                               <GPIOMUX(5,
-+                                GPO_PWM_PAD_OUT_BIT1,
-+                                GPO_PWM_PAD_OE_N_BIT1,
-+                                GPI_NONE)>;
-+                      bias-disable;
-+                      drive-strength = <35>;
-+                      input-disable;
-+                      input-schmitt-disable;
-+                      slew-rate = <0>;
-+              };
-+      };
-+
-+      sdio0_pins: sdio0-0 {
-+              clk-pins {
-+                      pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
-+                                GPO_ENABLE, GPI_NONE)>;
-+                      bias-disable;
-+                      input-disable;
-+                      input-schmitt-disable;
-+              };
-+              sdio-pins {
-+                      pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
-+                                GPI_SDIO0_PAD_CARD_DETECT_N)>,
-+                               <GPIOMUX(53,
-+                                GPO_SDIO0_PAD_CCMD_OUT,
-+                                GPO_SDIO0_PAD_CCMD_OEN,
-+                                GPI_SDIO0_PAD_CCMD_IN)>,
-+                               <GPIOMUX(49,
-+                                GPO_SDIO0_PAD_CDATA_OUT_BIT0,
-+                                GPO_SDIO0_PAD_CDATA_OEN_BIT0,
-+                                GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
-+                               <GPIOMUX(50,
-+                                GPO_SDIO0_PAD_CDATA_OUT_BIT1,
-+                                GPO_SDIO0_PAD_CDATA_OEN_BIT1,
-+                                GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
-+                               <GPIOMUX(51,
-+                                GPO_SDIO0_PAD_CDATA_OUT_BIT2,
-+                                GPO_SDIO0_PAD_CDATA_OEN_BIT2,
-+                                GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
-+                               <GPIOMUX(52,
-+                                GPO_SDIO0_PAD_CDATA_OUT_BIT3,
-+                                GPO_SDIO0_PAD_CDATA_OEN_BIT3,
-+                                GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
-+                      bias-pull-up;
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+      };
-+
-+      sdio1_pins: sdio1-0 {
-+              clk-pins {
-+                      pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
-+                                GPO_ENABLE, GPI_NONE)>;
-+                      bias-disable;
-+                      input-disable;
-+                      input-schmitt-disable;
-+              };
-+              sdio-pins {
-+                      pinmux = <GPIOMUX(29,
-+                                GPO_SDIO1_PAD_CCMD_OUT,
-+                                GPO_SDIO1_PAD_CCMD_OEN,
-+                                GPI_SDIO1_PAD_CCMD_IN)>,
-+                               <GPIOMUX(36,
-+                                GPO_SDIO1_PAD_CDATA_OUT_BIT0,
-+                                GPO_SDIO1_PAD_CDATA_OEN_BIT0,
-+                                GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
-+                               <GPIOMUX(30,
-+                                GPO_SDIO1_PAD_CDATA_OUT_BIT1,
-+                                GPO_SDIO1_PAD_CDATA_OEN_BIT1,
-+                                GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
-+                               <GPIOMUX(34,
-+                                GPO_SDIO1_PAD_CDATA_OUT_BIT2,
-+                                GPO_SDIO1_PAD_CDATA_OEN_BIT2,
-+                                GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
-+                               <GPIOMUX(31,
-+                                GPO_SDIO1_PAD_CDATA_OUT_BIT3,
-+                                GPO_SDIO1_PAD_CDATA_OEN_BIT3,
-+                                GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
-+                      bias-pull-up;
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+      };
-+
-+      spi2_pins: spi2-0 {
-+              mosi-pins {
-+                      pinmux = <GPIOMUX(18, GPO_SPI2_PAD_TXD,
-+                                GPO_ENABLE, GPI_NONE)>;
-+                      bias-disable;
-+                      input-disable;
-+                      input-schmitt-disable;
-+              };
-+              miso-pins {
-+                      pinmux = <GPIOMUX(16, GPO_LOW, GPO_DISABLE,
-+                                GPI_SPI2_PAD_RXD)>;
-+                      bias-pull-up;
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+              sck-pins {
-+                      pinmux = <GPIOMUX(12, GPO_SPI2_PAD_SCK_OUT,
-+                                GPO_ENABLE, GPI_NONE)>;
-+                      bias-disable;
-+                      input-disable;
-+                      input-schmitt-disable;
-+              };
-+              ss-pins {
-+                      pinmux = <GPIOMUX(15, GPO_SPI2_PAD_SS_0_N,
-+                                GPO_ENABLE, GPI_NONE)>,
-+                               <GPIOMUX(11, GPO_SPI2_PAD_SS_1_N,
-+                                GPO_ENABLE, GPI_NONE)>;
-+                      bias-disable;
-+                      input-disable;
-+                      input-schmitt-disable;
-+              };
-+      };
-+
-+      uart0_pins: uart0-0 {
-+              rx-pins {
-+                      pinmux = <GPIOMUX(40, GPO_LOW, GPO_DISABLE,
-+                                GPI_UART0_PAD_SIN)>,
-+                               <GPIOMUX(39, GPO_LOW, GPO_DISABLE,
-+                                GPI_UART0_PAD_CTSN)>;
-+                      bias-pull-up;
-+                      drive-strength = <14>;
-+                      input-enable;
-+                      input-schmitt-enable;
-+              };
-+              tx-pins {
-+                      pinmux = <GPIOMUX(41, GPO_UART0_PAD_SOUT,
-+                                GPO_ENABLE, GPI_NONE)>,
-+                               <GPIOMUX(42, GPO_UART0_PAD_RTSN,
-+                                GPO_ENABLE, GPI_NONE)>;
-+                      bias-disable;
-+                      drive-strength = <35>;
-+                      input-disable;
-+                      input-schmitt-disable;
-+              };
-+      };
-+
-+      uart3_pins: uart3-0 {
-+              rx-pins {
-+                      pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
-+                                GPI_UART3_PAD_SIN)>;
-+                      bias-pull-up;
-+                      drive-strength = <14>;
-+                      input-enable;
-+                      input-schmitt-enable;
-+                      slew-rate = <0>;
-+              };
-+              tx-pins {
-+                      pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
-+                                GPO_ENABLE, GPI_NONE)>;
-+                      bias-disable;
-+                      drive-strength = <35>;
-+                      input-disable;
-+                      input-schmitt-disable;
-+                      slew-rate = <0>;
-+              };
-+      };
-+};
-+
-+&i2c0 {
-+      clock-frequency = <100000>;
-+      i2c-sda-hold-time-ns = <300>;
-+      i2c-sda-falling-time-ns = <500>;
-+      i2c-scl-falling-time-ns = <500>;
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&i2c0_pins>;
-+      status = "okay";
-+
-+      pmic@5e {
-+              compatible = "ti,tps65086";
-+              reg = <0x5e>;
-+              gpio-controller;
-+              #gpio-cells = <2>;
-+
-+              regulators {
-+              };
-+      };
-+
-+      tda998x@70 {
-+              compatible = "nxp,tda998x";
-+              reg = <0x70>;
-+
-+              port {
-+                      tda998x_0_input: endpoint {
-+                              remote-endpoint = <&hdmi_out>;
-+                      };
-+              };
-+      };
-+};
-+
-+&i2c1 {
-+      clock-frequency = <400000>;
-+      i2c-sda-hold-time-ns = <300>;
-+      i2c-sda-falling-time-ns = <100>;
-+      i2c-scl-falling-time-ns = <100>;
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&i2c1_pins>;
-+      status = "okay";
-+};
-+
-+&i2c2 {
-+      clock-frequency = <100000>;
-+      i2c-sda-hold-time-ns = <300>;
-+      i2c-sda-falling-time-ns = <500>;
-+      i2c-scl-falling-time-ns = <500>;
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&i2c2_pins>;
-+      status = "okay";
-+};
-+
-+&osc_sys {
-+      clock-frequency = <25000000>;
-+};
-+
-+&osc_aud {
-+      clock-frequency = <27000000>;
-+};
-+
-+&ptc {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&pwm_pins>;
-+      status = "okay";
-+};
-+
-+&pwmdac {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&pwmdac_pins>;
-+      status = "okay";
-+};
-+
-+&qspi {
-+      nor_flash: nor-flash@0 {
-+              compatible = "spi-flash";
-+              reg = <0>;
-+              spi-max-frequency = <31250000>;
-+              page-size = <256>;
-+              block-size = <16>;
-+              cdns,read-delay = <4>;
-+              cdns,tshsl-ns = <1>;
-+              cdns,tsd2d-ns = <1>;
-+              cdns,tchsh-ns = <1>;
-+              cdns,tslch-ns = <1>;
-+              spi-tx-bus-width = <1>;
-+              spi-rx-bus-width = <1>;
-+      };
-+
-+      nand_flash: nand-flash@1 {
-+              compatible = "spi-flash-nand";
-+              reg = <1>;
-+              spi-max-frequency = <31250000>;
-+              page-size = <2048>;
-+              block-size = <17>;
-+              cdns,read-delay = <4>;
-+              cdns,tshsl-ns = <1>;
-+              cdns,tsd2d-ns = <1>;
-+              cdns,tchsh-ns = <1>;
-+              cdns,tslch-ns = <1>;
-+              spi-tx-bus-width = <1>;
-+              spi-rx-bus-width = <1>;
-+      };
-+};
-+
-+&sdio0 {
-+      broken-cd;
-+      bus-width = <4>;
-+      cap-sd-highspeed;
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&sdio0_pins>;
-+      status = "okay";
-+};
-+
-+&sdio1 {
-+      #address-cells = <1>;
-+      #size-cells = <0>;
-+      bus-width = <4>;
-+      cap-sd-highspeed;
-+      cap-sdio-irq;
-+      cap-power-off-card;
-+      mmc-pwrseq = <&wifi_pwrseq>;
-+      non-removable;
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&sdio1_pins>;
-+      status = "okay";
-+
-+      wifi@1 {
-+              compatible = "brcm,bcm4329-fmac";
-+              reg = <1>;
-+      };
-+};
-+
-+&spi2 {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&spi2_pins>;
-+      status = "okay";
-+
-+      spi_dev0: spi@0 {
-+              compatible = "rohm,dh2228fv";
-+              spi-max-frequency = <10000000>;
-+              reg = <0>;
-+      };
-+};
-+
-+&uart0 {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&uart0_pins>;
-+      status = "okay";
-+};
-+
-+&uart3 {
-+      pinctrl-names = "default";
-+      pinctrl-0 = <&uart3_pins>;
-+      status = "okay";
-+};
-+
-+&usb3 {
-+      dr_mode = "host";
-+      status = "okay";
-+};
-diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
-new file mode 100644
-index 000000000000..68616a1c9cf6
---- /dev/null
-+++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
-@@ -0,0 +1,32 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+/dts-v1/;
-+#include "jh7100-common.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+      model = "StarFive VisionFive V1";
-+      compatible = "starfive,visionfive-v1", "starfive,jh7100";
-+
-+      gpio-restart {
-+              compatible = "gpio-restart";
-+              gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
-+              priority = <224>;
-+      };
-+};
-+
-+&gpio {
-+      /* don't reset gpio mux for serial console and reset gpio */
-+      starfive,keep-gpiomux = <13 14 63>;
-+};
-+
-+&i2c0 {
-+      eeprom@50 {
-+              compatible = "atmel,24c04";
-+              reg = <0x50>;
-+              pagesize = <16>;
-+      };
-+};
-diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
-index d76a67098620..fab3611d135c 100644
---- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
-+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
-@@ -6,7 +6,9 @@
- 
- /dts-v1/;
- #include <dt-bindings/clock/starfive-jh7100.h>
-+#include <dt-bindings/clock/starfive-jh7100-audio.h>
- #include <dt-bindings/reset/starfive-jh7100.h>
-+#include <dt-bindings/reset/starfive-jh7100-audio.h>
- 
- / {
-       compatible = "starfive,jh7100";
-@@ -32,7 +34,9 @@ cpu@0 {
-                       i-tlb-sets = <1>;
-                       i-tlb-size = <32>;
-                       mmu-type = "riscv,sv39";
-+                      next-level-cache = <&ccache>;
-                       riscv,isa = "rv64imafdc";
-+                      starfive,itim = <&itim0>;
-                       tlb-split;
- 
-                       cpu0_intc: interrupt-controller {
-@@ -57,7 +61,9 @@ cpu@1 {
-                       i-tlb-sets = <1>;
-                       i-tlb-size = <32>;
-                       mmu-type = "riscv,sv39";
-+                      next-level-cache = <&ccache>;
-                       riscv,isa = "rv64imafdc";
-+                      starfive,itim = <&itim1>;
-                       tlb-split;
- 
-                       cpu1_intc: interrupt-controller {
-@@ -103,6 +109,24 @@ soc {
-               #size-cells = <2>;
-               ranges;
- 
-+              dtim: dtim@1000000 {
-+                      compatible = "starfive,dtim0";
-+                      reg = <0x0 0x1000000 0x0 0x2000>;
-+                      reg-names = "mem";
-+              };
-+
-+              itim0: itim@1808000 {
-+                      compatible = "starfive,itim0";
-+                      reg = <0x0 0x1808000 0x0 0x8000>;
-+                      reg-names = "mem";
-+              };
-+
-+              itim1: itim@1820000 {
-+                      compatible = "starfive,itim0";
-+                      reg = <0x0 0x1820000 0x0 0x8000>;
-+                      reg-names = "mem";
-+              };
-+
-               clint: clint@2000000 {
-                       compatible = "starfive,jh7100-clint", "sifive,clint0";
-                       reg = <0x0 0x2000000 0x0 0x10000>;
-@@ -110,6 +134,20 @@ clint: clint@2000000 {
-                                             <&cpu1_intc 3>, <&cpu1_intc 7>;
-               };
- 
-+              ccache: cache-controller@2010000 {
-+                      compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
-+                      reg = <0x0 0x2010000 0x0 0x1000>,
-+                            <0x0 0x8000000 0x0 0x2000000>;
-+                      reg-names = "control", "sideband";
-+                      interrupts = <128>, <131>, <129>, <130>;
-+                      cache-block-size = <64>;
-+                      cache-level = <2>;
-+                      cache-sets = <2048>;
-+                      cache-size = <2097152>;
-+                      cache-unified;
-+                      /*next-level-cache = <&L40 &L36>;*/
-+              };
-+
-               plic: interrupt-controller@c000000 {
-                       compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
-                       reg = <0x0 0xc000000 0x0 0x4000000>;
-@@ -121,6 +159,179 @@ plic: interrupt-controller@c000000 {
-                       riscv,ndev = <127>;
-               };
- 
-+              sdio0: mmc@10000000 {
-+                      compatible = "snps,dw-mshc";
-+                      reg = <0x0 0x10000000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
-+                               <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
-+                      clock-names = "biu", "ciu";
-+                      interrupts = <4>;
-+                      data-addr = <0>;
-+                      fifo-depth = <32>;
-+                      fifo-watermark-aligned;
-+                      status = "disabled";
-+              };
-+
-+              sdio1: mmc@10010000 {
-+                      compatible = "snps,dw-mshc";
-+                      reg = <0x0 0x10010000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
-+                               <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
-+                      clock-names = "biu", "ciu";
-+                      interrupts = <5>;
-+                      data-addr = <0>;
-+                      fifo-depth = <32>;
-+                      fifo-watermark-aligned;
-+                      status = "disabled";
-+              };
-+
-+              /* gmac device configuration */
-+              stmmac_axi_setup: stmmac-axi-config {
-+                      snps,wr_osr_lmt = <0xf>;
-+                      snps,rd_osr_lmt = <0xf>;
-+                      snps,blen = <256 128 64 32 0 0 0>;
-+              };
-+
-+              gmac: ethernet@10020000 {
-+                      compatible = "snps,dwmac";
-+                      reg = <0x0 0x10020000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_GMAC_GTX>,
-+                               <&clkgen JH7100_CLK_GMAC_AHB>,
-+                               <&clkgen JH7100_CLK_GMAC_PTP_REF>;
-+                      clock-names = "stmmaceth", "pclk", "ptp_ref";
-+                      resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
-+                      reset-names = "ahb";
-+                      interrupts = <6>, <7>;
-+                      interrupt-names = "macirq", "eth_wake_irq";
-+                      max-frame-size = <9000>;
-+                      phy-mode = "rgmii-txid";
-+                      snps,multicast-filter-bins = <256>;
-+                      snps,perfect-filter-entries = <128>;
-+                      rx-fifo-depth = <32768>;
-+                      tx-fifo-depth = <16384>;
-+                      snps,axi-config = <&stmmac_axi_setup>;
-+                      snps,fixed-burst;
-+                      /*snps,force_sf_dma_mode;*/
-+                      snps,force_thresh_dma_mode;
-+                      snps,no-pbl-x8 = <1>;
-+                      status = "disabled";
-+              };
-+
-+              dma2p: dma-controller@100b0000 {
-+                      compatible = "snps,axi-dma-1.01a";
-+                      reg = <0x0 0x100b0000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
-+                               <&clkgen JH7100_CLK_SGDMA2P_AHB>;
-+                      clock-names = "core-clk", "cfgr-clk";
-+                      interrupts = <2>;
-+                      #dma-cells = <1>;
-+                      dma-channels = <4>;
-+                      snps,dma-masters = <1>;
-+                      snps,data-width = <4>;
-+                      snps,block-size = <4096 4096 4096 4096>;
-+                      snps,priority = <0 1 2 3>;
-+                      snps,axi-max-burst-len = <128>;
-+                      dma-coherent;
-+              };
-+
-+              crypto: crypto@100d0000 {
-+                      compatible = "starfive,vic-sec";
-+                      reg = <0x0 0x100d0000 0x0 0x20000>,
-+                            <0x0 0x11800234 0x0 0xc>;
-+                      reg-names = "secmem", "secclk";
-+                      clocks = <&clkgen JH7100_CLK_SEC_AHB>;
-+                      interrupts = <31>;
-+              };
-+
-+              i2sadc0: i2sadc0@10400000 {
-+                      compatible = "snps,designware-i2sadc0";
-+                      reg = <0x0 0x10400000 0x0 0x1000>;
-+                      clocks = <&clkgen JH7100_CLK_APB1_BUS>;
-+                      clock-names = "i2sclk";
-+                      interrupt-parent = <&plic>;
-+                      #sound-dai-cells = <0>;
-+                      dmas = <&dma2p 28>;
-+                      dma-names = "rx";
-+              };
-+
-+              i2svad: i2svad@10420000 {
-+                      compatible = "starfive,sf-i2svad";
-+                      reg = <0x0 0x10420000 0x0 0x1000> ;
-+                      clocks = <&audclk JH7100_AUDCLK_I2SVAD_APB>;
-+                      clock-names = "i2svad_apb";
-+                      resets = <&audrst JH7100_AUDRSTN_I2SVAD_APB>,
-+                               <&audrst JH7100_AUDRSTN_I2SVAD_SRST>;
-+                      reset-names = "apb_i2svad", "i2svad_srst";
-+                      interrupts = <60>, <61>;
-+                      interrupt-names = "spintr", "slintr";
-+                      #sound-dai-cells = <0>;
-+              };
-+
-+              pwmdac: pwmdac@10440000 {
-+                      compatible = "starfive,pwmdac";
-+                      reg = <0x0 0x10440000 0x0 0x1000>;
-+                      clocks = <&clkgen JH7100_CLK_AUDIO_ROOT>,
-+                               <&clkgen JH7100_CLK_AUDIO_SRC>,
-+                               <&clkgen JH7100_CLK_AUDIO_12288>,
-+                               <&audclk JH7100_AUDCLK_DMA1P_AHB>,
-+                               <&audclk JH7100_AUDCLK_PWMDAC_APB>,
-+                               <&audclk JH7100_AUDCLK_DAC_MCLK>;
-+                      clock-names = "audio_root",
-+                                    "audio_src",
-+                                    "audio_12288",
-+                                    "dma1p_ahb",
-+                                    "pwmdac_apb",
-+                                    "dac_mclk";
-+                      resets = <&audrst JH7100_AUDRSTN_APB_BUS>,
-+                               <&audrst JH7100_AUDRSTN_DMA1P_AHB>,
-+                               <&audrst JH7100_AUDRSTN_PWMDAC_APB>;
-+                      reset-names = "apb_bus", "dma1p_ahb", "apb_pwmdac";
-+                      dmas = <&dma2p 23>;
-+                      dma-names = "tx";
-+                      #sound-dai-cells = <0>;
-+              };
-+
-+              i2sdac0: i2sdac0@10450000 {
-+                      compatible = "snps,designware-i2sdac0";
-+                      reg = <0x0 0x10450000 0x0 0x1000>;
-+                      clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
-+                               <&audclk JH7100_AUDCLK_I2SDAC_BCLK>,
-+                               <&audclk JH7100_AUDCLK_I2SDAC_LRCLK>,
-+                               <&audclk JH7100_AUDCLK_I2SDAC_APB>;
-+                      clock-names = "dac_mclk", "i2sdac0_bclk", "i2sdac0_lrclk", "i2sdac_apb";
-+                      resets = <&audrst JH7100_AUDRSTN_I2SDAC_APB>,
-+                               <&audrst JH7100_AUDRSTN_I2SDAC_SRST>;
-+                      reset-names = "apb_i2sdac", "i2sdac_srst";
-+                      #sound-dai-cells = <0>;
-+                      dmas = <&dma2p 30>;
-+                      dma-names = "tx";
-+              };
-+
-+              i2sdac1: i2sdac1@10460000 {
-+                      compatible = "snps,designware-i2sdac1";
-+                      reg = <0x0 0x10460000 0x0 0x1000>;
-+                      clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
-+                               <&audclk JH7100_AUDCLK_I2S1_BCLK>,
-+                               <&audclk JH7100_AUDCLK_I2S1_LRCLK>,
-+                               <&audclk JH7100_AUDCLK_I2S1_APB>;
-+                      clock-names = "dac_mclk", "i2sdac1_bclk", "i2sdac1_lrclk", "i2s1_apb";
-+                      resets = <&audrst JH7100_AUDRSTN_I2S1_APB>,
-+                               <&audrst JH7100_AUDRSTN_I2S1_SRST>;
-+                      #sound-dai-cells = <0>;
-+                      dmas = <&dma2p 31>;
-+                      dma-names = "tx";
-+              };
-+
-+              i2sdac16k: i2sdac16k@10470000 {
-+                      compatible = "snps,designware-i2sdac16k";
-+                      reg = <0x0 0x10470000 0x0 0x1000>;
-+                      clocks = <&clkgen JH7100_CLK_APB1_BUS>;
-+                      clock-names = "i2sclk";
-+                      #sound-dai-cells = <0>;
-+                      dmas = <&dma2p 29>;
-+                      dma-names = "tx";
-+              };
-+
-               audclk: clock-controller@10480000 {
-                       compatible = "starfive,jh7100-audclk";
-                       reg = <0x0 0x10480000 0x0 0x10000>;
-@@ -137,6 +348,79 @@ audrst: reset-controller@10490000 {
-                       #reset-cells = <1>;
-               };
- 
-+              spdif_transmitter: spdif-transmitter {
-+                      compatible = "linux,spdif-dit";
-+                      #sound-dai-cells = <0>;
-+              };
-+
-+              spdif_receiver: spdif-receiver {
-+                      compatible = "linux,spdif-dir";
-+                      #sound-dai-cells = <0>;
-+              };
-+
-+              pwmdac_codec: pwmdac-transmitter {
-+                      compatible = "linux,pwmdac-dit";
-+                      #sound-dai-cells = <0>;
-+              };
-+
-+              dmic_codec: dmic {
-+                      compatible = "dmic-codec";
-+                      #sound-dai-cells = <0>;
-+              };
-+
-+              sound: snd-card {
-+                      compatible = "simple-audio-card";
-+                      simple-audio-card,name = "Starfive-Multi-Sound-Card";
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+
-+                      /* pwmdac */
-+                      simple-audio-card,dai-link@0 {
-+                              reg = <0>;
-+                              status = "okay";
-+                              format = "left_j";
-+                              bitclock-master = <&sndcpu0>;
-+                              frame-master = <&sndcpu0>;
-+
-+                              sndcpu0: cpu {
-+                                      sound-dai = <&pwmdac>;
-+                              };
-+
-+                              codec {
-+                                      sound-dai = <&pwmdac_codec>;
-+                              };
-+                      };
-+              };
-+
-+              usb3: usb@104c0000 {
-+                      compatible = "cdns,usb3";
-+                      reg = <0x0 0x104c0000 0x0 0x10000>,     // memory area for HOST registers
-+                            <0x0 0x104d0000 0x0 0x10000>,     // memory area for DEVICE registers
-+                            <0x0 0x104e0000 0x0 0x10000>;     // memory area for OTG/DRD registers
-+                      reg-names = "otg", "xhci", "dev";
-+                      interrupts = <44>, <52>, <43>;
-+                      interrupt-names = "host", "peripheral", "otg";
-+                      phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
-+                      maximum-speed = "super-speed";
-+                      status = "disabled";
-+              };
-+
-+              dma1p: dma-controller@10500000 {
-+                      compatible = "snps,axi-dma-1.01a";
-+                      reg = <0x0 0x10500000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
-+                               <&clkgen JH7100_CLK_SGDMA1P_BUS>;
-+                      clock-names = "core-clk", "cfgr-clk";
-+                      interrupts = <1>;
-+                      #dma-cells = <1>;
-+                      dma-channels = <16>;
-+                      snps,dma-masters = <1>;
-+                      snps,data-width = <3>;
-+                      snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
-+                      snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
-+                      snps,axi-max-burst-len = <64>;
-+              };
-+
-               clkgen: clock-controller@11800000 {
-                       compatible = "starfive,jh7100-clkgen";
-                       reg = <0x0 0x11800000 0x0 0x10000>;
-@@ -145,12 +429,88 @@ clkgen: clock-controller@11800000 {
-                       #clock-cells = <1>;
-               };
- 
-+              otp: otp@11810000 {
-+                      compatible = "starfive,fu740-otp";
-+                      reg = <0x0 0x11810000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_OTP_APB>;
-+                      fuse-count = <0x200>;
-+              };
-+
-               rstgen: reset-controller@11840000 {
-                       compatible = "starfive,jh7100-reset";
-                       reg = <0x0 0x11840000 0x0 0x10000>;
-                       #reset-cells = <1>;
-               };
- 
-+              qspi: spi@11860000 {
-+                      compatible = "cdns,qspi-nor";
-+                      reg = <0x0 0x11860000 0x0 0x10000>,
-+                            <0x0 0x20000000 0x0 0x20000000>;
-+                      clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
-+                      interrupts = <3>;
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      cdns,fifo-depth = <256>;
-+                      cdns,fifo-width = <4>;
-+                      cdns,trigger-address = <0x0>;
-+                      spi-max-frequency = <250000000>;
-+                      status = "disabled";
-+              };
-+
-+              uart0: serial@11870000 {
-+                      compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
-+                      reg = <0x0 0x11870000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_UART0_CORE>,
-+                               <&clkgen JH7100_CLK_UART0_APB>;
-+                      clock-names = "baudclk", "apb_pclk";
-+                      resets = <&rstgen JH7100_RSTN_UART0_APB>;
-+                      interrupts = <92>;
-+                      reg-io-width = <4>;
-+                      reg-shift = <2>;
-+                      status = "disabled";
-+              };
-+
-+              uart1: serial@11880000 {
-+                      compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
-+                      reg = <0x0 0x11880000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_UART1_CORE>,
-+                               <&clkgen JH7100_CLK_UART1_APB>;
-+                      clock-names = "baudclk", "apb_pclk";
-+                      resets = <&rstgen JH7100_RSTN_UART1_APB>;
-+                      interrupts = <93>;
-+                      reg-io-width = <4>;
-+                      reg-shift = <2>;
-+                      status = "disabled";
-+              };
-+
-+              spi0: spi@11890000 {
-+                      compatible = "snps,dw-apb-ssi";
-+                      reg = <0x0 0x11890000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
-+                               <&clkgen JH7100_CLK_SPI0_APB>;
-+                      clock-names = "ssi_clk", "pclk";
-+                      resets = <&rstgen JH7100_RSTN_SPI0_APB>;
-+                      reset-names = "spi";
-+                      interrupts = <94>;
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      status = "disabled";
-+              };
-+
-+              spi1: spi@118a0000 {
-+                      compatible = "snps,dw-apb-ssi";
-+                      reg = <0x0 0x118a0000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
-+                               <&clkgen JH7100_CLK_SPI1_APB>;
-+                      clock-names = "ssi_clk", "pclk";
-+                      resets = <&rstgen JH7100_RSTN_SPI1_APB>;
-+                      reset-names = "spi";
-+                      interrupts = <95>;
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      status = "disabled";
-+              };
-+
-               i2c0: i2c@118b0000 {
-                       compatible = "snps,designware-i2c";
-                       reg = <0x0 0x118b0000 0x0 0x10000>;
-@@ -177,6 +537,41 @@ i2c1: i2c@118c0000 {
-                       status = "disabled";
-               };
- 
-+              trng: trng@118d0000 {
-+                      compatible = "starfive,vic-rng";
-+                      reg = <0x0 0x118d0000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_TRNG_APB>;
-+                      interrupts = <98>;
-+              };
-+
-+              vpu_enc: vpu_enc@118e0000 {
-+                      compatible = "cm,cm521-vpu";
-+                      reg = <0x0 0x118e0000 0x0 0x4000>;
-+                      reg-names = "control";
-+                      clocks = <&clkgen JH7100_CLK_VP6_CORE>;
-+                      clock-names = "vcodec";
-+                      interrupts = <26>;
-+              };
-+
-+              vpu_dec: vpu_dec@118f0000 {
-+                      compatible = "c&m,cm511-vpu";
-+                      reg = <0 0x118f0000 0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_VP6_CORE>;
-+                      clock-names = "vcodec";
-+                      interrupts = <23>;
-+                      //memory-region = <&vpu_reserved>;
-+              };
-+
-+              jpu: coadj12@11900000 {
-+                      compatible = "cm,codaj12-jpu-1";
-+                      reg = <0x0 0x11900000 0x0 0x300>;
-+                      reg-names = "control";
-+                      clocks = <&clkgen JH7100_CLK_JPEG_APB>;
-+                      clock-names = "jpege";
-+                      interrupts = <24>;
-+                      memory-region = <&jpu_reserved>;
-+              };
-+
-               gpio: pinctrl@11910000 {
-                       compatible = "starfive,jh7100-pinctrl";
-                       reg = <0x0 0x11910000 0x0 0x10000>,
-@@ -191,6 +586,86 @@ gpio: pinctrl@11910000 {
-                       #interrupt-cells = <2>;
-               };
- 
-+              nvdla@11940000 {
-+                      compatible = "nvidia,nvdla_os_initial";
-+                      interrupts = <22>;
-+                      memory-region = <&nvdla_reserved>;
-+                      reg = <0x0 0x11940000 0x0 0x40000>;
-+                      status = "okay";
-+              };
-+
-+              display: display-subsystem {
-+                      compatible = "starfive,display-subsystem";
-+                      dma-coherent;
-+                      status = "disabled";
-+              };
-+
-+              encoder: display-encoder {
-+                      compatible = "starfive,display-encoder";
-+                      status = "disabled";
-+              };
-+
-+              crtc: crtc@12000000 {
-+                      compatible = "starfive,jh7100-crtc";
-+                      reg = <0x0 0x12000000 0x0 0x10000>,
-+                            <0x0 0x12040000 0x0 0x10000>,
-+                            <0x0 0x12080000 0x0 0x10000>,
-+                            <0x0 0x120c0000 0x0 0x10000>,
-+                            <0x0 0x12240000 0x0 0x10000>,
-+                            <0x0 0x12250000 0x0 0x10000>,
-+                            <0x0 0x12260000 0x0 0x10000>;
-+                      reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
-+                      clocks = <&clkgen JH7100_CLK_DISP_AXI>, <&clkgen JH7100_CLK_VOUT_SRC>;
-+                      clock-names = "disp_axi", "vout_src";
-+                      resets = <&rstgen JH7100_RSTN_DISP_AXI>, <&rstgen JH7100_RSTN_VOUT_SRC>;
-+                      reset-names = "disp_axi", "vout_src";
-+                      interrupts = <101>, <103>;
-+                      interrupt-names = "lcdc_irq", "vpp1_irq";
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      status = "disabled";
-+
-+                      pp1 {
-+                              pp-id = <1>;
-+                              fifo-out;
-+                              //sys-bus-out;
-+                              src-format = <11>; //<COLOR_RGB565>;
-+                              src-width = <1920>;
-+                              src-height = <1080>;
-+                              dst-format = <7>; //<COLOR_RGB888_ARGB>;
-+                              dst-width = <1920>;
-+                              dst-height = <1080>;
-+                      };
-+              };
-+
-+              spi2: spi@12410000 {
-+                      compatible = "snps,dw-apb-ssi";
-+                      reg = <0x0 0x12410000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
-+                               <&clkgen JH7100_CLK_SPI2_APB>;
-+                      clock-names = "ssi_clk", "pclk";
-+                      resets = <&rstgen JH7100_RSTN_SPI2_APB>;
-+                      reset-names = "spi";
-+                      interrupts = <70>;
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      status = "disabled";
-+              };
-+
-+              spi3: spi@12420000 {
-+                      compatible = "snps,dw-apb-ssi";
-+                      reg = <0x0 0x12420000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
-+                               <&clkgen JH7100_CLK_SPI3_APB>;
-+                      clock-names = "ssi_clk", "pclk";
-+                      resets = <&rstgen JH7100_RSTN_SPI3_APB>;
-+                      reset-names = "spi";
-+                      interrupts = <71>;
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+                      status = "disabled";
-+              };
-+
-               uart2: serial@12430000 {
-                       compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
-                       reg = <0x0 0x12430000 0x0 0x10000>;
-@@ -242,5 +717,89 @@ i2c3: i2c@12460000 {
-                       #size-cells = <0>;
-                       status = "disabled";
-               };
-+
-+              watchdog@12480000 {
-+                      compatible = "starfive,si5-wdt";
-+                      reg = <0x0 0x12480000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_WDT_CORE>,
-+                               <&clkgen JH7100_CLK_WDTIMER_APB>;
-+                      clock-names = "wdt_coreclk", "wdtimer_apb";
-+                      resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
-+                               <&rstgen JH7100_RSTN_WDT>;
-+                      reset-names = "wdtimer_apb", "wdt";
-+                      interrupts = <80>;
-+              };
-+
-+              ptc: pwm@12490000 {
-+                      compatible = "starfive,pwm0";
-+                      reg = <0x0 0x12490000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_PWM_APB>;
-+                      resets = <&rstgen JH7100_RSTN_PWM_APB>;
-+                      #pwm-cells = <3>;
-+                      sifive,npwm = <8>;
-+                      status = "disabled";
-+              };
-+
-+              sfctemp: tmon@124a0000 {
-+                      compatible = "starfive,jh7100-temp";
-+                      reg = <0x0 0x124a0000 0x0 0x10000>;
-+                      clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
-+                               <&clkgen JH7100_CLK_TEMP_APB>;
-+                      clock-names = "sense", "bus";
-+                      resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
-+                               <&rstgen JH7100_RSTN_TEMP_APB>;
-+                      reset-names = "sense", "bus";
-+                      interrupts = <122>;
-+                      #thermal-sensor-cells = <0>;
-+              };
-+
-+              thermal-zones {
-+                      cpu-thermal {
-+                              polling-delay-passive = <250>;
-+                              polling-delay = <15000>;
-+
-+                              thermal-sensors = <&sfctemp>;
-+
-+                              cooling-maps {
-+                              };
-+
-+                              trips {
-+                                      cpu_alert0: cpu_alert0 {
-+                                              /* milliCelsius */
-+                                              temperature = <75000>;
-+                                              hysteresis = <2000>;
-+                                              type = "passive";
-+                                      };
-+
-+                                      cpu_crit: cpu_crit {
-+                                              /* milliCelsius */
-+                                              temperature = <90000>;
-+                                              hysteresis = <2000>;
-+                                              type = "critical";
-+                                      };
-+                              };
-+                      };
-+              };
-+
-+              xrp@f0000000 {
-+                      compatible = "cdns,xrp";
-+                      reg = <0x0  0xf0000000 0x0 0x01ffffff>,
-+                            <0x10 0x72000000 0x0 0x00001000>,
-+                            <0x10 0x72001000 0x0 0x00fff000>,
-+                            <0x0  0x124b0000 0x0 0x00010000>;
-+                      clocks = <&clkgen JH7100_CLK_VP6_CORE>;
-+                      interrupts = <27>, <28>;
-+                      firmware-name = "vp6_elf";
-+                      dsp-irq = <19 20>;
-+                      dsp-irq-src = <0x20 0x21>;
-+                      intc-irq-mode = <1>;
-+                      intc-irq = <0 1>;
-+                      #address-cells = <1>;
-+                      #size-cells = <1>;
-+                      ranges = <0x40000000 0x0  0x40000000 0x01000000>,
-+                               <0xb0000000 0x10 0x70000000 0x3000000>;
-+                      dsp@0 {
-+                      };
-+              };
-       };
- };
--- 
-2.30.2
-

diff --git a/target/linux/visionfive/patches-5.15/0053-sifive-sifive_l2_cache-Add-disabling-IRQ-option-work.patch b/target/linux/visionfive/patches-5.15/0053-sifive-sifive_l2_cache-Add-disabling-IRQ-option-work.patch
new file mode 100644 (file)
index 0000000..8199a1f
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0053-sifive-sifive_l2_cache-Add-disabling-IRQ-option-work.patch
@@ -0,0 +1,132 @@
+From 90d28a18e7ffc8f832b1e643c9867eee328708f4 Mon Sep 17 00:00:00 2001
+From: Tom <support@vamrs.com>
+Date: Sat, 13 Feb 2021 22:25:17 +0800
+Subject: [PATCH 53/84] sifive/sifive_l2_cache: Add disabling IRQ option
+ (workaround)
+
+---
+ drivers/irqchip/irq-sifive-plic.c    | 41 ++++++++++++++++++++++++++++
+ drivers/soc/sifive/Kconfig           |  4 +++
+ drivers/soc/sifive/sifive_l2_cache.c |  8 ++++++
+ 3 files changed, 53 insertions(+)
+
+--- a/drivers/irqchip/irq-sifive-plic.c
++++ b/drivers/irqchip/irq-sifive-plic.c
+@@ -277,6 +277,44 @@ static int plic_starting_cpu(unsigned in
+       return 0;
+ }
+ 
++#if IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
++#ifdef CONFIG_SOC_STARFIVE
++#define SIFIVE_L2_MAX_ECCINTR 4
++#else
++#define SIFIVE_L2_MAX_ECCINTR 3
++#endif
++static const struct of_device_id sifive_l2_ids[] = {
++      { .compatible = "sifive,fu540-c000-ccache" },
++      { .compatible = "starfive,ccache0" },
++      { /* end of table */ },
++};
++
++static void sifive_l2_irq_disable(struct plic_handler *handler)
++{
++      int i, irq;
++      struct of_phandle_args oirq;
++
++      struct device_node *np = of_find_matching_node(NULL, sifive_l2_ids);
++      if (!np) {
++              pr_err("Can't get L2 cache device node.\n");
++              return;
++      }
++
++      for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
++              if (!of_irq_parse_one(np, i, &oirq)) {
++                      irq = *oirq.args;
++                      if (irq) {
++                              pr_info("disable L2 cache irq %d in plic\n", irq);
++                              plic_toggle(handler, irq, 0);
++                              continue;
++                      }
++              }
++              pr_err("Can't get L2 cache irq(#%d).\n", i);
++      }
++}
++#endif
++
++
+ static int __init plic_init(struct device_node *node,
+               struct device_node *parent)
+ {
+@@ -370,6 +408,9 @@ static int __init plic_init(struct devic
+ done:
+               for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
+                       plic_toggle(handler, hwirq, 0);
++#if IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
++              sifive_l2_irq_disable(handler);
++#endif
+               nr_handlers++;
+       }
+ 
+--- a/drivers/soc/sifive/Kconfig
++++ b/drivers/soc/sifive/Kconfig
+@@ -22,4 +22,8 @@ config SIFIVE_L2_FLUSH_SIZE
+ 
+ endif # SIFIVE_L2_FLUSH
+ 
++config SIFIVE_L2_IRQ_DISABLE
++      bool "Disable Level 2 Cache Controller interrupts"
++      default y if SOC_STARFIVE
++
+ endif
+--- a/drivers/soc/sifive/sifive_l2_cache.c
++++ b/drivers/soc/sifive/sifive_l2_cache.c
+@@ -40,7 +40,9 @@
+ #define SIFIVE_L2_FLUSH64_LINE_LEN 64
+ 
+ static void __iomem *l2_base = NULL;
++#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
+ static int g_irq[SIFIVE_L2_MAX_ECCINTR];
++#endif
+ static struct riscv_cacheinfo_ops l2_cache_ops;
+ 
+ enum {
+@@ -188,6 +190,7 @@ static const struct attribute_group *l2_
+               return NULL;
+ }
+ 
++#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
+ static irqreturn_t l2_int_handler(int irq, void *device)
+ {
+       unsigned int add_h, add_l;
+@@ -231,12 +234,15 @@ static irqreturn_t l2_int_handler(int ir
+ 
+       return IRQ_HANDLED;
+ }
++#endif
+ 
+ static int __init sifive_l2_init(void)
+ {
+       struct device_node *np;
+       struct resource res;
++#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
+       int i, rc, intr_num;
++#endif
+ 
+       np = of_find_matching_node(NULL, sifive_l2_ids);
+       if (!np)
+@@ -249,6 +255,7 @@ static int __init sifive_l2_init(void)
+       if (!l2_base)
+               return -ENOMEM;
+ 
++#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
+       intr_num = of_property_count_u32_elems(np, "interrupts");
+       if (!intr_num) {
+               pr_err("L2CACHE: no interrupts property\n");
+@@ -263,6 +270,7 @@ static int __init sifive_l2_init(void)
+                       return rc;
+               }
+       }
++#endif
+ 
+       l2_config_read();
+ 

diff --git a/target/linux/visionfive/patches-5.15/0054-dt-bindings-clock-Add-JH7100-audio-clock-definitions.patch b/target/linux/visionfive/patches-5.15/0054-dt-bindings-clock-Add-JH7100-audio-clock-definitions.patch
deleted file mode 100644 (file)
index 949b23e..0000000
--- a/target/linux/visionfive/patches-5.15/0054-dt-bindings-clock-Add-JH7100-audio-clock-definitions.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From fb7d4d80584338afc786f87b85ef3476474893f5 Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Wed, 24 Nov 2021 01:33:43 +0100
-Subject: [PATCH 54/56] dt-bindings: clock: Add JH7100 audio clock definitions
-
-Add all clock outputs for the StarFive JH7100 audio clock generator.
-
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- .../dt-bindings/clock/starfive-jh7100-audio.h | 41 +++++++++++++++++++
- 1 file changed, 41 insertions(+)
- create mode 100644 include/dt-bindings/clock/starfive-jh7100-audio.h
-
-diff --git a/include/dt-bindings/clock/starfive-jh7100-audio.h b/include/dt-bindings/clock/starfive-jh7100-audio.h
-new file mode 100644
-index 000000000000..fbb4eae6572b
---- /dev/null
-+++ b/include/dt-bindings/clock/starfive-jh7100-audio.h
-@@ -0,0 +1,41 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
-+ */
-+
-+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
-+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
-+
-+#define JH7100_AUDCLK_ADC_MCLK                0
-+#define JH7100_AUDCLK_I2S1_MCLK               1
-+#define JH7100_AUDCLK_I2SADC_APB      2
-+#define JH7100_AUDCLK_I2SADC_BCLK     3
-+#define JH7100_AUDCLK_I2SADC_BCLK_N   4
-+#define JH7100_AUDCLK_I2SADC_LRCLK    5
-+#define JH7100_AUDCLK_PDM_APB         6
-+#define JH7100_AUDCLK_PDM_MCLK                7
-+#define JH7100_AUDCLK_I2SVAD_APB      8
-+#define JH7100_AUDCLK_SPDIF           9
-+#define JH7100_AUDCLK_SPDIF_APB               10
-+#define JH7100_AUDCLK_PWMDAC_APB      11
-+#define JH7100_AUDCLK_DAC_MCLK                12
-+#define JH7100_AUDCLK_I2SDAC_APB      13
-+#define JH7100_AUDCLK_I2SDAC_BCLK     14
-+#define JH7100_AUDCLK_I2SDAC_BCLK_N   15
-+#define JH7100_AUDCLK_I2SDAC_LRCLK    16
-+#define JH7100_AUDCLK_I2S1_APB                17
-+#define JH7100_AUDCLK_I2S1_BCLK               18
-+#define JH7100_AUDCLK_I2S1_BCLK_N     19
-+#define JH7100_AUDCLK_I2S1_LRCLK      20
-+#define JH7100_AUDCLK_I2SDAC16K_APB   21
-+#define JH7100_AUDCLK_APB0_BUS                22
-+#define JH7100_AUDCLK_DMA1P_AHB               23
-+#define JH7100_AUDCLK_USB_APB         24
-+#define JH7100_AUDCLK_USB_LPM         25
-+#define JH7100_AUDCLK_USB_STB         26
-+#define JH7100_AUDCLK_APB_EN          27
-+#define JH7100_AUDCLK_VAD_MEM         28
-+
-+#define JH7100_AUDCLK_END             29
-+
-+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ */
--- 
-2.30.2
-

diff --git a/target/linux/visionfive/patches-5.15/0054-sifive-sifive_l2_cache-Print-a-backtrace-on-out-of-r.patch b/target/linux/visionfive/patches-5.15/0054-sifive-sifive_l2_cache-Print-a-backtrace-on-out-of-r.patch
new file mode 100644 (file)
index 0000000..1dc8554
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0054-sifive-sifive_l2_cache-Print-a-backtrace-on-out-of-r.patch
@@ -0,0 +1,27 @@
+From bf4c658e0e113518a59beccf2f25c9e78a9e02d5 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Fri, 21 May 2021 08:35:33 +0200
+Subject: [PATCH 54/84] sifive/sifive_l2_cache: Print a backtrace on
+ out-of-range flushes
+
+This makes it easier to find out which driver passes a wrong address
+range.
+
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+---
+ drivers/soc/sifive/sifive_l2_cache.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/soc/sifive/sifive_l2_cache.c
++++ b/drivers/soc/sifive/sifive_l2_cache.c
+@@ -143,8 +143,8 @@ void sifive_l2_flush64_range(unsigned lo
+       if(start < CONFIG_SIFIVE_L2_FLUSH_START ||
+          (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START +
+                            CONFIG_SIFIVE_L2_FLUSH_SIZE)) {
+-              pr_warn("L2CACHE: flush64 out of range: %lx(%lx), skip flush\n",
+-                      start, len);
++              WARN(1, "L2CACHE: flush64 out of range: %lx(%lx), skip flush\n",
++                   start, len);
+               return;
+       }
+ 

diff --git a/target/linux/visionfive/patches-5.15/0055-dt-bindings-reset-Add-StarFive-JH7100-audio-reset-de.patch b/target/linux/visionfive/patches-5.15/0055-dt-bindings-reset-Add-StarFive-JH7100-audio-reset-de.patch
deleted file mode 100644 (file)
index da967c4..0000000
--- a/target/linux/visionfive/patches-5.15/0055-dt-bindings-reset-Add-StarFive-JH7100-audio-reset-de.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From e8ea9c809a8552d0553e447455f9df676496f7ac Mon Sep 17 00:00:00 2001
-From: Emil Renner Berthing <kernel@esmil.dk>
-Date: Sat, 20 Nov 2021 19:29:25 +0100
-Subject: [PATCH 55/56] dt-bindings: reset: Add StarFive JH7100 audio reset
- definitions
-
-Add all resets for the StarFive JH7100 audio reset controller.
-
-Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
----
- .../dt-bindings/reset/starfive-jh7100-audio.h | 31 +++++++++++++++++++
- 1 file changed, 31 insertions(+)
- create mode 100644 include/dt-bindings/reset/starfive-jh7100-audio.h
-
-diff --git a/include/dt-bindings/reset/starfive-jh7100-audio.h b/include/dt-bindings/reset/starfive-jh7100-audio.h
-new file mode 100644
-index 000000000000..30e3d4cf067a
---- /dev/null
-+++ b/include/dt-bindings/reset/starfive-jh7100-audio.h
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * Copyright (C) 2021 Emil Renner Berthing
-+ */
-+
-+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__
-+#define __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__
-+
-+#define JH7100_AUDRSTN_APB_BUS                0
-+#define JH7100_AUDRSTN_I2SADC_APB     1
-+#define JH7100_AUDRSTN_I2SADC_SRST    2
-+#define JH7100_AUDRSTN_PDM_APB                3
-+#define JH7100_AUDRSTN_I2SVAD_APB     4
-+#define JH7100_AUDRSTN_I2SVAD_SRST    5
-+#define JH7100_AUDRSTN_SPDIF_APB      6
-+#define JH7100_AUDRSTN_PWMDAC_APB     7
-+#define JH7100_AUDRSTN_I2SDAC_APB     8
-+#define JH7100_AUDRSTN_I2SDAC_SRST    9
-+#define JH7100_AUDRSTN_I2S1_APB               10
-+#define JH7100_AUDRSTN_I2S1_SRST      11
-+#define JH7100_AUDRSTN_I2SDAC16K_APB  12
-+#define JH7100_AUDRSTN_I2SDAC16K_SRST 13
-+#define JH7100_AUDRSTN_DMA1P_AHB      14
-+#define JH7100_AUDRSTN_USB_APB                15
-+#define JH7100_AUDRST_USB_AXI         16
-+#define JH7100_AUDRST_USB_PWRUP_RST_N 17
-+#define JH7100_AUDRST_USB_PONRST      18
-+
-+#define JH7100_AUDRSTN_END            19
-+
-+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__ */
--- 
-2.30.2
-

diff --git a/target/linux/visionfive/patches-5.15/0055-sifive-sifive_l2_cache-Align-the-address-to-cache-li.patch b/target/linux/visionfive/patches-5.15/0055-sifive-sifive_l2_cache-Align-the-address-to-cache-li.patch
new file mode 100644 (file)
index 0000000..624440f
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0055-sifive-sifive_l2_cache-Align-the-address-to-cache-li.patch
@@ -0,0 +1,25 @@
+From 24e2c7bb8713ae3dc6e5cac12970b1c888f3fae6 Mon Sep 17 00:00:00 2001
+From: Atish Patra <atish.patra@wdc.com>
+Date: Sat, 12 Jun 2021 16:52:26 -0700
+Subject: [PATCH 55/84] sifive/sifive_l2_cache: Align the address to cache line
+
+[Emil: fix suggested by Geert Uytterhoeven <geert@linux-m68k.org>]
+
+Signed-off-by: Atish Patra <atish.patra@wdc.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/soc/sifive/sifive_l2_cache.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/soc/sifive/sifive_l2_cache.c
++++ b/drivers/soc/sifive/sifive_l2_cache.c
+@@ -139,6 +139,9 @@ void sifive_l2_flush64_range(unsigned lo
+               return;
+       }
+ 
++      len = len + (start % SIFIVE_L2_FLUSH64_LINE_LEN);
++      start = ALIGN_DOWN(start, SIFIVE_L2_FLUSH64_LINE_LEN);
++
+       /* make sure the address is in the range */
+       if(start < CONFIG_SIFIVE_L2_FLUSH_START ||
+          (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START +

diff --git a/target/linux/visionfive/patches-5.15/0056-drivers-tty-serial-8250-update-driver-for-JH7100.patch b/target/linux/visionfive/patches-5.15/0056-drivers-tty-serial-8250-update-driver-for-JH7100.patch
new file mode 100644 (file)
index 0000000..c96240c
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0056-drivers-tty-serial-8250-update-driver-for-JH7100.patch
@@ -0,0 +1,28 @@
+From a7f7126083192dd40010d5f29fbe3ed25eb20cb8 Mon Sep 17 00:00:00 2001
+From: Samin Guo <samin.guo@starfivetech.com>
+Date: Fri, 8 Jan 2021 03:11:04 +0800
+Subject: [PATCH 56/84] drivers/tty/serial/8250: update driver for JH7100
+
+---
+ drivers/tty/serial/8250/8250_port.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/tty/serial/8250/8250_port.c
++++ b/drivers/tty/serial/8250/8250_port.c
+@@ -73,8 +73,16 @@ static const struct serial8250_config ua
+       },
+       [PORT_16550] = {
+               .name           = "16550",
++#ifdef CONFIG_SOC_STARFIVE
++              .fifo_size      = 16,
++              .tx_loadsz      = 16,
++              .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
++              .rxtrig_bytes   = {1, 4, 8, 14},
++              .flags          = UART_CAP_FIFO,
++#else
+               .fifo_size      = 1,
+               .tx_loadsz      = 1,
++#endif
+       },
+       [PORT_16550A] = {
+               .name           = "16550A",

diff --git a/target/linux/visionfive/patches-5.15/0056-serial-8250_lpss-Extract-dw8250_do_set_termios-for-c.patch b/target/linux/visionfive/patches-5.15/0056-serial-8250_lpss-Extract-dw8250_do_set_termios-for-c.patch
deleted file mode 100644 (file)
index aabf9ee..0000000
--- a/target/linux/visionfive/patches-5.15/0056-serial-8250_lpss-Extract-dw8250_do_set_termios-for-c.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From f8dcbd2b842cf77ea5acabe189fc580738ba5966 Mon Sep 17 00:00:00 2001
-From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
-Date: Tue, 5 Oct 2021 16:30:25 +0300
-Subject: [PATCH 56/56] serial: 8250_lpss: Extract dw8250_do_set_termios() for
- common use
-
-Some of the code currently used in dw8250_set_termios(), byt_set_termios()
-may be reused by other methods in the future. Extract it to a common helper
-function.
-
-Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
-Link: https://lore.kernel.org/r/20211005133026.21488-1-andriy.shevchenko@linux.intel.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/tty/serial/8250/8250_dw.c    |  6 +-----
- drivers/tty/serial/8250/8250_dwlib.c | 10 ++++++++++
- drivers/tty/serial/8250/8250_dwlib.h |  1 +
- drivers/tty/serial/8250/8250_lpss.c  |  6 +-----
- 4 files changed, 13 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
-index 8d93ccbb434d..1687f178b5e4 100644
---- a/drivers/tty/serial/8250/8250_dw.c
-+++ b/drivers/tty/serial/8250/8250_dw.c
-@@ -350,11 +350,7 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
-       }
-       clk_prepare_enable(d->clk);
- 
--      p->status &= ~UPSTAT_AUTOCTS;
--      if (termios->c_cflag & CRTSCTS)
--              p->status |= UPSTAT_AUTOCTS;
--
--      serial8250_do_set_termios(p, termios, old);
-+      dw8250_do_set_termios(p, termios, old);
- }
- 
- static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
-diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c
-index 6d6a78eead3e..622d3b0d89e7 100644
---- a/drivers/tty/serial/8250/8250_dwlib.c
-+++ b/drivers/tty/serial/8250/8250_dwlib.c
-@@ -77,6 +77,16 @@ static void dw8250_set_divisor(struct uart_port *p, unsigned int baud,
-       serial8250_do_set_divisor(p, baud, quot, quot_frac);
- }
- 
-+void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old)
-+{
-+      p->status &= ~UPSTAT_AUTOCTS;
-+      if (termios->c_cflag & CRTSCTS)
-+              p->status |= UPSTAT_AUTOCTS;
-+
-+      serial8250_do_set_termios(p, termios, old);
-+}
-+EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
-+
- void dw8250_setup_port(struct uart_port *p)
- {
-       struct uart_8250_port *up = up_to_u8250p(p);
-diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
-index 9a12953832d3..83d528e5cc21 100644
---- a/drivers/tty/serial/8250/8250_dwlib.h
-+++ b/drivers/tty/serial/8250/8250_dwlib.h
-@@ -16,4 +16,5 @@ struct dw8250_port_data {
-       u8                      dlf_size;
- };
- 
-+void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old);
- void dw8250_setup_port(struct uart_port *p);
-diff --git a/drivers/tty/serial/8250/8250_lpss.c b/drivers/tty/serial/8250/8250_lpss.c
-index 49ae73f4d3a0..022b6359aadf 100644
---- a/drivers/tty/serial/8250/8250_lpss.c
-+++ b/drivers/tty/serial/8250/8250_lpss.c
-@@ -100,11 +100,7 @@ static void byt_set_termios(struct uart_port *p, struct ktermios *termios,
-       reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
-       writel(reg, p->membase + BYT_PRV_CLK);
- 
--      p->status &= ~UPSTAT_AUTOCTS;
--      if (termios->c_cflag & CRTSCTS)
--              p->status |= UPSTAT_AUTOCTS;
--
--      serial8250_do_set_termios(p, termios, old);
-+      dw8250_do_set_termios(p, termios, old);
- }
- 
- static unsigned int byt_get_mctrl(struct uart_port *port)
--- 
-2.30.2
-

diff --git a/target/linux/visionfive/patches-5.15/0057-drivers-pwm-Add-SiFive-PWM-PTC-driver.patch b/target/linux/visionfive/patches-5.15/0057-drivers-pwm-Add-SiFive-PWM-PTC-driver.patch
new file mode 100644 (file)
index 0000000..27cef38
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0057-drivers-pwm-Add-SiFive-PWM-PTC-driver.patch
@@ -0,0 +1,336 @@
+From 65bbb5cab826a9e1b4201d64055520a1cabd24a4 Mon Sep 17 00:00:00 2001
+From: Chenjieqin <Jessica.Chen@starfivetech.com>
+Date: Fri, 8 Jan 2021 03:56:54 +0800
+Subject: [PATCH 57/84] drivers/pwm: Add SiFive PWM PTC driver
+
+---
+ drivers/pwm/Kconfig          |  11 ++
+ drivers/pwm/Makefile         |   1 +
+ drivers/pwm/pwm-sifive-ptc.c | 291 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 303 insertions(+)
+ create mode 100644 drivers/pwm/pwm-sifive-ptc.c
+
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -492,6 +492,17 @@ config PWM_SIFIVE
+         To compile this driver as a module, choose M here: the module
+         will be called pwm-sifive.
+ 
++config PWM_SIFIVE_PTC
++      tristate "SiFive PWM PTC support"
++      depends on SOC_SIFIVE || SOC_STARFIVE || COMPILE_TEST
++      depends on OF
++      depends on COMMON_CLK
++      help
++        Generic PWM framework driver for SiFive SoCs.
++
++        To compile this driver as a module, choose M here: the module
++        will be called pwm-sifive-ptc.
++
+ config PWM_SL28CPLD
+       tristate "Kontron sl28cpld PWM support"
+       depends on MFD_SL28CPLD || COMPILE_TEST
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -45,6 +45,7 @@ obj-$(CONFIG_PWM_RENESAS_TPU)        += pwm-ren
+ obj-$(CONFIG_PWM_ROCKCHIP)    += pwm-rockchip.o
+ obj-$(CONFIG_PWM_SAMSUNG)     += pwm-samsung.o
+ obj-$(CONFIG_PWM_SIFIVE)      += pwm-sifive.o
++obj-$(CONFIG_PWM_SIFIVE_PTC)  += pwm-sifive-ptc.o
+ obj-$(CONFIG_PWM_SL28CPLD)    += pwm-sl28cpld.o
+ obj-$(CONFIG_PWM_SPEAR)               += pwm-spear.o
+ obj-$(CONFIG_PWM_SPRD)                += pwm-sprd.o
+--- /dev/null
++++ b/drivers/pwm/pwm-sifive-ptc.c
+@@ -0,0 +1,291 @@
++/*
++ * Copyright (C) 2018 SiFive, Inc
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2, as published by
++ * the Free Software Foundation.
++ */
++
++#include <dt-bindings/pwm/pwm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/pwm.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++
++#define PTC_DEBUG                     0
++
++/* max channel of pwm */
++#define MAX_PWM                               8
++
++/* PTC Register offsets */
++#define REG_RPTC_CNTR                 0x0
++#define REG_RPTC_HRC                  0x4
++#define REG_RPTC_LRC                  0x8
++#define REG_RPTC_CTRL                 0xC
++
++/* Bit for PWM clock */
++#define BIT_PWM_CLOCK_EN              31
++
++/* Bit for clock gen soft reset */
++#define BIT_CLK_GEN_SOFT_RESET                13
++
++#define NS_1                          1000000000
++
++/* Access PTC register (cntr hrc lrc and ctrl) ,need to replace PWM_BASE_ADDR */
++#define REG_PTC_BASE_ADDR_SUB(base, N)        ((base) + ((N>3)?((N-4)*0x10+(1<<15)):(N*0x10)))
++#define REG_PTC_RPTC_CNTR(base,N)     (REG_PTC_BASE_ADDR_SUB(base,N))
++#define REG_PTC_RPTC_HRC(base,N)      (REG_PTC_BASE_ADDR_SUB(base,N) + 0x4)
++#define REG_PTC_RPTC_LRC(base,N)      (REG_PTC_BASE_ADDR_SUB(base,N) + 0x8)
++#define REG_PTC_RPTC_CTRL(base,N)     (REG_PTC_BASE_ADDR_SUB(base,N) + 0xC)
++
++/* pwm ptc device */
++struct sifive_pwm_ptc_device {
++      struct pwm_chip chip;
++      struct clk      *clk;
++      void __iomem    *regs;
++      int             irq;
++      /* apb clock frequency , from dts */
++      unsigned int    approx_period;
++};
++
++static inline struct sifive_pwm_ptc_device *chip_to_sifive_ptc(struct pwm_chip *c)
++{
++      return container_of(c, struct sifive_pwm_ptc_device, chip);
++}
++
++
++static void sifive_pwm_ptc_get_state(struct pwm_chip *chip, struct pwm_device *dev, struct pwm_state *state)
++{
++      struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
++      uint32_t data_lrc;
++      uint32_t data_hrc;
++      uint32_t pwm_clk_ns = 0;
++
++      /* get lrc and hrc data from registe*/
++      data_lrc = ioread32(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
++      data_hrc = ioread32(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
++
++      /* how many ns does apb clock elapse */
++      pwm_clk_ns = NS_1 / pwm->approx_period;
++
++      /* pwm period(ns) */
++      state->period     = data_lrc*pwm_clk_ns;
++
++      /* duty cycle(ns) ,means high level eclapse ns if it is normal polarity */
++      state->duty_cycle = data_hrc*pwm_clk_ns;
++
++      /* polarity,we don't use it now because it is not in dts */
++      state->polarity   = PWM_POLARITY_NORMAL;
++
++      /* enabled or not */
++      state->enabled    = 1;
++#ifdef PTC_DEBUG
++      printk("sifive_pwm_ptc_get_state in,no:%d....\r\n",dev->hwpwm);
++      printk("data_hrc:0x%x 0x%x \n", data_hrc, data_lrc);
++      printk("period:%llu\r\n",state->period);
++      printk("duty_cycle:%llu\r\n",state->duty_cycle);
++      printk("polarity:%d\r\n",state->polarity);
++      printk("enabled:%d\r\n",state->enabled);
++#endif
++}
++
++
++static int sifive_pwm_ptc_apply(struct pwm_chip *chip, struct pwm_device *dev, struct pwm_state *state)
++{
++      struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
++      uint32_t pwm_clk_ns = 0;
++      uint32_t data_hrc = 0;
++      uint32_t data_lrc = 0;
++      uint32_t period_data = 0;
++      uint32_t duty_data = 0;
++      void __iomem* reg_addr;
++
++#if PTC_DEBUG
++      printk("sifive_pwm_ptc_apply in,no:%d....\r\n",dev->hwpwm);
++      printk("set parameter......\r\n");
++      printk("period:%d\r\n",state->period);
++      printk("duty_cycle:%d\r\n",state->duty_cycle);
++      printk("polarity:%d\r\n",state->polarity);
++      printk("enabled:%d\r\n",state->enabled);
++#endif
++      /* duty_cycle should be less or equal than period */
++      if(state->duty_cycle > state->period)
++              state->duty_cycle = state->period;
++
++      /* calculate pwm real period (ns) */
++      pwm_clk_ns = NS_1 / pwm->approx_period;
++
++#if PTC_DEBUG
++      printk("approx_period,:%d,pwm_clk_ns:%d\r\n",pwm->approx_period,pwm_clk_ns);
++#endif
++
++      /* calculate period count */
++      period_data = state->period / pwm_clk_ns;
++
++      if (!state->enabled)
++              /* if is unenable,just set duty_dat to 0 , means low level always */
++              duty_data = 0;
++      else
++              /* calculate duty count*/
++              duty_data = state->duty_cycle / pwm_clk_ns;
++
++#if PTC_DEBUG
++      printk("period_data:%d,duty_data:%d\r\n",period_data,duty_data);
++#endif
++
++      if(state->polarity == PWM_POLARITY_NORMAL)
++              /* calculate data_hrc */
++              data_hrc = period_data - duty_data;
++      else
++              /* calculate data_hrc */
++              data_hrc = duty_data;
++
++      data_lrc = period_data;
++
++      /* set hrc */
++      reg_addr = REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm);
++#if PTC_DEBUG
++      printk("[sifive_pwm_ptc_config]reg_addr:0x%lx,data:%d....\n",reg_addr,data_hrc);
++#endif
++      iowrite32(data_hrc, reg_addr);
++
++#if PTC_DEBUG
++      printk("[sifive_pwm_ptc_config]hrc ok....\n");
++#endif
++
++      /* set lrc */
++      reg_addr = REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm);
++#if PTC_DEBUG
++      printk("[sifive_pwm_ptc_config]reg_addr:0x%lx,data:%d....\n",reg_addr,data_lrc);
++#endif
++
++      iowrite32(data_lrc, reg_addr);
++
++#if PTC_DEBUG
++      printk("[sifive_pwm_ptc_config]lrc ok....\n");
++#endif
++
++      return 0;
++}
++
++
++
++static const struct pwm_ops sifive_pwm_ptc_ops = {
++      .get_state      = sifive_pwm_ptc_get_state,
++      .apply          = (void *)sifive_pwm_ptc_apply,
++      .owner          = THIS_MODULE,
++};
++
++
++
++
++static int sifive_pwm_ptc_probe(struct platform_device *pdev)
++{
++      struct device *dev = &pdev->dev;
++      struct device_node *node = pdev->dev.of_node;
++      struct sifive_pwm_ptc_device *pwm;
++      struct pwm_chip *chip;
++      struct resource *res;
++      int ret;
++
++#if PTC_DEBUG
++      printk("sifive_pwm_ptc_probe in....\r\n");
++#endif
++      pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
++      if (!pwm) {
++              dev_err(dev, "Out of memory\n");
++              return -ENOMEM;
++      }
++
++      chip = &pwm->chip;
++      chip->dev = dev;
++      chip->ops = &sifive_pwm_ptc_ops;
++
++      /* how many parameters can be transfered to ptc,need to fix */
++      chip->of_pwm_n_cells = 3;
++      chip->base = -1;
++
++      /* get pwm channels count, max value is 8 */
++      ret = of_property_read_u32(node, "starfive,npwm", &chip->npwm);
++      if (ret < 0 || chip->npwm > MAX_PWM)
++              chip->npwm = MAX_PWM;
++
++#if PTC_DEBUG
++      printk("[sifive_pwm_ptc_probe] npwm:0x%lx....\r\n",chip->npwm);
++#endif
++      /* get apb clock frequency */
++      ret = of_property_read_u32(node, "sifive,approx-period", &pwm->approx_period);
++
++#if PTC_DEBUG
++      printk("[sifive_pwm_ptc_probe] approx_period:%d....\r\n",pwm->approx_period);
++#endif
++      /* get IO base address*/
++      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++#if PTC_DEBUG
++      printk("[sifive_pwm_ptc_probe] res start:0x%lx,end:0x%lx....\r\n",res->start,res->end);
++#endif
++      pwm->regs = devm_ioremap_resource(dev, res);
++      if (IS_ERR(pwm->regs))
++      {
++              dev_err(dev, "Unable to map IO resources\n");
++              return PTR_ERR(pwm->regs);
++      }
++
++#if PTC_DEBUG
++      printk("[sifive_pwm_ptc_probe] regs:0x%lx....\r\n",pwm->regs);
++#endif
++
++      pwm->clk = devm_clk_get(dev, NULL);
++      if (IS_ERR(pwm->clk)) {
++              dev_err(dev, "Unable to find controller clock\n");
++              return PTR_ERR(pwm->clk);
++      }
++
++      /* after add,it will display as /sys/class/pwm/pwmchip0,0 is chip->base
++       * after execute echo 0 > export in  , pwm0 can be seen */
++      ret = pwmchip_add(chip);
++      if (ret < 0) {
++              dev_err(dev, "cannot register PTC: %d\n", ret);
++              return ret;
++      }
++
++      platform_set_drvdata(pdev, pwm);
++
++#if PTC_DEBUG
++      printk("SiFive PWM PTC chip registered %d PWMs\n", chip->npwm);
++#endif
++
++      return 0;
++}
++
++static int sifive_pwm_ptc_remove(struct platform_device *dev)
++{
++      struct sifive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
++      struct pwm_chip *chip = &pwm->chip;
++
++      pwmchip_remove(chip);
++      return 0;
++}
++
++static const struct of_device_id sifive_pwm_ptc_of_match[] = {
++      { .compatible = "sifive,pwm0" },
++      { .compatible = "starfive,pwm0" },
++      { },
++};
++MODULE_DEVICE_TABLE(of, sifive_pwm_ptc_of_match);
++
++static struct platform_driver sifive_pwm_ptc_driver = {
++      .probe = sifive_pwm_ptc_probe,
++      .remove = sifive_pwm_ptc_remove,
++      .driver = {
++              .name = "pwm-sifive-ptc",
++              .of_match_table = of_match_ptr(sifive_pwm_ptc_of_match),
++      },
++};
++module_platform_driver(sifive_pwm_ptc_driver);
++
++MODULE_DESCRIPTION("SiFive PWM PTC driver");
++MODULE_LICENSE("GPL v2");

diff --git a/target/linux/visionfive/patches-5.15/0058-drivers-pwm-pwm-sifive-ptc-Clear-PWM-CNTR.patch b/target/linux/visionfive/patches-5.15/0058-drivers-pwm-pwm-sifive-ptc-Clear-PWM-CNTR.patch
new file mode 100644 (file)
index 0000000..de829b8
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0058-drivers-pwm-pwm-sifive-ptc-Clear-PWM-CNTR.patch
@@ -0,0 +1,23 @@
+From aa2d8aa99a833c08beb7efe05c6a620f35fcd01c Mon Sep 17 00:00:00 2001
+From: "yiming.li" <yiming.li@starfivetech.com>
+Date: Tue, 16 Mar 2021 01:45:19 +0800
+Subject: [PATCH 58/84] drivers/pwm/pwm-sifive-ptc: Clear PWM CNTR
+
+Clear CNTR of PWM after setting period & duty_cycle
+---
+ drivers/pwm/pwm-sifive-ptc.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/pwm/pwm-sifive-ptc.c
++++ b/drivers/pwm/pwm-sifive-ptc.c
+@@ -167,6 +167,10 @@ static int sifive_pwm_ptc_apply(struct p
+       printk("[sifive_pwm_ptc_config]lrc ok....\n");
+ #endif
+ 
++      /* Clear REG_RPTC_CNTR after setting period & duty_cycle*/
++      reg_addr = REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm);
++      iowrite32(0, reg_addr);
++
+       return 0;
+ }
+ 

diff --git a/target/linux/visionfive/patches-5.15/0059-WIP-dt-bindings-dma-dw-axi-dmac-Increase-DMA-channel.patch b/target/linux/visionfive/patches-5.15/0059-WIP-dt-bindings-dma-dw-axi-dmac-Increase-DMA-channel.patch
new file mode 100644 (file)
index 0000000..17f7594
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0059-WIP-dt-bindings-dma-dw-axi-dmac-Increase-DMA-channel.patch
@@ -0,0 +1,45 @@
+From 1fb888eac86296d7d93a338b40b3e2f1a6b774b6 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Thu, 27 May 2021 20:13:43 +0200
+Subject: [PATCH 59/84] [WIP] dt-bindings: dma: dw-axi-dmac: Increase DMA
+ channel limit to 16
+
+The first DMAC instance in the StarFive JH7100 SoC supports 16 DMA
+channels.
+
+FIXME Given there are more changes to the driver than just increasing
+      DMAC_MAX_CHANNELS, we probably need a new compatible value, too.
+
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+---
+ Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
++++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+@@ -51,7 +51,7 @@ properties:
+ 
+   dma-channels:
+     minimum: 1
+-    maximum: 8
++    maximum: 16
+ 
+   snps,dma-masters:
+     description: |
+@@ -71,14 +71,14 @@ properties:
+       Channel priority specifier associated with the DMA channels.
+     $ref: /schemas/types.yaml#/definitions/uint32-array
+     minItems: 1
+-    maxItems: 8
++    maxItems: 16
+ 
+   snps,block-size:
+     description: |
+       Channel block size specifier associated with the DMA channels.
+     $ref: /schemas/types.yaml#/definitions/uint32-array
+     minItems: 1
+-    maxItems: 8
++    maxItems: 16
+ 
+   snps,axi-max-burst-len:
+     description: |

diff --git a/target/linux/visionfive/patches-5.15/0060-dmaengine-dw-axi-dmac-Fix-RMW-on-channel-suspend-reg.patch b/target/linux/visionfive/patches-5.15/0060-dmaengine-dw-axi-dmac-Fix-RMW-on-channel-suspend-reg.patch
new file mode 100644 (file)
index 0000000..33c5395
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0060-dmaengine-dw-axi-dmac-Fix-RMW-on-channel-suspend-reg.patch
@@ -0,0 +1,46 @@
+From e2a58411cae031fe061d1de2afe1721a09007d33 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Fri, 17 Dec 2021 14:47:47 +0100
+Subject: [PATCH 60/84] dmaengine: dw-axi-dmac: Fix RMW on channel suspend
+ register
+
+Found by comparing the parallel implementation of more than 8 channel
+support for the StarFive JH7100 SoC by Samin.
+
+Fixes: 824351668a41 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8")
+Co-developed-by: Samin Guo <samin.guo@starfivetech.com>
+Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+@@ -1164,8 +1164,9 @@ static int dma_chan_pause(struct dma_cha
+                       BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
+               axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
+       } else {
+-              val = BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
+-                    BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
++              val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
++              val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
++                      BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
+               axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
+       }
+ 
+@@ -1190,12 +1191,13 @@ static inline void axi_chan_resume(struc
+ {
+       u32 val;
+ 
+-      val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
+       if (chan->chip->dw->hdata->reg_map_8_channels) {
++              val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
+               val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
+               val |=  (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
+               axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
+       } else {
++              val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
+               val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT);
+               val |=  (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT);
+               axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);

diff --git a/target/linux/visionfive/patches-5.15/0061-dmaengine-dw-axi-dmac-Handle-xfer-start-while-non-id.patch b/target/linux/visionfive/patches-5.15/0061-dmaengine-dw-axi-dmac-Handle-xfer-start-while-non-id.patch
new file mode 100644 (file)
index 0000000..01fdd5a
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0061-dmaengine-dw-axi-dmac-Handle-xfer-start-while-non-id.patch
@@ -0,0 +1,63 @@
+From c035b9b81a56bf9f267be57e5a733ad9ca8bec31 Mon Sep 17 00:00:00 2001
+From: Samin Guo <samin.guo@starfivetech.com>
+Date: Wed, 17 Nov 2021 14:50:45 +0800
+Subject: [PATCH 61/84] dmaengine: dw-axi-dmac: Handle xfer start while
+ non-idle
+
+Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
+Signed-off-by: Curry Zhang <curry.zhang@starfivetech.com>
+---
+ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 13 ++++++++++++-
+ drivers/dma/dw-axi-dmac/dw-axi-dmac.h          |  1 +
+ 2 files changed, 13 insertions(+), 1 deletion(-)
+
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+@@ -377,11 +377,13 @@ static void axi_chan_block_xfer_start(st
+       u32 irq_mask;
+       u8 lms = 0; /* Select AXI0 master for LLI fetching */
+ 
++      chan->is_err = false;
+       if (unlikely(axi_chan_is_hw_enable(chan))) {
+               dev_err(chan2dev(chan), "%s is non-idle!\n",
+                       axi_chan_name(chan));
+ 
+-              return;
++              axi_chan_disable(chan);
++              chan->is_err = true;
+       }
+ 
+       axi_dma_enable(chan->chip);
+@@ -1013,6 +1015,14 @@ static noinline void axi_chan_handle_err
+ 
+       /* The bad descriptor currently is in the head of vc list */
+       vd = vchan_next_desc(&chan->vc);
++      if (chan->is_err) {
++              struct axi_dma_desc *desc = vd_to_axi_desc(vd);
++
++              axi_chan_block_xfer_start(chan, desc);
++              chan->is_err = false;
++              goto out;
++      }
++
+       /* Remove the completed descriptor from issued list */
+       list_del(&vd->node);
+ 
+@@ -1027,6 +1037,7 @@ static noinline void axi_chan_handle_err
+       /* Try to restart the controller */
+       axi_chan_start_first_queued(chan);
+ 
++out:
+       spin_unlock_irqrestore(&chan->vc.lock, flags);
+ }
+ 
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+@@ -49,6 +49,7 @@ struct axi_dma_chan {
+       struct dma_slave_config         config;
+       enum dma_transfer_direction     direction;
+       bool                            cyclic;
++      bool                            is_err;
+       /* these other elements are all protected by vc.lock */
+       bool                            is_paused;
+ };

diff --git a/target/linux/visionfive/patches-5.15/0062-dmaengine-dw-axi-dmac-Add-StarFive-JH7100-support.patch b/target/linux/visionfive/patches-5.15/0062-dmaengine-dw-axi-dmac-Add-StarFive-JH7100-support.patch
new file mode 100644 (file)
index 0000000..ad68262
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0062-dmaengine-dw-axi-dmac-Add-StarFive-JH7100-support.patch
@@ -0,0 +1,63 @@
+From a3d4bd5e48a3e2211d2f2c83b159a082eefe3d9a Mon Sep 17 00:00:00 2001
+From: Samin Guo <samin.guo@starfivetech.com>
+Date: Wed, 17 Nov 2021 14:50:45 +0800
+Subject: [PATCH 62/84] dmaengine: dw-axi-dmac: Add StarFive JH7100 support
+
+Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 11 ++++++++++-
+ drivers/dma/dw-axi-dmac/dw-axi-dmac.h          |  4 ++++
+ 2 files changed, 14 insertions(+), 1 deletion(-)
+
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+@@ -86,7 +86,7 @@ static inline void axi_chan_config_write
+ 
+       cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
+                 config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
+-      if (chan->chip->dw->hdata->reg_map_8_channels) {
++      if (!IS_ENABLED(CONFIG_SOC_STARFIVE) && chan->chip->dw->hdata->reg_map_8_channels) {
+               cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
+                        config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
+                        config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
+@@ -672,8 +672,13 @@ static int dw_axi_dma_set_hw_desc(struct
+ 
+       hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
+ 
++#ifdef CONFIG_SOC_STARFIVE
++      ctllo |= DWAXIDMAC_BURST_TRANS_LEN_16 << CH_CTL_L_DST_MSIZE_POS |
++               DWAXIDMAC_BURST_TRANS_LEN_16 << CH_CTL_L_SRC_MSIZE_POS;
++#else
+       ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
+                DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
++#endif
+       hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
+ 
+       set_desc_src_master(hw_desc);
+@@ -1473,7 +1478,11 @@ static int dw_probe(struct platform_devi
+        * Therefore, set constraint to 1024 * 4.
+        */
+       dw->dma.dev->dma_parms = &dw->dma_parms;
++#ifdef CONFIG_SOC_STARFIVE
++      dma_set_max_seg_size(&pdev->dev, DMAC_MAX_BLK_SIZE);
++#else
+       dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
++#endif
+       platform_set_drvdata(pdev, chip);
+ 
+       pm_runtime_enable(chip->dev);
+--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+@@ -282,7 +282,11 @@ enum {
+ #define CH_CTL_L_SRC_MAST             BIT(0)
+ 
+ /* CH_CFG_H */
++#ifdef CONFIG_SOC_STARFIVE
++#define CH_CFG_H_PRIORITY_POS         15
++#else
+ #define CH_CFG_H_PRIORITY_POS         17
++#endif
+ #define CH_CFG_H_DST_PER_POS          12
+ #define CH_CFG_H_SRC_PER_POS          7
+ #define CH_CFG_H_HS_SEL_DST_POS               4

diff --git a/target/linux/visionfive/patches-5.15/0063-dmaengine-Add-dw-axi-dmac-starfive-driver-for-JH7100.patch b/target/linux/visionfive/patches-5.15/0063-dmaengine-Add-dw-axi-dmac-starfive-driver-for-JH7100.patch
new file mode 100644 (file)
index 0000000..455c58a
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0063-dmaengine-Add-dw-axi-dmac-starfive-driver-for-JH7100.patch
@@ -0,0 +1,701 @@
+From b78bf7781920f785e645a60b2038ccfcdbf764b1 Mon Sep 17 00:00:00 2001
+From: Tom <support@vamrs.com>
+Date: Fri, 8 Jan 2021 02:57:50 +0800
+Subject: [PATCH 63/84] dmaengine: Add dw-axi-dmac-starfive driver for JH7100
+
+---
+ drivers/dma/Kconfig                           |   7 +
+ drivers/dma/Makefile                          |   1 +
+ drivers/dma/dw-axi-dmac-starfive/Makefile     |   2 +
+ .../dw-axi-dmac-starfive-misc.c               | 323 ++++++++++++++++++
+ .../starfive_dmaengine_memcpy.c               | 288 ++++++++++++++++
+ include/soc/starfive/jh7100_dma.h             |  31 ++
+ 6 files changed, 652 insertions(+)
+ create mode 100644 drivers/dma/dw-axi-dmac-starfive/Makefile
+ create mode 100644 drivers/dma/dw-axi-dmac-starfive/dw-axi-dmac-starfive-misc.c
+ create mode 100644 drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c
+ create mode 100644 include/soc/starfive/jh7100_dma.h
+
+--- a/drivers/dma/Kconfig
++++ b/drivers/dma/Kconfig
+@@ -181,6 +181,13 @@ config DW_AXI_DMAC
+         NOTE: This driver wasn't tested on 64 bit platform because
+         of lack 64 bit platform with Synopsys DW AXI DMAC.
+ 
++config DW_AXI_DMAC_STARFIVE
++      tristate "Synopsys DesignWare AXI DMA support for StarFive SOC"
++      depends on SOC_STARFIVE
++      help
++        Enable support for Synopsys DesignWare AXI DMA controller.
++        NOTE: It's for StarFive SOC.
++
+ config EP93XX_DMA
+       bool "Cirrus Logic EP93xx DMA support"
+       depends on ARCH_EP93XX || COMPILE_TEST
+--- a/drivers/dma/Makefile
++++ b/drivers/dma/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
+ obj-$(CONFIG_DMA_SUN4I) += sun4i-dma.o
+ obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
+ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
++obj-$(CONFIG_DW_AXI_DMAC_STARFIVE) += dw-axi-dmac-starfive/
+ obj-$(CONFIG_DW_DMAC_CORE) += dw/
+ obj-$(CONFIG_DW_EDMA) += dw-edma/
+ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
+--- /dev/null
++++ b/drivers/dma/dw-axi-dmac-starfive/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0-only
++obj-$(CONFIG_DW_AXI_DMAC_STARFIVE) += starfive_dmaengine_memcpy.o dw-axi-dmac-starfive-misc.o
+\ No newline at end of file
+--- /dev/null
++++ b/drivers/dma/dw-axi-dmac-starfive/dw-axi-dmac-starfive-misc.c
+@@ -0,0 +1,323 @@
++/*
++ * Copyright 2020 StarFive, Inc <samin.guo@starfivetech.com>
++ *
++ * DW AXI dma driver for StarFive SoC VIC7100.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation, version 2.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#include <asm/uaccess.h>
++#include <linux/dmaengine.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/miscdevice.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/string.h>
++#include <linux/types.h>
++#include <linux/uaccess.h>
++
++#include <soc/sifive/sifive_l2_cache.h>
++#include <soc/starfive/jh7100_dma.h>
++
++#define DRIVER_NAME                   "dwaxidma"
++#define AXIDMA_IOC_MAGIC              'A'
++#define AXIDMA_IOCGETCHN              _IO(AXIDMA_IOC_MAGIC, 0)
++#define AXIDMA_IOCCFGANDSTART         _IO(AXIDMA_IOC_MAGIC, 1)
++#define AXIDMA_IOCGETSTATUS           _IO(AXIDMA_IOC_MAGIC, 2)
++#define AXIDMA_IOCRELEASECHN          _IO(AXIDMA_IOC_MAGIC, 3)
++
++#define AXI_DMA_MAX_CHANS             20
++
++#define DMA_CHN_UNUSED                        0
++#define DMA_CHN_USED                  1
++#define DMA_STATUS_UNFINISHED         0
++#define DMA_STATUS_FINISHED           1
++
++/* for DEBUG*/
++//#define DW_DMA_CHECK_RESULTS
++//#define DW_DMA_PRINT_MEM
++//#define DW_DMA_FLUSH_DESC
++
++struct axidma_chncfg {
++      unsigned long src_addr; /*dma addr*/
++      unsigned long dst_addr; /*dma addr*/
++      unsigned long virt_src; /*mmap src addr*/
++      unsigned long virt_dst; /*mmap dst addr*/
++      unsigned long phys;     /*desc phys addr*/
++      unsigned int len;       /*transport lenth*/
++      int mem_fd;             /*fd*/
++      unsigned char chn_num;  /*dma channels number*/
++      unsigned char status;   /*dma transport status*/
++};
++
++struct axidma_chns {
++      struct dma_chan *dma_chan;
++      unsigned char used;
++      unsigned char status;
++      unsigned char reserve[2];
++};
++
++struct axidma_chns channels[AXI_DMA_MAX_CHANS];
++#ifdef DW_DMA_PRINT_MEM
++void print_in_line_u64(u8 *p_name, u64 *p_buf, u32 len)
++{
++      u32 i, j;
++      u32 line;
++      u32* ptmp;
++      u32 len_tmp;
++      u32 rest = len / 4;
++
++      printk("%s: 0x%#llx, 0x%x\n",
++              p_name, dw_virt_to_phys((void *)p_buf), len);
++
++      if(len >= 0x1000)
++              len_tmp = 0x1000 / 32;  //print 128 size of memory.
++      else
++              len_tmp = len / 8;      //print real 100% size of memory.
++
++      rest = len / 4;                 //one line print 8 u32
++
++      for (i = 0; i < len_tmp; i += 4, rest -= line) {
++              if (!(i % 4))
++                      printk(KERN_CONT KERN_INFO" %#llx: ",
++                              dw_virt_to_phys((void *)(p_buf + i)));
++
++              ptmp = (u32*)(p_buf + i);
++              line = (rest > 8) ? 8 : rest;
++
++              for (j = 0; j < line; j++)
++                      printk(KERN_CONT KERN_INFO "%08x ", *(ptmp + j));
++
++              printk(KERN_CONT KERN_INFO"\n");
++      }
++}
++#endif
++
++static int axidma_open(struct inode *inode, struct file *file)
++{
++      /*Open: do nothing*/
++      return 0;
++}
++
++static int axidma_release(struct inode *inode, struct file *file)
++{
++      /* Release: do nothing */
++      return 0;
++}
++
++static ssize_t axidma_write(struct file *file, const char __user *data,
++                      size_t len, loff_t *ppos)
++{
++      /* Write: do nothing */
++      return 0;
++}
++
++static void dma_complete_func(void *status)
++{
++      *(char *)status = DMA_STATUS_FINISHED;
++}
++
++static long axidma_unlocked_ioctl(struct file *file, unsigned int cmd,
++                              unsigned long arg)
++{
++      int i, ret;
++      dma_cap_mask_t mask;
++      dma_cookie_t cookie;
++      struct dma_device *dma_dev;
++      struct axidma_chncfg chncfg;
++      struct dma_async_tx_descriptor *tx;
++
++#ifdef DW_DMA_FLUSH_DESC
++      void *des_chncfg = &chncfg;
++      chncfg.phys = dw_virt_to_phys(des_chncfg);
++#endif
++      memset(&chncfg, 0, sizeof(struct axidma_chncfg));
++
++      switch(cmd) {
++      case AXIDMA_IOCGETCHN:
++              for(i = 0; i < AXI_DMA_MAX_CHANS; i++) {
++                      if(DMA_CHN_UNUSED == channels[i].used)
++                              break;
++              }
++              if(AXI_DMA_MAX_CHANS == i) {
++                      printk("Get dma chn failed, because no idle channel\n");
++                      goto error;
++              } else {
++                      channels[i].used = DMA_CHN_USED;
++                      channels[i].status = DMA_STATUS_UNFINISHED;
++                      chncfg.status = DMA_STATUS_UNFINISHED;
++                      chncfg.chn_num = i;
++              }
++              dma_cap_zero(mask);
++              dma_cap_set(DMA_MEMCPY, mask);
++              channels[i].dma_chan = dma_request_channel(mask, NULL, NULL);
++              if(!channels[i].dma_chan) {
++                      printk("dma request channel failed\n");
++                      channels[i].used = DMA_CHN_UNUSED;
++                      goto error;
++              }
++              ret = copy_to_user((void __user *)arg, &chncfg,
++                              sizeof(struct axidma_chncfg));
++              if(ret) {
++                      printk("Copy to user failed\n");
++                      goto error;
++              }
++              break;
++      case AXIDMA_IOCCFGANDSTART:
++#ifdef DW_DMA_CHECK_RESULTS
++              void *src,*dst;
++#endif
++              ret = copy_from_user(&chncfg, (void __user *)arg,
++                                   sizeof(struct axidma_chncfg));
++              if(ret) {
++                      printk("Copy from user failed\n");
++                      goto error;
++              }
++
++              if((chncfg.chn_num >= AXI_DMA_MAX_CHANS) ||
++                 (!channels[chncfg.chn_num].dma_chan)) {
++                      printk("chn_num[%d] is invalid\n", chncfg.chn_num);
++                      goto error;
++              }
++              dma_dev = channels[chncfg.chn_num].dma_chan->device;
++#ifdef DW_DMA_FLUSH_DESC
++              sifive_l2_flush64_range(chncfg.phys,sizeof(chncfg));
++#endif
++#ifdef DW_DMA_CHECK_RESULTS
++              src = dw_phys_to_virt(chncfg.src_addr);
++              dst = dw_phys_to_virt(chncfg.dst_addr);
++#endif
++              sifive_l2_flush64_range(chncfg.src_addr, chncfg.len);
++
++              tx = dma_dev->device_prep_dma_memcpy(
++                      channels[chncfg.chn_num].dma_chan,
++                      chncfg.dst_addr, chncfg.src_addr, chncfg.len,
++                      DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
++              if(!tx){
++                      printk("Failed to prepare DMA memcpy\n");
++                      goto error;
++              }
++              channels[chncfg.chn_num].status = DMA_STATUS_UNFINISHED;
++              tx->callback_param = &channels[chncfg.chn_num].status;
++              tx->callback = dma_complete_func;
++              cookie = tx->tx_submit(tx);
++              if(dma_submit_error(cookie)) {
++                      printk("Failed to dma tx_submit\n");
++                      goto error;
++              }
++              dma_async_issue_pending(channels[chncfg.chn_num].dma_chan);
++              /*flush dcache*/
++              sifive_l2_flush64_range(chncfg.dst_addr, chncfg.len);
++#ifdef DW_DMA_PRINT_MEM
++              print_in_line_u64((u8 *)"src", (u64 *)src, chncfg.len);
++              print_in_line_u64((u8 *)"dst", (u64 *)dst, chncfg.len);
++#endif
++#ifdef DW_DMA_CHECK_RESULTS
++              if(memcmp(src, dst, chncfg.len))
++                      printk("check data faild.\n");
++              else
++                      printk("check data ok.\n");
++#endif
++              break;
++
++      case AXIDMA_IOCGETSTATUS:
++              ret = copy_from_user(&chncfg, (void __user *)arg,
++                      sizeof(struct axidma_chncfg));
++              if(ret) {
++                      printk("Copy from user failed\n");
++                      goto error;
++              }
++
++              if(chncfg.chn_num >= AXI_DMA_MAX_CHANS) {
++                      printk("chn_num[%d] is invalid\n", chncfg.chn_num);
++                      goto error;
++              }
++
++              chncfg.status = channels[chncfg.chn_num].status;
++
++              ret = copy_to_user((void __user *)arg, &chncfg,
++                                 sizeof(struct axidma_chncfg));
++              if(ret) {
++                      printk("Copy to user failed\n");
++                      goto error;
++              }
++              break;
++
++      case AXIDMA_IOCRELEASECHN:
++              ret = copy_from_user(&chncfg, (void __user *)arg,
++                                   sizeof(struct axidma_chncfg));
++              if(ret) {
++                      printk("Copy from user failed\n");
++                      goto error;
++              }
++
++              if((chncfg.chn_num >= AXI_DMA_MAX_CHANS) ||
++                 (!channels[chncfg.chn_num].dma_chan)) {
++                      printk("chn_num[%d] is invalid\n", chncfg.chn_num);
++                      goto error;
++              }
++
++              dma_release_channel(channels[chncfg.chn_num].dma_chan);
++              channels[chncfg.chn_num].used = DMA_CHN_UNUSED;
++              channels[chncfg.chn_num].status = DMA_STATUS_UNFINISHED;
++              break;
++
++      default:
++              printk("Don't support cmd [%d]\n", cmd);
++              break;
++      }
++      return 0;
++
++error:
++      return -EFAULT;
++}
++
++/*
++ *    Kernel Interfaces
++ */
++static struct file_operations axidma_fops = {
++      .owner          = THIS_MODULE,
++      .llseek         = no_llseek,
++      .write          = axidma_write,
++      .unlocked_ioctl = axidma_unlocked_ioctl,
++      .open           = axidma_open,
++      .release        = axidma_release,
++};
++
++static struct miscdevice axidma_miscdev = {
++      .minor          = MISC_DYNAMIC_MINOR,
++      .name           = DRIVER_NAME,
++      .fops           = &axidma_fops,
++};
++
++static int __init axidma_init(void)
++{
++      int ret = misc_register(&axidma_miscdev);
++      if(ret) {
++              printk (KERN_ERR "cannot register miscdev (err=%d)\n", ret);
++              return ret;
++      }
++
++      memset(&channels, 0, sizeof(channels));
++
++      return 0;
++}
++
++static void __exit axidma_exit(void)
++{
++      misc_deregister(&axidma_miscdev);
++}
++
++module_init(axidma_init);
++module_exit(axidma_exit);
++
++MODULE_AUTHOR("samin.guo");
++MODULE_DESCRIPTION("DW Axi Dmac Driver");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c
+@@ -0,0 +1,288 @@
++/*
++ * Copyright 2020 StarFive, Inc <samin.guo@starfivetech.com>
++ *
++ * API for dma mem2mem.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation, version 2.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/acpi_iort.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/cdev.h>
++#include <linux/dmaengine.h>
++#include <linux/wait.h>
++#include <linux/string.h>
++#include <linux/dma-mapping.h>
++#include <linux/dma-map-ops.h>
++#include <linux/slab.h>
++
++#include <soc/sifive/sifive_l2_cache.h>
++#include <soc/starfive/jh7100_dma.h>
++
++static volatile int dma_finished = 0;
++static DECLARE_WAIT_QUEUE_HEAD(wq);
++
++u64 dw_virt_to_phys(void *vaddr)
++{
++      u64 pfn_offset = ((u64)vaddr) & 0xfff;
++
++      return _dw_virt_to_phys((u64 *)vaddr) + pfn_offset;
++}
++EXPORT_SYMBOL(dw_virt_to_phys);
++
++void *dw_phys_to_virt(u64 phys)
++{
++      u64 pfn_offset = phys & 0xfff;
++
++      return (void *)(_dw_phys_to_virt(phys) + pfn_offset);
++}
++EXPORT_SYMBOL(dw_phys_to_virt);
++
++static void tx_callback(void *dma_async_param)
++{
++      dma_finished = 1;
++      wake_up_interruptible(&wq);
++}
++
++static int _dma_async_alloc_buf(struct device *dma_dev,
++                              void **src, void **dst, size_t size,
++                              dma_addr_t *src_dma, dma_addr_t *dst_dma)
++{
++      *src = dma_alloc_coherent(dma_dev, size, src_dma, GFP_KERNEL);
++      if(!(*src)) {
++              DMA_DEBUG("src alloc err.\n");
++              goto _FAILED_ALLOC_SRC;
++      }
++
++      *dst = dma_alloc_coherent(dma_dev, size, dst_dma, GFP_KERNEL);
++      if(!(*dst)) {
++              DMA_DEBUG("dst alloc err.\n");
++              goto _FAILED_ALLOC_DST;
++      }
++
++      return 0;
++
++_FAILED_ALLOC_DST:
++      dma_free_coherent(dma_dev, size, *src, *src_dma);
++
++_FAILED_ALLOC_SRC:
++      dma_free_coherent(dma_dev, size, *dst, *dst_dma);
++
++      return -1;
++}
++
++static int _dma_async_prebuf(void *src, void *dst, size_t size)
++{
++      memset((u8 *)src, 0xff, size);
++      memset((u8 *)dst, 0x00, size);
++      return 0;
++}
++
++static int _dma_async_check_data(void *src, void *dst, size_t size)
++{
++      return memcmp(src, dst, size);
++}
++
++static void _dma_async_release(struct dma_chan *chan)
++{
++      dma_release_channel(chan);
++}
++
++static struct dma_chan *_dma_get_channel(enum dma_transaction_type tx_type)
++{
++      dma_cap_mask_t dma_mask;
++
++      dma_cap_zero(dma_mask);
++      dma_cap_set(tx_type, dma_mask);
++
++      return dma_request_channel(dma_mask, NULL, NULL);
++}
++
++static struct dma_async_tx_descriptor *_dma_async_get_desc(
++      struct dma_chan *chan,
++      dma_addr_t src_dma, dma_addr_t dst_dma,
++      size_t size)
++{
++      dma_finished = 0;
++      return dmaengine_prep_dma_memcpy(chan, dst_dma, src_dma, size,
++                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++}
++
++static void _dma_async_do_start(struct dma_async_tx_descriptor *desc,
++                              struct dma_chan *chan)
++{
++      dma_cookie_t dma_cookie = dmaengine_submit(desc);
++      if (dma_submit_error(dma_cookie))
++              DMA_DEBUG("Failed to do DMA tx_submit\n");
++
++      dma_async_issue_pending(chan);
++      wait_event_interruptible(wq, dma_finished);
++}
++
++int dw_dma_async_do_memcpy(void *src, void *dst, size_t size)
++{
++      int ret;
++      struct device *dma_dev;
++      struct dma_chan *chan;
++      dma_addr_t src_dma, dst_dma;
++      struct dma_async_tx_descriptor *desc;
++
++      const struct iommu_ops *iommu;
++      u64 dma_addr = 0, dma_size = 0;
++
++      dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL);
++      if(!dma_dev){
++              dev_err(dma_dev, "kmalloc error.\n");
++              return -ENOMEM;
++      }
++
++      dma_dev->bus = NULL;
++      dma_dev->coherent_dma_mask = 0xffffffff;
++
++      iort_dma_setup(dma_dev, &dma_addr, &dma_size);
++      iommu = iort_iommu_configure_id(dma_dev, NULL);
++      if (PTR_ERR(iommu) == -EPROBE_DEFER)
++              return -EPROBE_DEFER;
++
++      arch_setup_dma_ops(dma_dev, dst_dma, dma_size, iommu, true);
++
++      if(_dma_async_alloc_buf(dma_dev, &src, &dst, size, &src_dma, &dst_dma)) {
++              dev_err(dma_dev, "Err alloc.\n");
++              return -ENOMEM;
++      }
++
++      DMA_DEBUG("src=%#llx, dst=%#llx\n", (u64)src, (u64)dst);
++      DMA_DEBUG("dma_src=%#x dma_dst=%#x\n", (u32)src_dma, (u32)dst_dma);
++
++      _dma_async_prebuf(src, dst, size);
++
++      chan = _dma_get_channel(DMA_MEMCPY);
++      if(!chan ){
++              DMA_PRINTK("Err get chan.\n");
++              return -EBUSY;
++      }
++      DMA_DEBUG("get chan ok.\n");
++
++      desc = _dma_async_get_desc(chan, src_dma, dst_dma, size);
++      if(!desc){
++              DMA_PRINTK("Err get desc.\n");
++              dma_release_channel(chan);
++              return -ENOMEM;
++      }
++      DMA_DEBUG("get desc ok.\n");
++
++      desc->callback = tx_callback;
++
++      sifive_l2_flush64_range(src_dma, size);
++      sifive_l2_flush64_range(dst_dma, size);
++
++      _dma_async_do_start(desc, chan);
++      _dma_async_release(chan);
++
++      ret = _dma_async_check_data(src, dst, size);
++
++      dma_free_coherent(dma_dev, size, src, src_dma);
++      dma_free_coherent(dma_dev, size, dst, dst_dma);
++
++      return ret;
++}
++EXPORT_SYMBOL(dw_dma_async_do_memcpy);
++
++/*
++* phys addr for dma.
++*/
++int dw_dma_memcpy_raw(dma_addr_t src_dma, dma_addr_t dst_dma, size_t size)
++{
++      struct dma_chan *chan;
++      struct device *dma_dev;
++      struct dma_async_tx_descriptor *desc;
++
++      const struct iommu_ops *iommu;
++      u64 dma_addr = 0, dma_size = 0;
++
++      dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL);
++      if(!dma_dev){
++              DMA_PRINTK("kmalloc error.\n");
++              return -ENOMEM;
++      }
++
++      dma_dev->bus = NULL;
++      dma_dev->coherent_dma_mask = 0xffffffff;
++
++      iort_dma_setup(dma_dev, &dma_addr, &dma_size);
++      iommu = iort_iommu_configure_id(dma_dev, NULL);
++      if (PTR_ERR(iommu) == -EPROBE_DEFER)
++              return -EPROBE_DEFER;
++
++      arch_setup_dma_ops(dma_dev, dst_dma, dma_size, iommu, true);
++
++      chan = _dma_get_channel(DMA_MEMCPY);
++      if(!chan){
++              DMA_PRINTK("Error get chan.\n");
++              return -EBUSY;
++      }
++      DMA_DEBUG("get chan ok.\n");
++
++      DMA_DEBUG("src_dma=%#llx, dst_dma=%#llx \n", src_dma, dst_dma);
++      desc = _dma_async_get_desc(chan, src_dma, dst_dma, size);
++      if(!desc){
++              DMA_PRINTK("Error get desc.\n");
++              dma_release_channel(chan);
++              return -ENOMEM;
++      }
++      DMA_DEBUG("get desc ok.\n");
++
++      desc->callback = tx_callback;
++
++      sifive_l2_flush64_range(src_dma, size);
++      sifive_l2_flush64_range(dst_dma, size);
++
++      _dma_async_do_start(desc, chan);
++      _dma_async_release(chan);
++
++      return 0;
++}
++EXPORT_SYMBOL(dw_dma_memcpy_raw);
++
++/*
++*virtl addr for cpu.
++*/
++int dw_dma_memcpy(void *src, void *dst, size_t size)
++{
++      dma_addr_t src_dma, dst_dma;
++
++      src_dma = dw_virt_to_phys(src);
++      dst_dma = dw_virt_to_phys(dst);
++
++      dw_dma_memcpy_raw(src_dma, dst_dma, size);
++      return 0;
++}
++EXPORT_SYMBOL(dw_dma_memcpy);
++
++int dw_dma_mem2mem_test(void)
++{
++      int ret;
++      void *src = NULL;
++      void *dst = NULL;
++      size_t size = 256;
++
++      ret = dw_dma_async_do_memcpy(src, dst, size);
++      if(ret){
++              DMA_PRINTK("memcpy failed.\n");
++      } else {
++              DMA_PRINTK("memcpy ok.\n");
++      }
++
++      return ret;
++}
+--- /dev/null
++++ b/include/soc/starfive/jh7100_dma.h
+@@ -0,0 +1,31 @@
++#ifndef STARFIVE_JH7100_DMA_H
++#define STARFIVE_JH7100_DMA_H
++
++#include <asm/io.h>
++
++#define CONFIG_DW_DEBUG
++
++#define DMA_PRINTK(fmt,...) \
++      printk("[DW_DMA] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
++
++#ifdef CONFIG_DW_DEBUG
++#define DMA_DEBUG(fmt,...) \
++      printk("[DW_DMA_DEBUG] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
++#else
++#define DMA_BEBUG(fmt,...)
++#endif
++
++#define _dw_virt_to_phys(vaddr) (pfn_to_phys(virt_to_pfn(vaddr)))
++#define _dw_phys_to_virt(paddr) (page_to_virt(phys_to_page(paddr)))
++
++void *dw_phys_to_virt(u64 phys);
++u64 dw_virt_to_phys(void *vaddr);
++
++int dw_dma_async_do_memcpy(void *src, void *dst, size_t size);
++int dw_dma_memcpy_raw(dma_addr_t src_dma, dma_addr_t dst_dma, size_t size);
++int dw_dma_memcpy(void *src, void *dst, size_t size);
++
++int dw_dma_mem2mem_arry(void);
++int dw_dma_mem2mem_test(void);
++
++#endif /* STARFIVE_JH7100_DMA_H */

diff --git a/target/linux/visionfive/patches-5.15/0064-dmaengine-dw-axi-dmac-starfive-Remove-calls-specific.patch b/target/linux/visionfive/patches-5.15/0064-dmaengine-dw-axi-dmac-starfive-Remove-calls-specific.patch
new file mode 100644 (file)
index 0000000..faddea9
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0064-dmaengine-dw-axi-dmac-starfive-Remove-calls-specific.patch
@@ -0,0 +1,90 @@
+From 0ea04cb5659424f37263664ee737c876c44c9ef7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Tue, 29 Jun 2021 16:04:44 +0200
+Subject: [PATCH 64/84] dmaengine: dw-axi-dmac-starfive: Remove calls specific
+ to ARM64 ACPI
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+iort_dma_setup() is being removed by commit db59e1b6e49201be ("ACPI:
+arm64: Move DMA setup operations out of IORT") in iommu/next:
+
+    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_async_
+    do_memcpy’:
+    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:152:2: error: implicit decl
+    aration of function ‘iort_dma_setup’ [-Werror=implicit-function-declaration]
+      152 |  iort_dma_setup(dma_dev, &dma_addr, &dma_size);
+         |  ^~~~~~~~~~~~~~
+    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:153:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion]
+      153 |  iommu = iort_iommu_configure_id(dma_dev, NULL);
+         |        ^
+    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_memcpy_raw’:
+    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:223:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion]
+      223 |  iommu = iort_iommu_configure_id(dma_dev, NULL);
+         |        ^
+
+iort_dma_setup() and iort_iommu_configure_id() are part of the ARM64
+ACPI implementation.  As CONFIG_ACPI_IORT cannot be enabled on RISC-V,
+they were dummies anyway, so these calls can just be removed.
+
+[Emil: remove unused local variables too]
+
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+Boot-tested, but the affected code paths were not exercised.
+---
+ .../starfive_dmaengine_memcpy.c               | 20 ++-----------------
+ 1 file changed, 2 insertions(+), 18 deletions(-)
+
+--- a/drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c
++++ b/drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c
+@@ -138,9 +138,6 @@ int dw_dma_async_do_memcpy(void *src, vo
+       dma_addr_t src_dma, dst_dma;
+       struct dma_async_tx_descriptor *desc;
+ 
+-      const struct iommu_ops *iommu;
+-      u64 dma_addr = 0, dma_size = 0;
+-
+       dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL);
+       if(!dma_dev){
+               dev_err(dma_dev, "kmalloc error.\n");
+@@ -150,12 +147,7 @@ int dw_dma_async_do_memcpy(void *src, vo
+       dma_dev->bus = NULL;
+       dma_dev->coherent_dma_mask = 0xffffffff;
+ 
+-      iort_dma_setup(dma_dev, &dma_addr, &dma_size);
+-      iommu = iort_iommu_configure_id(dma_dev, NULL);
+-      if (PTR_ERR(iommu) == -EPROBE_DEFER)
+-              return -EPROBE_DEFER;
+-
+-      arch_setup_dma_ops(dma_dev, dst_dma, dma_size, iommu, true);
++      arch_setup_dma_ops(dma_dev, dst_dma, 0, NULL, true);
+ 
+       if(_dma_async_alloc_buf(dma_dev, &src, &dst, size, &src_dma, &dst_dma)) {
+               dev_err(dma_dev, "Err alloc.\n");
+@@ -208,9 +200,6 @@ int dw_dma_memcpy_raw(dma_addr_t src_dma
+       struct device *dma_dev;
+       struct dma_async_tx_descriptor *desc;
+ 
+-      const struct iommu_ops *iommu;
+-      u64 dma_addr = 0, dma_size = 0;
+-
+       dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL);
+       if(!dma_dev){
+               DMA_PRINTK("kmalloc error.\n");
+@@ -220,12 +209,7 @@ int dw_dma_memcpy_raw(dma_addr_t src_dma
+       dma_dev->bus = NULL;
+       dma_dev->coherent_dma_mask = 0xffffffff;
+ 
+-      iort_dma_setup(dma_dev, &dma_addr, &dma_size);
+-      iommu = iort_iommu_configure_id(dma_dev, NULL);
+-      if (PTR_ERR(iommu) == -EPROBE_DEFER)
+-              return -EPROBE_DEFER;
+-
+-      arch_setup_dma_ops(dma_dev, dst_dma, dma_size, iommu, true);
++      arch_setup_dma_ops(dma_dev, dst_dma, 0, NULL, true);
+ 
+       chan = _dma_get_channel(DMA_MEMCPY);
+       if(!chan){

diff --git a/target/linux/visionfive/patches-5.15/0065-net-phy-motorcomm-Support-the-YT8521-gigabit-PHY.patch b/target/linux/visionfive/patches-5.15/0065-net-phy-motorcomm-Support-the-YT8521-gigabit-PHY.patch
new file mode 100644 (file)
index 0000000..9670fd9
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0065-net-phy-motorcomm-Support-the-YT8521-gigabit-PHY.patch
@@ -0,0 +1,510 @@
+From 95c030528684acd46ede62c9350dc62c2a9f568e Mon Sep 17 00:00:00 2001
+From: Walker Chen <walker.chen@starfivetech.com>
+Date: Wed, 17 Nov 2021 10:38:48 +0800
+Subject: [PATCH 65/84] net: phy: motorcomm: Support the YT8521 gigabit PHY
+
+Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
+---
+ drivers/net/phy/Kconfig     |   2 +-
+ drivers/net/phy/motorcomm.c | 448 ++++++++++++++++++++++++++++++++++++
+ 2 files changed, 449 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -319,7 +319,7 @@ config MOTORCOMM_PHY
+       tristate "Motorcomm PHYs"
+       help
+         Enables support for Motorcomm network PHYs.
+-        Currently supports the YT8511 gigabit PHY.
++        Currently supports the YT8511 and YT8521 gigabit PHYs.
+ 
+ config NATIONAL_PHY
+       tristate "National Semiconductor PHYs"
+--- a/drivers/net/phy/motorcomm.c
++++ b/drivers/net/phy/motorcomm.c
+@@ -10,6 +10,8 @@
+ #include <linux/phy.h>
+ 
+ #define PHY_ID_YT8511         0x0000010a
++#define PHY_ID_YT8521                 0x0000011a
++#define MOTORCOMM_PHY_ID_MASK         0x00000fff
+ 
+ #define YT8511_PAGE_SELECT    0x1e
+ #define YT8511_PAGE           0x1f
+@@ -38,6 +40,53 @@
+ #define YT8511_DELAY_FE_TX_EN (0xf << 12)
+ #define YT8511_DELAY_FE_TX_DIS        (0x2 << 12)
+ 
++#define YT8521_SLEEP_SW_EN    BIT(15)
++#define YT8521_LINK_STATUS    BIT(10)
++#define YT8521_DUPLEX                 0x2000
++#define YT8521_SPEED_MODE     0xc000
++#define YTPHY_REG_SPACE_UTP   0
++#define YTPHY_REG_SPACE_FIBER         2
++#define REG_PHY_SPEC_STATUS   0x11
++/* based on yt8521 wol config register */
++#define YTPHY_UTP_INTR_REG    0x12
++
++#define SYS_WAKEUP_BASED_ON_ETH_PKT   0
++
++/* to enable system WOL of phy, please define this macro to 1
++ * otherwise, define it to 0.
++ */
++#define YTPHY_ENABLE_WOL      0
++
++#if (YTPHY_ENABLE_WOL)
++      #undef SYS_WAKEUP_BASED_ON_ETH_PKT
++      #define SYS_WAKEUP_BASED_ON_ETH_PKT     1
++#endif
++
++#if (YTPHY_ENABLE_WOL)
++enum ytphy_wol_type_e {
++      YTPHY_WOL_TYPE_LEVEL,
++      YTPHY_WOL_TYPE_PULSE,
++      YTPHY_WOL_TYPE_MAX
++};
++typedef enum ytphy_wol_type_e ytphy_wol_type_t;
++
++enum ytphy_wol_width_e {
++      YTPHY_WOL_WIDTH_84MS,
++      YTPHY_WOL_WIDTH_168MS,
++      YTPHY_WOL_WIDTH_336MS,
++      YTPHY_WOL_WIDTH_672MS,
++      YTPHY_WOL_WIDTH_MAX
++};
++typedef enum ytphy_wol_width_e ytphy_wol_width_t;
++
++struct ytphy_wol_cfg_s {
++      int enable;
++      int type;
++      int width;
++};
++typedef struct ytphy_wol_cfg_s ytphy_wol_cfg_t;
++#endif /*(YTPHY_ENABLE_WOL)*/
++
+ static int yt8511_read_page(struct phy_device *phydev)
+ {
+       return __phy_read(phydev, YT8511_PAGE_SELECT);
+@@ -111,6 +160,386 @@ err_restore_page:
+       return phy_restore_page(phydev, oldpage, ret);
+ }
+ 
++int genphy_config_init(struct phy_device *phydev)
++{
++      return genphy_read_abilities(phydev);
++}
++
++static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
++{
++      int ret;
++      int val;
++
++      ret = phy_write(phydev, YT8511_PAGE_SELECT, regnum);
++      if (ret < 0)
++              return ret;
++
++      val = phy_read(phydev, YT8511_PAGE);
++
++      return val;
++}
++
++static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
++{
++      int ret;
++
++      ret = phy_write(phydev, YT8511_PAGE_SELECT, regnum);
++      if (ret < 0)
++              return ret;
++
++      ret = phy_write(phydev, YT8511_PAGE, val);
++
++      return ret;
++}
++
++int yt8521_soft_reset(struct phy_device *phydev)
++{
++      int ret, val;
++
++      val = ytphy_read_ext(phydev, 0xa001);
++      ytphy_write_ext(phydev, 0xa001, (val & ~0x8000));
++
++      ret = genphy_soft_reset(phydev);
++      if (ret < 0)
++              return ret;
++
++      return 0;
++}
++
++#if (YTPHY_ENABLE_WOL)
++static int ytphy_switch_reg_space(struct phy_device *phydev, int space)
++{
++      int ret;
++
++      if (space == YTPHY_REG_SPACE_UTP)
++              ret = ytphy_write_ext(phydev, 0xa000, 0);
++      else
++              ret = ytphy_write_ext(phydev, 0xa000, 2);
++
++      return ret;
++}
++
++static int ytphy_wol_en_cfg(struct phy_device *phydev, ytphy_wol_cfg_t wol_cfg)
++{
++      int ret=0;
++      int val=0;
++
++      val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG);
++      if (val < 0)
++              return val;
++
++      if(wol_cfg.enable) {
++              val |= YTPHY_WOL_CFG_EN;
++
++              if(wol_cfg.type == YTPHY_WOL_TYPE_LEVEL) {
++                      val &= ~YTPHY_WOL_CFG_TYPE;
++                      val &= ~YTPHY_WOL_CFG_INTR_SEL;
++              } else if(wol_cfg.type == YTPHY_WOL_TYPE_PULSE) {
++                      val |= YTPHY_WOL_CFG_TYPE;
++                      val |= YTPHY_WOL_CFG_INTR_SEL;
++
++                      if(wol_cfg.width == YTPHY_WOL_WIDTH_84MS) {
++                              val &= ~YTPHY_WOL_CFG_WIDTH1;
++                              val &= ~YTPHY_WOL_CFG_WIDTH2;
++                      } else if(wol_cfg.width == YTPHY_WOL_WIDTH_168MS) {
++                              val |= YTPHY_WOL_CFG_WIDTH1;
++                              val &= ~YTPHY_WOL_CFG_WIDTH2;
++                      } else if(wol_cfg.width == YTPHY_WOL_WIDTH_336MS) {
++                              val &= ~YTPHY_WOL_CFG_WIDTH1;
++                              val |= YTPHY_WOL_CFG_WIDTH2;
++                      } else if(wol_cfg.width == YTPHY_WOL_WIDTH_672MS) {
++                              val |= YTPHY_WOL_CFG_WIDTH1;
++                              val |= YTPHY_WOL_CFG_WIDTH2;
++                      }
++              }
++      } else {
++              val &= ~YTPHY_WOL_CFG_EN;
++              val &= ~YTPHY_WOL_CFG_INTR_SEL;
++      }
++
++      ret = ytphy_write_ext(phydev, YTPHY_WOL_CFG_REG, val);
++      if (ret < 0)
++              return ret;
++
++      return 0;
++}
++
++static void ytphy_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
++{
++      int val = 0;
++
++      wol->supported = WAKE_MAGIC;
++      wol->wolopts = 0;
++
++      val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG);
++      if (val < 0)
++              return;
++
++      if (val & YTPHY_WOL_CFG_EN)
++              wol->wolopts |= WAKE_MAGIC;
++
++      return;
++}
++
++static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
++{
++      int ret, pre_page, val;
++      ytphy_wol_cfg_t wol_cfg;
++      struct net_device *p_attached_dev = phydev->attached_dev;
++
++      memset(&wol_cfg,0,sizeof(ytphy_wol_cfg_t));
++      pre_page = ytphy_read_ext(phydev, 0xa000);
++      if (pre_page < 0)
++              return pre_page;
++
++      /* Switch to phy UTP page */
++      ret = ytphy_switch_reg_space(phydev, YTPHY_REG_SPACE_UTP);
++      if (ret < 0)
++              return ret;
++
++      if (wol->wolopts & WAKE_MAGIC) {
++              /* Enable the WOL interrupt */
++              val = phy_read(phydev, YTPHY_UTP_INTR_REG);
++              val |= YTPHY_WOL_INTR;
++              ret = phy_write(phydev, YTPHY_UTP_INTR_REG, val);
++              if (ret < 0)
++                      return ret;
++
++              /* Set the WOL config */
++              wol_cfg.enable = 1; //enable
++              wol_cfg.type= YTPHY_WOL_TYPE_PULSE;
++              wol_cfg.width= YTPHY_WOL_WIDTH_672MS;
++              ret = ytphy_wol_en_cfg(phydev, wol_cfg);
++              if (ret < 0)
++                      return ret;
++
++              /* Store the device address for the magic packet */
++              ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR2,
++                              ((p_attached_dev->dev_addr[0] << 8) |
++                               p_attached_dev->dev_addr[1]));
++              if (ret < 0)
++                      return ret;
++              ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR1,
++                              ((p_attached_dev->dev_addr[2] << 8) |
++                               p_attached_dev->dev_addr[3]));
++              if (ret < 0)
++                      return ret;
++              ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR0,
++                              ((p_attached_dev->dev_addr[4] << 8) |
++                               p_attached_dev->dev_addr[5]));
++              if (ret < 0)
++                      return ret;
++      } else {
++              wol_cfg.enable = 0; //disable
++              wol_cfg.type= YTPHY_WOL_TYPE_MAX;
++              wol_cfg.width= YTPHY_WOL_WIDTH_MAX;
++              ret = ytphy_wol_en_cfg(phydev, wol_cfg);
++              if (ret < 0)
++                      return ret;
++      }
++
++      /* Recover to previous register space page */
++      ret = ytphy_switch_reg_space(phydev, pre_page);
++      if (ret < 0)
++              return ret;
++
++      return 0;
++}
++#endif /*(YTPHY_ENABLE_WOL)*/
++
++static int yt8521_config_init(struct phy_device *phydev)
++{
++      int ret;
++      int val;
++
++      phydev->irq = PHY_POLL;
++
++      ytphy_write_ext(phydev, 0xa000, 0);
++
++      ret = genphy_config_init(phydev);
++      if (ret < 0)
++              return ret;
++
++      /* disable auto sleep */
++      val = ytphy_read_ext(phydev, YT8511_EXT_SLEEP_CTRL);
++      if (val < 0)
++              return val;
++
++      val &= ~YT8521_SLEEP_SW_EN;
++
++      ret = ytphy_write_ext(phydev, YT8511_EXT_SLEEP_CTRL, val);
++      if (ret < 0)
++              return ret;
++
++      /*  enable tx delay 450ps per step */
++      val = ytphy_read_ext(phydev, 0xa003);
++      if (val < 0) {
++              printk(KERN_INFO "yt8521_config: read 0xa003 error!\n");
++              return val;
++      }
++      val |= 0x3;
++      ret = ytphy_write_ext(phydev, 0xa003, val);
++      if (ret < 0) {
++              printk(KERN_INFO "yt8521_config: set 0xa003 error!\n");
++              return ret;
++      }
++
++      /* disable rx delay */
++      val = ytphy_read_ext(phydev, 0xa001);
++      if (val < 0) {
++              printk(KERN_INFO "yt8521_config: read 0xa001 error!\n");
++              return val;
++      }
++      val &= ~(1<<8);
++      ret = ytphy_write_ext(phydev, 0xa001, val);
++      if (ret < 0) {
++              printk(KERN_INFO "yt8521_config: failed to disable rx_delay!\n");
++              return ret;
++      }
++
++      /* enable RXC clock when no wire plug */
++      ret = ytphy_write_ext(phydev, 0xa000, 0);
++      if (ret < 0)
++              return ret;
++
++      val = ytphy_read_ext(phydev, YT8511_EXT_CLK_GATE);
++      if (val < 0)
++              return val;
++      val &= ~(1 << 12);
++      ret = ytphy_write_ext(phydev, YT8511_EXT_CLK_GATE, val);
++      if (ret < 0)
++              return ret;
++
++      return ret;
++}
++
++/*
++ * for fiber mode, there is no 10M speed mode and
++ * this function is for this purpose.
++ */
++static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp)
++{
++      int speed_mode, duplex;
++      int speed = SPEED_UNKNOWN;
++
++      duplex = (val & YT8521_DUPLEX) >> 13;
++      speed_mode = (val & YT8521_SPEED_MODE) >> 14;
++      switch (speed_mode) {
++      case 0:
++              if (is_utp)
++                      speed = SPEED_10;
++              break;
++      case 1:
++              speed = SPEED_100;
++              break;
++      case 2:
++              speed = SPEED_1000;
++              break;
++      case 3:
++              break;
++      default:
++              speed = SPEED_UNKNOWN;
++              break;
++      }
++
++      phydev->speed = speed;
++      phydev->duplex = duplex;
++      return 0;
++}
++
++static int yt8521_read_status(struct phy_device *phydev)
++{
++      int ret;
++      volatile int val;
++      volatile int link;
++      int link_utp = 0;
++
++      /* reading UTP */
++      ret = ytphy_write_ext(phydev, 0xa000, 0);
++      if (ret < 0)
++              return ret;
++
++      val = phy_read(phydev, REG_PHY_SPEC_STATUS);
++      if (val < 0)
++              return val;
++
++      link = val & YT8521_LINK_STATUS;
++      if (link) {
++              link_utp = 1;
++              yt8521_adjust_status(phydev, val, 1);
++      } else {
++              link_utp = 0;
++      }
++
++      if (link_utp) {
++              phydev->link = 1;
++              ytphy_write_ext(phydev, 0xa000, 0);
++      } else {
++              phydev->link = 0;
++      }
++
++      return 0;
++}
++
++int yt8521_suspend(struct phy_device *phydev)
++{
++#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
++      int value;
++
++      ytphy_write_ext(phydev, 0xa000, 0);
++      value = phy_read(phydev, MII_BMCR);
++      phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
++
++      ytphy_write_ext(phydev, 0xa000, 2);
++      value = phy_read(phydev, MII_BMCR);
++      phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
++
++      ytphy_write_ext(phydev, 0xa000, 0);
++#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
++
++      return 0;
++}
++
++int yt8521_resume(struct phy_device *phydev)
++{
++#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
++      int value;
++      int ret;
++
++      ytphy_write_ext(phydev, 0xa000, 0);
++      value = phy_read(phydev, MII_BMCR);
++      phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
++
++      /* disable auto sleep */
++      value = ytphy_read_ext(phydev, YT8511_EXT_SLEEP_CTRL);
++      if (value < 0)
++              return value;
++
++      value &= ~YT8521_SLEEP_SW_EN;
++      ret = ytphy_write_ext(phydev, YT8511_EXT_SLEEP_CTRL, value);
++      if (ret < 0)
++              return ret;
++
++      /* enable RXC clock when no wire plug */
++      value = ytphy_read_ext(phydev, YT8511_EXT_CLK_GATE);
++      if (value < 0)
++              return value;
++      value &= ~(1 << 12);
++      ret = ytphy_write_ext(phydev, YT8511_EXT_CLK_GATE, value);
++      if (ret < 0)
++              return ret;
++
++      ytphy_write_ext(phydev, 0xa000, 2);
++      value = phy_read(phydev, MII_BMCR);
++      phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
++
++      ytphy_write_ext(phydev, 0xa000, 0);
++
++#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
++
++      return 0;
++}
++
+ static struct phy_driver motorcomm_phy_drvs[] = {
+       {
+               PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
+@@ -121,16 +550,35 @@ static struct phy_driver motorcomm_phy_d
+               .read_page      = yt8511_read_page,
+               .write_page     = yt8511_write_page,
+       },
++      {
++              PHY_ID_MATCH_EXACT(PHY_ID_YT8521),
++              .name           = "YT8521 Gigabit Ethernet",
++              .phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
++              .flags          = PHY_POLL,
++              .soft_reset     = yt8521_soft_reset,
++              .config_aneg    = genphy_config_aneg,
++              .aneg_done      = genphy_aneg_done,
++              .config_init    = yt8521_config_init,
++              .read_status    = yt8521_read_status,
++              .suspend        = yt8521_suspend,
++              .resume         = yt8521_resume,
++#if (YTPHY_ENABLE_WOL)
++              .get_wol        = &ytphy_get_wol,
++              .set_wol        = &ytphy_set_wol,
++#endif
++      },
+ };
+ 
+ module_phy_driver(motorcomm_phy_drvs);
+ 
+ MODULE_DESCRIPTION("Motorcomm PHY driver");
+ MODULE_AUTHOR("Peter Geis");
++MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
+ MODULE_LICENSE("GPL");
+ 
+ static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
+       { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
++      { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
+       { /* sentinal */ }
+ };
+ 

diff --git a/target/linux/visionfive/patches-5.15/0066-net-stmmac-Configure-gtxclk-based-on-speed.patch b/target/linux/visionfive/patches-5.15/0066-net-stmmac-Configure-gtxclk-based-on-speed.patch
new file mode 100644 (file)
index 0000000..a3c6338
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0066-net-stmmac-Configure-gtxclk-based-on-speed.patch
@@ -0,0 +1,72 @@
+From a8b55db68a4bc3c6b0ce9cb03e82529fa42209ef Mon Sep 17 00:00:00 2001
+From: Tom <support@vamrs.com>
+Date: Tue, 6 Apr 2021 13:30:26 +0800
+Subject: [PATCH 66/84] net: stmmac: Configure gtxclk based on speed
+
+---
+ .../ethernet/stmicro/stmmac/dwmac-generic.c   | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c
+@@ -16,6 +16,50 @@
+ #include "stmmac.h"
+ #include "stmmac_platform.h"
+ 
++/*
++ * GMAC_GTXCLK 为 gmac 的时钟分频寄存器，低8位为分频值
++ * bit         name                    access  default         descript
++ * [31]        clk_gmac_gtxclk enable  RW      0x0             "1:enable; 0:disable"
++ * [30]        reserved                -       0x0             reserved
++ * [29:8]      reserved                -       0x0             reserved
++ * [7:0] clk_gmac_gtxclk divide ratio  RW      0x4             divide value
++ *
++ * gmac 的 root 时钟为500M, gtxclk 需求的时钟如下：
++ * 1000M: gtxclk为125M，分频值为500/125 = 0x4
++ * 100M:  gtxclk为25M， 分频值为500/25  = 0x14
++ * 10M:   gtxclk为2.5M，分频值为500/2.5 = 0xc8
++ */
++#ifdef CONFIG_SOC_STARFIVE
++#define CLKGEN_BASE                    0x11800000
++#define CLKGEN_GMAC_GTXCLK_OFFSET      0x1EC
++#define CLKGEN_GMAC_GTXCLK_ADDR        (CLKGEN_BASE + CLKGEN_GMAC_GTXCLK_OFFSET)
++
++#define CLKGEN_125M_DIV                0x4
++#define CLKGEN_25M_DIV                 0x14
++#define CLKGEN_2_5M_DIV                0xc8
++
++static void dwmac_fixed_speed(void *priv, unsigned int speed)
++{
++      u32 value;
++      void *addr = ioremap(CLKGEN_GMAC_GTXCLK_ADDR, sizeof(value));
++      if (!addr) {
++              pr_err("%s can't remap CLKGEN_GMAC_GTXCLK_ADDR\n", __func__);
++              return;
++      }
++
++      value = readl(addr) & (~0x000000FF);
++
++      switch (speed) {
++              case SPEED_1000: value |= CLKGEN_125M_DIV; break;
++              case SPEED_100:  value |= CLKGEN_25M_DIV;  break;
++              case SPEED_10:   value |= CLKGEN_2_5M_DIV; break;
++              default: iounmap(addr); return;
++      }
++      writel(value, addr); /*set gmac gtxclk*/
++      iounmap(addr);
++}
++#endif
++
+ static int dwmac_generic_probe(struct platform_device *pdev)
+ {
+       struct plat_stmmacenet_data *plat_dat;
+@@ -52,6 +96,9 @@ static int dwmac_generic_probe(struct pl
+               if (ret)
+                       goto err_remove_config_dt;
+       }
++#ifdef CONFIG_SOC_STARFIVE
++      plat_dat->fix_mac_speed = dwmac_fixed_speed;
++#endif
+ 
+       ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+       if (ret)

diff --git a/target/linux/visionfive/patches-5.15/0067-net-stmmac-use-GFP_DMA32.patch b/target/linux/visionfive/patches-5.15/0067-net-stmmac-use-GFP_DMA32.patch
new file mode 100644 (file)
index 0000000..7b1c9ed
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0067-net-stmmac-use-GFP_DMA32.patch
@@ -0,0 +1,49 @@
+From 4a75f8889870a8b461c4f0afb6588a3729017490 Mon Sep 17 00:00:00 2001
+From: Matteo Croce <mcroce@microsoft.com>
+Date: Fri, 21 May 2021 03:26:38 +0200
+Subject: [PATCH 67/84] net: stmmac: use GFP_DMA32
+
+Signed-off-by: Matteo Croce <mcroce@microsoft.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -1465,14 +1465,16 @@ static int stmmac_init_rx_buffers(struct
+       struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
+ 
+       if (!buf->page) {
+-              buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
++              buf->page = page_pool_alloc_pages(rx_q->page_pool,
++                                                GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32);
+               if (!buf->page)
+                       return -ENOMEM;
+               buf->page_offset = stmmac_rx_offset(priv);
+       }
+ 
+       if (priv->sph && !buf->sec_page) {
+-              buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
++              buf->sec_page = page_pool_alloc_pages(rx_q->page_pool,
++                                                    GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32);
+               if (!buf->sec_page)
+                       return -ENOMEM;
+ 
+@@ -4508,13 +4510,15 @@ static inline void stmmac_rx_refill(stru
+                       p = rx_q->dma_rx + entry;
+ 
+               if (!buf->page) {
+-                      buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
++                      buf->page = page_pool_alloc_pages(rx_q->page_pool,
++                                                        GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32);
+                       if (!buf->page)
+                               break;
+               }
+ 
+               if (priv->sph && !buf->sec_page) {
+-                      buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
++                      buf->sec_page = page_pool_alloc_pages(rx_q->page_pool,
++                                                            GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32);
+                       if (!buf->sec_page)
+                               break;
+ 

diff --git a/target/linux/visionfive/patches-5.15/0068-ASoC-starfive-Add-StarFive-JH7100-audio-drivers.patch b/target/linux/visionfive/patches-5.15/0068-ASoC-starfive-Add-StarFive-JH7100-audio-drivers.patch
new file mode 100644 (file)
index 0000000..46c64b6
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0068-ASoC-starfive-Add-StarFive-JH7100-audio-drivers.patch
@@ -0,0 +1,4370 @@
+From dbb9e602b02acfba1af0d96e953f60256bea7ec5 Mon Sep 17 00:00:00 2001
+From: Walker Chen <walker.chen@starfivetech.com>
+Date: Wed, 17 Nov 2021 15:50:50 +0800
+Subject: [PATCH 68/84] ASoC: starfive: Add StarFive JH7100 audio drivers
+
+Signed-off-by: Michael Yan <michael.yan@starfivetech.com>
+Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
+Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ sound/soc/Kconfig                       |    1 +
+ sound/soc/Makefile                      |    1 +
+ sound/soc/starfive/Kconfig              |   59 ++
+ sound/soc/starfive/Makefile             |   24 +
+ sound/soc/starfive/i2svad-pcm.c         |  249 ++++++
+ sound/soc/starfive/i2svad.c             | 1089 +++++++++++++++++++++++
+ sound/soc/starfive/i2svad.h             |  246 +++++
+ sound/soc/starfive/pdm.c                |  362 ++++++++
+ sound/soc/starfive/pdm.h                |   43 +
+ sound/soc/starfive/pwmdac-pcm.c         |  232 +++++
+ sound/soc/starfive/pwmdac-transmitter.c |   82 ++
+ sound/soc/starfive/pwmdac.c             |  901 +++++++++++++++++++
+ sound/soc/starfive/pwmdac.h             |  153 ++++
+ sound/soc/starfive/spdif-pcm.c          |  288 ++++++
+ sound/soc/starfive/spdif.c              |  384 ++++++++
+ sound/soc/starfive/spdif.h              |  154 ++++
+ 16 files changed, 4268 insertions(+)
+ create mode 100644 sound/soc/starfive/Kconfig
+ create mode 100644 sound/soc/starfive/Makefile
+ create mode 100644 sound/soc/starfive/i2svad-pcm.c
+ create mode 100644 sound/soc/starfive/i2svad.c
+ create mode 100644 sound/soc/starfive/i2svad.h
+ create mode 100644 sound/soc/starfive/pdm.c
+ create mode 100644 sound/soc/starfive/pdm.h
+ create mode 100644 sound/soc/starfive/pwmdac-pcm.c
+ create mode 100644 sound/soc/starfive/pwmdac-transmitter.c
+ create mode 100644 sound/soc/starfive/pwmdac.c
+ create mode 100644 sound/soc/starfive/pwmdac.h
+ create mode 100644 sound/soc/starfive/spdif-pcm.c
+ create mode 100644 sound/soc/starfive/spdif.c
+ create mode 100644 sound/soc/starfive/spdif.h
+
+--- a/sound/soc/Kconfig
++++ b/sound/soc/Kconfig
+@@ -83,6 +83,7 @@ source "sound/soc/sh/Kconfig"
+ source "sound/soc/sof/Kconfig"
+ source "sound/soc/spear/Kconfig"
+ source "sound/soc/sprd/Kconfig"
++source "sound/soc/starfive/Kconfig"
+ source "sound/soc/sti/Kconfig"
+ source "sound/soc/stm/Kconfig"
+ source "sound/soc/sunxi/Kconfig"
+--- a/sound/soc/Makefile
++++ b/sound/soc/Makefile
+@@ -49,6 +49,7 @@ obj-$(CONFIG_SND_SOC)        += pxa/
+ obj-$(CONFIG_SND_SOC) += qcom/
+ obj-$(CONFIG_SND_SOC) += rockchip/
+ obj-$(CONFIG_SND_SOC) += samsung/
++obj-$(CONFIG_SND_SOC) += starfive/
+ obj-$(CONFIG_SND_SOC) += sh/
+ obj-$(CONFIG_SND_SOC) += sof/
+ obj-$(CONFIG_SND_SOC) += spear/
+--- /dev/null
++++ b/sound/soc/starfive/Kconfig
+@@ -0,0 +1,59 @@
++# SPDX-License-Identifier: GPL-2.0
++# Copyright (C) 2021 StarFive Technology Co., Ltd.
++
++config SND_STARFIVE_SPDIF
++      tristate "starfive spdif"
++      depends on SOC_STARFIVE || COMPILE_TEST
++      select SND_SOC_GENERIC_DMAENGINE_PCM
++      select REGMAP_MMIO
++      help
++        Say Y or M if you want to add support for codecs attached to the
++        I2S interface on VIC vic_starlight board. You will also need to select
++        the drivers for the rest of VIC audio subsystem.
++
++config SND_STARFIVE_SPDIF_PCM
++      bool "PCM PIO extension for spdif driver"
++      depends on SND_STARFIVE_SPDIF
++      help
++       Say Y or N if you want to add a custom ALSA extension that registers
++       a PCM and uses PIO to transfer data.
++
++config SND_STARFIVE_PWMDAC
++      tristate "starfive pwmdac Device Driver"
++      depends on SOC_STARFIVE || COMPILE_TEST
++      select SND_SOC_GENERIC_DMAENGINE_PCM
++      help
++       Say Y or M if you want to add support for sf pwmdac driver.
++
++config SND_STARFIVE_PWMDAC_PCM
++      bool "PCM PIO extension for pwmdac driver"
++      depends on SND_STARFIVE_PWMDAC
++      help
++       Say Y or N if you want to add a custom ALSA extension that registers
++       a PCM and uses PIO to transfer data.
++
++config SND_STARFIVE_PDM
++      tristate "starfive pdm Device Driver"
++      depends on SOC_STARFIVE || COMPILE_TEST
++      select REGMAP_MMIO
++      help
++       Say Y or M if you want to add support for sf pdm driver.
++
++config SND_STARFIVE_I2SVAD
++      tristate "starfive I2SVAD Device Driver"
++      depends on SOC_STARFIVE || COMPILE_TEST
++      select SND_SOC_GENERIC_DMAENGINE_PCM
++      help
++       Say Y or M if you want to add support for I2SVAD driver for
++       starfive I2SVAD device.
++
++config SND_STARFIVE_I2SVAD_PCM
++      bool "PCM PIO extension for I2SVAD driver"
++      depends on SND_STARFIVE_I2SVAD
++      help
++       Say Y or N if you want to add a custom ALSA extension that registers
++       a PCM and uses PIO to transfer data.
++
++       This functionality is specially suited for I2SVAD devices that don't have
++       DMA support.
++
+--- /dev/null
++++ b/sound/soc/starfive/Makefile
+@@ -0,0 +1,24 @@
++# SPDX-License-Identifier: GPL-2.0
++#
++# Copyright (C) 2021 StarFive Technology Co., Ltd.
++#
++snd-soc-starfive-spdif-y := spdif.o
++snd-soc-starfive-spdif-$(CONFIG_SND_STARFIVE_SPDIF_PCM) += spdif-pcm.o
++
++obj-$(CONFIG_SND_STARFIVE_SPDIF) += snd-soc-starfive-spdif.o
++
++snd-soc-starfive-pwmdac-y := pwmdac.o
++snd-soc-starfive-pwmdac-$(CONFIG_SND_STARFIVE_PWMDAC_PCM) += pwmdac-pcm.o
++snd-soc-starfive-pwmdac-transmitter-y := pwmdac-transmitter.o
++
++obj-$(CONFIG_SND_STARFIVE_PWMDAC) += snd-soc-starfive-pwmdac.o
++obj-$(CONFIG_SND_STARFIVE_PWMDAC) += snd-soc-starfive-pwmdac-transmitter.o
++
++snd-soc-starfive-pdm-y := pdm.o
++
++obj-$(CONFIG_SND_STARFIVE_PDM) += snd-soc-starfive-pdm.o
++
++snd-soc-starfive-i2svad-y := i2svad.o
++snd-soc-starfive-i2svad-$(CONFIG_SND_STARFIVE_I2SVAD_PCM) += i2svad-pcm.o
++
++obj-$(CONFIG_SND_STARFIVE_I2SVAD) += snd-soc-starfive-i2svad.o
+--- /dev/null
++++ b/sound/soc/starfive/i2svad-pcm.c
+@@ -0,0 +1,249 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/io.h>
++#include <linux/rcupdate.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++
++#include "i2svad.h"
++
++#define BUFFER_BYTES_MAX      (3 * 2 * 8 * PERIOD_BYTES_MIN)
++#define PERIOD_BYTES_MIN      4096
++#define PERIODS_MIN           2
++
++#define i2svad_pcm_tx_fn(sample_bits) \
++static unsigned int i2svad_pcm_tx_##sample_bits(struct i2svad_dev *dev, \
++              struct snd_pcm_runtime *runtime, unsigned int tx_ptr, \
++              bool *period_elapsed) \
++{ \
++      const u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
++      unsigned int period_pos = tx_ptr % runtime->period_size; \
++      int i; \
++\
++      for (i = 0; i < dev->fifo_th; i++) { \
++              iowrite32(p[tx_ptr][0], dev->i2s_base + LRBR_LTHR(0)); \
++              iowrite32(p[tx_ptr][1], dev->i2s_base + RRBR_RTHR(0)); \
++              period_pos++; \
++              if (++tx_ptr >= runtime->buffer_size) \
++                      tx_ptr = 0; \
++      } \
++      *period_elapsed = period_pos >= runtime->period_size; \
++      return tx_ptr; \
++}
++
++#define i2svad_pcm_rx_fn(sample_bits) \
++static unsigned int i2svad_pcm_rx_##sample_bits(struct i2svad_dev *dev, \
++              struct snd_pcm_runtime *runtime, unsigned int rx_ptr, \
++              bool *period_elapsed) \
++{ \
++      u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
++      unsigned int period_pos = rx_ptr % runtime->period_size; \
++      int i; \
++\
++      for (i = 0; i < dev->fifo_th; i++) { \
++              p[rx_ptr][0] = ioread32(dev->i2s_base + LRBR_LTHR(0)); \
++              p[rx_ptr][1] = ioread32(dev->i2s_base + RRBR_RTHR(0)); \
++              period_pos++; \
++              if (++rx_ptr >= runtime->buffer_size) \
++                      rx_ptr = 0; \
++      } \
++      *period_elapsed = period_pos >= runtime->period_size; \
++      return rx_ptr; \
++}
++
++i2svad_pcm_tx_fn(16);
++i2svad_pcm_rx_fn(16);
++
++#undef i2svad_pcm_tx_fn
++#undef i2svad_pcm_rx_fn
++
++static const struct snd_pcm_hardware i2svad_pcm_hardware = {
++      .info = SNDRV_PCM_INFO_INTERLEAVED |
++              SNDRV_PCM_INFO_MMAP |
++              SNDRV_PCM_INFO_MMAP_VALID |
++              SNDRV_PCM_INFO_BLOCK_TRANSFER,
++      .rates = SNDRV_PCM_RATE_32000 |
++              SNDRV_PCM_RATE_44100 |
++              SNDRV_PCM_RATE_48000,
++      .rate_min = 32000,
++      .rate_max = 48000,
++      .formats = SNDRV_PCM_FMTBIT_S16_LE,
++      .channels_min = 2,
++      .channels_max = 2,
++      .buffer_bytes_max = BUFFER_BYTES_MAX,
++      .period_bytes_min = PERIOD_BYTES_MIN,
++      .period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
++      .periods_min = PERIODS_MIN,
++      .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
++      .fifo_size = 16,
++};
++
++static void i2svad_pcm_transfer(struct i2svad_dev *dev, bool push)
++{
++      struct snd_pcm_substream *substream;
++      bool active, period_elapsed;
++
++      rcu_read_lock();
++      if (push)
++              substream = rcu_dereference(dev->tx_substream);
++      else
++              substream = rcu_dereference(dev->rx_substream);
++      active = substream && snd_pcm_running(substream);
++      if (active) {
++              unsigned int ptr;
++              unsigned int new_ptr;
++
++              if (push) {
++                      ptr = READ_ONCE(dev->tx_ptr);
++                      new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
++                                      &period_elapsed);
++                      cmpxchg(&dev->tx_ptr, ptr, new_ptr);
++              } else {
++                      ptr = READ_ONCE(dev->rx_ptr);
++                      new_ptr = dev->rx_fn(dev, substream->runtime, ptr,
++                                      &period_elapsed);
++                      cmpxchg(&dev->rx_ptr, ptr, new_ptr);
++              }
++
++              if (period_elapsed)
++                      snd_pcm_period_elapsed(substream);
++      }
++      rcu_read_unlock();
++}
++
++void i2svad_pcm_push_tx(struct i2svad_dev *dev)
++{
++      i2svad_pcm_transfer(dev, true);
++}
++
++void i2svad_pcm_pop_rx(struct i2svad_dev *dev)
++{
++      i2svad_pcm_transfer(dev, false);
++}
++
++static int i2svad_pcm_open(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
++      struct i2svad_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
++
++      snd_soc_set_runtime_hwparams(substream, &i2svad_pcm_hardware);
++      snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
++      runtime->private_data = dev;
++
++      return 0;
++}
++
++static int i2svad_pcm_close(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream)
++{
++      synchronize_rcu();
++      return 0;
++}
++
++static int i2svad_pcm_hw_params(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream,
++                      struct snd_pcm_hw_params *hw_params)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct i2svad_dev *dev = runtime->private_data;
++
++      switch (params_channels(hw_params)) {
++      case 2:
++              break;
++      default:
++              dev_err(dev->dev, "invalid channels number\n");
++              return -EINVAL;
++      }
++
++      switch (params_format(hw_params)) {
++      case SNDRV_PCM_FORMAT_S16_LE:
++              dev->tx_fn = i2svad_pcm_tx_16;
++              dev->rx_fn = i2svad_pcm_rx_16;
++              break;
++      default:
++              dev_err(dev->dev, "invalid format\n");
++              return -EINVAL;
++      }
++
++      return 0;
++}
++
++static int i2svad_pcm_trigger(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream, int cmd)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct i2svad_dev *dev = runtime->private_data;
++      int ret = 0;
++
++      switch (cmd) {
++      case SNDRV_PCM_TRIGGER_START:
++      case SNDRV_PCM_TRIGGER_RESUME:
++      case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++              if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                      WRITE_ONCE(dev->tx_ptr, 0);
++                      rcu_assign_pointer(dev->tx_substream, substream);
++              } else {
++                      WRITE_ONCE(dev->rx_ptr, 0);
++                      rcu_assign_pointer(dev->rx_substream, substream);
++              }
++              break;
++      case SNDRV_PCM_TRIGGER_STOP:
++      case SNDRV_PCM_TRIGGER_SUSPEND:
++      case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++              if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++                      rcu_assign_pointer(dev->tx_substream, NULL);
++              else
++                      rcu_assign_pointer(dev->rx_substream, NULL);
++              break;
++      default:
++              ret = -EINVAL;
++              break;
++      }
++
++      return ret;
++}
++
++static snd_pcm_uframes_t i2svad_pcm_pointer(struct snd_soc_component *component,
++                                      struct snd_pcm_substream *substream)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct i2svad_dev *dev = runtime->private_data;
++      snd_pcm_uframes_t pos;
++
++      if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++              pos = READ_ONCE(dev->tx_ptr);
++      else
++              pos = READ_ONCE(dev->rx_ptr);
++
++      return pos < runtime->buffer_size ? pos : 0;
++}
++
++static int i2svad_pcm_new(struct snd_soc_component *component,
++                      struct snd_soc_pcm_runtime *rtd)
++{
++      size_t size = i2svad_pcm_hardware.buffer_bytes_max;
++
++      snd_pcm_set_managed_buffer_all(rtd->pcm,
++                      SNDRV_DMA_TYPE_CONTINUOUS,
++                      NULL, size, size);
++      return 0;
++}
++
++static const struct snd_soc_component_driver i2svad_pcm_component = {
++      .open           = i2svad_pcm_open,
++      .close          = i2svad_pcm_close,
++      .hw_params      = i2svad_pcm_hw_params,
++      .trigger        = i2svad_pcm_trigger,
++      .pointer        = i2svad_pcm_pointer,
++      .pcm_construct  = i2svad_pcm_new,
++};
++
++int i2svad_pcm_register(struct platform_device *pdev)
++{
++      return devm_snd_soc_register_component(&pdev->dev, &i2svad_pcm_component,
++                                      NULL, 0);
++}
+--- /dev/null
++++ b/sound/soc/starfive/i2svad.c
+@@ -0,0 +1,1089 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/pm_runtime.h>
++#include <sound/designware_i2s.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/dmaengine_pcm.h>
++#include <linux/kthread.h>
++
++#include "i2svad.h"
++
++/* vad control function*/
++static void vad_start(struct vad_params *vad)
++{
++      regmap_update_bits(vad->vad_map, VAD_MEM_SW,
++                      VAD_MEM_SW_MASK, VAD_MEM_SW_TO_VAD);
++      regmap_update_bits(vad->vad_map, VAD_SW,
++                      VAD_SW_MASK, VAD_SW_VAD_XMEM_ENABLE|VAD_SW_ADC_ENABLE);
++      regmap_update_bits(vad->vad_map, VAD_SPINT_EN,
++                      VAD_SPINT_EN_MASK, VAD_SPINT_EN_ENABLE);
++      regmap_update_bits(vad->vad_map, VAD_SLINT_EN,
++                      VAD_SLINT_EN_MASK, VAD_SLINT_EN_ENABLE);
++}
++
++static void vad_stop(struct vad_params *vad)
++{
++      regmap_update_bits(vad->vad_map, VAD_SPINT_EN,
++                      VAD_SPINT_EN_MASK, VAD_SLINT_EN_DISABLE);
++      regmap_update_bits(vad->vad_map, VAD_SLINT_EN,
++                      VAD_SLINT_EN_MASK, VAD_SLINT_EN_DISABLE);
++      regmap_update_bits(vad->vad_map, VAD_SW,
++                      VAD_SW_MASK, VAD_SW_VAD_XMEM_DISABLE|VAD_SW_ADC_DISABLE);
++      regmap_update_bits(vad->vad_map, VAD_MEM_SW,
++                      VAD_MEM_SW_MASK, VAD_MEM_SW_TO_AXI);
++}
++
++static void vad_status(struct vad_params *vad)
++{
++      u32 sp_value,sp_en;
++      u32 sl_value,sl_en;
++
++      regmap_read(vad->vad_map, VAD_SPINT,&sp_value);
++      regmap_read(vad->vad_map, VAD_SPINT_EN,&sp_en);
++      if (sp_value&sp_en){
++              regmap_update_bits(vad->vad_map, VAD_SPINT_CLR,
++                              VAD_SPINT_CLR_MASK, VAD_SPINT_CLR_VAD_SPINT);
++              vad->vstatus = VAD_STATUS_SPINT;
++              vad_stop(vad);
++              vad_start(vad);
++      }
++
++      regmap_read(vad->vad_map, VAD_SLINT,&sl_value);
++      regmap_read(vad->vad_map, VAD_SLINT_EN,&sl_en);
++      if (sl_value&sl_en){
++              regmap_update_bits(vad->vad_map, VAD_SLINT_CLR,
++                              VAD_SLINT_CLR_MASK, VAD_SLINT_CLR_VAD_SLINT);
++              vad->vstatus = VAD_STATUS_SLINT;
++      }
++}
++
++static int vad_trigger(struct vad_params *vad,int cmd)
++{
++      int ret = 0;
++
++      switch (cmd) {
++      case SNDRV_PCM_TRIGGER_START:
++      case SNDRV_PCM_TRIGGER_RESUME:
++      case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++              if(vad->vswitch)
++              {
++                      vad_start(vad);
++              }
++              break;
++
++      case SNDRV_PCM_TRIGGER_STOP:
++      case SNDRV_PCM_TRIGGER_SUSPEND:
++      case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++              vad_stop(vad);
++              break;
++      default:
++              ret = -EINVAL;
++              break;
++      }
++      return ret;
++}
++
++static void vad_init(struct vad_params *vad)
++{
++      /* left_margin */
++      regmap_update_bits(vad->vad_map, VAD_LEFT_MARGIN,
++                      VAD_LEFT_MARGIN_MASK, 0x0);
++      /* right_margin */
++      regmap_update_bits(vad->vad_map, VAD_RIGHT_MARGIN,
++                      VAD_RIGHT_MARGIN_MASK, 0x0);
++      /*low-energy transition range threshold ——NL*/
++      regmap_update_bits(vad->vad_map, VAD_N_LOW_CONT_FRAMES,
++                      VAD_N_LOW_CONT_FRAMES_MASK, 0x3);
++      /* low-energy transition range */
++      regmap_update_bits(vad->vad_map, VAD_N_LOW_SEEK_FRAMES,
++                      VAD_N_LOW_SEEK_FRAMES_MASK, 0x8);
++      /* high-energy transition range threshold——NH */
++      regmap_update_bits(vad->vad_map, VAD_N_HIGH_CONT_FRAMES,
++                      VAD_N_HIGH_CONT_FRAMES_MASK, 0x5);
++      /* high-energy transition range */
++      regmap_update_bits(vad->vad_map, VAD_N_HIGH_SEEK_FRAMES,
++                      VAD_N_HIGH_SEEK_FRAMES_MASK, 0x1E);
++      /*low-energy voice range threshold——NVL*/
++      regmap_update_bits(vad->vad_map, VAD_N_SPEECH_LOW_HIGH_FRAMES,
++                      VAD_N_SPEECH_LOW_HIGH_FRAMES_MASK, 0x2);
++      /*low-energy voice range*/
++      regmap_update_bits(vad->vad_map, VAD_N_SPEECH_LOW_SEEK_FRAMES,
++                      VAD_N_SPEECH_LOW_SEEK_FRAMES_MASK, 0x12);
++      /*mean silence frame range*/
++      regmap_update_bits(vad->vad_map, VAD_MEAN_SIL_FRAMES,
++                      VAD_MEAN_SIL_FRAMES_MASK, 0xA);
++      /*low-energy threshold scaling factor,12bit(0~0xFFF)*/
++      regmap_update_bits(vad->vad_map, VAD_N_ALPHA,
++                      VAD_N_ALPHA_MASK, 0x1A);
++      /*high-energy threshold scaling factor,12bit(0~0xFFF)*/
++      regmap_update_bits(vad->vad_map, VAD_N_BETA,
++                      VAD_N_BETA_MASK, 0x34);
++      regmap_update_bits(vad->vad_map, VAD_LEFT_WD,
++                      VAD_LEFT_WD_MASK, VAD_LEFT_WD_BIT_15_0);
++      regmap_update_bits(vad->vad_map, VAD_RIGHT_WD,
++                      VAD_RIGHT_WD_MASK, VAD_RIGHT_WD_BIT_15_0);
++      regmap_update_bits(vad->vad_map, VAD_LR_SEL,
++                      VAD_LR_SEL_MASK, VAD_LR_SEL_L);
++      regmap_update_bits(vad->vad_map, VAD_STOP_DELAY,
++                      VAD_STOP_DELAY_MASK, VAD_STOP_DELAY_0_SAMPLE);
++      regmap_update_bits(vad->vad_map, VAD_ADDR_START,
++                      VAD_ADDR_START_MASK, 0x0);
++      regmap_update_bits(vad->vad_map, VAD_ADDR_WRAP,
++                      VAD_ADDR_WRAP_MASK, 0x2000);
++      regmap_update_bits(vad->vad_map, VAD_MEM_SW,
++                      VAD_MEM_SW_MASK, VAD_MEM_SW_TO_AXI);
++      regmap_update_bits(vad->vad_map, VAD_SPINT_CLR,
++                      VAD_SPINT_CLR_MASK, VAD_SPINT_CLR_VAD_SPINT);
++      regmap_update_bits(vad->vad_map, VAD_SLINT_CLR,
++                      VAD_SLINT_CLR_MASK, VAD_SLINT_CLR_VAD_SLINT);
++}
++
++
++static int vad_switch_info(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_info *uinfo)
++{
++      uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
++      uinfo->count = 1;
++      uinfo->value.integer.min = 0;
++      uinfo->value.integer.max = 1;
++
++      return 0;
++}
++
++static int vad_switch_get(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
++
++      ucontrol->value.integer.value[0] = dev->vad.vswitch;
++
++      return 0;
++}
++
++static int vad_switch_put(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
++      int val;
++
++      val = ucontrol->value.integer.value[0];
++      if (val && !dev->vad.vswitch) {
++              dev->vad.vswitch = true;
++      } else if (!val && dev->vad.vswitch) {
++              dev->vad.vswitch = false;
++              vad_stop(&(dev->vad));
++      }
++
++      return 0;
++}
++
++
++static int vad_status_info(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_info *uinfo)
++{
++      uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++      uinfo->count = 1;
++      uinfo->value.integer.min = 0;
++      uinfo->value.integer.max = 2;
++
++      return 0;
++}
++
++static int vad_status_get(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
++
++      ucontrol->value.integer.value[0] = dev->vad.vstatus;
++      dev->vad.vstatus = VAD_STATUS_NORMAL;
++
++      return 0;
++}
++
++
++#define SOC_VAD_SWITCH_DECL(xname) \
++{     .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
++      .info = vad_switch_info, .get = vad_switch_get, \
++      .put = vad_switch_put, }
++
++#define SOC_VAD_STATUS_DECL(xname) \
++{     .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
++      .info = vad_status_info, .get = vad_status_get, }
++
++
++static const struct snd_kcontrol_new vad_snd_controls[] = {
++      SOC_VAD_SWITCH_DECL("vad switch"),
++      SOC_VAD_STATUS_DECL("vad status"),
++};
++
++static int vad_probe(struct snd_soc_component *component)
++{
++      struct i2svad_dev *priv = snd_soc_component_get_drvdata(component);
++
++      snd_soc_component_init_regmap(component, priv->vad.vad_map);
++      snd_soc_add_component_controls(component, vad_snd_controls,
++                              ARRAY_SIZE(vad_snd_controls));
++
++      return 0;
++}
++
++/* i2s control function*/
++static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
++{
++      writel(val, io_base + reg);
++}
++
++static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
++{
++      return readl(io_base + reg);
++}
++
++static inline void i2s_disable_channels(struct i2svad_dev *dev, u32 stream)
++{
++      u32 i = 0;
++
++      if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
++              for (i = 0; i < ALL_CHANNEL_NUM; i++)
++                      i2s_write_reg(dev->i2s_base, TER(i), 0);
++      } else {
++              for (i = 0; i < ALL_CHANNEL_NUM; i++)
++                      i2s_write_reg(dev->i2s_base, RER(i), 0);
++      }
++}
++
++static inline void i2s_clear_irqs(struct i2svad_dev *dev, u32 stream)
++{
++      u32 i = 0;
++
++      if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
++              for (i = 0; i < ALL_CHANNEL_NUM; i++)
++                      i2s_read_reg(dev->i2s_base, TOR(i));
++      } else {
++              for (i = 0; i < ALL_CHANNEL_NUM; i++)
++                      i2s_read_reg(dev->i2s_base, ROR(i));
++      }
++}
++
++static inline void i2s_disable_irqs(struct i2svad_dev *dev, u32 stream,
++                              int chan_nr)
++{
++      u32 i, irq;
++
++      if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
++              for (i = 0; i < (chan_nr / 2); i++) {
++                      irq = i2s_read_reg(dev->i2s_base, IMR(i));
++                      i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
++              }
++      } else {
++              for (i = 0; i < (chan_nr / 2); i++) {
++                      irq = i2s_read_reg(dev->i2s_base, IMR(i));
++                      i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
++              }
++      }
++}
++
++static inline void i2s_enable_irqs(struct i2svad_dev *dev, u32 stream,
++                              int chan_nr)
++{
++      u32 i, irq;
++
++      if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
++              for (i = 0; i < (chan_nr / 2); i++) {
++                      irq = i2s_read_reg(dev->i2s_base, IMR(i));
++                      i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
++              }
++      } else {
++              for (i = 0; i < (chan_nr / 2); i++) {
++                      irq = i2s_read_reg(dev->i2s_base, IMR(i));
++                      i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
++              }
++      }
++}
++
++static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
++{
++      struct i2svad_dev *dev = dev_id;
++      bool irq_valid = false;
++      u32 isr[4];
++      int i;
++
++      for (i = 0; i < ALL_CHANNEL_NUM; i++)
++              isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
++
++      i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
++      i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
++
++      for (i = 0; i < 4; i++) {
++              /*
++               * Check if TX fifo is empty. If empty fill FIFO with samples
++               * NOTE: Only two channels supported
++               */
++              if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
++                      i2svad_pcm_push_tx(dev);
++                      irq_valid = true;
++              }
++
++              /*
++               * Data available. Retrieve samples from FIFO
++               * NOTE: Only two channels supported
++               */
++              if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
++                      i2svad_pcm_pop_rx(dev);
++                      irq_valid = true;
++              }
++
++              /* Error Handling: TX */
++              if (isr[i] & ISR_TXFO) {
++                      //dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i);
++                      irq_valid = true;
++              }
++
++              /* Error Handling: TX */
++              if (isr[i] & ISR_RXFO) {
++                      //dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i);
++                      irq_valid = true;
++              }
++      }
++
++      vad_status(&(dev->vad));
++
++      if (irq_valid)
++              return IRQ_HANDLED;
++      else
++              return IRQ_NONE;
++}
++
++static void i2s_start(struct i2svad_dev *dev,
++                      struct snd_pcm_substream *substream)
++{
++      struct i2s_clk_config_data *config = &dev->config;
++
++      i2s_write_reg(dev->i2s_base, IER, 1);
++      i2s_enable_irqs(dev, substream->stream, config->chan_nr);
++
++      if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++              i2s_write_reg(dev->i2s_base, ITER, 1);
++      else
++              i2s_write_reg(dev->i2s_base, IRER, 1);
++
++      i2s_write_reg(dev->i2s_base, CER, 1);
++}
++
++static void i2s_stop(struct i2svad_dev *dev,
++              struct snd_pcm_substream *substream)
++{
++
++      i2s_clear_irqs(dev, substream->stream);
++      if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++              i2s_write_reg(dev->i2s_base, ITER, 0);
++      else
++              i2s_write_reg(dev->i2s_base, IRER, 0);
++
++      i2s_disable_irqs(dev, substream->stream, 8);
++
++      if (!dev->active) {
++              i2s_write_reg(dev->i2s_base, CER, 0);
++              i2s_write_reg(dev->i2s_base, IER, 0);
++      }
++}
++
++static int dw_i2s_startup(struct snd_pcm_substream *substream,
++              struct snd_soc_dai *cpu_dai)
++{
++      struct i2svad_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
++      union dw_i2s_snd_dma_data *dma_data = NULL;
++
++
++      if (!(dev->capability & DWC_I2S_RECORD) &&
++                      (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
++              return -EINVAL;
++
++      if (!(dev->capability & DWC_I2S_PLAY) &&
++                      (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
++              return -EINVAL;
++
++      if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++              dma_data = &dev->play_dma_data;
++      else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++              dma_data = &dev->capture_dma_data;
++
++      snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
++
++      return 0;
++}
++
++static void dw_i2s_config(struct i2svad_dev *dev, int stream)
++{
++      u32 ch_reg;
++      struct i2s_clk_config_data *config = &dev->config;
++
++
++      i2s_disable_channels(dev, stream);
++
++      for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
++              if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                      i2s_write_reg(dev->i2s_base, TCR(ch_reg),
++                                      dev->xfer_resolution);
++                      i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
++                                      dev->fifo_th - 1);
++                      i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
++              } else {
++                      i2s_write_reg(dev->i2s_base, RCR(ch_reg),
++                                      dev->xfer_resolution);
++                      i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
++                                      dev->fifo_th - 1);
++                      i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
++              }
++
++      }
++}
++
++static int i2svad_clks_get(struct platform_device *pdev,
++                              struct i2svad_dev *dev)
++{
++      dev->clk_apb_i2svad = devm_clk_get(&pdev->dev, "i2svad_apb");
++      if (IS_ERR(dev->clk_apb_i2svad)) {
++              dev_err(&pdev->dev, "failed to get clk_apb_i2svad: %ld\n",
++                              PTR_ERR(dev->clk_apb_i2svad));
++              return PTR_ERR(dev->clk_apb_i2svad);
++        }
++
++      return 0;
++}
++
++static int i2svad_resets_get(struct platform_device *pdev,
++                              struct i2svad_dev *dev)
++{
++      struct reset_control_bulk_data resets[] = {
++              { .id = "apb_i2svad" },
++              { .id = "i2svad_srst" },
++      };
++        int ret = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(resets), resets);
++      if (ret)
++              return ret;
++
++      dev->rst_apb_i2svad = resets[0].rstc;
++      dev->rst_i2svad_srst = resets[1].rstc;
++
++      return 0;
++}
++
++static int i2svad_clk_init(struct platform_device *pdev,
++                              struct i2svad_dev *dev)
++{
++      int ret;
++
++      ret = clk_prepare_enable(dev->clk_apb_i2svad);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to prepare enable clk_audio_root\n");
++              return ret;
++      }
++
++      ret = reset_control_deassert(dev->rst_apb_i2svad);
++        if (ret) {
++                printk(KERN_INFO "failed to deassert apb_i2svad\n");
++                return ret;
++        }
++
++      ret = reset_control_deassert(dev->rst_i2svad_srst);
++        if (ret) {
++                printk(KERN_INFO "failed to deassert i2svad_srst\n");
++                return ret;
++        }
++
++      return 0;
++}
++
++static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
++              struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++      struct i2svad_dev *dev = snd_soc_dai_get_drvdata(dai);
++      struct i2s_clk_config_data *config = &dev->config;
++      int ret;
++
++      switch (params_format(params)) {
++      case SNDRV_PCM_FORMAT_S16_LE:
++              config->data_width = 16;
++              dev->ccr = 0x00;
++              dev->xfer_resolution = 0x02;
++              break;
++
++      case SNDRV_PCM_FORMAT_S24_LE:
++              config->data_width = 24;
++              dev->ccr = 0x08;
++              dev->xfer_resolution = 0x04;
++              break;
++
++      case SNDRV_PCM_FORMAT_S32_LE:
++              config->data_width = 32;
++              dev->ccr = 0x10;
++              dev->xfer_resolution = 0x05;
++              break;
++
++      default:
++              dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
++              return -EINVAL;
++      }
++
++      config->chan_nr = params_channels(params);
++
++      switch (config->chan_nr) {
++      case EIGHT_CHANNEL_SUPPORT:
++      case SIX_CHANNEL_SUPPORT:
++      case FOUR_CHANNEL_SUPPORT:
++      case TWO_CHANNEL_SUPPORT:
++              break;
++      default:
++              dev_err(dev->dev, "channel not supported\n");
++              return -EINVAL;
++      }
++
++      dw_i2s_config(dev, substream->stream);
++
++      i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
++
++      config->sample_rate = params_rate(params);
++
++      if (dev->capability & DW_I2S_MASTER) {
++              if (dev->i2s_clk_cfg) {
++                      ret = dev->i2s_clk_cfg(config);
++                      if (ret < 0) {
++                              dev_err(dev->dev, "runtime audio clk config fail\n");
++                              return ret;
++                      }
++              } else {
++                      u32 bitclk = config->sample_rate *
++                                      config->data_width * 2;
++
++                      ret = clk_set_rate(dev->clk, bitclk);
++                      if (ret) {
++                              dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
++                                      ret);
++                              return ret;
++                      }
++              }
++      }
++      return 0;
++}
++
++static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
++              struct snd_soc_dai *dai)
++{
++      snd_soc_dai_set_dma_data(dai, substream, NULL);
++}
++
++static int dw_i2s_prepare(struct snd_pcm_substream *substream,
++                      struct snd_soc_dai *dai)
++{
++      struct i2svad_dev *dev = snd_soc_dai_get_drvdata(dai);
++
++      if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++              i2s_write_reg(dev->i2s_base, TXFFR, 1);
++      else
++              i2s_write_reg(dev->i2s_base, RXFFR, 1);
++
++      return 0;
++}
++
++static int dw_i2s_trigger(struct snd_pcm_substream *substream,
++              int cmd, struct snd_soc_dai *dai)
++{
++      struct i2svad_dev *dev = snd_soc_dai_get_drvdata(dai);
++      int ret = 0;
++
++      switch (cmd) {
++      case SNDRV_PCM_TRIGGER_START:
++      case SNDRV_PCM_TRIGGER_RESUME:
++      case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++              dev->active++;
++              i2s_start(dev, substream);
++              break;
++
++      case SNDRV_PCM_TRIGGER_STOP:
++      case SNDRV_PCM_TRIGGER_SUSPEND:
++      case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++              dev->active--;
++              i2s_stop(dev, substream);
++              break;
++      default:
++              ret = -EINVAL;
++              break;
++      }
++
++      if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++      {
++              vad_trigger(&(dev->vad),cmd);
++      }
++      return ret;
++}
++
++static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
++{
++      struct i2svad_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
++      int ret = 0;
++
++      switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++      case SND_SOC_DAIFMT_CBM_CFM:
++              if (dev->capability & DW_I2S_SLAVE)
++                      ret = 0;
++              else
++                      ret = -EINVAL;
++              break;
++      case SND_SOC_DAIFMT_CBS_CFS:
++              if (dev->capability & DW_I2S_MASTER)
++                      ret = 0;
++              else
++                      ret = -EINVAL;
++              break;
++      case SND_SOC_DAIFMT_CBM_CFS:
++      case SND_SOC_DAIFMT_CBS_CFM:
++              ret = -EINVAL;
++              break;
++      default:
++              dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
++              ret = -EINVAL;
++              break;
++      }
++      return ret;
++}
++
++static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
++      .startup        = dw_i2s_startup,
++      .shutdown       = dw_i2s_shutdown,
++      .hw_params      = dw_i2s_hw_params,
++      .prepare        = dw_i2s_prepare,
++      .trigger        = dw_i2s_trigger,
++      .set_fmt        = dw_i2s_set_fmt,
++};
++
++#ifdef CONFIG_PM
++static int dw_i2s_runtime_suspend(struct device *dev)
++{
++      struct i2svad_dev *dw_dev = dev_get_drvdata(dev);
++
++      if (dw_dev->capability & DW_I2S_MASTER)
++              clk_disable(dw_dev->clk);
++      return 0;
++}
++
++static int dw_i2s_runtime_resume(struct device *dev)
++{
++      struct i2svad_dev *dw_dev = dev_get_drvdata(dev);
++
++      if (dw_dev->capability & DW_I2S_MASTER)
++              clk_enable(dw_dev->clk);
++      return 0;
++}
++
++static int dw_i2s_suspend(struct snd_soc_component *component)
++{
++      struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
++
++      if (dev->capability & DW_I2S_MASTER)
++              clk_disable(dev->clk);
++      return 0;
++}
++
++static int dw_i2s_resume(struct snd_soc_component *component)
++{
++      struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
++      struct snd_soc_dai *dai;
++      int stream;
++
++      if (dev->capability & DW_I2S_MASTER)
++              clk_enable(dev->clk);
++
++      for_each_component_dais(component, dai) {
++              for_each_pcm_streams(stream)
++                      if (snd_soc_dai_stream_active(dai, stream))
++                              dw_i2s_config(dev, stream);
++      }
++
++      return 0;
++}
++
++#else
++#define dw_i2s_suspend        NULL
++#define dw_i2s_resume NULL
++#endif
++
++static int dw_i2svad_probe(struct snd_soc_component *component)
++{
++      vad_probe(component);
++      return 0;
++}
++
++static const struct snd_soc_component_driver dw_i2s_component = {
++      .name           = "dw-i2s",
++      .probe          = dw_i2svad_probe,
++      .suspend        = dw_i2s_suspend,
++      .resume         = dw_i2s_resume,
++};
++
++/*
++ * The following tables allow a direct lookup of various parameters
++ * defined in the I2S block's configuration in terms of sound system
++ * parameters.  Each table is sized to the number of entries possible
++ * according to the number of configuration bits describing an I2S
++ * block parameter.
++ */
++
++/* Maximum bit resolution of a channel - not uniformly spaced */
++static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
++      12, 16, 20, 24, 32, 0, 0, 0
++};
++
++/* Width of (DMA) bus */
++static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
++      DMA_SLAVE_BUSWIDTH_1_BYTE,
++      DMA_SLAVE_BUSWIDTH_2_BYTES,
++      DMA_SLAVE_BUSWIDTH_4_BYTES,
++      DMA_SLAVE_BUSWIDTH_UNDEFINED
++};
++
++/* PCM format to support channel resolution */
++static const u32 formats[COMP_MAX_WORDSIZE] = {
++      SNDRV_PCM_FMTBIT_S16_LE,
++      SNDRV_PCM_FMTBIT_S16_LE,
++      SNDRV_PCM_FMTBIT_S24_LE,
++      SNDRV_PCM_FMTBIT_S24_LE,
++      SNDRV_PCM_FMTBIT_S32_LE,
++      0,
++      0,
++      0
++};
++
++static const struct regmap_config sf_i2s_regmap_cfg = {
++      .reg_bits       = 32,
++      .val_bits       = 32,
++      .reg_stride     = 4,
++      .max_register   = 0x1000,
++};
++
++static int dw_configure_dai(struct i2svad_dev *dev,
++                              struct snd_soc_dai_driver *dw_i2s_dai,
++                              unsigned int rates)
++{
++      /*
++       * Read component parameter registers to extract
++       * the I2S block's configuration.
++       */
++      u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
++      u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
++      u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
++      u32 idx;
++
++      if (dev->capability & DWC_I2S_RECORD &&
++                      dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
++              comp1 = comp1 & ~BIT(5);
++
++      if (dev->capability & DWC_I2S_PLAY &&
++                      dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
++              comp1 = comp1 & ~BIT(6);
++
++      if (COMP1_TX_ENABLED(comp1)) {
++              dev_dbg(dev->dev, " designware: play supported\n");
++              idx = COMP1_TX_WORDSIZE_0(comp1);
++              if (WARN_ON(idx >= ARRAY_SIZE(formats)))
++                      return -EINVAL;
++              if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
++                      idx = 1;
++              dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
++              dw_i2s_dai->playback.channels_max =
++                              1 << (COMP1_TX_CHANNELS(comp1) + 1);
++              //dw_i2s_dai->playback.formats = formats[idx];
++              dw_i2s_dai->playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
++              dw_i2s_dai->playback.rates = rates;
++      }
++
++      if (COMP1_RX_ENABLED(comp1)) {
++              dev_dbg(dev->dev, "designware: record supported\n");
++              idx = COMP2_RX_WORDSIZE_0(comp2);
++              if (WARN_ON(idx >= ARRAY_SIZE(formats)))
++                      return -EINVAL;
++              if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
++                      idx = 1;
++              dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
++              dw_i2s_dai->capture.channels_max =
++                              1 << (COMP1_RX_CHANNELS(comp1) + 1);
++              //dw_i2s_dai->capture.formats = formats[idx];
++              dw_i2s_dai->capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
++              dw_i2s_dai->capture.rates = rates;
++      }
++
++      if (COMP1_MODE_EN(comp1)) {
++              dev_dbg(dev->dev, "designware: i2s master mode supported\n");
++              dev->capability |= DW_I2S_MASTER;
++      } else {
++              dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
++              dev->capability |= DW_I2S_SLAVE;
++      }
++
++      dev->fifo_th = fifo_depth / 2;
++      return 0;
++}
++
++static int dw_configure_dai_by_pd(struct i2svad_dev *dev,
++                              struct snd_soc_dai_driver *dw_i2s_dai,
++                              struct resource *res,
++                              const struct i2s_platform_data *pdata)
++{
++      u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
++      u32 idx = COMP1_APB_DATA_WIDTH(comp1);
++      int ret;
++
++      if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
++              return -EINVAL;
++
++      ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
++      if (ret < 0)
++              return ret;
++
++      if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
++              idx = 1;
++      /* Set DMA slaves info */
++      dev->play_dma_data.pd.data = pdata->play_dma_data;
++      dev->capture_dma_data.pd.data = pdata->capture_dma_data;
++      dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
++      dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
++      dev->play_dma_data.pd.max_burst = 16;
++      dev->capture_dma_data.pd.max_burst = 16;
++      dev->play_dma_data.pd.addr_width = bus_widths[idx];
++      dev->capture_dma_data.pd.addr_width = bus_widths[idx];
++      dev->play_dma_data.pd.filter = pdata->filter;
++      dev->capture_dma_data.pd.filter = pdata->filter;
++
++      return 0;
++}
++
++static int dw_configure_dai_by_dt(struct i2svad_dev *dev,
++                              struct snd_soc_dai_driver *dw_i2s_dai,
++                              struct resource *res)
++{
++      u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
++      u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
++      u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
++      u32 idx = COMP1_APB_DATA_WIDTH(comp1);
++      u32 idx2;
++      int ret;
++
++      if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
++              return -EINVAL;
++
++      ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
++      if (ret < 0)
++              return ret;
++
++      if (COMP1_TX_ENABLED(comp1)) {
++              idx2 = COMP1_TX_WORDSIZE_0(comp1);
++
++              dev->capability |= DWC_I2S_PLAY;
++              dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
++              dev->play_dma_data.dt.addr_width = bus_widths[idx];
++              dev->play_dma_data.dt.fifo_size = fifo_depth *
++                      (fifo_width[idx2]) >> 8;
++              dev->play_dma_data.dt.maxburst = 16;
++      }
++      if (COMP1_RX_ENABLED(comp1)) {
++              idx2 = COMP2_RX_WORDSIZE_0(comp2);
++
++              dev->capability |= DWC_I2S_RECORD;
++              dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
++              dev->capture_dma_data.dt.addr_width = bus_widths[idx];
++              dev->capture_dma_data.dt.fifo_size = fifo_depth *
++                      (fifo_width[idx2] >> 8);
++              dev->capture_dma_data.dt.maxburst = 16;
++      }
++
++      return 0;
++
++}
++
++static int dw_i2s_probe(struct platform_device *pdev)
++{
++      const struct i2s_platform_data *pdata = pdev->dev.platform_data;
++      struct i2svad_dev *dev;
++      struct resource *res;
++      int ret, irq;
++      struct snd_soc_dai_driver *dw_i2s_dai;
++      const char *clk_id;
++
++      dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
++      if (!dev)
++              return -ENOMEM;
++
++      dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
++      if (!dw_i2s_dai)
++              return -ENOMEM;
++
++      dw_i2s_dai->ops = &dw_i2s_dai_ops;
++
++      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
++      if (IS_ERR(dev->i2s_base))
++              return PTR_ERR(dev->i2s_base);
++
++      dev->vad.vad_base = dev->i2s_base;
++      dev->vad.vad_map = devm_regmap_init_mmio(&pdev->dev, dev->i2s_base, &sf_i2s_regmap_cfg);
++      if (IS_ERR(dev->vad.vad_map)) {
++              dev_err(&pdev->dev, "failed to init regmap: %ld\n",
++                      PTR_ERR(dev->vad.vad_map));
++              return PTR_ERR(dev->vad.vad_map);
++      }
++
++      dev->dev = &pdev->dev;
++
++      ret = i2svad_clks_get(pdev, dev);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to get i2svad clock\n");
++              return ret;
++      }
++
++      ret = i2svad_resets_get(pdev, dev);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to get i2svad reset controls\n");
++              return ret;
++        }
++
++      ret = i2svad_clk_init(pdev, dev);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to initialize i2svad clock\n");
++              return ret;
++      }
++
++      irq = platform_get_irq(pdev, 0);
++      if (irq >= 0) {
++              ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
++                              pdev->name, dev);
++              if (ret < 0) {
++                      dev_err(&pdev->dev, "failed to request irq\n");
++                      return ret;
++              }
++      }
++
++      dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
++      dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
++      if (pdata) {
++              dev->capability = pdata->cap;
++              clk_id = NULL;
++              dev->quirks = pdata->quirks;
++              if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
++                      dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
++                      dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
++              }
++              ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
++      } else {
++              clk_id = "i2sclk";
++              ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
++      }
++      if (ret < 0)
++              return ret;
++
++      if (dev->capability & DW_I2S_MASTER) {
++              if (pdata) {
++                      dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
++                      if (!dev->i2s_clk_cfg) {
++                              dev_err(&pdev->dev, "no clock configure method\n");
++                              return -ENODEV;
++                      }
++              }
++              dev->clk = devm_clk_get(&pdev->dev, clk_id);
++
++              if (IS_ERR(dev->clk))
++                      return PTR_ERR(dev->clk);
++
++              ret = clk_prepare_enable(dev->clk);
++              if (ret < 0)
++                      return ret;
++      }
++
++      dev_set_drvdata(&pdev->dev, dev);
++      ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
++                                       dw_i2s_dai, 1);
++      if (ret != 0) {
++              dev_err(&pdev->dev, "not able to register dai\n");
++              goto err_clk_disable;
++      }
++
++      if (!pdata) {
++              if (irq >= 0) {
++                      ret = i2svad_pcm_register(pdev);
++                      dev->use_pio = true;
++              } else {
++                      ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
++                                      0);
++                      dev->use_pio = false;
++              }
++
++              if (ret) {
++                      dev_err(&pdev->dev, "could not register pcm: %d\n",
++                                      ret);
++                      goto err_clk_disable;
++              }
++      }
++
++      vad_init(&(dev->vad));
++      pm_runtime_enable(&pdev->dev);
++
++      return 0;
++
++err_clk_disable:
++      if (dev->capability & DW_I2S_MASTER)
++              clk_disable_unprepare(dev->clk);
++      return ret;
++}
++
++static int dw_i2s_remove(struct platform_device *pdev)
++{
++      struct i2svad_dev *dev = dev_get_drvdata(&pdev->dev);
++
++      if (dev->capability & DW_I2S_MASTER)
++              clk_disable_unprepare(dev->clk);
++
++      pm_runtime_disable(&pdev->dev);
++      return 0;
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id dw_i2s_of_match[] = {
++      { .compatible = "starfive,sf-i2svad", },
++      {},
++};
++
++MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
++#endif
++
++static const struct dev_pm_ops dwc_pm_ops = {
++      SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
++};
++
++static struct platform_driver dw_i2s_driver = {
++      .probe          = dw_i2s_probe,
++      .remove         = dw_i2s_remove,
++      .driver         = {
++              .name   = "sf-i2svad",
++              .of_match_table = of_match_ptr(dw_i2s_of_match),
++              .pm = &dwc_pm_ops,
++      },
++};
++
++module_platform_driver(dw_i2s_driver);
++
++MODULE_AUTHOR("jenny zhang <jenny.zhang@starfivetech.com>");
++MODULE_DESCRIPTION("starfive I2SVAD SoC Interface");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:sf-i2svad");
+--- /dev/null
++++ b/sound/soc/starfive/i2svad.h
+@@ -0,0 +1,246 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef __SND_SOC_STARFIVE_I2SVAD_H
++#define __SND_SOC_STARFIVE_I2SVAD_H
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/reset.h>
++#include <linux/types.h>
++#include <sound/dmaengine_pcm.h>
++#include <sound/pcm.h>
++#include <sound/designware_i2s.h>
++
++/* common register for all channel */
++#define IER           0x000
++#define IRER          0x004
++#define ITER          0x008
++#define CER           0x00C
++#define CCR           0x010
++#define RXFFR         0x014
++#define TXFFR         0x018
++
++/* Interrupt status register fields */
++#define ISR_TXFO      BIT(5)
++#define ISR_TXFE      BIT(4)
++#define ISR_RXFO      BIT(1)
++#define ISR_RXDA      BIT(0)
++
++/* I2STxRxRegisters for all channels */
++#define LRBR_LTHR(x)  (0x40 * x + 0x020)
++#define RRBR_RTHR(x)  (0x40 * x + 0x024)
++#define RER(x)                (0x40 * x + 0x028)
++#define TER(x)                (0x40 * x + 0x02C)
++#define RCR(x)                (0x40 * x + 0x030)
++#define TCR(x)                (0x40 * x + 0x034)
++#define ISR(x)                (0x40 * x + 0x038)
++#define IMR(x)                (0x40 * x + 0x03C)
++#define ROR(x)                (0x40 * x + 0x040)
++#define TOR(x)                (0x40 * x + 0x044)
++#define RFCR(x)               (0x40 * x + 0x048)
++#define TFCR(x)               (0x40 * x + 0x04C)
++#define RFF(x)                (0x40 * x + 0x050)
++#define TFF(x)                (0x40 * x + 0x054)
++
++/* I2SCOMPRegisters */
++#define I2S_COMP_PARAM_2      0x01F0
++#define I2S_COMP_PARAM_1      0x01F4
++#define I2S_COMP_VERSION      0x01F8
++#define I2S_COMP_TYPE         0x01FC
++
++/* VAD Registers */
++#define VAD_LEFT_MARGIN                               0x800  /* left_margin */
++#define VAD_RIGHT_MARGIN                      0x804  /* right_margin */
++#define VAD_N_LOW_CONT_FRAMES                 0x808  /* low-energy transition range threshold ——NL*/
++#define VAD_N_LOW_SEEK_FRAMES                 0x80C  /* low-energy transition range */
++#define VAD_N_HIGH_CONT_FRAMES                        0x810  /* high-energy transition range threshold——NH */
++#define VAD_N_HIGH_SEEK_FRAMES                        0x814  /* high-energy transition range */
++#define VAD_N_SPEECH_LOW_HIGH_FRAMES          0x818  /* low-energy voice range threshold——NVL*/
++#define VAD_N_SPEECH_LOW_SEEK_FRAMES          0x81C  /* low-energy voice range*/
++#define VAD_MEAN_SIL_FRAMES                   0x820  /* mean silence frame range*/
++#define VAD_N_ALPHA                           0x824  /* low-energy threshold scaling factor,12bit(0~0xFFF)*/
++#define VAD_N_BETA                            0x828  /* high-energy threshold scaling factor,12bit(0~0xFFF)*/
++#define VAD_FIFO_DEPTH                                0x82C  /* status register for VAD */
++#define VAD_LR_SEL                            0x840  /* L/R channel data selection for processing */
++#define VAD_SW                                        0x844  /* push enable signal*/
++#define VAD_LEFT_WD                           0x848  /* select left channel*/
++#define VAD_RIGHT_WD                          0x84C  /* select right channel*/
++#define VAD_STOP_DELAY                                0x850  /* delay stop for 0-3 samples*/
++#define VAD_ADDR_START                                0x854  /* vad memory start address, align with 64bit*/
++#define VAD_ADDR_WRAP                         0x858  /* vad memory highest address for Push, align with 64bit,(addr_wrap-1) is the max physical address*/
++#define VAD_MEM_SW                            0x85C  /* xmem switch */
++#define VAD_SPINT_CLR                         0x860  /* clear vad_spint interrup status*/
++#define VAD_SPINT_EN                          0x864  /* disable/enable vad_spint from vad_flag rising edge*/
++#define VAD_SLINT_CLR                         0x868  /* clear vad_slint interrup status*/
++#define VAD_SLINT_EN                          0x86C  /* disable/enable  vad_slint from vad_flag falling edge*/
++#define VAD_RAW_SPINT                         0x870  /* status of spint before vad_spint_en*/
++#define VAD_RAW_SLINT                         0x874  /* status of slint before vad_slint_en*/
++#define VAD_SPINT                             0x878  /* status of spint after vad_spint_en*/
++#define VAD_SLINT                             0x87C  /* status of slint before vad_slint_en*/
++#define VAD_XMEM_ADDR                         0x880  /* next xmem address ,align to 16bi*/
++#define VAD_I2S_CTRL_REG_ADDR                 0x884
++
++/*
++ * vad parameter register fields
++ */
++#define VAD_LEFT_MARGIN_MASK                  GENMASK(4, 0)
++#define VAD_RIGHT_MARGIN_MASK                 GENMASK(4, 0)
++#define VAD_N_LOW_CONT_FRAMES_MASK            GENMASK(4, 0)
++#define VAD_N_LOW_SEEK_FRAMES_MASK            GENMASK(4, 0)
++#define VAD_N_HIGH_CONT_FRAMES_MASK           GENMASK(4, 0)
++#define VAD_N_HIGH_SEEK_FRAMES_MASK           GENMASK(4, 0)
++#define VAD_N_SPEECH_LOW_HIGH_FRAMES_MASK     GENMASK(4, 0)
++#define VAD_N_SPEECH_LOW_SEEK_FRAMES_MASK     GENMASK(4, 0)
++#define VAD_MEAN_SIL_FRAMES_MASK              GENMASK(4, 0)
++#define VAD_N_ALPHA_MASK                      GENMASK(11, 0)
++#define VAD_N_BETA_MASK                               GENMASK(11, 0)
++#define VAD_LR_SEL_MASK                               GENMASK(0, 0)
++#define VAD_LR_SEL_L                          (0 << 0)
++#define VAD_LR_SEL_R                          (1 << 0)
++
++#define VAD_SW_MASK                           GENMASK(1, 0)
++#define VAD_SW_VAD_XMEM_ENABLE                        (1 << 0)
++#define VAD_SW_VAD_XMEM_DISABLE                       (0 << 0)
++#define VAD_SW_ADC_ENABLE                     (1 << 1)
++#define VAD_SW_ADC_DISABLE                    (0 << 1)
++
++
++#define VAD_LEFT_WD_MASK                      GENMASK(0, 0)
++#define VAD_LEFT_WD_BIT_31_16                 (1 << 1)
++#define VAD_LEFT_WD_BIT_15_0                  (0 << 1)
++
++
++#define VAD_RIGHT_WD_MASK                     GENMASK(0, 0)
++#define VAD_RIGHT_WD_BIT_31_16                        (1 << 1)
++#define VAD_RIGHT_WD_BIT_15_0                 (0 << 1)
++
++
++#define VAD_STOP_DELAY_MASK                   GENMASK(1, 0)
++#define VAD_STOP_DELAY_0_SAMPLE                       0
++#define VAD_STOP_DELAY_1_SAMPLE                       1
++#define VAD_STOP_DELAY_2_SAMPLE                       2
++#define VAD_STOP_DELAY_3_SAMPLE                       3
++
++#define VAD_ADDR_START_MASK                   GENMASK(12, 0)
++#define VAD_ADDR_WRAP_MASK                    GENMASK(13, 0)
++#define VAD_MEM_SW_MASK                               GENMASK(0, 0)
++#define VAD_SPINT_CLR_MASK                    GENMASK(0, 0)
++#define VAD_SPINT_EN_MASK                     GENMASK(0, 0)
++#define VAD_SLINT_CLR_MASK                    GENMASK(0, 0)
++#define VAD_SLINT_EN_MASK                     GENMASK(0, 0)
++#define VAD_I2S_CTRL_REG_ADDR_MASK            GENMASK(0, 0)
++
++#define VAD_MEM_SW_TO_VAD                     (1 << 0)
++#define VAD_MEM_SW_TO_AXI                     (0 << 0)
++
++#define VAD_SPINT_CLR_VAD_SPINT                       (1 << 0)
++
++#define VAD_SPINT_EN_ENABLE                   (1 << 0)
++#define VAD_SPINT_EN_DISABLE                  (0 << 0)
++
++#define VAD_SLINT_CLR_VAD_SLINT                       (1 << 0)
++
++#define VAD_SLINT_EN_ENABLE                   (1 << 0)
++#define VAD_SLINT_EN_DISABLE                  (0 << 0)
++
++#define VAD_STATUS_NORMAL                     0
++#define VAD_STATUS_SPINT                      1
++#define VAD_STATUS_SLINT                      2
++
++/*
++ * Component parameter register fields - define the I2S block's
++ * configuration.
++ */
++#define COMP1_TX_WORDSIZE_3(r)                (((r) & GENMASK(27, 25)) >> 25)
++#define COMP1_TX_WORDSIZE_2(r)                (((r) & GENMASK(24, 22)) >> 22)
++#define COMP1_TX_WORDSIZE_1(r)                (((r) & GENMASK(21, 19)) >> 19)
++#define COMP1_TX_WORDSIZE_0(r)                (((r) & GENMASK(18, 16)) >> 16)
++#define COMP1_TX_CHANNELS(r)          (((r) & GENMASK(10, 9)) >> 9)
++#define COMP1_RX_CHANNELS(r)          (((r) & GENMASK(8, 7)) >> 7)
++#define COMP1_RX_ENABLED(r)           (((r) & BIT(6)) >> 6)
++#define COMP1_TX_ENABLED(r)           (((r) & BIT(5)) >> 5)
++#define COMP1_MODE_EN(r)              (((r) & BIT(4)) >> 4)
++#define COMP1_FIFO_DEPTH_GLOBAL(r)    (((r) & GENMASK(3, 2)) >> 2)
++#define COMP1_APB_DATA_WIDTH(r)               (((r) & GENMASK(1, 0)) >> 0)
++
++#define COMP2_RX_WORDSIZE_3(r)                (((r) & GENMASK(12, 10)) >> 10)
++#define COMP2_RX_WORDSIZE_2(r)                (((r) & GENMASK(9, 7)) >> 7)
++#define COMP2_RX_WORDSIZE_1(r)                (((r) & GENMASK(5, 3)) >> 3)
++#define COMP2_RX_WORDSIZE_0(r)                (((r) & GENMASK(2, 0)) >> 0)
++
++/* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
++#define COMP_MAX_WORDSIZE             (1 << 3)
++#define COMP_MAX_DATA_WIDTH           (1 << 2)
++
++#define MAX_CHANNEL_NUM               8
++#define MIN_CHANNEL_NUM               2
++#define ALL_CHANNEL_NUM               4
++
++
++union dw_i2s_snd_dma_data {
++      struct i2s_dma_data pd;
++      struct snd_dmaengine_dai_dma_data dt;
++};
++
++struct vad_params {
++      void __iomem *vad_base;
++      struct regmap *vad_map;
++      unsigned int vswitch;
++      unsigned int vstatus; /*vad detect status: 1:SPINT 2:SLINT 0:normal*/
++};
++
++struct i2svad_dev {
++      void __iomem *i2s_base;
++      struct clk *clk;
++      int active;
++      unsigned int capability;
++      unsigned int quirks;
++      unsigned int i2s_reg_comp1;
++      unsigned int i2s_reg_comp2;
++      struct device *dev;
++      u32 ccr;
++      u32 xfer_resolution;
++      u32 fifo_th;
++
++      struct clk *clk_apb_i2svad;
++      struct reset_control *rst_apb_i2svad;
++      struct reset_control *rst_i2svad_srst;
++
++      /* data related to DMA transfers b/w i2s and DMAC */
++      union dw_i2s_snd_dma_data play_dma_data;
++      union dw_i2s_snd_dma_data capture_dma_data;
++      struct i2s_clk_config_data config;
++      int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
++
++      /* data related to PIO transfers */
++      bool use_pio;
++      struct snd_pcm_substream __rcu *tx_substream;
++      struct snd_pcm_substream __rcu *rx_substream;
++      unsigned int (*tx_fn)(struct i2svad_dev *dev,
++                      struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
++                      bool *period_elapsed);
++      unsigned int (*rx_fn)(struct i2svad_dev *dev,
++                      struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
++                      bool *period_elapsed);
++      unsigned int tx_ptr;
++      unsigned int rx_ptr;
++
++      struct vad_params vad;
++};
++
++#if IS_ENABLED(CONFIG_SND_STARFIVE_I2SVAD_PCM)
++void i2svad_pcm_push_tx(struct i2svad_dev *dev);
++void i2svad_pcm_pop_rx(struct i2svad_dev *dev);
++int i2svad_pcm_register(struct platform_device *pdev);
++#else
++void i2svad_pcm_push_tx(struct i2svad_dev *dev) { }
++void i2svad_pcm_pop_rx(struct i2svad_dev *dev) { }
++int i2svad_pcm_register(struct platform_device *pdev)
++{
++      return -EINVAL;
++}
++#endif
++
++#endif
+--- /dev/null
++++ b/sound/soc/starfive/pdm.c
+@@ -0,0 +1,362 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/clk.h>
++#include <linux/module.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
++#include <linux/regmap.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/tlv.h>
++
++#include "pdm.h"
++
++#define AUDIOC_CLK    (12288000)
++#define PDM_MUL       (128)
++
++struct sf_pdm {
++      struct regmap *pdm_map;
++      struct regmap *clk_map;
++      struct clk *clk;
++};
++
++static const DECLARE_TLV_DB_SCALE(volume_tlv, -9450, 150, 0);
++
++static const struct snd_kcontrol_new sf_pdm_snd_controls[] = {
++      SOC_SINGLE("DC compensation Control", PDM_DMIC_CTRL0, 30, 1, 0),
++      SOC_SINGLE("High Pass Filter Control", PDM_DMIC_CTRL0, 28, 1, 0),
++      SOC_SINGLE("Left Channel Volume Control", PDM_DMIC_CTRL0, 23, 1, 0),
++      SOC_SINGLE("Right Channel Volume Control", PDM_DMIC_CTRL0, 22, 1, 0),
++      SOC_SINGLE_TLV("Volume", PDM_DMIC_CTRL0, 16, 0x3F, 1, volume_tlv),
++      SOC_SINGLE("Data MSB Shift", PDM_DMIC_CTRL0, 1, 7, 0),
++      SOC_SINGLE("SCALE", PDM_DC_SCALE0, 0, 0x3F, 0),
++      SOC_SINGLE("DC offset", PDM_DC_SCALE0, 8, 0xFFFFF, 0),
++};
++
++static int sf_pdm_set_mclk(struct regmap *map, unsigned int clk, unsigned int weight)
++{
++      int mclk_div,bclk_div,lrclk_div;
++      u32     pdm_div;
++
++      /*
++      audio source clk:12288000, mclk_div:4, mclk:3M
++      support 8K/16K/32K/48K sample reate
++      suapport 16/24/32 bit weight
++      bit weight 32
++      mclk bclk  lrclk
++      3M   1.5M  48K
++      3M   1M    32K
++      3M   0.5M  16K
++      3M   0.25M  8K
++
++      bit weight 24,set lrclk_div as 32
++      mclk bclk  lrclk
++      3M   1.5M  48K
++      3M   1M    32K
++      3M   0.5M  16K
++      3M   0.25M  8K
++
++      bit weight 16
++      mclk bclk   lrclk
++      3M   0.75M  48K
++      3M   0.5M   32K
++      3M   0.25M  16K
++      3M   0.125M 8K
++      */
++
++      switch (clk) {
++      case 8000:
++      case 16000:
++      case 32000:
++      case 48000:
++              break;
++      default:
++              printk(KERN_ERR "sample rate:%d\n", clk);
++              return -EINVAL;
++      }
++
++      switch (weight) {
++      case 16:
++      case 24:
++      case 32:
++              break;
++      default:
++              printk(KERN_ERR "bit weight:%d\n", weight);
++              return -EINVAL;
++      }
++
++      if (24 == weight) {
++              weight = 32;
++      }
++
++      mclk_div = 4;
++      bclk_div = AUDIOC_CLK/mclk_div/(clk*weight);
++      lrclk_div = weight;
++
++      /* PDM MCLK = 128*LRCLK */
++      pdm_div = AUDIOC_CLK/(PDM_MUL*clk);
++
++      regmap_update_bits(map, AUDIO_CLK_ADC_MCLK, 0x0F, mclk_div);
++      regmap_update_bits(map, AUDIO_CLK_I2SADC_BCLK, 0x1F, bclk_div);
++      regmap_update_bits(map, AUDIO_CLK_ADC_LRCLK, 0x3F, lrclk_div);
++      regmap_update_bits(map, AUDIO_CLK_PDM_CLK, 0x0F, pdm_div);
++
++      return 0;
++}
++
++static void sf_pdm_enable(struct regmap *map)
++{
++      /* Enable PDM */
++      regmap_update_bits(map, PDM_DMIC_CTRL0, 0x01<<PDM_DMIC_RVOL_OFFSET, 0);
++      regmap_update_bits(map, PDM_DMIC_CTRL0, 0x01<<PDM_DMIC_LVOL_OFFSET, 0);
++}
++
++static void sf_pdm_disable(struct regmap *map)
++{
++      regmap_update_bits(map, PDM_DMIC_CTRL0,
++              0x01<<PDM_DMIC_RVOL_OFFSET, 0x01<<PDM_DMIC_RVOL_OFFSET);
++      regmap_update_bits(map, PDM_DMIC_CTRL0,
++              0x01<<PDM_DMIC_LVOL_OFFSET, 0x01<<PDM_DMIC_LVOL_OFFSET);
++}
++
++static int sf_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
++                      struct snd_soc_dai *dai)
++{
++      struct sf_pdm *priv = snd_soc_dai_get_drvdata(dai);
++
++      switch (cmd) {
++      case SNDRV_PCM_TRIGGER_START:
++      case SNDRV_PCM_TRIGGER_RESUME:
++      case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++              sf_pdm_enable(priv->pdm_map);
++              return 0;
++
++      case SNDRV_PCM_TRIGGER_STOP:
++      case SNDRV_PCM_TRIGGER_SUSPEND:
++      case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++              sf_pdm_disable(priv->pdm_map);
++              return 0;
++
++      default:
++              return -EINVAL;
++      }
++}
++
++static int sf_pdm_hw_params(struct snd_pcm_substream *substream,
++                      struct snd_pcm_hw_params *params,
++                      struct snd_soc_dai *dai)
++{
++      struct sf_pdm *priv = snd_soc_dai_get_drvdata(dai);
++      unsigned int rate = params_rate(params);
++      unsigned int width;
++      int ret;
++
++      if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++              return 0;
++
++      width = params_width(params);
++      switch (width) {
++      case 16:
++      case 24:
++      case 32:
++              break;
++      default:
++              dev_err(dai->dev, "unsupported sample width\n");
++              return -EINVAL;
++      }
++
++      ret = sf_pdm_set_mclk(priv->clk_map, rate, width);
++      if (ret < 0) {
++              dev_err(dai->dev, "unsupported sample rate\n");
++              return -EINVAL;
++      }
++
++      return 0;
++}
++
++static const struct snd_soc_dai_ops sf_pdm_dai_ops = {
++      .trigger        = sf_pdm_trigger,
++      .hw_params      = sf_pdm_hw_params,
++};
++
++static int sf_pdm_dai_probe(struct snd_soc_dai *dai)
++{
++      struct sf_pdm *priv = snd_soc_dai_get_drvdata(dai);
++
++      /* Reset */
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x01<<PDM_DMIC_SW_RSTN_OFFSET, 0x00);
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x01<<PDM_DMIC_SW_RSTN_OFFSET, 0x01<<PDM_DMIC_SW_RSTN_OFFSET);
++
++      /* Make sure the device is initially disabled */
++      sf_pdm_disable(priv->pdm_map);
++
++      /* MUTE */
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x3F<<PDM_DMIC_VOL_OFFSET, 0x3F<<PDM_DMIC_VOL_OFFSET);
++
++      /* UNMUTE */
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x3F<<PDM_DMIC_VOL_OFFSET, 0);
++
++      /* enable high pass filter */
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x01<<PDM_DMIC_ENHPF_OFFSET, 0x01<<PDM_DMIC_ENHPF_OFFSET);
++
++      /* i2s slaver mode */
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x01<<PDM_DMIC_I2SMODE_OFFSET, 0x01<<PDM_DMIC_I2SMODE_OFFSET);
++
++      /* disable fast mode */
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x01<<PDM_DMIC_FASTMODE_OFFSET, 0);
++
++      /* enable dc bypass mode */
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x01<<PDM_DMIC_DCBPS_OFFSET, 0);
++
++      /* dmic msb shift 0 */
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x07<<PDM_DMIC_MSB_SHIFT_OFFSET, 0);
++
++      /* scale:0 */
++      regmap_update_bits(priv->pdm_map, PDM_DC_SCALE0, 0x3F, 0x08);
++
++      /* DC offset:0 */
++      regmap_update_bits(priv->pdm_map, PDM_DC_SCALE0,
++              0xFFFFF<<PDM_DMIC_DCOFF1_OFFSET, 0xC0005<<PDM_DMIC_DCOFF1_OFFSET);
++
++      return 0;
++}
++
++static int sf_pdm_dai_remove(struct snd_soc_dai *dai)
++{
++      struct sf_pdm *priv = snd_soc_dai_get_drvdata(dai);
++
++      /* MUTE */
++      regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
++              0x3F<<PDM_DMIC_VOL_OFFSET, 0x3F<<PDM_DMIC_VOL_OFFSET);
++
++      return 0;
++}
++
++#define SF_PCM_RATE (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|\
++                                      SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_48000)
++
++static struct snd_soc_dai_driver sf_pdm_dai_drv = {
++      .name = "PDM",
++      .id = 0,
++      .capture = {
++              .stream_name    = "Capture",
++              .channels_min   = 2,
++              .channels_max   = 2,
++              .rates          =       SF_PCM_RATE,
++              .formats        =       SNDRV_PCM_FMTBIT_S16_LE|\
++                                              SNDRV_PCM_FMTBIT_S24_LE|\
++                                              SNDRV_PCM_FMTBIT_S32_LE,
++      },
++      .ops            = &sf_pdm_dai_ops,
++      .probe          = sf_pdm_dai_probe,
++      .remove         = sf_pdm_dai_remove,
++      .symmetric_rate = 1,
++};
++
++static int pdm_probe(struct snd_soc_component *component)
++{
++      struct sf_pdm *priv = snd_soc_component_get_drvdata(component);
++
++      snd_soc_component_init_regmap(component, priv->pdm_map);
++      snd_soc_add_component_controls(component, sf_pdm_snd_controls,
++                              ARRAY_SIZE(sf_pdm_snd_controls));
++
++      return 0;
++}
++
++static const struct snd_soc_component_driver sf_pdm_component_drv = {
++      .name = "sf-pdm",
++      .probe = pdm_probe,
++};
++
++static const struct regmap_config sf_pdm_regmap_cfg = {
++      .reg_bits       = 32,
++      .val_bits       = 32,
++      .reg_stride     = 4,
++      .max_register   = 0x20,
++};
++
++static const struct regmap_config sf_audio_clk_regmap_cfg = {
++      .reg_bits       = 32,
++      .val_bits       = 32,
++      .reg_stride     = 4,
++      .max_register   = 0x100,
++};
++
++static int sf_pdm_probe(struct platform_device *pdev)
++{
++      struct device *dev = &pdev->dev;
++      struct sf_pdm *priv;
++      struct resource *res;
++      void __iomem *regs;
++
++      priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++      if (!priv)
++              return -ENOMEM;
++      platform_set_drvdata(pdev, priv);
++
++      res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pdm");
++      regs = devm_ioremap_resource(&pdev->dev, res);
++      if (IS_ERR(regs))
++              return PTR_ERR(regs);
++
++      priv->pdm_map = devm_regmap_init_mmio(dev, regs, &sf_pdm_regmap_cfg);
++      if (IS_ERR(priv->pdm_map)) {
++              dev_err(dev, "failed to init regmap: %ld\n",
++                      PTR_ERR(priv->pdm_map));
++              return PTR_ERR(priv->pdm_map);
++      }
++
++      res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audio-clk");
++      regs = devm_ioremap_resource(&pdev->dev, res);
++      if (IS_ERR(regs))
++              return PTR_ERR(regs);
++
++      priv->clk_map = devm_regmap_init_mmio(dev, regs, &sf_audio_clk_regmap_cfg);
++      if (IS_ERR(priv->clk_map)) {
++              dev_err(dev, "failed to init regmap: %ld\n",
++                      PTR_ERR(priv->clk_map));
++              return PTR_ERR(priv->clk_map);
++      }
++
++      return devm_snd_soc_register_component(dev, &sf_pdm_component_drv,
++                                      &sf_pdm_dai_drv, 1);
++}
++
++static int sf_pdm_dev_remove(struct platform_device *pdev)
++{
++      return 0;
++}
++static const struct of_device_id sf_pdm_of_match[] = {
++      {.compatible = "starfive,sf-pdm",},
++      {}
++};
++MODULE_DEVICE_TABLE(of, sf_pdm_of_match);
++
++static struct platform_driver sf_pdm_driver = {
++
++      .driver = {
++              .name = "sf-pdm",
++              .of_match_table = sf_pdm_of_match,
++      },
++      .probe = sf_pdm_probe,
++      .remove = sf_pdm_dev_remove,
++};
++module_platform_driver(sf_pdm_driver);
++
++MODULE_AUTHOR("michael.yan <michael.yan@starfivetech.com>");
++MODULE_DESCRIPTION("starfive PDM Controller Driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/sound/soc/starfive/pdm.h
+@@ -0,0 +1,43 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef __SND_SOC_STARFIVE_PDM_H
++#define __SND_SOC_STARFIVE_PDM_H
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/types.h>
++#include <sound/dmaengine_pcm.h>
++#include <sound/pcm.h>
++#include <linux/dmaengine.h>
++#include <linux/types.h>
++
++#define PDM_DMIC_CTRL0                        (0x00)
++#define PDM_DC_SCALE0                 (0x04)
++#define PDM_DMIC_CTRL1                        (0x10)
++#define PDM_DC_SCALE1                 (0x14)
++
++/* PDM CTRL OFFSET */
++#define PDM_DMIC_MSB_SHIFT_OFFSET     (1)
++#define PDM_DMIC_VOL_OFFSET           (16)
++#define PDM_DMIC_RVOL_OFFSET          (22)
++#define PDM_DMIC_LVOL_OFFSET          (23)
++#define PDM_DMIC_I2SMODE_OFFSET               (24)
++#define PDM_DMIC_ENHPF_OFFSET         (28)
++#define PDM_DMIC_FASTMODE_OFFSET      (29)
++#define PDM_DMIC_DCBPS_OFFSET         (30)
++#define PDM_DMIC_SW_RSTN_OFFSET               (31)
++
++/* PDM SCALE OFFSET */
++#define PDM_DMIC_DCOFF3_OFFSET                (24)
++#define PDM_DMIC_DCOFF2_OFFSET                (16)
++#define PDM_DMIC_DCOFF1_OFFSET                (8)
++#define PDM_DMIC_SCALE_OFFSET         (0)
++
++#define AUDIO_CLK_ADC_MCLK            0x0
++#define AUDIO_CLK_I2SADC_BCLK         0xC
++#define AUDIO_CLK_ADC_LRCLK           0x14
++#define AUDIO_CLK_PDM_CLK             0x1C
++
++#endif /* __SND_SOC_STARFIVE_PDM_H */
+--- /dev/null
++++ b/sound/soc/starfive/pwmdac-pcm.c
+@@ -0,0 +1,232 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/io.h>
++#include <linux/rcupdate.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include "pwmdac.h"
++
++#define BUFFER_BYTES_MAX      (3 * 2 * 8 * PERIOD_BYTES_MIN)
++#define PERIOD_BYTES_MIN      4096
++#define PERIODS_MIN           2
++
++static unsigned int sf_pwmdac_pcm_tx_8(struct sf_pwmdac_dev *dev,
++              struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
++              bool *period_elapsed)
++{
++      const u8 (*p)[2] = (void *)runtime->dma_area;
++      unsigned int period_pos = tx_ptr % runtime->period_size;
++      int i;
++      u32 basedat = 0;
++
++      for (i = 0; i < dev->fifo_th; i++) {
++              basedat = (p[tx_ptr][0]<<8)|(p[tx_ptr][1] << 24);
++              iowrite32(basedat,dev->pwmdac_base + PWMDAC_WDATA);
++              period_pos++;
++              if (++tx_ptr >= runtime->buffer_size)
++                      tx_ptr = 0;
++      }
++
++      *period_elapsed = period_pos >= runtime->period_size;
++
++      return tx_ptr;
++}
++
++
++static unsigned int sf_pwmdac_pcm_tx_16(struct sf_pwmdac_dev *dev,
++              struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
++              bool *period_elapsed)
++{
++      const u16 (*p)[2] = (void *)runtime->dma_area;
++      unsigned int period_pos = tx_ptr % runtime->period_size;
++      int i;
++      u32 basedat = 0;
++
++      for (i = 0; i < dev->fifo_th; i++) {
++              basedat = (p[tx_ptr][0])|(p[tx_ptr][1] << 16);
++              iowrite32(basedat,dev->pwmdac_base + PWMDAC_WDATA);
++              period_pos++;
++              if (++tx_ptr >= runtime->buffer_size)
++                      tx_ptr = 0;
++      }
++
++      *period_elapsed = period_pos >= runtime->period_size;
++      return tx_ptr;
++}
++
++static const struct snd_pcm_hardware sf_pcm_hardware = {
++      .info = SNDRV_PCM_INFO_INTERLEAVED |
++              SNDRV_PCM_INFO_MMAP |
++              SNDRV_PCM_INFO_MMAP_VALID |
++              SNDRV_PCM_INFO_BLOCK_TRANSFER,
++      .rates = SNDRV_PCM_RATE_16000,
++      .rate_min = 16000,
++      .rate_max = 16000,
++      .formats = SNDRV_PCM_FMTBIT_S16_LE,
++      .channels_min = 2,
++      .channels_max = 2,
++      .buffer_bytes_max = BUFFER_BYTES_MAX,
++      .period_bytes_min = PERIOD_BYTES_MIN,
++      .period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
++      .periods_min = PERIODS_MIN,
++      .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
++      .fifo_size = 2,
++};
++
++static void sf_pcm_transfer(struct sf_pwmdac_dev *dev, bool push)
++{
++      struct snd_pcm_substream *substream;
++      bool active, period_elapsed;
++
++      rcu_read_lock();
++      if (push)
++              substream = rcu_dereference(dev->tx_substream);
++
++      active = substream && snd_pcm_running(substream);
++      if (active) {
++              unsigned int ptr;
++              unsigned int new_ptr;
++
++              if (push) {
++                      ptr = READ_ONCE(dev->tx_ptr);
++                      new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
++                                      &period_elapsed);
++                      cmpxchg(&dev->tx_ptr, ptr, new_ptr);
++              }
++
++              if (period_elapsed)
++                      snd_pcm_period_elapsed(substream);
++      }
++      rcu_read_unlock();
++}
++
++void sf_pwmdac_pcm_push_tx(struct sf_pwmdac_dev *dev)
++{
++      sf_pcm_transfer(dev, true);
++}
++
++
++static int sf_pcm_open(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
++      struct sf_pwmdac_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
++
++      snd_soc_set_runtime_hwparams(substream, &sf_pcm_hardware);
++      snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
++      runtime->private_data = dev;
++
++      return 0;
++}
++
++
++static int sf_pcm_close(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream)
++{
++      synchronize_rcu();
++      return 0;
++}
++
++static int sf_pcm_hw_params(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream,
++                      struct snd_pcm_hw_params *hw_params)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct sf_pwmdac_dev *dev = runtime->private_data;
++
++      switch (params_channels(hw_params)) {
++      case 2:
++              break;
++      default:
++              dev_err(dev->dev, "invalid channels number\n");
++              return -EINVAL;
++      }
++
++      switch (params_format(hw_params)) {
++      case SNDRV_PCM_FORMAT_U8:
++      case SNDRV_PCM_FORMAT_S8:
++              dev->tx_fn = sf_pwmdac_pcm_tx_8;
++              break;
++      case SNDRV_PCM_FORMAT_S16_LE:
++              dev->tx_fn = sf_pwmdac_pcm_tx_16;
++              break;
++      default:
++              dev_err(dev->dev, "invalid format\n");
++              return -EINVAL;
++      }
++
++              return 0;
++}
++
++
++static int sf_pcm_trigger(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream, int cmd)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct sf_pwmdac_dev *dev = runtime->private_data;
++      int ret = 0;
++
++      switch (cmd) {
++      case SNDRV_PCM_TRIGGER_START:
++      case SNDRV_PCM_TRIGGER_RESUME:
++      case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++              if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                      WRITE_ONCE(dev->tx_ptr, 0);
++                      rcu_assign_pointer(dev->tx_substream, substream);
++              }
++              break;
++      case SNDRV_PCM_TRIGGER_STOP:
++      case SNDRV_PCM_TRIGGER_SUSPEND:
++      case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++              if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++                      rcu_assign_pointer(dev->tx_substream, NULL);
++              break;
++      default:
++              ret = -EINVAL;
++              break;
++      }
++
++      return ret;
++}
++
++static snd_pcm_uframes_t sf_pcm_pointer(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct sf_pwmdac_dev *dev = runtime->private_data;
++      snd_pcm_uframes_t pos;
++
++      if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++              pos = READ_ONCE(dev->tx_ptr);
++
++      return pos < runtime->buffer_size ? pos : 0;
++}
++
++static int sf_pcm_new(struct snd_soc_component *component,
++                      struct snd_soc_pcm_runtime *rtd)
++{
++      size_t size = sf_pcm_hardware.buffer_bytes_max;
++
++      snd_pcm_set_managed_buffer_all(rtd->pcm,
++                      SNDRV_DMA_TYPE_CONTINUOUS,
++                      NULL, size, size);
++      return 0;
++}
++
++static const struct snd_soc_component_driver dw_pcm_component = {
++      .open           = sf_pcm_open,
++      .close          = sf_pcm_close,
++      .hw_params      = sf_pcm_hw_params,
++      .trigger        = sf_pcm_trigger,
++      .pointer        = sf_pcm_pointer,
++      .pcm_construct  = sf_pcm_new,
++};
++
++int sf_pwmdac_pcm_register(struct platform_device *pdev)
++{
++      return devm_snd_soc_register_component(&pdev->dev, &dw_pcm_component,
++                                      NULL, 0);
++}
+--- /dev/null
++++ b/sound/soc/starfive/pwmdac-transmitter.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/slab.h>
++#include <sound/soc.h>
++#include <sound/pcm.h>
++#include <sound/initval.h>
++#include <linux/of.h>
++
++#define DRV_NAME "pwmdac-dit"
++
++#define STUB_RATES    SNDRV_PCM_RATE_8000_192000
++#define STUB_FORMATS  (SNDRV_PCM_FMTBIT_S8|\
++                      SNDRV_PCM_FMTBIT_U8      |\
++                      SNDRV_PCM_FMTBIT_S16_LE  | \
++                      SNDRV_PCM_FMTBIT_S20_3LE | \
++                      SNDRV_PCM_FMTBIT_S24_LE  | \
++                      SNDRV_PCM_FMTBIT_S32_LE)
++
++static const struct snd_soc_dapm_widget dit_widgets[] = {
++      SND_SOC_DAPM_OUTPUT("pwmdac-out"),
++};
++
++static const struct snd_soc_dapm_route dit_routes[] = {
++      { "pwmdac-out", NULL, "Playback" },
++};
++
++static struct snd_soc_component_driver soc_codec_pwmdac_dit = {
++      .dapm_widgets           = dit_widgets,
++      .num_dapm_widgets       = ARRAY_SIZE(dit_widgets),
++      .dapm_routes            = dit_routes,
++      .num_dapm_routes        = ARRAY_SIZE(dit_routes),
++      .idle_bias_on           = 1,
++      .use_pmdown_time        = 1,
++      .endianness             = 1,
++      .non_legacy_dai_naming  = 1,
++};
++
++static struct snd_soc_dai_driver dit_stub_dai = {
++      .name           = "pwmdac-dit-hifi",
++      .playback       = {
++              .stream_name    = "Playback",
++              .channels_min   = 1,
++              .channels_max   = 384,
++              .rates          = STUB_RATES,
++              .formats        = STUB_FORMATS,
++      },
++};
++
++static int pwmdac_dit_probe(struct platform_device *pdev)
++{
++
++      return devm_snd_soc_register_component(&pdev->dev,
++                      &soc_codec_pwmdac_dit,
++                      &dit_stub_dai, 1);
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id pwmdac_dit_dt_ids[] = {
++      { .compatible = "linux,pwmdac-dit", },
++      { }
++};
++MODULE_DEVICE_TABLE(of, pwmdac_dit_dt_ids);
++#endif
++
++static struct platform_driver pwmdac_dit_driver = {
++      .probe          = pwmdac_dit_probe,
++      .driver         = {
++              .name   = DRV_NAME,
++              .of_match_table = of_match_ptr(pwmdac_dit_dt_ids),
++      },
++};
++
++module_platform_driver(pwmdac_dit_driver);
++
++MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
++MODULE_DESCRIPTION("pwmdac dummy codec driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform: starfive-pwmdac dummy codec");
+--- /dev/null
++++ b/sound/soc/starfive/pwmdac.c
+@@ -0,0 +1,901 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * PWMDAC driver for the StarFive JH7100 SoC
++ *
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/pm_runtime.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/dmaengine_pcm.h>
++#include "pwmdac.h"
++#include <linux/kthread.h>
++
++struct ct_pwmdac {
++      char *name;
++      unsigned int vals;
++};
++
++static const struct ct_pwmdac pwmdac_ct_shift_bit[] = {
++      { .name = "8bit", .vals = PWMDAC_SHIFT_8 },
++      { .name = "10bit", .vals = PWMDAC_SHIFT_10 }
++};
++
++static const struct ct_pwmdac pwmdac_ct_duty_cycle[] = {
++      { .name = "left", .vals = PWMDAC_CYCLE_LEFT },
++      { .name = "right", .vals = PWMDAC_CYCLE_RIGHT },
++      { .name = "center", .vals = PWMDAC_CYCLE_CENTER }
++};
++
++static const struct ct_pwmdac pwmdac_ct_data_mode[] = {
++      { .name = "unsinged", .vals = UNSINGED_DATA },
++      { .name = "inverter", .vals = INVERTER_DATA_MSB }
++};
++
++static const struct ct_pwmdac pwmdac_ct_lr_change[] = {
++      { .name = "no_change", .vals = NO_CHANGE },
++      { .name = "change", .vals = CHANGE }
++};
++
++static const struct ct_pwmdac pwmdac_ct_shift[] = {
++      { .name = "left 0 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_0 },
++      { .name = "left 1 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_1 },
++      { .name = "left 2 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_2 },
++      { .name = "left 3 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_3 },
++      { .name = "left 4 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_4 },
++      { .name = "left 5 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_5 },
++      { .name = "left 6 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_6 }
++};
++
++static int pwmdac_shift_bit_info(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_info *uinfo)
++{
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_shift_bit);
++
++      uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
++      uinfo->count = 1;
++      uinfo->value.enumerated.items = items;
++      if (uinfo->value.enumerated.item >= items) {
++              uinfo->value.enumerated.item = items - 1;
++      }
++      strcpy(uinfo->value.enumerated.name,
++                      pwmdac_ct_shift_bit[uinfo->value.enumerated.item].name);
++
++      return 0;
++}
++static int pwmdac_shift_bit_get(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++      unsigned int item;
++
++      if (dev->shift_bit == pwmdac_ct_shift_bit[0].vals)
++              item = 0;
++      else
++              item = 1;
++
++      ucontrol->value.enumerated.item[0] = item;
++
++      return 0;
++}
++
++static int pwmdac_shift_bit_put(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++      int sel = ucontrol->value.enumerated.item[0];
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_shift_bit);
++
++      if (sel > items)
++              return 0;
++
++      switch (sel) {
++      case 1:
++              dev->shift_bit = pwmdac_ct_shift_bit[1].vals;
++              break;
++      default:
++              dev->shift_bit = pwmdac_ct_shift_bit[0].vals;
++              break;
++      }
++
++      return 0;
++}
++
++static int pwmdac_duty_cycle_info(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_info *uinfo)
++{
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_duty_cycle);
++
++      uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
++      uinfo->count = 1;
++      uinfo->value.enumerated.items = items;
++      if (uinfo->value.enumerated.item >= items)
++              uinfo->value.enumerated.item = items - 1;
++      strcpy(uinfo->value.enumerated.name,
++              pwmdac_ct_duty_cycle[uinfo->value.enumerated.item].name);
++
++      return 0;
++}
++
++static int pwmdac_duty_cycle_get(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++
++      ucontrol->value.enumerated.item[0] = dev->duty_cycle;
++      return 0;
++}
++
++static int pwmdac_duty_cycle_put(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++      int sel = ucontrol->value.enumerated.item[0];
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_duty_cycle);
++
++      if (sel > items)
++              return 0;
++
++      dev->duty_cycle = pwmdac_ct_duty_cycle[sel].vals;
++      return 0;
++}
++
++/*
++static int pwmdac_datan_info(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_info *uinfo)
++{
++      uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++      uinfo->count = 1;
++      uinfo->value.integer.min = 1;
++      uinfo->value.integer.max = PWMDAC_SAMPLE_CNT_511;
++      uinfo->value.integer.step = 1;
++      return 0;
++}
++
++static int pwmdac_datan_get(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++
++      ucontrol->value.integer.value[0] = dev->datan;
++
++      return 0;
++}
++
++static int pwmdac_datan_put(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++      int sel = ucontrol->value.integer.value[0];
++
++      if (sel > PWMDAC_SAMPLE_CNT_511)
++              return 0;
++
++      dev->datan = sel;
++
++      return 0;
++}
++*/
++
++static int pwmdac_data_mode_info(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_info *uinfo)
++{
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_data_mode);
++
++      uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
++      uinfo->count = 1;
++      uinfo->value.enumerated.items = items;
++      if (uinfo->value.enumerated.item >= items)
++              uinfo->value.enumerated.item = items - 1;
++      strcpy(uinfo->value.enumerated.name,
++              pwmdac_ct_data_mode[uinfo->value.enumerated.item].name);
++
++      return 0;
++}
++
++static int pwmdac_data_mode_get(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++
++      ucontrol->value.enumerated.item[0] = dev->data_mode;
++      return 0;
++}
++
++static int pwmdac_data_mode_put(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++      int sel = ucontrol->value.enumerated.item[0];
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_data_mode);
++
++      if (sel > items)
++              return 0;
++
++      dev->data_mode = pwmdac_ct_data_mode[sel].vals;
++      return 0;
++}
++
++static int pwmdac_shift_info(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_info *uinfo)
++{
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_shift);
++
++      uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
++      uinfo->count = 1;
++      uinfo->value.enumerated.items = items;
++      if (uinfo->value.enumerated.item >= items)
++              uinfo->value.enumerated.item = items - 1;
++      strcpy(uinfo->value.enumerated.name,
++              pwmdac_ct_shift[uinfo->value.enumerated.item].name);
++
++      return 0;
++}
++
++static int pwmdac_shift_get(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++      unsigned int item = dev->shift;
++
++      ucontrol->value.enumerated.item[0] = pwmdac_ct_shift[item].vals;
++      return 0;
++}
++
++static int pwmdac_shift_put(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++      int sel = ucontrol->value.enumerated.item[0];
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_shift);
++
++      if (sel > items)
++              return 0;
++
++      dev->shift = pwmdac_ct_shift[sel].vals;
++      return 0;
++}
++
++static int pwmdac_lr_change_info(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_info *uinfo)
++{
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_lr_change);
++
++      uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
++      uinfo->count = 1;
++      uinfo->value.enumerated.items = items;
++      if (uinfo->value.enumerated.item >= items)
++              uinfo->value.enumerated.item = items - 1;
++      strcpy(uinfo->value.enumerated.name,
++              pwmdac_ct_lr_change[uinfo->value.enumerated.item].name);
++
++      return 0;
++}
++
++static int pwmdac_lr_change_get(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++
++      ucontrol->value.enumerated.item[0] = dev->lr_change;
++      return 0;
++}
++
++static int pwmdac_lr_change_put(struct snd_kcontrol *kcontrol,
++                              struct snd_ctl_elem_value *ucontrol)
++{
++      struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++      struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
++      int sel = ucontrol->value.enumerated.item[0];
++      unsigned int items = ARRAY_SIZE(pwmdac_ct_lr_change);
++
++      if (sel > items)
++              return 0;
++
++      dev->lr_change = pwmdac_ct_lr_change[sel].vals;
++      return 0;
++}
++
++static inline void pwmdc_write_reg(void __iomem *io_base, int reg, u32 val)
++{
++      writel(val, io_base + reg);
++}
++
++static inline u32 pwmdc_read_reg(void __iomem *io_base, int reg)
++{
++      return readl(io_base + reg);
++}
++
++/*
++ * 32bit-4byte
++*/
++static void pwmdac_set_ctrl_enable(struct sf_pwmdac_dev *dev)
++{
++      u32 date;
++      date = pwmdc_read_reg(dev->pwmdac_base, PWMDAC_CTRL);
++      pwmdc_write_reg(dev->pwmdac_base, PWMDAC_CTRL, date | BIT(0) );
++}
++
++/*
++ * 32bit-4byte
++*/
++static void pwmdac_set_ctrl_disable(struct sf_pwmdac_dev *dev)
++{
++      u32 date;
++      date = pwmdc_read_reg(dev->pwmdac_base, PWMDAC_CTRL);
++      pwmdc_write_reg(dev->pwmdac_base, PWMDAC_CTRL, date & ~ BIT(0));
++}
++
++/*
++ * 8:8-bit
++ * 10:10-bit
++*/
++static void pwmdac_set_ctrl_shift(struct sf_pwmdac_dev *dev, u8 data)
++{
++      u32 value = 0;
++
++      if (data == 8) {
++              value = (~((~value) | 0x02));
++              pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
++      }
++      else if(data == 10){
++              value |= 0x02;
++              pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
++      }
++}
++
++/*
++ * 00:left
++ * 01:right
++ * 10:center
++*/
++static void pwmdac_set_ctrl_dutyCycle(struct sf_pwmdac_dev *dev, u8 data)
++{
++      u32 value = 0;
++
++      value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
++      if (data == 0) { //left
++              value = (~((~value) | (0x03<<2)));
++              pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
++      }
++      else if (data == 1) { //right
++              value = (~((~value) | (0x01<<3))) | (0x01<<2);
++              pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
++      }
++      else if (data == 2) { //center
++              value = (~((~value) | (0x01<<2))) | (0x01<<3);
++              pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
++      }
++}
++
++
++static void pwmdac_set_ctrl_N(struct sf_pwmdac_dev *dev, u16 data)
++{
++      u32 value = 0;
++
++      value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
++      pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, (value & 0xF) | ((data - 1) << 4));
++}
++
++
++static void pwmdac_LR_data_change(struct sf_pwmdac_dev *dev, u8 data)
++{
++      u32 value = 0;
++
++      value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
++      switch (data) {
++      case NO_CHANGE:
++              value &= (~SFC_PWMDAC_LEFT_RIGHT_DATA_CHANGE);
++              break;
++      case CHANGE:
++              value |= SFC_PWMDAC_LEFT_RIGHT_DATA_CHANGE;
++              break;
++      }
++      pwmdc_write_reg(dev->pwmdac_base, PWMDAC_CTRL, value);
++}
++
++static void pwmdac_data_mode(struct sf_pwmdac_dev *dev, u8 data)
++{
++      u32 value = 0;
++
++      value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
++      if (data == UNSINGED_DATA) {
++              value &= (~SFC_PWMDAC_DATA_MODE);
++      }
++      else if (data == INVERTER_DATA_MSB) {
++              value |= SFC_PWMDAC_DATA_MODE;
++      }
++      pwmdc_write_reg(dev->pwmdac_base,PWMDAC_CTRL, value);
++}
++
++static int pwmdac_data_shift(struct sf_pwmdac_dev *dev,u8 data)
++{
++      u32 value = 0;
++
++      if ((data < PWMDAC_DATA_LEFT_SHIFT_BIT_0) || (data > PWMDAC_DATA_LEFT_SHIFT_BIT_7)) {
++              return -1;
++      }
++
++      value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
++      value &= ( ~ ( PWMDAC_DATA_LEFT_SHIFT_BIT_ALL << 15 ) );
++      value |= (data<<15);
++      pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
++      return 0;
++}
++
++static int get_pwmdac_fifo_state(struct sf_pwmdac_dev *dev)
++{
++      u32 value;
++
++      value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_SATAE);
++      if ((value & 0x02) == 0)
++              return FIFO_UN_FULL;
++
++      return FIFO_FULL;
++}
++
++
++static void pwmdac_set(struct sf_pwmdac_dev *dev)
++{
++      ///8-bit + left + N=16
++      pwmdac_set_ctrl_shift(dev, dev->shift_bit);
++      pwmdac_set_ctrl_dutyCycle(dev, dev->duty_cycle);
++      pwmdac_set_ctrl_N(dev, dev->datan);
++      pwmdac_set_ctrl_enable(dev);
++
++      pwmdac_LR_data_change(dev, dev->lr_change);
++      pwmdac_data_mode(dev, dev->data_mode);
++      if (dev->shift) {
++              pwmdac_data_shift(dev, dev->shift);
++      }
++}
++
++static void pwmdac_stop(struct sf_pwmdac_dev *dev)
++{
++      pwmdac_set_ctrl_disable(dev);
++}
++
++static int pwmdac_config(struct sf_pwmdac_dev *dev)
++{
++      switch (dev->mode) {
++      case shift_8Bit_unsigned:
++      case shift_8Bit_unsigned_dataShift:
++              /* 8 bit, unsigned */
++              dev->shift_bit  = PWMDAC_SHIFT_8;
++              dev->duty_cycle = PWMDAC_CYCLE_CENTER;
++              dev->datan              = PWMDAC_SAMPLE_CNT_8;
++              dev->data_mode  = UNSINGED_DATA;
++              break;
++
++      case shift_8Bit_inverter:
++      case shift_8Bit_inverter_dataShift:
++              /* 8 bit, invert */
++              dev->shift_bit  = PWMDAC_SHIFT_8;
++              dev->duty_cycle = PWMDAC_CYCLE_CENTER;
++              dev->datan              = PWMDAC_SAMPLE_CNT_8;
++              dev->data_mode  = INVERTER_DATA_MSB;
++              break;
++
++      case shift_10Bit_unsigned:
++      case shift_10Bit_unsigned_dataShift:
++              /* 10 bit, unsigend */
++              dev->shift_bit  = PWMDAC_SHIFT_10;
++              dev->duty_cycle = PWMDAC_CYCLE_CENTER;
++              dev->datan              = PWMDAC_SAMPLE_CNT_8;
++              dev->data_mode  = UNSINGED_DATA;
++              break;
++
++      case shift_10Bit_inverter:
++      case shift_10Bit_inverter_dataShift:
++              /* 10 bit, invert */
++              dev->shift_bit  = PWMDAC_SHIFT_10;
++              dev->duty_cycle = PWMDAC_CYCLE_CENTER;
++              dev->datan              = PWMDAC_SAMPLE_CNT_8;
++              dev->data_mode  = INVERTER_DATA_MSB;
++              break;
++
++      default:
++              return -1;
++      }
++
++      if ((dev->mode == shift_8Bit_unsigned_dataShift) || (dev->mode == shift_8Bit_inverter_dataShift)
++              || (dev->mode == shift_10Bit_unsigned_dataShift) || (dev->mode == shift_10Bit_inverter_dataShift)) {
++              dev->shift = 4; /*0~7*/
++      } else {
++              dev->shift = 0;
++      }
++      dev->lr_change = NO_CHANGE;
++      return 0;
++}
++
++static int sf_pwmdac_prepare(struct snd_pcm_substream *substream,
++                      struct snd_soc_dai *dai)
++{
++      //struct sf_pwmdac_dev *dev = snd_soc_dai_get_drvdata(dai);
++      //pwmdac_set(dev);
++      return 0;
++}
++
++static int pwmdac_tx_thread(void *dev)
++{
++      struct sf_pwmdac_dev *pwmdac_dev = (struct sf_pwmdac_dev *)dev;
++
++      set_current_state(TASK_INTERRUPTIBLE);
++      while (!schedule_timeout(usecs_to_jiffies(50))) {
++              if (pwmdac_dev->tx_thread_exit)
++                      break;
++              if (get_pwmdac_fifo_state(pwmdac_dev)==0) {
++                      sf_pwmdac_pcm_push_tx(pwmdac_dev);
++              }
++
++              set_current_state(TASK_INTERRUPTIBLE);
++      }
++
++      pwmdac_dev->tx_thread = NULL;
++      return 0;
++}
++
++static int sf_pwmdac_trigger(struct snd_pcm_substream *substream,
++              int cmd, struct snd_soc_dai *dai)
++{
++      struct sf_pwmdac_dev *dev = snd_soc_dai_get_drvdata(dai);
++      int ret = 0;
++
++      switch (cmd) {
++      case SNDRV_PCM_TRIGGER_START:
++      case SNDRV_PCM_TRIGGER_RESUME:
++      case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++              dev->active++;
++              pwmdac_set(dev);
++              if (dev->use_pio) {
++                      dev->tx_thread = kthread_create(pwmdac_tx_thread, (void *)dev, "pwmdac");
++                      if (IS_ERR(dev->tx_thread)) {
++                              return PTR_ERR(dev->tx_thread);
++                      }
++                      wake_up_process(dev->tx_thread);
++                      dev->tx_thread_exit = 0;
++              }
++              break;
++
++      case SNDRV_PCM_TRIGGER_STOP:
++      case SNDRV_PCM_TRIGGER_SUSPEND:
++      case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++              dev->active--;
++              pwmdac_stop(dev);
++              if (dev->use_pio) {
++                      if(dev->tx_thread) {
++                              dev->tx_thread_exit = 1;
++                      }
++              }
++              break;
++      default:
++              ret = -EINVAL;
++              break;
++      }
++      return ret;
++
++      return 0;
++}
++
++static int sf_pwmdac_hw_params(struct snd_pcm_substream *substream,
++      struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++      struct sf_pwmdac_dev *dev = dev_get_drvdata(dai->dev);
++
++      dev->play_dma_data.addr = dev->mapbase + PWMDAC_WDATA;
++
++      switch (params_channels(params)) {
++      case 2:
++              dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++              break;
++      case 1:
++              dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++              break;
++      default:
++              dev_err(dai->dev, "%d channels not supported\n",
++                              params_channels(params));
++              return -EINVAL;
++      }
++
++      dev->play_dma_data.fifo_size = 1;
++      dev->play_dma_data.maxburst = 16;
++
++      snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, NULL);
++      snd_soc_dai_set_drvdata(dai, dev);
++
++      return 0;
++}
++
++static int sf_pwmdac_clks_get(struct platform_device *pdev,
++                              struct sf_pwmdac_dev *dev)
++{
++      static struct clk_bulk_data clks[] = {
++              { .id = "audio_root" },         //clock-names in dts file
++              { .id = "audio_src" },
++              { .id = "audio_12288" },
++              { .id = "dma1p_ahb" },
++              { .id = "pwmdac_apb" },
++              { .id = "dac_mclk" },
++      };
++      int ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(clks), clks);
++      dev->clk_audio_root = clks[0].clk;
++      dev->clk_audio_src = clks[1].clk;
++      dev->clk_audio_12288 = clks[2].clk;
++      dev->clk_dma1p_ahb = clks[3].clk;
++      dev->clk_pwmdac_apb = clks[4].clk;
++      dev->clk_dac_mclk = clks[5].clk;
++
++      return ret;
++}
++
++static int sf_pwmdac_resets_get(struct platform_device *pdev,
++                              struct sf_pwmdac_dev *dev)
++{
++      struct reset_control_bulk_data resets[] = {
++              { .id = "apb_bus" },
++              { .id = "dma1p_ahb" },
++              { .id = "apb_pwmdac" },
++      };
++        int ret = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(resets), resets);
++      if (ret)
++              return ret;
++
++      dev->rst_apb_bus = resets[0].rstc;
++      dev->rst_dma1p_ahb = resets[1].rstc;
++      dev->rst_apb_pwmdac = resets[2].rstc;
++      return 0;
++}
++
++static int sf_pwmdac_clk_init(struct platform_device *pdev,
++                              struct sf_pwmdac_dev *dev)
++{
++      int ret = 0;
++
++      ret = clk_prepare_enable(dev->clk_audio_root);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to prepare enable clk_audio_root\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = clk_prepare_enable(dev->clk_audio_src);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to prepare enable clk_audio_src\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = clk_prepare_enable(dev->clk_audio_12288);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to prepare enable clk_audio_12288\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = clk_prepare_enable(dev->clk_dma1p_ahb);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to prepare enable clk_dma1p_ahb\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = reset_control_deassert(dev->rst_apb_bus);
++      if (ret) {
++              printk(KERN_INFO "failed to deassert apb_bus\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = reset_control_deassert(dev->rst_dma1p_ahb);
++      if (ret) {
++              printk(KERN_INFO "failed to deassert dma1p_ahb\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = clk_set_rate(dev->clk_audio_src, 12288000);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to set 12.288 MHz rate for clk_audio_src\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = reset_control_assert(dev->rst_apb_pwmdac);
++      if (ret) {
++              printk(KERN_INFO "failed to assert apb_pwmdac\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = clk_prepare_enable(dev->clk_dac_mclk);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to prepare enable clk_dac_mclk\n");
++              goto err_clk_pwmdac;
++      }
++
++      /* we want 4096kHz but the clock driver always rounds down so add a little slack */
++      ret = clk_set_rate(dev->clk_dac_mclk, 4096000 + 64);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to set 4096kHz rate for clk_dac_mclk\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = clk_prepare_enable(dev->clk_pwmdac_apb);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to prepare enable clk_pwmdac_apb\n");
++              goto err_clk_pwmdac;
++      }
++
++      ret = reset_control_deassert(dev->rst_apb_pwmdac);
++      if (ret) {
++              printk(KERN_INFO "failed to deassert apb_pwmdac\n");
++              goto err_clk_pwmdac;
++      }
++      printk(KERN_INFO "Initialize pwmdac...success\n");
++
++err_clk_pwmdac:
++      return ret;
++}
++
++static int sf_pwmdac_dai_probe(struct snd_soc_dai *dai)
++{
++      struct sf_pwmdac_dev *dev = dev_get_drvdata(dai->dev);
++
++      dev->play_dma_data.addr = dev->mapbase + PWMDAC_WDATA;
++      dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++      dev->play_dma_data.fifo_size = 1;
++      dev->play_dma_data.maxburst = 16;
++
++      snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, NULL);
++      snd_soc_dai_set_drvdata(dai, dev);
++
++      return 0;
++}
++#define SOC_PWMDAC_ENUM_DECL(xname, xinfo, xget, xput) \
++{     .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
++      .info = xinfo, .get = xget, \
++      .put = xput,}
++static const struct snd_kcontrol_new pwmdac_snd_controls[] = {
++      SOC_PWMDAC_ENUM_DECL("shift_bit", pwmdac_shift_bit_info,
++              pwmdac_shift_bit_get, pwmdac_shift_bit_put),
++      SOC_PWMDAC_ENUM_DECL("duty_cycle", pwmdac_duty_cycle_info,
++              pwmdac_duty_cycle_get, pwmdac_duty_cycle_put),
++      SOC_PWMDAC_ENUM_DECL("data_mode", pwmdac_data_mode_info,
++              pwmdac_data_mode_get, pwmdac_data_mode_put),
++      SOC_PWMDAC_ENUM_DECL("shift", pwmdac_shift_info,
++              pwmdac_shift_get, pwmdac_shift_put),
++      SOC_PWMDAC_ENUM_DECL("lr_change", pwmdac_lr_change_info,
++              pwmdac_lr_change_get, pwmdac_lr_change_put),
++};
++static int pwmdac_probe(struct snd_soc_component *component)
++{
++//    struct sf_pwmdac_dev *priv = snd_soc_component_get_drvdata(component);
++      snd_soc_add_component_controls(component, pwmdac_snd_controls,
++                              ARRAY_SIZE(pwmdac_snd_controls));
++      return 0;
++}
++
++
++static const struct snd_soc_dai_ops sf_pwmdac_dai_ops = {
++      .hw_params      = sf_pwmdac_hw_params,
++      .prepare        = sf_pwmdac_prepare,
++      .trigger        = sf_pwmdac_trigger,
++};
++
++static const struct snd_soc_component_driver sf_pwmdac_component = {
++      .name           = "sf-pwmdac",
++      .probe          = pwmdac_probe,
++};
++
++static struct snd_soc_dai_driver pwmdac_dai = {
++      .name = "pwmdac",
++      .id = 0,
++      .probe  = sf_pwmdac_dai_probe,
++      .playback = {
++              .channels_min = 1,
++              .channels_max = 2,
++              .rates = SNDRV_PCM_RATE_16000,
++              .formats = SNDRV_PCM_FMTBIT_S16_LE,
++      },
++      .ops = &sf_pwmdac_dai_ops,
++};
++
++static int sf_pwmdac_probe(struct platform_device *pdev)
++{
++      struct sf_pwmdac_dev *dev;
++      struct resource *res;
++      int ret;
++
++      dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
++      if (!dev)
++              return -ENOMEM;
++
++      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      dev->mapbase = res->start;
++      dev->pwmdac_base = devm_ioremap_resource(&pdev->dev, res);
++      if (IS_ERR(dev->pwmdac_base))
++              return PTR_ERR(dev->pwmdac_base);
++
++      ret = sf_pwmdac_clks_get(pdev, dev);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to get audio clock\n");
++              return ret;
++      }
++
++      ret = sf_pwmdac_resets_get(pdev, dev);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to get audio reset controls\n");
++              return ret;
++        }
++
++      ret = sf_pwmdac_clk_init(pdev, dev);
++      if (ret) {
++              dev_err(&pdev->dev, "failed to enable audio clock\n");
++              return ret;
++      }
++
++      dev->dev = &pdev->dev;
++      dev->mode = shift_8Bit_inverter;
++      dev->fifo_th = 1;//8byte
++      pwmdac_config(dev);
++
++      dev->use_pio = false;
++      dev_set_drvdata(&pdev->dev, dev);
++      ret = devm_snd_soc_register_component(&pdev->dev, &sf_pwmdac_component,
++                                       &pwmdac_dai, 1);
++      if (ret != 0) {
++              dev_err(&pdev->dev, "not able to register dai\n");
++              return ret;
++      }
++
++      if (dev->use_pio) {
++              ret = sf_pwmdac_pcm_register(pdev);
++      } else {
++              ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
++                              0);
++      }
++      return 0;
++}
++
++
++static int sf_pwmdac_remove(struct platform_device *pdev)
++{
++      return 0;
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id sf_pwmdac_of_match[] = {
++      { .compatible = "starfive,pwmdac",       },
++      {},
++};
++
++MODULE_DEVICE_TABLE(of, sf_pwmdac_of_match);
++#endif
++
++
++static struct platform_driver sf_pwmdac_driver = {
++      .probe          = sf_pwmdac_probe,
++      .remove         = sf_pwmdac_remove,
++      .driver         = {
++              .name   = "sf-pwmdac",
++              .of_match_table = of_match_ptr(sf_pwmdac_of_match),
++      },
++};
++
++module_platform_driver(sf_pwmdac_driver);
++
++MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION("starfive pwmdac SoC Interface");
++MODULE_ALIAS("platform:starfive-pwmdac");
+--- /dev/null
++++ b/sound/soc/starfive/pwmdac.h
+@@ -0,0 +1,153 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef __SND_SOC_STARFIVE_PWMDAC_H
++#define __SND_SOC_STARFIVE_PWMDAC_H
++
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/types.h>
++#include <sound/dmaengine_pcm.h>
++#include <sound/pcm.h>
++
++#define PWMDAC_WDATA  0       // PWMDAC_BASE_ADDR
++#define PWMDAC_CTRL   0x04    // PWMDAC_BASE_ADDR + 0x04
++#define PWMDAC_SATAE  0x08    // PWMDAC_BASE_ADDR + 0x08
++#define PWMDAC_RESERVED       0x0C    // PWMDAC_BASE_ADDR + 0x0C
++
++#define SFC_PWMDAC_SHIFT      BIT(1)
++#define SFC_PWMDAC_DUTY_CYCLE BIT(2)
++#define SFC_PWMDAC_CNT_N      BIT(4)
++
++#define SFC_PWMDAC_LEFT_RIGHT_DATA_CHANGE     BIT(13)
++#define SFC_PWMDAC_DATA_MODE                  BIT(14)
++
++#define FIFO_UN_FULL  0
++#define FIFO_FULL     1
++
++enum pwmdac_lr_change{
++      NO_CHANGE = 0,
++      CHANGE,
++};
++
++enum pwmdac_d_mode{
++      UNSINGED_DATA = 0,
++      INVERTER_DATA_MSB,
++};
++
++enum pwmdac_shift_bit{
++      PWMDAC_SHIFT_8 = 8,     /* pwmdac shift 8 bit */
++      PWMDAC_SHIFT_10 = 10,   /* pwmdac shift 10 bit */
++};
++
++enum pwmdac_duty_cycle{
++      PWMDAC_CYCLE_LEFT = 0,          /* pwmdac duty cycle left */
++      PWMDAC_CYCLE_RIGHT = 1,         /* pwmdac duty cycle right */
++      PWMDAC_CYCLE_CENTER = 2,        /* pwmdac duty cycle center */
++};
++
++/*sample count [12:4] <511*/
++enum pwmdac_sample_count{
++      PWMDAC_SAMPLE_CNT_1 = 1,
++      PWMDAC_SAMPLE_CNT_2,
++      PWMDAC_SAMPLE_CNT_3,
++      PWMDAC_SAMPLE_CNT_4,
++      PWMDAC_SAMPLE_CNT_5,
++      PWMDAC_SAMPLE_CNT_6,
++      PWMDAC_SAMPLE_CNT_7,
++      PWMDAC_SAMPLE_CNT_8 = 1,        //(32.468/8) == (12.288/3) == 4.096
++      PWMDAC_SAMPLE_CNT_9,
++      PWMDAC_SAMPLE_CNT_10,
++      PWMDAC_SAMPLE_CNT_11,
++      PWMDAC_SAMPLE_CNT_12,
++      PWMDAC_SAMPLE_CNT_13,
++      PWMDAC_SAMPLE_CNT_14,
++      PWMDAC_SAMPLE_CNT_15,
++      PWMDAC_SAMPLE_CNT_16,
++      PWMDAC_SAMPLE_CNT_17,
++      PWMDAC_SAMPLE_CNT_18,
++      PWMDAC_SAMPLE_CNT_19,
++      PWMDAC_SAMPLE_CNT_20 = 20,
++      PWMDAC_SAMPLE_CNT_30 = 30,
++      PWMDAC_SAMPLE_CNT_511 = 511,
++};
++
++
++enum data_shift{
++      PWMDAC_DATA_LEFT_SHIFT_BIT_0 = 0,
++      PWMDAC_DATA_LEFT_SHIFT_BIT_1,
++      PWMDAC_DATA_LEFT_SHIFT_BIT_2,
++      PWMDAC_DATA_LEFT_SHIFT_BIT_3,
++      PWMDAC_DATA_LEFT_SHIFT_BIT_4,
++      PWMDAC_DATA_LEFT_SHIFT_BIT_5,
++      PWMDAC_DATA_LEFT_SHIFT_BIT_6,
++      PWMDAC_DATA_LEFT_SHIFT_BIT_7,
++      PWMDAC_DATA_LEFT_SHIFT_BIT_ALL,
++};
++
++enum pwmdac_config_list{
++      shift_8Bit_unsigned = 0,
++      shift_8Bit_unsigned_dataShift,
++      shift_10Bit_unsigned,
++      shift_10Bit_unsigned_dataShift,
++
++      shift_8Bit_inverter,
++      shift_8Bit_inverter_dataShift,
++      shift_10Bit_inverter,
++      shift_10Bit_inverter_dataShift,
++};
++
++struct sf_pwmdac_dev {
++      void __iomem *pwmdac_base;
++      resource_size_t mapbase;
++      u8  mode;
++      u8 shift_bit;
++      u8 duty_cycle;
++      u8 datan;
++      u8 data_mode;
++      u8 lr_change;
++      u8 shift;
++      u8 fifo_th;
++      bool use_pio;
++      spinlock_t lock;
++      int active;
++
++      struct clk *clk_audio_root;
++      struct clk *clk_audio_src;
++      struct clk *clk_audio_12288;
++      struct clk *clk_dma1p_ahb;
++      struct clk *clk_pwmdac_apb;
++      struct clk *clk_dac_mclk;
++      struct reset_control *rst_apb_bus;
++      struct reset_control *rst_dma1p_ahb;
++      struct reset_control *rst_apb_pwmdac;
++
++      struct device *dev;
++      struct snd_dmaengine_dai_dma_data play_dma_data;
++      struct snd_pcm_substream __rcu *tx_substream;
++      unsigned int (*tx_fn)(struct sf_pwmdac_dev *dev,
++                      struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
++                      bool *period_elapsed);
++      unsigned int tx_ptr;
++      struct task_struct *tx_thread;
++      bool tx_thread_exit;
++};
++
++
++
++#if IS_ENABLED(CONFIG_SND_STARFIVE_PWMDAC_PCM)
++void sf_pwmdac_pcm_push_tx(struct sf_pwmdac_dev *dev);
++void sf_pwmdac_pcm_pop_rx(struct sf_pwmdac_dev *dev);
++int sf_pwmdac_pcm_register(struct platform_device *pdev);
++#else
++void sf_pwmdac_pcm_push_tx(struct sf_pwmdac_dev *dev) { }
++void sf_pwmdac_pcm_pop_rx(struct sf_pwmdac_dev *dev) { }
++int sf_pwmdac_pcm_register(struct platform_device *pdev)
++{
++      return -EINVAL;
++}
++#endif
++
++#endif
+--- /dev/null
++++ b/sound/soc/starfive/spdif-pcm.c
+@@ -0,0 +1,288 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/io.h>
++#include <linux/rcupdate.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++
++#include "spdif.h"
++
++#define BUFFER_BYTES_MAX      (3 * 2 * 8 * PERIOD_BYTES_MIN)
++#define PERIOD_BYTES_MIN      4096
++#define PERIODS_MIN                   2
++
++static unsigned int sf_spdif_pcm_tx(struct sf_spdif_dev *dev,
++              struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
++              bool *period_elapsed, snd_pcm_format_t format)
++{
++      const u16 (*p16)[2] = (void *)runtime->dma_area;
++      const u32 (*p32)[2] = (void *)runtime->dma_area;
++      u32 data[2];
++      unsigned int period_pos = tx_ptr % runtime->period_size;
++      int i;
++
++      for (i = 0; i < dev->fifo_th; i++) {
++              if (SNDRV_PCM_FORMAT_S16_LE == format) {
++                      data[0] = p16[tx_ptr][0];
++                      data[1] = p16[tx_ptr][1];
++                      data[0] = data[0]<<8;
++                      data[1] = data[1]<<8;
++              } else if (SNDRV_PCM_FORMAT_S24_LE == format) {
++                      data[0] = p32[tx_ptr][0];
++                      data[1] = p32[tx_ptr][1];
++              } else if (SNDRV_PCM_FORMAT_S32_LE == format) {
++                      data[0] = p32[tx_ptr][0];
++                      data[1] = p32[tx_ptr][1];
++                      data[0] = data[0]>>8;
++                      data[1] = data[1]>>8;
++              }
++
++              iowrite32(data[0], dev->spdif_base + SPDIF_FIFO_ADDR);
++              iowrite32(data[1], dev->spdif_base + SPDIF_FIFO_ADDR);
++              period_pos++;
++              if (++tx_ptr >= runtime->buffer_size) {
++                      tx_ptr = 0;
++              }
++      }
++
++      *period_elapsed = period_pos >= runtime->period_size;
++      return tx_ptr;
++}
++
++static unsigned int sf_spdif_pcm_rx(struct sf_spdif_dev *dev,
++              struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
++              bool *period_elapsed, snd_pcm_format_t format)
++{
++      u16 (*p16)[2] = (void *)runtime->dma_area;
++      u32 (*p32)[2] = (void *)runtime->dma_area;
++      u32 data[2];
++      unsigned int period_pos = rx_ptr % runtime->period_size;
++      int i;
++
++      for (i = 0; i < dev->fifo_th; i++) {
++              data[0] = ioread32(dev->spdif_base + SPDIF_FIFO_ADDR);
++              data[1] = ioread32(dev->spdif_base + SPDIF_FIFO_ADDR);
++              if (SNDRV_PCM_FORMAT_S16_LE == format) {
++                      p16[rx_ptr][0] = data[0]>>8;
++                      p16[rx_ptr][1] = data[1]>>8;
++              } else if (SNDRV_PCM_FORMAT_S24_LE == format) {
++                      p32[rx_ptr][0] = data[0];
++                      p32[rx_ptr][1] = data[1];
++              } else if (SNDRV_PCM_FORMAT_S32_LE == format) {
++                      p32[rx_ptr][0] = data[0]<<8;
++                      p32[rx_ptr][1] = data[1]<<8;
++              }
++
++              period_pos++;
++              if (++rx_ptr >= runtime->buffer_size)
++                      rx_ptr = 0;
++      }
++
++      *period_elapsed = period_pos >= runtime->period_size;
++      return rx_ptr;
++}
++
++static const struct snd_pcm_hardware sf_pcm_hardware = {
++      .info = SNDRV_PCM_INFO_INTERLEAVED |
++              SNDRV_PCM_INFO_MMAP |
++              SNDRV_PCM_INFO_MMAP_VALID |
++              SNDRV_PCM_INFO_BLOCK_TRANSFER,
++      .rates = SNDRV_PCM_RATE_8000 |
++              SNDRV_PCM_RATE_11025 |
++              SNDRV_PCM_RATE_16000 |
++              SNDRV_PCM_RATE_22050 |
++              SNDRV_PCM_RATE_32000 |
++              SNDRV_PCM_RATE_44100 |
++              SNDRV_PCM_RATE_48000,
++      .rate_min = 8000,
++      .rate_max = 48000,
++      .formats = SNDRV_PCM_FMTBIT_S16_LE |
++              SNDRV_PCM_FMTBIT_S24_LE |
++              SNDRV_PCM_FMTBIT_S32_LE,
++      .channels_min = 2,
++      .channels_max = 2,
++      .buffer_bytes_max = BUFFER_BYTES_MAX,
++      .period_bytes_min = PERIOD_BYTES_MIN,
++      .period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
++      .periods_min = PERIODS_MIN,
++      .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
++      .fifo_size = 16,
++};
++
++static void sf_spdif_pcm_transfer(struct sf_spdif_dev *dev, bool push)
++{
++      struct snd_pcm_substream *substream;
++      bool active, period_elapsed;
++
++      rcu_read_lock();
++      if (push)
++              substream = rcu_dereference(dev->tx_substream);
++      else
++              substream = rcu_dereference(dev->rx_substream);
++      active = substream && snd_pcm_running(substream);
++      if (active) {
++              unsigned int ptr;
++              unsigned int new_ptr;
++
++              if (push) {
++                      ptr = READ_ONCE(dev->tx_ptr);
++                      new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
++                                      &period_elapsed, dev->format);
++                      cmpxchg(&dev->tx_ptr, ptr, new_ptr);
++              } else {
++                      ptr = READ_ONCE(dev->rx_ptr);
++                      new_ptr = dev->rx_fn(dev, substream->runtime, ptr,
++                                      &period_elapsed, dev->format);
++                      cmpxchg(&dev->rx_ptr, ptr, new_ptr);
++              }
++
++              if (period_elapsed)
++                      snd_pcm_period_elapsed(substream);
++      }
++      rcu_read_unlock();
++}
++
++void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev)
++{
++      sf_spdif_pcm_transfer(dev, true);
++}
++
++void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev)
++{
++      sf_spdif_pcm_transfer(dev, false);
++}
++
++static int sf_pcm_open(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
++      struct sf_spdif_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
++
++      snd_soc_set_runtime_hwparams(substream, &sf_pcm_hardware);
++      snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
++      runtime->private_data = dev;
++
++      return 0;
++}
++
++static int sf_pcm_close(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream)
++{
++      synchronize_rcu();
++      return 0;
++}
++
++static int sf_pcm_hw_params(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream,
++                      struct snd_pcm_hw_params *hw_params)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct sf_spdif_dev *dev = runtime->private_data;
++
++      switch (params_channels(hw_params)) {
++      case 2:
++              break;
++      default:
++              dev_err(dev->dev, "invalid channels number\n");
++              return -EINVAL;
++      }
++
++      dev->format = params_format(hw_params);
++      switch (dev->format) {
++      case SNDRV_PCM_FORMAT_S16_LE:
++      case SNDRV_PCM_FORMAT_S24_LE:
++      case SNDRV_PCM_FORMAT_S32_LE:
++              break;
++      default:
++              dev_err(dev->dev, "invalid format\n");
++              return -EINVAL;
++      }
++
++      dev->tx_fn = sf_spdif_pcm_tx;
++      dev->rx_fn = sf_spdif_pcm_rx;
++
++      return 0;
++}
++
++static int sf_pcm_trigger(struct snd_soc_component *component,
++                      struct snd_pcm_substream *substream, int cmd)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct sf_spdif_dev *dev = runtime->private_data;
++      int ret = 0;
++
++      switch (cmd) {
++      case SNDRV_PCM_TRIGGER_START:
++      case SNDRV_PCM_TRIGGER_RESUME:
++      case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++              if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                      WRITE_ONCE(dev->tx_ptr, 0);
++                      rcu_assign_pointer(dev->tx_substream, substream);
++              } else {
++                      WRITE_ONCE(dev->rx_ptr, 0);
++                      rcu_assign_pointer(dev->rx_substream, substream);
++              }
++              break;
++      case SNDRV_PCM_TRIGGER_STOP:
++      case SNDRV_PCM_TRIGGER_SUSPEND:
++      case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++              if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++                      rcu_assign_pointer(dev->tx_substream, NULL);
++              else
++                      rcu_assign_pointer(dev->rx_substream, NULL);
++              break;
++      default:
++              ret = -EINVAL;
++              break;
++      }
++
++      return ret;
++}
++
++static snd_pcm_uframes_t sf_pcm_pointer(struct snd_soc_component *component,
++                                      struct snd_pcm_substream *substream)
++{
++      struct snd_pcm_runtime *runtime = substream->runtime;
++      struct sf_spdif_dev *dev = runtime->private_data;
++      snd_pcm_uframes_t pos;
++
++      if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++              pos = READ_ONCE(dev->tx_ptr);
++      }
++      else {
++              pos = READ_ONCE(dev->rx_ptr);
++      }
++
++      return pos < runtime->buffer_size ? pos : 0;
++}
++
++static int sf_pcm_new(struct snd_soc_component *component,
++                      struct snd_soc_pcm_runtime *rtd)
++{
++      size_t size = sf_pcm_hardware.buffer_bytes_max;
++
++      snd_pcm_set_managed_buffer_all(rtd->pcm,
++                      SNDRV_DMA_TYPE_CONTINUOUS,
++                      NULL, size, size);
++
++      return 0;
++}
++
++static const struct snd_soc_component_driver sf_pcm_component = {
++      .open           = sf_pcm_open,
++      .close          = sf_pcm_close,
++      .hw_params      = sf_pcm_hw_params,
++      .trigger        = sf_pcm_trigger,
++      .pointer        = sf_pcm_pointer,
++      .pcm_construct  = sf_pcm_new,
++};
++
++int sf_spdif_pcm_register(struct platform_device *pdev)
++{
++      return devm_snd_soc_register_component(&pdev->dev, &sf_pcm_component,
++                                      NULL, 0);
++}
++
+--- /dev/null
++++ b/sound/soc/starfive/spdif.c
+@@ -0,0 +1,384 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/regmap.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/initval.h>
++#include <sound/dmaengine_pcm.h>
++
++#include "spdif.h"
++
++static irqreturn_t spdif_irq_handler(int irq, void *dev_id)
++{
++      struct sf_spdif_dev *dev = dev_id;
++      bool irq_valid = false;
++      unsigned int intr;
++      unsigned int stat;
++
++      regmap_read(dev->regmap, SPDIF_INT_REG, &intr);
++      regmap_read(dev->regmap, SPDIF_STAT_REG, &stat);
++      regmap_update_bits(dev->regmap, SPDIF_CTRL,
++              SPDIF_MASK_ENABLE, 0);
++      regmap_update_bits(dev->regmap, SPDIF_INT_REG,
++              SPDIF_INT_REG_BIT, 0);
++
++      if ((stat & SPDIF_EMPTY_FLAG) || (stat & SPDIF_AEMPTY_FLAG)) {
++              sf_spdif_pcm_push_tx(dev);
++              irq_valid = true;
++      }
++
++      if ((stat & SPDIF_FULL_FLAG) || (stat & SPDIF_AFULL_FLAG)) {
++              sf_spdif_pcm_pop_rx(dev);
++              irq_valid = true;
++      }
++
++      if (stat & SPDIF_PARITY_FLAG) {
++              irq_valid = true;
++      }
++
++      if (stat & SPDIF_UNDERR_FLAG) {
++              irq_valid = true;
++      }
++
++      if (stat & SPDIF_OVRERR_FLAG) {
++              irq_valid = true;
++      }
++
++      if (stat & SPDIF_SYNCERR_FLAG) {
++              irq_valid = true;
++      }
++
++      if (stat & SPDIF_LOCK_FLAG) {
++              irq_valid = true;
++      }
++
++      if (stat & SPDIF_BEGIN_FLAG) {
++              irq_valid = true;
++      }
++
++      if (stat & SPDIF_RIGHT_LEFT) {
++              irq_valid = true;
++      }
++
++      regmap_update_bits(dev->regmap, SPDIF_CTRL,
++              SPDIF_MASK_ENABLE, SPDIF_MASK_ENABLE);
++
++      if (irq_valid)
++              return IRQ_HANDLED;
++      else
++              return IRQ_NONE;
++}
++
++static int sf_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
++      struct snd_soc_dai *dai)
++{
++      struct sf_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
++      bool tx;
++
++      tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++      if (tx) {
++              /* tx mode */
++              regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++                      SPDIF_TR_MODE, SPDIF_TR_MODE);
++
++              regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++                      SPDIF_MASK_FIFO, SPDIF_EMPTY_MASK | SPDIF_AEMPTY_MASK);
++      } else {
++              /* rx mode */
++              regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++                      SPDIF_TR_MODE, 0);
++
++              regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++                      SPDIF_MASK_FIFO, SPDIF_FULL_MASK | SPDIF_AFULL_MASK);
++      }
++
++      switch (cmd) {
++      case SNDRV_PCM_TRIGGER_START:
++      case SNDRV_PCM_TRIGGER_RESUME:
++      case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++              /* clock recovery form the SPDIF data stream  0:clk_enable */
++              regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++                      SPDIF_CLK_ENABLE, 0);
++
++              regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++                      SPDIF_ENABLE, SPDIF_ENABLE);
++              break;
++      case SNDRV_PCM_TRIGGER_STOP:
++      case SNDRV_PCM_TRIGGER_SUSPEND:
++      case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++              /* clock recovery form the SPDIF data stream  1:power save mode */
++              regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++                      SPDIF_CLK_ENABLE, SPDIF_CLK_ENABLE);
++
++              regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++                      SPDIF_ENABLE, 0);
++              break;
++      default:
++              printk(KERN_ERR "%s L.%d cmd:%d\n", __func__, __LINE__, cmd);
++              return -EINVAL;
++      }
++
++      return 0;
++}
++
++static int sf_spdif_hw_params(struct snd_pcm_substream *substream,
++      struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++      struct sf_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
++      unsigned int channels;
++      unsigned int rate;
++      unsigned int format;
++      unsigned int tsamplerate;
++
++      channels = params_channels(params);
++      rate = params_rate(params);
++      format = params_format(params);
++
++      switch (channels) {
++      case 2:
++              break;
++      default:
++              dev_err(dai->dev, "invalid channels number\n");
++              return -EINVAL;
++      }
++
++      switch (format) {
++      case SNDRV_PCM_FORMAT_S16_LE:
++      case SNDRV_PCM_FORMAT_S24_LE:
++      case SNDRV_PCM_FORMAT_S32_LE:
++              break;
++      default:
++              dev_err(spdif->dev, "invalid format\n");
++              return -EINVAL;
++      }
++
++      switch (rate) {
++      case 8000:
++      case 11025:
++      case 16000:
++      case 22050:
++              break;
++      default:
++              printk(KERN_ERR "channel:%d sample rate:%d\n", channels, rate);
++              return -EINVAL;
++      }
++
++      /* 12288000/128=96000 */
++      tsamplerate = (96000 + rate/2)/rate - 1;
++
++      if (rate < 3) {
++              return -EINVAL;
++      }
++
++      /* transmission sample rate */
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL, 0xFF, tsamplerate);
++
++      return 0;
++}
++
++static int sf_spdif_dai_probe(struct snd_soc_dai *dai)
++{
++      struct sf_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
++
++      #if 0
++      spdif->play_dma_data.addr = (dma_addr_t)spdif->spdif_base + SPDIF_FIFO_ADDR;
++      spdif->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++      spdif->play_dma_data.fifo_size = 16;
++      spdif->play_dma_data.maxburst = 16;
++      spdif->capture_dma_data.addr = (dma_addr_t)spdif->spdif_base + SPDIF_FIFO_ADDR;
++      spdif->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++      spdif->capture_dma_data.fifo_size = 16;
++      spdif->capture_dma_data.maxburst = 16;
++      snd_soc_dai_init_dma_data(dai, &spdif->play_dma_data, &spdif->capture_dma_data);
++      snd_soc_dai_set_drvdata(dai, spdif);
++      #endif
++
++      /* reset */
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++              SPDIF_ENABLE | SPDIF_SFR_ENABLE | SPDIF_FIFO_ENABLE, 0);
++
++      /* clear irq */
++      regmap_update_bits(spdif->regmap, SPDIF_INT_REG,
++              SPDIF_INT_REG_BIT, 0);
++
++      /* power save mode */
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++              SPDIF_CLK_ENABLE, SPDIF_CLK_ENABLE);
++
++      /* power save mode */
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++              SPDIF_CLK_ENABLE, SPDIF_CLK_ENABLE);
++
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++              SPDIF_PARITCHECK|SPDIF_VALIDITYCHECK|SPDIF_DUPLICATE,
++              SPDIF_PARITCHECK|SPDIF_VALIDITYCHECK|SPDIF_DUPLICATE);
++
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++              SPDIF_SETPREAMBB, SPDIF_SETPREAMBB);
++
++      regmap_update_bits(spdif->regmap, SPDIF_INT_REG,
++              0x1FFF<<SPDIF_PREAMBLEDEL, 0x3<<SPDIF_PREAMBLEDEL);
++
++      regmap_update_bits(spdif->regmap, SPDIF_FIFO_CTRL,
++              0xFFFFFFFF, 0x20|(0x20<<SPDIF_AFULL_THRESHOLD));
++
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++              SPDIF_PARITYGEN, SPDIF_PARITYGEN);
++
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++              SPDIF_MASK_ENABLE, SPDIF_MASK_ENABLE);
++
++      /* APB access to FIFO enable, disable if use DMA/FIFO */
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++              SPDIF_USE_FIFO_IF, 0);
++
++      /* two channel */
++      regmap_update_bits(spdif->regmap, SPDIF_CTRL,
++              SPDIF_CHANNEL_MODE, 0);
++
++      return 0;
++}
++
++static const struct snd_soc_dai_ops sf_spdif_dai_ops = {
++      .trigger = sf_spdif_trigger,
++      .hw_params = sf_spdif_hw_params,
++};
++
++#define SF_PCM_RATE_44100_192000  (SNDRV_PCM_RATE_44100 | \
++                                                                      SNDRV_PCM_RATE_48000 | \
++                                                                      SNDRV_PCM_RATE_96000 | \
++                                                                      SNDRV_PCM_RATE_192000)
++
++#define SF_PCM_RATE_8000_22050  (SNDRV_PCM_RATE_8000 | \
++                                                                      SNDRV_PCM_RATE_11025 | \
++                                                                      SNDRV_PCM_RATE_16000 | \
++                                                                      SNDRV_PCM_RATE_22050)
++
++static struct snd_soc_dai_driver sf_spdif_dai = {
++      .name = "spdif",
++      .id = 0,
++      .probe = sf_spdif_dai_probe,
++      .playback = {
++              .stream_name = "Playback",
++              .channels_min = 2,
++              .channels_max = 2,
++              .rates = SF_PCM_RATE_8000_22050,
++              .formats = SNDRV_PCM_FMTBIT_S16_LE \
++                                      |SNDRV_PCM_FMTBIT_S24_LE \
++                                      |SNDRV_PCM_FMTBIT_S32_LE,
++      },
++      .capture = {
++              .stream_name = "Capture",
++              .channels_min = 2,
++              .channels_max = 2,
++              .rates = SF_PCM_RATE_8000_22050,
++              .formats = SNDRV_PCM_FMTBIT_S16_LE \
++                                      |SNDRV_PCM_FMTBIT_S24_LE \
++                                      |SNDRV_PCM_FMTBIT_S32_LE,
++      },
++      .ops = &sf_spdif_dai_ops,
++      .symmetric_rate = 1,
++};
++
++static const struct snd_soc_component_driver sf_spdif_component = {
++      .name = "sf-spdif",
++};
++
++static const struct regmap_config sf_spdif_regmap_config = {
++      .reg_bits = 32,
++      .reg_stride = 4,
++      .val_bits = 32,
++      .max_register = 0x200,
++};
++
++static int sf_spdif_probe(struct platform_device *pdev)
++{
++      struct sf_spdif_dev *spdif;
++      struct resource *res;
++      void __iomem *base;
++      int ret;
++      int irq;
++
++      spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
++      if (!spdif)
++              return -ENOMEM;
++
++      platform_set_drvdata(pdev, spdif);
++
++      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      base = devm_ioremap_resource(&pdev->dev, res);
++      if (IS_ERR(base))
++              return PTR_ERR(base);
++
++      spdif->spdif_base = base;
++      spdif->regmap = devm_regmap_init_mmio(&pdev->dev, spdif->spdif_base,
++                                      &sf_spdif_regmap_config);
++      if (IS_ERR(spdif->regmap))
++              return PTR_ERR(spdif->regmap);
++
++      spdif->dev = &pdev->dev;
++      spdif->fifo_th = 16;
++
++      irq = platform_get_irq(pdev, 0);
++      if (irq >= 0) {
++              ret = devm_request_irq(&pdev->dev, irq, spdif_irq_handler, 0,
++                              pdev->name, spdif);
++              if (ret < 0) {
++                      dev_err(&pdev->dev, "failed to request irq\n");
++                      return ret;
++              }
++      }
++
++      ret = devm_snd_soc_register_component(&pdev->dev, &sf_spdif_component,
++                                       &sf_spdif_dai, 1);
++      if (ret)
++              goto err_clk_disable;
++
++      if (irq >= 0) {
++              ret = sf_spdif_pcm_register(pdev);
++              spdif->use_pio = true;
++      } else {
++              ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
++                                      0);
++              spdif->use_pio = false;
++      }
++
++      if (ret)
++              goto err_clk_disable;
++
++      return 0;
++
++err_clk_disable:
++      return ret;
++}
++
++static const struct of_device_id sf_spdif_of_match[] = {
++      { .compatible = "starfive,sf-spdif", },
++      {},
++};
++MODULE_DEVICE_TABLE(of, sf_spdif_of_match);
++
++static struct platform_driver sf_spdif_driver = {
++      .driver = {
++              .name = "sf-spdif",
++              .of_match_table = sf_spdif_of_match,
++      },
++      .probe = sf_spdif_probe,
++};
++module_platform_driver(sf_spdif_driver);
++
++MODULE_AUTHOR("michael.yan <michael.yan@starfive.com>");
++MODULE_DESCRIPTION("starfive SPDIF driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/sound/soc/starfive/spdif.h
+@@ -0,0 +1,154 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef __SND_SOC_STARFIVE_SPDIF_H
++#define __SND_SOC_STARFIVE_SPDIF_H
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/types.h>
++#include <sound/dmaengine_pcm.h>
++#include <sound/pcm.h>
++#include <linux/dmaengine.h>
++#include <linux/types.h>
++
++#define SPDIF_CTRL            (0x0)
++#define SPDIF_INT_REG         (0x4)
++#define SPDIF_FIFO_CTRL               (0x8)
++#define SPDIF_STAT_REG                (0xC)
++
++#define SPDIF_FIFO_ADDR               (0x100)
++#define DMAC_SPDIF_POLLING_LEN        (256)
++
++///ctrl: sampled on the rising clock edge
++#define SPDIF_TSAMPLERATE     0///[SRATEW-1:0]
++#define SPDIF_SFR_ENABLE      (1<<8)  ///0:SFR reg reset to defualt value; auto set back to '1' after reset
++#define SPDIF_ENABLE          (1<<9)  ///0:reset of SPDIF block, SRF bits are unchanged; 1:enables SPDIF module
++#define SPDIF_FIFO_ENABLE     (1<<10) ///0:FIFO pointers are reset to zero,threshold levels for FIFO are unchaned; auto set back to '1'
++#define SPDIF_CLK_ENABLE      (1<<11) ///1:blocked and the modules are in power save mode; 0:block feeds the modules
++#define SPDIF_TR_MODE         (1<<12) ///0:rx; 1:tx
++#define SPDIF_PARITCHECK      (1<<13) ///0:party bit rx in a sub-frame is repeated on the parity; 1:check on a parity error
++#define SPDIF_PARITYGEN               (1<<14) ///0:parity bit from FIFO is transmitted in sub-frame;1:parity bit generated inside the core and added to a transmitted sub-frame
++#define SPDIF_VALIDITYCHECK   (1<<15) ///0:validity bit in frame isn't checked and all frame are written; 1:validity bit rx is checked
++#define SPDIF_CHANNEL_MODE    (1<<16) ///0:two-channel; 1:single-channel
++#define SPDIF_DUPLICATE               (1<<17) ///only tx -single-channel mode; 0:secondary channel; 1: left(primary) channel
++#define SPDIF_SETPREAMBB      (1<<18) ///only tx; 0:first preamble B after reset tx valid sub-frame; 1:first preamble B is tx after preambleddel(INT_REG)
++#define SPDIF_USE_FIFO_IF     (1<<19) ///0:FIFO disabled ,APB accese FIFO; 1:FIFO enable, APB access to FIFO disable;
++///#define RESERVED           (1<<20)
++#define SPDIF_PARITY_MASK     (1<<21)
++#define SPDIF_UNDERR_MASK     (1<<22)
++#define SPDIF_OVRERR_MASK     (1<<23)
++#define SPDIF_EMPTY_MASK      (1<<24)
++#define SPDIF_AEMPTY_MASK     (1<<25)
++#define SPDIF_FULL_MASK               (1<<26)
++#define SPDIF_AFULL_MASK      (1<<27)
++#define SPDIF_SYNCERR_MASK    (1<<28)
++#define SPDIF_LOCK_MASK               (1<<29)
++#define SPDIF_BEGIN_MASK      (1<<30)
++#define SPDIF_INTEREQ_MAKS    (1<<31)
++
++#define SPDIF_MASK_ENABLE     (SPDIF_PARITY_MASK | SPDIF_UNDERR_MASK | SPDIF_OVRERR_MASK | SPDIF_EMPTY_MASK | \
++                                                       SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | SPDIF_AFULL_MASK | SPDIF_SYNCERR_MASK |  \
++                                                       SPDIF_LOCK_MASK | SPDIF_BEGIN_MASK | SPDIF_INTEREQ_MAKS)
++
++#define SPDIF_MASK_FIFO               (SPDIF_EMPTY_MASK | SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | SPDIF_AFULL_MASK)
++
++////INT_REG
++#define SPDIF_RSAMPLERATE     0               ///[SRATEW-1:0]
++#define SPDIF_PREAMBLEDEL     8               ///[PDELAYW+7:8]        first B delay
++#define SPDIF_PARITYO         (1<<21) ///0:clear parity error
++#define SPDIF_TDATA_UNDERR    (1<<22) ///tx data underrun error;0:clear
++#define SPDIF_RDATA_OVRERR    (1<<23) ///rx data overrun error; 0:clear
++#define SPDIF_FIFO_EMPTY      (1<<24) ///empty; 0:clear
++#define SPDIF_FIOF_AEMPTY     (1<<25) ///almost empty; 0:clear
++#define SPDIF_FIFO_FULL               (1<<26) ///FIFO full; 0:clear
++#define SPDIF_FIFO_AFULL      (1<<27) ///FIFO almost full; 0:clear
++#define SPDIF_SYNCERR         (1<<28) ///sync error; 0:clear
++#define SPDIF_LOCK                    (1<<29) ///sync; 0:clear
++#define SPDIF_BLOCK_BEGIN     (1<<30) ///new start block rx data
++
++#define SPDIF_INT_REG_BIT     (SPDIF_PARITYO | SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR | SPDIF_FIFO_EMPTY |   \
++                                                       SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL | SPDIF_SYNCERR |       \
++                                                       SPDIF_LOCK | SPDIF_BLOCK_BEGIN)
++
++#define SPDIF_ERROR_INT_STATUS        (SPDIF_PARITYO | SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR)
++#define SPDIF_FIFO_INT_STATUS (SPDIF_FIFO_EMPTY | SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL)
++
++#define SPDIF_INT_PARITY_ERROR        (-1)
++#define SPDIF_INT_TDATA_UNDERR        (-2)
++#define SPDIF_INT_RDATA_OVRERR        (-3)
++#define SPDIF_INT_FIFO_EMPTY  1
++#define SPDIF_INT_FIFO_AEMPTY 2
++#define SPDIF_INT_FIFO_FULL   3
++#define SPDIF_INT_FIFO_AFULL  4
++#define SPDIF_INT_SYNCERR     (-4)
++#define SPDIF_INT_LOCK                5       // reciever has become synchronized with input data stream
++#define SPDIF_INT_BLOCK_BEGIN 6       // start a new block in recieve data, written into FIFO
++
++///FIFO_CTRL
++#define SPDIF_AEMPTY_THRESHOLD        0       // [depth-1:0]
++#define SPDIF_AFULL_THRESHOLD 16      // [depth+15:16]
++
++///STAT_REG
++#define SPDIF_FIFO_LEVEL      (1<<0)
++#define SPDIF_PARITY_FLAG     (1<<21) // 1:error; 0:repeated
++#define SPDIF_UNDERR_FLAG     (1<<22) // 1:error
++#define SPDIF_OVRERR_FLAG     (1<<23) // 1:error
++#define SPDIF_EMPTY_FLAG      (1<<24) // 1:fifo empty
++#define SPDIF_AEMPTY_FLAG     (1<<25) // 1:fifo almost empty
++#define SPDIF_FULL_FLAG               (1<<26) // 1:fifo full
++#define SPDIF_AFULL_FLAG      (1<<27) // 1:fifo almost full
++#define SPDIF_SYNCERR_FLAG    (1<<28) // 1:rx sync error
++#define SPDIF_LOCK_FLAG               (1<<29) // 1:RX sync
++#define SPDIF_BEGIN_FLAG      (1<<30) // 1:start a new block
++#define SPDIF_RIGHT_LEFT      (1<<31) // 1:left channel received and tx into FIFO; 0:right channel received and tx into FIFO
++
++#define SPDIF_STAT            (SPDIF_PARITY_FLAG | SPDIF_UNDERR_FLAG | SPDIF_OVRERR_FLAG | SPDIF_EMPTY_FLAG |         \
++                                               SPDIF_AEMPTY_FLAG | SPDIF_FULL_FLAG | SPDIF_AFULL_FLAG | SPDIF_SYNCERR_FLAG |          \
++                                               SPDIF_LOCK_FLAG | SPDIF_BEGIN_FLAG | SPDIF_RIGHT_LEFT)
++struct sf_spdif_dev {
++      void __iomem *spdif_base;
++      struct regmap *regmap;
++      struct device *dev;
++      u32 fifo_th;
++      int active;
++
++      /* data related to DMA transfers b/w i2s and DMAC */
++      struct snd_dmaengine_dai_dma_data play_dma_data;
++      struct snd_dmaengine_dai_dma_data capture_dma_data;
++
++      bool use_pio;
++      struct snd_pcm_substream __rcu *tx_substream;
++      struct snd_pcm_substream __rcu *rx_substream;
++
++      unsigned int (*tx_fn)(struct sf_spdif_dev *dev,
++                      struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
++                      bool *period_elapsed, snd_pcm_format_t format);
++      unsigned int (*rx_fn)(struct sf_spdif_dev *dev,
++                      struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
++                      bool *period_elapsed, snd_pcm_format_t format);
++
++      snd_pcm_format_t format;
++      //unsigned int sample_bits;
++      unsigned int tx_ptr;
++      unsigned int rx_ptr;
++
++      struct snd_dmaengine_dai_dma_data dma_data;
++};
++
++#if IS_ENABLED(CONFIG_SND_STARFIVE_SPDIF_PCM)
++void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev);
++void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev);
++int sf_spdif_pcm_register(struct platform_device *pdev);
++#else
++void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev) { }
++void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev) { }
++int sf_spdif_pcm_register(struct platform_device *pdev)
++{
++      return -EINVAL;
++}
++#endif
++
++
++#endif        /* __SND_SOC_STARFIVE_SPDIF_H */

diff --git a/target/linux/visionfive/patches-5.15/0069-drm-starfive-Add-StarFive-drm-driver.patch b/target/linux/visionfive/patches-5.15/0069-drm-starfive-Add-StarFive-drm-driver.patch
new file mode 100644 (file)
index 0000000..c037308
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0069-drm-starfive-Add-StarFive-drm-driver.patch
@@ -0,0 +1,3588 @@
+From 5046ce73e9cdf9fbc9d956ab596804869d31a2fb Mon Sep 17 00:00:00 2001
+From: "sw.multimedia" <sw.multimedia@starfivetech.com>
+Date: Tue, 31 Aug 2021 16:48:57 +0800
+Subject: [PATCH 69/84] drm/starfive: Add StarFive drm driver
+
+1. Add starfive DRM Display driver framework
+2. Support M31 Phy and tda998x
+
+Signed-off-by: jack.zhu <jack.zhu@starfivetech.com>
+Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/gpu/drm/Kconfig                       |   2 +
+ drivers/gpu/drm/Makefile                      |   1 +
+ drivers/gpu/drm/starfive/Kconfig              |  16 +
+ drivers/gpu/drm/starfive/Makefile             |  13 +
+ drivers/gpu/drm/starfive/README.txt           |  56 ++
+ drivers/gpu/drm/starfive/starfive_drm_crtc.c  | 520 +++++++++++
+ drivers/gpu/drm/starfive/starfive_drm_crtc.h  |  82 ++
+ drivers/gpu/drm/starfive/starfive_drm_drv.c   | 268 ++++++
+ drivers/gpu/drm/starfive/starfive_drm_drv.h   |  25 +
+ .../gpu/drm/starfive/starfive_drm_encoder.c   | 130 +++
+ .../gpu/drm/starfive/starfive_drm_encoder.h   |  17 +
+ drivers/gpu/drm/starfive/starfive_drm_gem.c   | 347 ++++++++
+ drivers/gpu/drm/starfive/starfive_drm_gem.h   |  39 +
+ drivers/gpu/drm/starfive/starfive_drm_lcdc.c  | 520 +++++++++++
+ drivers/gpu/drm/starfive/starfive_drm_lcdc.h  | 160 ++++
+ drivers/gpu/drm/starfive/starfive_drm_plane.c | 226 +++++
+ drivers/gpu/drm/starfive/starfive_drm_plane.h |  12 +
+ drivers/gpu/drm/starfive/starfive_drm_vpp.c   | 822 ++++++++++++++++++
+ drivers/gpu/drm/starfive/starfive_drm_vpp.h   | 213 +++++
+ 19 files changed, 3469 insertions(+)
+ create mode 100644 drivers/gpu/drm/starfive/Kconfig
+ create mode 100644 drivers/gpu/drm/starfive/Makefile
+ create mode 100644 drivers/gpu/drm/starfive/README.txt
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_crtc.c
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_crtc.h
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_drv.c
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_drv.h
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_encoder.c
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_encoder.h
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_gem.c
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_gem.h
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_lcdc.c
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_lcdc.h
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_plane.c
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_plane.h
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_vpp.c
+ create mode 100644 drivers/gpu/drm/starfive/starfive_drm_vpp.h
+
+--- a/drivers/gpu/drm/Kconfig
++++ b/drivers/gpu/drm/Kconfig
+@@ -315,6 +315,8 @@ source "drivers/gpu/drm/shmobile/Kconfig
+ 
+ source "drivers/gpu/drm/sun4i/Kconfig"
+ 
++source "drivers/gpu/drm/starfive/Kconfig"
++
+ source "drivers/gpu/drm/omapdrm/Kconfig"
+ 
+ source "drivers/gpu/drm/tilcdc/Kconfig"
+--- a/drivers/gpu/drm/Makefile
++++ b/drivers/gpu/drm/Makefile
+@@ -96,6 +96,7 @@ obj-y                        += rcar-du/
+ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
+ obj-y                 += omapdrm/
+ obj-$(CONFIG_DRM_SUN4I) += sun4i/
++obj-$(CONFIG_DRM_STARFIVE) += starfive/
+ obj-y                 += tilcdc/
+ obj-$(CONFIG_DRM_QXL) += qxl/
+ obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/Kconfig
+@@ -0,0 +1,16 @@
++# SPDX-License-Identifier: GPL-2.0
++# Copyright (C) 2021 StarFive Technology Co., Ltd.
++
++config DRM_STARFIVE
++      tristate "DRM Support for StarFive SoCs"
++      depends on DRM
++      depends on SOC_STARFIVE || COMPILE_TEST
++      select DRM_GEM_CMA_HELPER
++      select DRM_KMS_HELPER
++      select DRM_MIPI_DSI
++      select DRM_PANEL
++      help
++        Choose this option if you have a StarFive SoCs.
++        The module will be called starfive-drm
++        This driver provides kernel mode setting and
++        buffer management to userspace.
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/Makefile
+@@ -0,0 +1,13 @@
++# SPDX-License-Identifier: GPL-2.0
++#
++# Copyright (C) 2021 StarFive Technology Co., Ltd.
++#
++starfive-drm-y := starfive_drm_drv.o \
++                starfive_drm_gem.o \
++                starfive_drm_crtc.o \
++                starfive_drm_encoder.o \
++                starfive_drm_plane.o \
++                starfive_drm_lcdc.o \
++                starfive_drm_vpp.o
++
++obj-$(CONFIG_DRM_STARFIVE) += starfive-drm.o
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/README.txt
+@@ -0,0 +1,56 @@
++Display Subsystem:(default FBdev)
++
++Steps switch to DRM:
++1、Disable fbdev,close below config items：
++CONFIG_FB_STARFIVE=y
++CONFIG_FB_STARFIVE_HDMI_TDA998X=y
++CONFIG_FB_STARFIVE_VIDEO=y
++
++2、open DRM hdmi pipeline,enable items:
++CONFIG_DRM_I2C_NXP_TDA998X=y
++CONFIG_DRM_I2C_NXP_TDA9950=y
++CONFIG_DRM_STARFIVE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++
++Precautions：when use DRM hdmi pipeline,please make sure CONFIG_DRM_STARFIVE_MIPI_DSI is disable ,
++                       or will cause color abnormal.
++
++3、open DRM mipi pipeline
++
++enable items:
++      CONFIG_PHY_M31_DPHY_RX0=y
++      CONFIG_DRM_STARFIVE_MIPI_DSI=y
++
++
++change jh7100.dtsi display-encoder as below：
++
++      display-encoder {
++              compatible = "starfive,display-encoder";
++              encoder-type = <6>; //2-TMDS, 3-LVDS, 6-DSI, 8-DPI
++              status = "okay";
++
++              ports {
++                      port@0 {
++                              endpoint {
++                                      remote-endpoint = <&dsi_out_port>;
++                              };
++                      };
++
++                      port@1 {
++                              endpoint {
++                                      remote-endpoint = <&crtc_0_out>;
++                              };
++                      };
++              };
++      };
++
++install libdrm:
++make buildroot_initramfs-menuconfig
++choose:
++BR2_PACKAGE_LIBDRM=y
++BR2_PACKAGE_LIBDRM_RADEON=y
++BR2_PACKAGE_LIBDRM_AMDGPU=y
++BR2_PACKAGE_LIBDRM_NOUVEAU=y
++BR2_PACKAGE_LIBDRM_ETNAVIV=y
++BR2_PACKAGE_LIBDRM_INSTALL_TESTS=y
++
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
+@@ -0,0 +1,520 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/clk.h>
++#include <linux/component.h>
++#include <linux/of_device.h>
++#include <linux/delay.h>
++#include <drm/drm_atomic.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_atomic_uapi.h>
++#include <drm/drm_fb_cma_helper.h>
++#include <drm/drm_print.h>
++#include <drm/drm_probe_helper.h>
++#include <drm/drm_vblank.h>
++#include <drm/drm_gem_atomic_helper.h>
++#include "starfive_drm_drv.h"
++#include "starfive_drm_crtc.h"
++#include "starfive_drm_plane.h"
++#include "starfive_drm_lcdc.h"
++#include "starfive_drm_vpp.h"
++//#include <video/sys_comm_regs.h>
++
++struct resource_name {
++      char name[10];
++};
++
++static const struct resource_name mem_res_name[] = {
++      {"lcdc"},
++      {"vpp0"},
++      {"vpp1"},
++      {"vpp2"},
++      {"clk"},
++      {"rst"},
++      {"sys"}
++};
++
++static inline struct drm_encoder *
++starfive_head_atom_get_encoder(struct starfive_crtc *sf_crtc)
++{
++      struct drm_encoder *encoder = NULL;
++
++      /* We only ever have a single encoder */
++      drm_for_each_encoder_mask(encoder, sf_crtc->crtc.dev,
++                      sf_crtc->crtc.state->encoder_mask)
++              break;
++
++      return encoder;
++}
++
++static int ddrfmt_to_ppfmt(struct starfive_crtc *sf_crtc)
++{
++      int ddrfmt = sf_crtc->ddr_format;
++      int ret = 0;
++
++      sf_crtc->lcdcfmt = WIN_FMT_xRGB8888; //lcdc default used
++      sf_crtc->pp_conn_lcdc = 1;//default config
++      switch (ddrfmt) {
++      case DRM_FORMAT_UYVY:
++              sf_crtc->vpp_format = COLOR_YUV422_UYVY;
++              break;
++      case DRM_FORMAT_VYUY:
++              sf_crtc->vpp_format = COLOR_YUV422_VYUY;
++              break;
++      case DRM_FORMAT_YUYV:
++              sf_crtc->vpp_format = COLOR_YUV422_YUYV;
++              break;
++      case DRM_FORMAT_YVYU:
++              sf_crtc->vpp_format = COLOR_YUV422_YVYU;
++              break;
++      case DRM_FORMAT_YUV420:
++              sf_crtc->vpp_format = COLOR_YUV420P;
++              break;
++      case DRM_FORMAT_NV21:
++              sf_crtc->vpp_format = COLOR_YUV420_NV21;
++              break;
++      case DRM_FORMAT_NV12:
++              sf_crtc->vpp_format = COLOR_YUV420_NV12;
++              break;
++      case DRM_FORMAT_ARGB8888:
++              sf_crtc->vpp_format = COLOR_RGB888_ARGB;
++              break;
++      case DRM_FORMAT_ABGR8888:
++              sf_crtc->vpp_format = COLOR_RGB888_ABGR;
++              break;
++      case DRM_FORMAT_RGBA8888:
++              sf_crtc->vpp_format = COLOR_RGB888_RGBA;
++              break;
++      case DRM_FORMAT_BGRA8888:
++              sf_crtc->vpp_format = COLOR_RGB888_BGRA;
++              break;
++      case DRM_FORMAT_RGB565:
++              sf_crtc->vpp_format = COLOR_RGB565;
++              //sf_crtc->lcdcfmt = WIN_FMT_RGB565;
++              //this format no need pp, lcdc can direct read ddr buff
++              //sf_crtc->pp_conn_lcdc = -1;
++              break;
++      case DRM_FORMAT_XRGB1555:
++              sf_crtc->lcdcfmt = WIN_FMT_xRGB1555;
++              sf_crtc->pp_conn_lcdc = -1;//this format no need pp, lcdc can direct read ddr buff;
++              break;
++      case DRM_FORMAT_XRGB4444:
++              sf_crtc->lcdcfmt = WIN_FMT_xRGB4444;
++              sf_crtc->pp_conn_lcdc = -1;//this format no need pp, lcdc can direct read ddr buff;
++              break;
++
++      default:
++              ret = -1;
++              break;
++      }
++
++      return ret;
++}
++
++void starfive_crtc_hw_config_simple(struct starfive_crtc *starfive_crtc)
++{
++
++}
++
++static void starfive_crtc_destroy(struct drm_crtc *crtc)
++{
++      drm_crtc_cleanup(crtc);
++}
++
++static void starfive_crtc_destroy_state(struct drm_crtc *crtc,
++                              struct drm_crtc_state *state)
++{
++      struct starfive_crtc_state *s = to_starfive_crtc_state(state);
++
++      __drm_atomic_helper_crtc_destroy_state(&s->base);
++      kfree(s);
++}
++
++static void starfive_crtc_reset(struct drm_crtc *crtc)
++{
++      struct starfive_crtc_state *crtc_state =
++      kzalloc(sizeof(*crtc_state), GFP_KERNEL);
++
++      if (crtc->state)
++              starfive_crtc_destroy_state(crtc, crtc->state);
++
++      __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
++}
++
++static struct drm_crtc_state *starfive_crtc_duplicate_state(struct drm_crtc *crtc)
++{
++      struct starfive_crtc_state *starfive_state;
++
++      starfive_state = kzalloc(sizeof(*starfive_state), GFP_KERNEL);
++      if (!starfive_state)
++              return NULL;
++
++      __drm_atomic_helper_crtc_duplicate_state(crtc, &starfive_state->base);
++
++      return &starfive_state->base;
++}
++
++static int starfive_crtc_enable_vblank(struct drm_crtc *crtc)
++{
++      //need set hw
++      return 0;
++}
++
++static void starfive_crtc_disable_vblank(struct drm_crtc *crtc)
++{
++      //need set hw
++}
++
++static const struct drm_crtc_funcs starfive_crtc_funcs = {
++      .set_config = drm_atomic_helper_set_config,
++      .page_flip = drm_atomic_helper_page_flip,
++      .destroy = starfive_crtc_destroy,
++      .set_property = NULL,
++      .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
++      .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
++      .reset = starfive_crtc_reset,
++      .atomic_duplicate_state = starfive_crtc_duplicate_state,
++      .atomic_destroy_state = starfive_crtc_destroy_state,
++      //.gamma_set = drm_atomic_helper_legacy_gamma_set,
++      .enable_vblank = starfive_crtc_enable_vblank,
++      .disable_vblank = starfive_crtc_disable_vblank,
++      //.set_crc_source = starfive_crtc_set_crc_source,
++      //.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
++      //.verify_crc_source = starfive_crtc_verify_crc_source,
++};
++
++static bool starfive_crtc_mode_fixup(struct drm_crtc *crtc,
++                                   const struct drm_display_mode *mode,
++                                   struct drm_display_mode *adjusted_mode)
++{
++      /* Nothing to do here, but this callback is mandatory. */
++      return true;
++}
++
++static int starfive_crtc_atomic_check(struct drm_crtc *crtc,
++                                    struct drm_atomic_state *state)
++{
++      //state->no_vblank = true;      // hardware without VBLANK interrupt ???
++      struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
++                                                                              crtc);
++      crtc_state->no_vblank = true;
++
++      return 0;
++}
++
++static void starfive_crtc_atomic_begin(struct drm_crtc *crtc,
++                                     struct drm_atomic_state *old_crtc_state)
++{
++      //starfive_crtc_gamma_set(crtcp, crtc, old_crtc_state);
++}
++
++static void starfive_crtc_atomic_flush(struct drm_crtc *crtc,
++                                     struct drm_atomic_state *old_crtc_state)
++{
++      struct starfive_crtc *crtcp = to_starfive_crtc(crtc);
++      int ret;
++
++      //starfive_flush_dcache(crtcp->dma_addr, 1920*1080*2);
++      DRM_DEBUG_DRIVER("ddr_format_change [%d], dma_addr_change [%d]\n",
++                      crtcp->ddr_format_change, crtcp->dma_addr_change);
++      if (crtcp->ddr_format_change || crtcp->dma_addr_change) {
++              ret = ddrfmt_to_ppfmt(crtcp);
++              starfive_pp_update(crtcp);
++      } else {
++              DRM_DEBUG_DRIVER("%s with no change\n", __func__);
++      }
++}
++
++static void starfive_crtc_atomic_enable(struct drm_crtc *crtc,
++                                      struct drm_atomic_state *state)
++{
++      struct starfive_crtc *crtcp = to_starfive_crtc(crtc);
++      int ret;
++
++// enable crtc HW
++#ifdef CONFIG_DRM_STARFIVE_MIPI_DSI
++      dsitx_vout_init(crtcp);
++      lcdc_dsi_sel(crtcp);
++#else
++      vout_reset(crtcp);
++#endif
++      ret = ddrfmt_to_ppfmt(crtcp);
++      starfive_pp_enable(crtcp);
++      starfive_lcdc_enable(crtcp);
++      crtcp->is_enabled = true;  // should before
++}
++
++static void starfive_crtc_atomic_disable(struct drm_crtc *crtc,
++                                       struct drm_atomic_state *state)
++{
++      struct starfive_crtc *crtcp = to_starfive_crtc(crtc);
++      int pp_id;
++
++      for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
++              if (crtcp->pp[pp_id].inited == 1) {
++                      pp_disable_intr(crtcp, pp_id);
++                      vout_disable(crtcp); // disable crtc HW
++              }
++      }
++      crtcp->is_enabled = false;
++}
++
++static enum drm_mode_status starfive_crtc_mode_valid(struct drm_crtc *crtc,
++                                                   const struct drm_display_mode *mode)
++{
++      int refresh = drm_mode_vrefresh(mode);
++
++      if (refresh > 60) //lcdc miss support 60+ fps
++              return MODE_BAD;
++      else
++              return MODE_OK;
++}
++
++static const struct drm_crtc_helper_funcs starfive_crtc_helper_funcs = {
++      .mode_fixup = starfive_crtc_mode_fixup,
++      .atomic_check = starfive_crtc_atomic_check,
++      .atomic_begin = starfive_crtc_atomic_begin,
++      .atomic_flush = starfive_crtc_atomic_flush,
++      .atomic_enable = starfive_crtc_atomic_enable,
++      .atomic_disable = starfive_crtc_atomic_disable,
++      .mode_valid = starfive_crtc_mode_valid,
++};
++
++int starfive_crtc_create(struct drm_device *drm_dev,
++                       struct starfive_crtc *starfive_crtc,
++                       const struct drm_crtc_funcs *crtc_funcs,
++                       const struct drm_crtc_helper_funcs *crtc_helper_funcs)
++{
++      struct drm_crtc *crtc = &starfive_crtc->crtc;
++      struct device *dev = drm_dev->dev;
++      struct device_node *port;
++      int ret;
++
++      starfive_crtc->planes = devm_kzalloc(dev, sizeof(struct drm_plane), GFP_KERNEL);
++      ret = starfive_plane_init(drm_dev, starfive_crtc, DRM_PLANE_TYPE_PRIMARY);
++      if (ret) {
++              dev_err(drm_dev->dev, "failed to construct primary plane\n");
++              return ret;
++      }
++
++      drm_crtc_init_with_planes(drm_dev, crtc, starfive_crtc->planes, NULL,
++                      crtc_funcs, NULL);
++      drm_crtc_helper_add(crtc, crtc_helper_funcs);
++      port = of_get_child_by_name(starfive_crtc->dev->of_node, "port");
++      if (!port) {
++              DRM_ERROR("no port node found in %s\n", dev->of_node->full_name);
++              ret = -ENOENT;
++      }
++
++      crtc->port = port;
++      return 0;
++}
++
++static int starfive_crtc_get_memres(struct platform_device *pdev, struct starfive_crtc *sf_crtc)
++{
++      struct device *dev = &pdev->dev;
++      int i;
++
++      for (i = 0; i < ARRAY_SIZE(mem_res_name); i++) {
++              const char *name = mem_res_name[i].name;
++              struct resource *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
++              void __iomem *regs = devm_ioremap_resource(dev, res);
++
++              if (IS_ERR(regs))
++                      return PTR_ERR(regs);
++
++              if (!strcmp(name, "lcdc"))
++                      sf_crtc->base_lcdc = regs;
++              else if (!strcmp(name, "vpp0"))
++                      sf_crtc->base_vpp0 = regs;
++              else if (!strcmp(name, "vpp1"))
++                      sf_crtc->base_vpp1 = regs;
++              else if (!strcmp(name, "vpp2"))
++                      sf_crtc->base_vpp2 = regs;
++              else if (!strcmp(name, "clk"))
++                      sf_crtc->base_clk = regs;
++              else if (!strcmp(name, "rst"))
++                      sf_crtc->base_rst = regs;
++              else if (!strcmp(name, "sys"))
++                      sf_crtc->base_syscfg = regs;
++              else
++                      dev_err(&pdev->dev, "Could not match resource name\n");
++      }
++
++      sf_crtc->topclk = ioremap(0x11800000, 0x10000);
++      sf_crtc->toprst = ioremap(0x11840000, 0x10000);
++
++      return 0;
++}
++
++static int starfive_parse_dt(struct device *dev, struct starfive_crtc *sf_crtc)
++{
++      int ret;
++      struct device_node *np = dev->of_node;
++      struct device_node *child;
++      int pp_num = 0;
++
++      if (!np)
++              return -EINVAL;
++
++      sf_crtc->pp = devm_kzalloc(dev, sizeof(struct pp_mode) * PP_NUM, GFP_KERNEL);
++      if (!sf_crtc->pp)
++              return -ENOMEM;
++
++      for_each_child_of_node(np, child) {
++              if (of_property_read_u32(child, "pp-id", &pp_num)) {
++                      ret = -EINVAL;
++                      continue;
++              }
++              if (pp_num >= PP_NUM)
++                      dev_err(dev, " pp-id number %d is not support!\n", pp_num);
++
++              sf_crtc->pp[pp_num].pp_id = pp_num;
++              sf_crtc->pp[pp_num].bus_out = of_property_read_bool(child, "sys-bus-out");
++              sf_crtc->pp[pp_num].fifo_out = of_property_read_bool(child, "fifo-out");
++              if (of_property_read_u32(child, "src-format", &sf_crtc->pp[pp_num].src.format)) {
++                      dev_err(dev, "Missing src-format property in the DT.\n");
++                      ret = -EINVAL;
++              }
++              if (of_property_read_u32(child, "src-width", &sf_crtc->pp[pp_num].src.width)) {
++                      dev_err(dev, "Missing src-width property in the DT. w %d\n",
++                                      sf_crtc->pp[pp_num].src.width);
++                      ret = -EINVAL;
++              }
++              if (of_property_read_u32(child, "src-height", &sf_crtc->pp[pp_num].src.height)) {
++                      dev_err(dev, "Missing src-height property in the DT.\n");
++                      ret = -EINVAL;
++              }
++              if (of_property_read_u32(child, "dst-format", &sf_crtc->pp[pp_num].dst.format)) {
++                      dev_err(dev, "Missing dst-format property in the DT.\n");
++                      ret = -EINVAL;
++              }
++              if (of_property_read_u32(child, "dst-width", &sf_crtc->pp[pp_num].dst.width)) {
++                      dev_err(dev, "Missing dst-width property in the DT.\n");
++                      ret = -EINVAL;
++              }
++              if (of_property_read_u32(child, "dst-height", &sf_crtc->pp[pp_num].dst.height)) {
++                      dev_err(dev, "Missing dst-height property in the DT.\n");
++                      ret = -EINVAL;
++              }
++              sf_crtc->pp[pp_num].inited = 1;
++      }
++
++      return ret;
++}
++
++static int starfive_crtc_bind(struct device *dev, struct device *master, void *data)
++{
++      struct platform_device *pdev = to_platform_device(dev);
++      struct drm_device *drm_dev = data;
++      struct starfive_crtc *crtcp;
++      int ret;
++
++      crtcp = devm_kzalloc(dev, sizeof(*crtcp), GFP_KERNEL);
++      if (!crtcp)
++              return -ENOMEM;
++
++      crtcp->dev = dev;
++      crtcp->drm_dev = drm_dev;
++      dev_set_drvdata(dev, crtcp);
++
++      spin_lock_init(&crtcp->reg_lock);
++
++      starfive_crtc_get_memres(pdev, crtcp);
++      ret = starfive_parse_dt(dev, crtcp);
++
++      crtcp->pp_conn_lcdc = starfive_pp_get_2lcdc_id(crtcp);
++
++      crtcp->lcdc_irq = platform_get_irq_byname(pdev, "lcdc_irq");
++      if (crtcp->lcdc_irq == -EPROBE_DEFER)
++              return crtcp->lcdc_irq;
++      if (crtcp->lcdc_irq < 0) {
++              dev_err(dev, "couldn't get lcdc irq\n");
++              return crtcp->lcdc_irq;
++      }
++
++      crtcp->vpp1_irq = platform_get_irq_byname(pdev, "vpp1_irq");
++      if (crtcp->vpp1_irq == -EPROBE_DEFER)
++              return crtcp->vpp1_irq;
++      if (crtcp->vpp1_irq < 0) {
++              dev_err(dev, "couldn't get vpp1 irq\n");
++              return crtcp->vpp1_irq;
++      }
++
++      ret = devm_request_irq(&pdev->dev, crtcp->lcdc_irq, lcdc_isr_handler, 0,
++                             "sf_lcdc", crtcp);
++      if (ret) {
++              dev_err(&pdev->dev, "failure requesting irq %i: %d\n",
++                              crtcp->lcdc_irq, ret);
++              return ret;
++      }
++
++      ret = devm_request_irq(&pdev->dev, crtcp->vpp1_irq, vpp1_isr_handler, 0,
++                              "sf_vpp1", crtcp);
++      if (ret) {
++              dev_err(&pdev->dev, "failure requesting irq %i: %d\n",
++                      crtcp->vpp1_irq, ret);
++              return ret;
++      }
++
++      ret = starfive_crtc_create(drm_dev, crtcp,
++                                 &starfive_crtc_funcs,
++                                 &starfive_crtc_helper_funcs);
++      if (ret)
++              return ret;
++
++      crtcp->is_enabled = false;
++
++      /* starfive_set_crtc_possible_masks(drm_dev, crtcp); */
++
++      /*
++      ret = drm_self_refresh_helper_init(crtcp);
++      if (ret)
++              DRM_DEV_DEBUG_KMS(crtcp->dev,
++                      "Failed to init %s with SR helpers %d, ignoring\n",
++                      crtcp->name, ret);
++      */
++
++      return 0;
++}
++
++static void starfive_crtc_unbind(struct device *dev, struct device *master, void *data)
++{
++      struct platform_device *pdev = to_platform_device(dev);
++      struct starfive_crtc *crtcp = dev_get_drvdata(dev);
++
++      drm_crtc_cleanup(&crtcp->crtc);
++      platform_set_drvdata(pdev, NULL);
++}
++
++static const struct component_ops starfive_crtc_component_ops = {
++      .bind   = starfive_crtc_bind,
++      .unbind = starfive_crtc_unbind,
++};
++
++static const struct of_device_id starfive_crtc_driver_dt_match[] = {
++      { .compatible = "starfive,jh7100-crtc" },
++      { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, starfive_crtc_driver_dt_match);
++
++static int starfive_crtc_probe(struct platform_device *pdev)
++{
++      return component_add(&pdev->dev, &starfive_crtc_component_ops);
++}
++
++static int starfive_crtc_remove(struct platform_device *pdev)
++{
++      component_del(&pdev->dev, &starfive_crtc_component_ops);
++      return 0;
++}
++
++struct platform_driver starfive_crtc_driver = {
++      .probe = starfive_crtc_probe,
++      .remove = starfive_crtc_remove,
++      .driver = {
++              .name = "starfive-crtc",
++              .of_match_table = of_match_ptr(starfive_crtc_driver_dt_match),
++      },
++};
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.h
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef _STARFIVE_DRM_CRTC_H
++#define _STARFIVE_DRM_CRTC_H
++#include <drm/drm_crtc.h>
++
++enum COLOR_FORMAT {
++      COLOR_YUV422_UYVY = 0,  //00={Y1,V0,Y0,U0}
++      COLOR_YUV422_VYUY = 1,  //01={Y1,U0,Y0,V0}
++      COLOR_YUV422_YUYV = 2,  //10={V0,Y1,U0,Y0}
++      COLOR_YUV422_YVYU = 3,  //11={U0,Y1,V0,Y0}
++
++      COLOR_YUV420P,
++      COLOR_YUV420_NV21,
++      COLOR_YUV420_NV12,
++
++      COLOR_RGB888_ARGB,
++      COLOR_RGB888_ABGR,
++      COLOR_RGB888_RGBA,
++      COLOR_RGB888_BGRA,
++      COLOR_RGB565,
++};
++
++struct starfive_crtc_state {
++      struct drm_crtc_state base;
++};
++
++#define to_starfive_crtc_state(s) \
++              container_of(s, struct starfive_crtc_state, base)
++
++struct starfive_crtc {
++      struct drm_crtc         crtc;
++      struct device           *dev;
++      struct drm_device       *drm_dev;
++      bool is_enabled;
++
++      void __iomem    *base_clk;      // 0x12240000
++      void __iomem    *base_rst;      // 0x12250000
++      void __iomem    *base_syscfg;   // 0x12260000
++      void __iomem    *base_vpp0;     // 0x12040000
++      void __iomem    *base_vpp1;     // 0x12080000
++      void __iomem    *base_vpp2;     // 0x120c0000
++      void __iomem    *base_lcdc;     // 0x12000000
++
++      void __iomem    *topclk;        // 0x11800000, 0x10000
++      void __iomem    *toprst;        // 0x11840000, 0x10000
++
++      int             lcdc_irq;
++      int             vpp0_irq;
++      int             vpp1_irq;
++      int             vpp2_irq;
++
++      struct pp_mode  *pp;
++
++      int             winNum;
++      int             pp_conn_lcdc;
++      unsigned int    ddr_format;
++      bool            ddr_format_change;
++      enum            COLOR_FORMAT vpp_format;
++      int             lcdcfmt;
++
++      /* one time only one process allowed to config the register */
++      spinlock_t      reg_lock;
++
++      struct drm_plane        *planes;
++
++      u8              lut_r[256];
++      u8              lut_g[256];
++      u8              lut_b[256];
++
++      bool            gamma_lut;
++      dma_addr_t      dma_addr;
++      bool            dma_addr_change;
++      size_t          size;
++};
++#define to_starfive_crtc(x) container_of(x, struct starfive_crtc, crtc)
++
++void starfive_crtc_hw_config_simple(struct starfive_crtc *starfive_crtc);
++
++#endif /* _STARFIVE_DRM_CRTC_H */
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_drv.c
+@@ -0,0 +1,268 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/component.h>
++#include <linux/iommu.h>
++#include <linux/module.h>
++#include <linux/of_address.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/soc/mediatek/mtk-mmsys.h>
++#include <linux/dma-mapping.h>
++#include <drm/drm_atomic.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_drv.h>
++#include <drm/drm_fb_helper.h>
++#include <drm/drm_fourcc.h>
++#include <drm/drm_gem.h>
++#include <drm/drm_gem_cma_helper.h>
++#include <drm/drm_gem_framebuffer_helper.h>
++#include <drm/drm_of.h>
++#include <drm/drm_probe_helper.h>
++#include <drm/drm_vblank.h>
++#include "starfive_drm_drv.h"
++#include "starfive_drm_gem.h"
++
++#define DRIVER_NAME   "starfive"
++#define DRIVER_DESC   "starfive Soc DRM"
++#define DRIVER_DATE   "20210519"
++#define DRIVER_MAJOR  1
++#define DRIVER_MINOR  0
++
++static struct drm_framebuffer *
++starfive_drm_mode_fb_create(struct drm_device *dev, struct drm_file *file,
++              const struct drm_mode_fb_cmd2 *mode_cmd)
++{
++      return drm_gem_fb_create(dev, file, mode_cmd);
++}
++
++static const struct drm_mode_config_funcs starfive_drm_mode_config_funcs = {
++      .fb_create = starfive_drm_mode_fb_create,
++      .atomic_check = drm_atomic_helper_check,
++      .atomic_commit = drm_atomic_helper_commit,
++};
++
++static const struct drm_mode_config_helper_funcs starfive_drm_mode_config_helpers = {
++      .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
++};
++
++static const struct file_operations starfive_drm_driver_fops = {
++      .owner = THIS_MODULE,
++      .open = drm_open,
++      .mmap = starfive_drm_gem_mmap,
++      .poll = drm_poll,
++      .read = drm_read,
++      .unlocked_ioctl = drm_ioctl,
++      .compat_ioctl = drm_compat_ioctl,
++      .release = drm_release,
++};
++
++static struct drm_driver starfive_drm_driver = {
++      .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
++      .dumb_create = starfive_drm_gem_dumb_create,
++      .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
++      .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
++      .gem_prime_import_sg_table = starfive_drm_gem_prime_import_sg_table,
++      .gem_prime_mmap = starfive_drm_gem_mmap_buf,
++      .fops = &starfive_drm_driver_fops,
++      .name = DRIVER_NAME,
++      .desc = DRIVER_DESC,
++      .date = DRIVER_DATE,
++      .major = DRIVER_MAJOR,
++      .minor = DRIVER_MINOR,
++};
++
++static int compare_dev(struct device *dev, void *data)
++{
++      return dev == (struct device *)data;
++}
++
++static void starfive_drm_match_add(struct device *dev,
++                                 struct component_match **match,
++                                 struct platform_driver *const *drivers,
++                                 int count)
++{
++      int i;
++
++      for (i = 0; i < count; i++) {
++              struct device_driver *drv = &drivers[i]->driver;
++              struct device *p = NULL, *d;
++
++              while ((d = platform_find_device_by_driver(p, drv))) {
++                      put_device(p);
++                      component_match_add(dev, match, compare_dev, d);
++                      p = d;
++              }
++              put_device(p);
++      }
++}
++
++static void starfive_cleanup(struct drm_device *ddev)
++{
++      struct starfive_drm_private *private = ddev->dev_private;
++
++      drm_kms_helper_poll_fini(ddev);
++      drm_atomic_helper_shutdown(ddev);
++      drm_mode_config_cleanup(ddev);
++      component_unbind_all(ddev->dev, ddev);
++      kfree(private);
++      ddev->dev_private = NULL;
++}
++
++static int starfive_drm_bind(struct device *dev)
++{
++      struct drm_device *drm_dev;
++      struct starfive_drm_private *private;
++      int ret;
++
++      drm_dev = drm_dev_alloc(&starfive_drm_driver, dev);
++      if (IS_ERR(drm_dev))
++              return PTR_ERR(drm_dev);
++
++      dev_set_drvdata(dev, drm_dev);
++
++      private = devm_kzalloc(drm_dev->dev, sizeof(*private), GFP_KERNEL);
++      if (!private) {
++              ret = -ENOMEM;
++              goto err_free;
++      }
++
++      drm_dev->dev_private = private;
++
++      /*
++      ret = starfive_drm_init_iommu(drm_dev);
++      if (ret)
++              goto err_free;
++      */
++
++      ret = drmm_mode_config_init(drm_dev);
++      if (ret)
++              return ret;
++
++      drm_dev->mode_config.min_width = 64;
++      drm_dev->mode_config.min_height = 64;
++
++      /*
++       * set max width and height as default value(4096x4096).
++       * this value would be used to check framebuffer size limitation
++       * at drm_mode_addfb().
++       */
++      drm_dev->mode_config.max_width = 4096;
++      drm_dev->mode_config.max_height = 4096;
++      drm_dev->mode_config.funcs = &starfive_drm_mode_config_funcs;
++      drm_dev->mode_config.helper_private = &starfive_drm_mode_config_helpers;
++      drm_dev->mode_config.async_page_flip = 1;
++
++      ret = component_bind_all(dev, drm_dev);
++      if (ret)
++              goto err_component_bind_all;
++
++      ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc);
++      if (ret)
++              goto err_drm_vblank_init;
++
++      drm_mode_config_reset(drm_dev);
++
++      /* init kms poll for handling hpd */
++      drm_kms_helper_poll_init(drm_dev);
++
++      ret = drm_dev_register(drm_dev, 0);
++      if (ret)
++              goto err_drm_dev_register;
++#ifdef CONFIG_FRAMEBUFFER_CONSOLE
++      drm_fbdev_generic_setup(drm_dev, 16);
++#endif
++      return 0;
++
++err_drm_dev_register:
++err_component_bind_all:
++      starfive_cleanup(drm_dev);
++err_drm_vblank_init:
++err_free:
++      drm_dev_put(drm_dev);
++
++      return ret;
++}
++
++static void starfive_drm_unbind(struct device *dev)
++{
++      struct drm_device *drm_dev = dev_get_drvdata(dev);
++
++      drm_dev_unregister(drm_dev);
++}
++
++static const struct component_master_ops starfive_drm_ops = {
++      .bind = starfive_drm_bind,
++      .unbind = starfive_drm_unbind,
++};
++
++static struct platform_driver * const starfive_component_drivers[] = {
++      &starfive_crtc_driver,
++#ifdef CONFIG_DRM_STARFIVE_MIPI_DSI
++      &starfive_dsi_platform_driver,
++#endif
++      &starfive_encoder_driver,
++};
++
++static int starfive_drm_probe(struct platform_device *pdev)
++{
++      struct device *dev = &pdev->dev;
++      struct component_match *match = NULL;
++
++      starfive_drm_match_add(dev, &match,
++                             starfive_component_drivers,
++                             ARRAY_SIZE(starfive_component_drivers));
++      if (IS_ERR(match))
++              return PTR_ERR(match);
++
++      return component_master_add_with_match(dev, &starfive_drm_ops, match);
++}
++
++static int starfive_drm_remove(struct platform_device *pdev)
++{
++      component_master_del(&pdev->dev, &starfive_drm_ops);
++      return 0;
++}
++
++static const struct of_device_id starfive_drm_dt_ids[] = {
++      { .compatible = "starfive,display-subsystem" },
++      { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, starfive_drm_dt_ids);
++
++static struct platform_driver starfive_drm_platform_driver = {
++      .probe  = starfive_drm_probe,
++      .remove = starfive_drm_remove,
++      .driver = {
++              .name           = "starfive-drm",
++              .of_match_table = starfive_drm_dt_ids,
++              //.pm     = &starfive_drm_pm_ops,
++      },
++};
++
++static int __init starfive_drm_init(void)
++{
++      int ret;
++
++      ret = platform_register_drivers(starfive_component_drivers,
++                                      ARRAY_SIZE(starfive_component_drivers));
++      if (ret)
++              return ret;
++
++      return platform_driver_register(&starfive_drm_platform_driver);
++}
++
++static void __exit starfive_drm_exit(void)
++{
++      platform_unregister_drivers(starfive_component_drivers,
++                                  ARRAY_SIZE(starfive_component_drivers));
++      platform_driver_unregister(&starfive_drm_platform_driver);
++}
++
++module_init(starfive_drm_init);
++module_exit(starfive_drm_exit);
++
++MODULE_AUTHOR("StarFive <StarFive@starfivetech.com>");
++MODULE_DESCRIPTION("StarFive SoC DRM driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_drv.h
+@@ -0,0 +1,25 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef _STARFIVE_DRM_DRV_H
++#define _STARFIVE_DRM_DRV_H
++
++#include <drm/drm_fb_helper.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_gem.h>
++#include <linux/module.h>
++#include <linux/component.h>
++
++struct starfive_drm_private {
++      struct drm_fb_helper fbdev_helper;
++      struct drm_gem_object *fbdev_bo;
++      struct mutex mm_lock;
++      struct drm_mm mm;
++};
++
++extern struct platform_driver starfive_crtc_driver;
++extern struct platform_driver starfive_encoder_driver;
++extern struct platform_driver starfive_dsi_platform_driver;
++
++#endif /* _STARFIVE_DRM_DRV_H_ */
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_encoder.c
+@@ -0,0 +1,130 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/clk.h>
++#include <linux/component.h>
++#include <linux/of_device.h>
++#include <drm/drm_atomic.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_atomic_uapi.h>
++#include <drm/drm_fb_cma_helper.h>
++#include <drm/drm_print.h>
++#include <drm/drm_probe_helper.h>
++#include <drm/drm_vblank.h>
++#include <drm/drm_of.h>
++#include "starfive_drm_drv.h"
++#include "starfive_drm_encoder.h"
++
++static void starfive_encoder_destroy(struct drm_encoder *encoder)
++{
++      drm_encoder_cleanup(encoder);
++      kfree(encoder);
++}
++
++static const struct drm_encoder_funcs starfive_encoder_funcs = {
++      .destroy = starfive_encoder_destroy,
++};
++
++
++static int starfive_encoder_bind(struct device *dev, struct device *master, void *data)
++{
++      struct drm_device *drm_dev = data;
++      struct device_node *np = dev->of_node;
++      struct starfive_encoder *encoderp;
++      int ret;
++      struct drm_panel *tmp_panel;
++      struct drm_bridge *tmp_bridge;
++      u32 crtcs = 0;
++
++      encoderp = devm_kzalloc(dev, sizeof(*encoderp), GFP_KERNEL);
++      if (!encoderp)
++              return -ENOMEM;
++
++      encoderp->dev = dev;
++      encoderp->drm_dev = drm_dev;
++      dev_set_drvdata(dev, encoderp);
++
++      if (dev->of_node) {
++              crtcs = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
++
++              if (of_property_read_u32(np, "encoder-type", &encoderp->encoder_type)) {
++                      DRM_ERROR("Missing encoder-type property in the DT.\n");
++                      encoderp->encoder_type = DRM_MODE_ENCODER_TMDS;
++              }
++      }
++
++      /* If no CRTCs were found, fall back to our old behaviour */
++      if (crtcs == 0) {
++              dev_warn(dev, "Falling back to first CRTC\n");
++              crtcs = 1 << 0;
++      }
++
++      encoderp->encoder.possible_crtcs = crtcs;
++
++      ret = drm_encoder_init(drm_dev, &encoderp->encoder,
++                      &starfive_encoder_funcs,
++                      encoderp->encoder_type, NULL);
++      if (ret)
++              goto err_encoder;
++
++      ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
++                      &tmp_panel, &tmp_bridge);
++      if (ret)
++              dev_err(dev, "endpoint returns %d\n", ret);
++
++      if (tmp_panel)
++              DRM_INFO("found panel on endpoint\n");
++      if (tmp_bridge)
++              DRM_INFO("found bridge on endpoint\n");
++
++      ret = drm_bridge_attach(&encoderp->encoder, tmp_bridge, NULL, 0);
++      if (ret)
++              goto err_bridge;
++
++      return 0;
++
++err_bridge:
++      drm_encoder_cleanup(&encoderp->encoder);
++err_encoder:
++      return ret;
++
++}
++
++static void starfive_encoder_unbind(struct device *dev, struct device *master, void *data)
++{
++      struct starfive_encoder *encoderp = dev_get_drvdata(dev);
++
++      starfive_encoder_destroy(&encoderp->encoder);
++}
++
++static const struct component_ops starfive_encoder_component_ops = {
++      .bind   = starfive_encoder_bind,
++      .unbind = starfive_encoder_unbind,
++};
++
++static const struct of_device_id starfive_encoder_driver_dt_match[] = {
++      { .compatible = "starfive,display-encoder" },
++      { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, starfive_encoder_driver_dt_match);
++
++static int starfive_encoder_probe(struct platform_device *pdev)
++{
++      return component_add(&pdev->dev, &starfive_encoder_component_ops);
++}
++
++static int starfive_encoder_remove(struct platform_device *pdev)
++{
++      component_del(&pdev->dev, &starfive_encoder_component_ops);
++      return 0;
++}
++
++struct platform_driver starfive_encoder_driver = {
++      .probe = starfive_encoder_probe,
++      .remove = starfive_encoder_remove,
++      .driver = {
++              .name = "display-encoder",
++              .of_match_table = of_match_ptr(starfive_encoder_driver_dt_match),
++      },
++};
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_encoder.h
+@@ -0,0 +1,17 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef _STARFIVE_DRM_ENCODER_H
++#define _STARFIVE_DRM_ENCODER_H
++
++struct starfive_encoder {
++      struct drm_encoder      encoder;
++      struct device           *dev;
++      struct drm_device       *drm_dev;
++      bool                    is_enabled;
++      int                     encoder_type;
++};
++#define to_starfive_encoder(x) container_of(x, struct starfive_encoder, encoder)
++
++#endif /* _STARFIVE_DRM_CRTC_H */
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_gem.c
+@@ -0,0 +1,347 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/dma-buf.h>
++#include <linux/iommu.h>
++#include <linux/vmalloc.h>
++#include <drm/drm.h>
++#include <drm/drm_gem.h>
++#include <drm/drm_prime.h>
++#include <drm/drm_vma_manager.h>
++#include <drm/drm_gem_cma_helper.h>
++#include "starfive_drm_drv.h"
++#include "starfive_drm_gem.h"
++
++static const struct drm_gem_object_funcs starfive_gem_object_funcs;
++static const struct vm_operations_struct mmap_mem_ops = {
++#ifdef CONFIG_HAVE_IOREMAP_PROT
++      .access = generic_access_phys
++#endif
++};
++
++static int starfive_drm_gem_object_mmap_dma(struct drm_gem_object *obj,
++                                          struct vm_area_struct *vma)
++{
++      struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
++      struct drm_device *drm = obj->dev;
++
++      return dma_mmap_attrs(drm->dev, vma, starfive_obj->kvaddr,
++                      starfive_obj->dma_addr, obj->size, starfive_obj->dma_attrs);
++}
++
++static int starfive_drm_gem_object_mmap(struct drm_gem_object *obj,
++                                      struct vm_area_struct *vma)
++{
++      int ret;
++
++      /*
++       * We allocated a struct page table for rk_obj, so clear
++       * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap().
++       */
++      vma->vm_flags &= ~VM_PFNMAP;
++      ret = starfive_drm_gem_object_mmap_dma(obj, vma);
++      if (ret)
++              drm_gem_vm_close(vma);
++
++      return ret;
++}
++
++int starfive_drm_gem_mmap_buf(struct drm_gem_object *obj,
++                            struct vm_area_struct *vma)
++{
++      int ret = drm_gem_mmap_obj(obj, obj->size, vma);
++
++      if (ret)
++              return ret;
++
++      return starfive_drm_gem_object_mmap(obj, vma);
++}
++
++int starfive_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
++{
++      struct drm_gem_object *obj;
++      int ret;
++
++      ret = drm_gem_mmap(filp, vma);
++      if (ret)
++              return ret;
++
++      obj = vma->vm_private_data;
++
++      /*
++       * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
++       * whole buffer from the start.
++       */
++      vma->vm_pgoff = 0;
++
++      return starfive_drm_gem_object_mmap(obj, vma);
++}
++
++void starfive_drm_gem_free_object(struct drm_gem_object *obj)
++{
++      struct starfive_drm_gem_obj *starfive_gem = to_starfive_gem_obj(obj);
++      struct drm_device *drm_dev = obj->dev;
++
++      if (starfive_gem->sg)
++              drm_prime_gem_destroy(obj, starfive_gem->sg);
++      else
++              dma_free_attrs(drm_dev->dev, obj->size, starfive_gem->kvaddr,
++                              starfive_gem->dma_addr, starfive_gem->dma_attrs);
++
++      /* release file pointer to gem object. */
++      drm_gem_object_release(obj);
++
++      kfree(starfive_gem);
++}
++
++static struct starfive_drm_gem_obj *
++starfive_drm_gem_alloc_object(struct drm_device *drm, unsigned int size)
++{
++      struct starfive_drm_gem_obj *starfive_obj;
++      struct drm_gem_object *obj;
++      int ret;
++
++      starfive_obj = kzalloc(sizeof(*starfive_obj), GFP_KERNEL);
++      if (!starfive_obj)
++              return ERR_PTR(-ENOMEM);
++
++      obj = &starfive_obj->base;
++      ret = drm_gem_object_init(drm, obj, round_up(size, PAGE_SIZE));
++      if (ret)
++              return ERR_PTR(ret);
++
++      return starfive_obj;
++}
++
++static int starfive_drm_gem_alloc_dma(struct starfive_drm_gem_obj *starfive_obj,
++                                    bool alloc_kmap)
++{
++      struct drm_gem_object *obj = &starfive_obj->base;
++      struct drm_device *drm = obj->dev;
++
++      starfive_obj->dma_attrs = DMA_ATTR_WRITE_COMBINE;
++      if (!alloc_kmap)
++              starfive_obj->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
++
++      starfive_obj->kvaddr = dma_alloc_attrs(drm->dev, obj->size,
++                                             &starfive_obj->dma_addr, GFP_KERNEL,
++                                             starfive_obj->dma_attrs);
++
++      DRM_INFO("kvaddr = 0x%px\n", starfive_obj->kvaddr);
++      DRM_INFO("dma_addr = 0x%llx, size = %lu\n", starfive_obj->dma_addr, obj->size);
++      if (!starfive_obj->kvaddr) {
++              DRM_ERROR("failed to allocate %zu byte dma buffer", obj->size);
++              return -ENOMEM;
++      }
++
++      return 0;
++}
++
++static int starfive_drm_gem_alloc_buf(struct starfive_drm_gem_obj *starfive_obj,
++                              bool alloc_kmap)
++{
++      return starfive_drm_gem_alloc_dma(starfive_obj, alloc_kmap);
++}
++
++static void starfive_drm_gem_release_object(struct starfive_drm_gem_obj *starfive_obj)
++{
++      drm_gem_object_release(&starfive_obj->base);
++      kfree(starfive_obj);
++}
++
++static struct starfive_drm_gem_obj *
++starfive_drm_gem_create_object(struct drm_device *drm, unsigned int size,
++                              bool alloc_kmap)
++{
++      struct starfive_drm_gem_obj *starfive_obj;
++      int ret;
++
++      starfive_obj = starfive_drm_gem_alloc_object(drm, size);
++      if (IS_ERR(starfive_obj))
++              return starfive_obj;
++
++      ret = starfive_drm_gem_alloc_buf(starfive_obj, alloc_kmap);
++      if (ret)
++              goto err_free_obj;
++
++      starfive_obj->base.funcs = &starfive_gem_object_funcs;
++
++      return starfive_obj;
++
++err_free_obj:
++      starfive_drm_gem_release_object(starfive_obj);
++      return ERR_PTR(ret);
++
++}
++
++static struct starfive_drm_gem_obj *
++starfive_drm_gem_create_with_handle(struct drm_file *file_priv,
++                                  struct drm_device *drm,
++                                  unsigned int size,
++                                  unsigned int *handle)
++{
++      struct starfive_drm_gem_obj *starfive_gem;
++      struct drm_gem_object *gem;
++      int ret;
++#ifdef CONFIG_FRAMEBUFFER_CONSOLE
++      //config true, for console display
++      starfive_gem = starfive_drm_gem_create_object(drm, size, true);
++#else
++      starfive_gem = starfive_drm_gem_create_object(drm, size, false);
++#endif
++      if (IS_ERR(starfive_gem))
++              return ERR_CAST(starfive_gem);
++
++      gem = &starfive_gem->base;
++
++      /*
++       * allocate a id of idr table where the obj is registered
++       * and handle has the id what user can see.
++       */
++      ret = drm_gem_handle_create(file_priv, gem, handle);
++      if (ret)
++              goto err_handle_create;
++
++      /* drop reference from allocate - handle holds it now. */
++      drm_gem_object_put(gem);
++
++      return starfive_gem;
++
++err_handle_create:
++      starfive_drm_gem_free_object(gem);
++
++      return ERR_PTR(ret);
++}
++
++int starfive_drm_gem_dumb_create(struct drm_file *file_priv,
++                               struct drm_device *dev,
++                               struct drm_mode_create_dumb *args)
++{
++      struct starfive_drm_gem_obj *starfive_gem;
++
++      args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
++      args->size = args->pitch * args->height;
++
++      starfive_gem = starfive_drm_gem_create_with_handle(file_priv, dev,
++                                      args->size, &args->handle);
++
++      return PTR_ERR_OR_ZERO(starfive_gem);
++}
++
++struct sg_table *starfive_drm_gem_prime_get_sg_table(struct drm_gem_object *obj)
++{
++      struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
++      struct drm_device *drm = obj->dev;
++      struct sg_table *sgt;
++      int ret;
++
++      if (starfive_obj->pages)
++              return drm_prime_pages_to_sg(obj->dev, starfive_obj->pages,
++                                           starfive_obj->num_pages);
++
++      sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
++      if (!sgt)
++              return ERR_PTR(-ENOMEM);
++
++      ret = dma_get_sgtable_attrs(drm->dev, sgt, starfive_obj->kvaddr,
++                                  starfive_obj->dma_addr, obj->size,
++                                  starfive_obj->dma_attrs);
++      if (ret) {
++              DRM_ERROR("failed to allocate sgt, %d\n", ret);
++              kfree(sgt);
++              return ERR_PTR(ret);
++      }
++
++      return sgt;
++}
++
++static int
++starfive_drm_gem_dma_map_sg(struct drm_device *drm,
++                          struct dma_buf_attachment *attach,
++                          struct sg_table *sg,
++                          struct starfive_drm_gem_obj *starfive_obj)
++{
++      int err;
++
++      err = dma_map_sgtable(drm->dev, sg, DMA_BIDIRECTIONAL, 0);
++      if (err)
++              return err;
++
++      if (drm_prime_get_contiguous_size(sg) < attach->dmabuf->size) {
++              DRM_ERROR("failed to map sg_table to contiguous linear address.\n");
++              dma_unmap_sgtable(drm->dev, sg, DMA_BIDIRECTIONAL, 0);
++              return -EINVAL;
++      }
++
++      starfive_obj->dma_addr = sg_dma_address(sg->sgl);
++      starfive_obj->sg = sg;
++
++      return 0;
++}
++
++struct drm_gem_object *
++starfive_drm_gem_prime_import_sg_table(struct drm_device *drm,
++                                     struct dma_buf_attachment *attach,
++                                     struct sg_table *sg)
++{
++      struct starfive_drm_gem_obj *starfive_obj;
++      int ret;
++
++      starfive_obj = starfive_drm_gem_alloc_object(drm, attach->dmabuf->size);
++      if (IS_ERR(starfive_obj))
++              return ERR_CAST(starfive_obj);
++
++      ret = starfive_drm_gem_dma_map_sg(drm, attach, sg, starfive_obj);
++      if (ret < 0) {
++              DRM_ERROR("failed to import sg table: %d\n", ret);
++              goto err_free_obj;
++      }
++
++      return &starfive_obj->base;
++
++err_free_obj:
++      starfive_drm_gem_release_object(starfive_obj);
++      return ERR_PTR(ret);
++}
++
++int starfive_drm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
++{
++      struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
++
++      if (starfive_obj->pages) {
++              void *vaddr = vmap(starfive_obj->pages, starfive_obj->num_pages, VM_MAP,
++                                              pgprot_writecombine(PAGE_KERNEL));
++              if (!vaddr)
++                      return -ENOMEM;
++              dma_buf_map_set_vaddr(map, vaddr);
++              return 0;
++      }
++
++      if (starfive_obj->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING)
++              return -ENOMEM;
++
++      dma_buf_map_set_vaddr(map, starfive_obj->kvaddr);
++
++      return 0;
++}
++
++
++void starfive_drm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map)
++{
++      struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
++
++      if (starfive_obj->pages) {
++              vunmap(map->vaddr);
++              return;
++      }
++      /* Nothing to do if allocated by DMA mapping API. */
++}
++
++static const struct drm_gem_object_funcs starfive_gem_object_funcs = {
++      .free           = starfive_drm_gem_free_object,
++      .get_sg_table   = starfive_drm_gem_prime_get_sg_table,
++      .vmap           = starfive_drm_gem_prime_vmap,
++      .vunmap         = starfive_drm_gem_prime_vunmap,
++      .vm_ops         = &drm_gem_cma_vm_ops,
++};
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_gem.h
+@@ -0,0 +1,39 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef _STARFIVE_DRM_GEM_H
++#define _STARFIVE_DRM_GEM_H
++
++#include <drm/drm_gem.h>
++
++struct starfive_drm_gem_obj {
++      struct drm_gem_object   base;
++      //void                  *cookie; //mtk
++      void                    *kvaddr;
++      dma_addr_t              dma_addr;
++      unsigned long           dma_attrs;
++
++      /* Used when IOMMU is enabled */
++      unsigned long           num_pages;
++      struct sg_table         *sg;
++      struct page             **pages;
++};
++#define to_starfive_gem_obj(x)        container_of(x, struct starfive_drm_gem_obj, base)
++
++void starfive_drm_gem_free_object(struct drm_gem_object *obj);
++int starfive_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
++int starfive_drm_gem_mmap_buf(struct drm_gem_object *obj,
++                            struct vm_area_struct *vma);
++int starfive_drm_gem_dumb_create(struct drm_file *file_priv,
++                               struct drm_device *dev,
++                               struct drm_mode_create_dumb *args);
++struct sg_table *starfive_drm_gem_prime_get_sg_table(struct drm_gem_object *obj);
++struct drm_gem_object *
++starfive_drm_gem_prime_import_sg_table(struct drm_device *dev,
++                                     struct dma_buf_attachment *attach,
++                                     struct sg_table *sg);
++int starfive_drm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
++void starfive_drm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
++
++#endif /* _STARFIVE_DRM_GEM_H */
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
+@@ -0,0 +1,520 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/module.h>
++#include <drm/drm_crtc.h>
++#include "starfive_drm_lcdc.h"
++#include "starfive_drm_vpp.h"
++
++static const struct res_name mem_res_name[] = {
++      {"lcdc"},
++      {"vpp0"},
++      {"vpp1"},
++      {"vpp2"},
++      {"clk"},
++      {"rst"},
++      {"sys"}
++};
++
++static u32 sf_fb_clkread32(struct starfive_crtc *sf_crtc, u32 reg)
++{
++      return ioread32(sf_crtc->base_clk + reg);
++}
++
++static void sf_fb_clkwrite32(struct starfive_crtc *sf_crtc, u32 reg, u32 val)
++{
++      iowrite32(val, sf_crtc->base_clk + reg);
++}
++
++static u32 sf_fb_lcdcread32(struct starfive_crtc *sf_crtc, u32 reg)
++{
++      return ioread32(sf_crtc->base_lcdc + reg);
++}
++
++static void sf_fb_lcdcwrite32(struct starfive_crtc *sf_crtc, u32 reg, u32 val)
++{
++      iowrite32(val, sf_crtc->base_lcdc + reg);
++}
++
++static u32 starfive_lcdc_rstread32(struct starfive_crtc *sf_crtc, u32 reg)
++{
++      return ioread32(sf_crtc->base_rst + reg);
++}
++
++static void starfive_lcdc_rstwrite32(struct starfive_crtc *sf_crtc, u32 reg, u32 val)
++{
++      iowrite32(val, sf_crtc->base_rst + reg);
++}
++
++static void lcdc_mode_cfg(struct starfive_crtc *sf_crtc, uint32_t workMode, int dotEdge,
++                      int syncEdge, int r2yBypass, int srcSel, int intSrc, int intFreq)
++{
++      u32 lcdcEn = 0x1;
++      u32 cfg = lcdcEn |
++              workMode << LCDC_WORK_MODE |
++              dotEdge << LCDC_DOTCLK_P |
++              syncEdge << LCDC_HSYNC_P |
++              syncEdge << LCDC_VSYNC_P |
++              0x0 << LCDC_DITHER_EN |
++              r2yBypass << LCDC_R2Y_BPS |
++              srcSel << LCDC_TV_LCD_PATHSEL |
++              intSrc << LCDC_INT_SEL |
++              intFreq << LCDC_INT_FREQ;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_GCTRL, cfg);
++      dev_dbg(sf_crtc->dev, "LCDC WorkMode: 0x%x, LCDC Path: %d\n", workMode, srcSel);
++}
++
++static void lcdc_timing_cfg(struct starfive_crtc *sf_crtc,
++                          struct drm_crtc_state *state, int vunit)
++{
++      int hpw, hbk, hfp, vpw, vbk, vfp;
++      u32 htiming, vtiming, hvwid;
++
++      //h-sync
++      int hsync_len = state->adjusted_mode.crtc_hsync_end -
++              state->adjusted_mode.crtc_hsync_start;
++      //h-bp
++      int left_margin = state->adjusted_mode.crtc_htotal -
++              state->adjusted_mode.crtc_hsync_end;
++      //h-fp
++      int right_margin = state->adjusted_mode.crtc_hsync_start -
++              state->adjusted_mode.crtc_hdisplay;
++      //v-sync
++      int vsync_len = state->adjusted_mode.crtc_vsync_end -
++              state->adjusted_mode.crtc_vsync_start;
++      //v-bp
++      int upper_margin = state->adjusted_mode.crtc_vtotal -
++              state->adjusted_mode.crtc_vsync_end;
++      //v-fp
++      int lower_margin = state->adjusted_mode.crtc_vsync_start -
++              state->adjusted_mode.crtc_vdisplay;
++
++      hpw = hsync_len - 1;
++      hbk = hsync_len + left_margin;
++      hfp = right_margin;
++      vpw = vsync_len - 1;
++      vbk = vsync_len + upper_margin;
++      vfp = lower_margin;
++
++      dev_dbg(sf_crtc->dev, "%s: h-sync = %d, h-bp = %d, h-fp = %d", __func__,
++                      hsync_len, left_margin, right_margin);
++      dev_dbg(sf_crtc->dev, "%s: v-sync = %d, v-bp = %d, v-fp = %d", __func__,
++                      vsync_len, upper_margin, lower_margin);
++
++      htiming = hbk | hfp << LCDC_RGB_HFP;
++      vtiming = vbk | vfp << LCDC_RGB_VFP;
++      hvwid = hpw | vpw << LCDC_RGB_VPW | vunit << LCDC_RGB_UNIT;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_H_TMG, htiming);
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_V_TMG, vtiming);
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_W_TMG, hvwid);
++      dev_dbg(sf_crtc->dev, "LCDC HPW: %d, HBK: %d, HFP: %d\n", hpw, hbk, hfp);
++      dev_dbg(sf_crtc->dev, "LCDC VPW: %d, VBK: %d, VFP: %d\n", vpw, vbk, vfp);
++      dev_dbg(sf_crtc->dev, "LCDC V-Unit: %d, 0-HSYNC and 1-dotClk period\n", vunit);
++}
++
++//? background size
++//lcdc_desize_cfg(sf_dev, sf_dev->display_info.xres-1, sf_dev->display_info.yres-1);
++static void lcdc_desize_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
++{
++      int hsize = state->adjusted_mode.crtc_hdisplay - 1;
++      int vsize = state->adjusted_mode.crtc_vdisplay - 1;
++      u32 sizecfg = hsize | vsize << LCDC_BG_VSIZE;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_BACKGROUD, sizecfg);
++      dev_dbg(sf_crtc->dev, "LCDC Dest H-Size: %d, V-Size: %d\n", hsize, vsize);
++}
++
++static void lcdc_rgb_dclk_cfg(struct starfive_crtc *sf_crtc, int dot_clk_sel)
++{
++      u32 cfg = dot_clk_sel << 16;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_DCLK, cfg);
++      dev_dbg(sf_crtc->dev, "LCDC Dot_clock_output_sel: 0x%x\n", cfg);
++}
++
++// color table
++//win0, no lock transfer
++//win3, no srcSel and addrMode, 0 assigned to them
++//lcdc_win_cfgA(sf_dev, winNum, sf_dev->display_info.xres-1, sf_dev->display_info.yres-1,
++//            0x1, 0x0, 0x0, 0x1, 0x0, 0x0);
++static void lcdc_win_cfgA(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state,
++                        int winNum, int layEn, int clorTab,
++                        int colorEn, int addrMode, int lock)
++{
++      int hsize = state->adjusted_mode.crtc_hdisplay - 1;
++      int vsize = state->adjusted_mode.crtc_vdisplay - 1;
++      int srcSel_v = 1;
++      u32 cfg;
++
++      if (sf_crtc->pp_conn_lcdc < 0)
++              srcSel_v = 0;
++
++      cfg = hsize | vsize << LCDC_WIN_VSIZE | layEn << LCDC_WIN_EN |
++              clorTab << LCDC_CC_EN | colorEn << LCDC_CK_EN |
++              srcSel_v << LCDC_WIN_ISSEL | addrMode << LCDC_WIN_PM |
++              lock << LCDC_WIN_CLK;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_A + winNum * 0xC, cfg);
++      dev_dbg(sf_crtc->dev,
++                      "LCDC Win%d H-Size: %d, V-Size: %d, layEn: %d, Src: %d, AddrMode: %d\n",
++                      winNum, hsize, vsize, layEn, srcSel_v, addrMode);
++}
++
++static void lcdc_win_cfgB(struct starfive_crtc *sf_crtc,
++                        int winNum, int xpos, int ypos, int argbOrd)
++{
++      int win_format = sf_crtc->lcdcfmt;
++      u32 cfg;
++
++#ifdef CONFIG_DRM_STARFIVE_MIPI_DSI
++      argbOrd = 0;
++#else
++      argbOrd = 1;
++#endif
++
++      cfg = xpos |
++              ypos << LCDC_WIN_VPOS |
++              win_format << LCDC_WIN_FMT |
++              argbOrd << LCDC_WIN_ARGB_ORDER;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_B + winNum * 0xC, cfg);
++      dev_dbg(sf_crtc->dev,
++                      "LCDC Win%d Xpos: %d, Ypos: %d, win_format: 0x%x, ARGB Order: 0x%x\n",
++                      winNum, xpos, ypos, win_format, argbOrd);
++}
++
++//? Color key
++static void lcdc_win_cfgC(struct starfive_crtc *sf_crtc, int winNum, int colorKey)
++{
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_C + winNum * 0xC, colorKey);
++      dev_dbg(sf_crtc->dev, "LCDC Win%d Color Key: 0x%6x\n", winNum, colorKey);
++}
++
++//? hsize
++//lcdc_win_srcSize(sf_dev, winNum, sf_dev->display_info.xres-1);
++static void lcdc_win_srcSize(struct starfive_crtc *sf_crtc,
++                           struct drm_crtc_state *state, int winNum)
++{
++      int addr, off, winsize, preCfg, cfg;
++      int hsize = state->adjusted_mode.crtc_hdisplay - 1;
++
++      switch (winNum) {
++      case 0:
++              addr = LCDC_WIN01_HSIZE;
++              off = 0xfffff000;
++              winsize = hsize;
++              break;
++      case 1:
++              addr = LCDC_WIN01_HSIZE;
++              off = 0xff000fff;
++              winsize = hsize << LCDC_IMG_HSIZE;
++              break;
++      case 2:
++              addr = LCDC_WIN23_HSIZE;
++              off = 0xfffff000;
++              winsize = hsize;
++              break;
++      case 3:
++              addr = LCDC_WIN23_HSIZE;
++              off = 0xff000fff;
++              winsize = hsize << LCDC_IMG_HSIZE;
++              break;
++      case 4:
++              addr = LCDC_WIN45_HSIZE;
++              off = 0xfffff000;
++              winsize = hsize;
++              break;
++      case 5:
++              addr = LCDC_WIN45_HSIZE;
++              off = 0xff000fff;
++              winsize = hsize << LCDC_IMG_HSIZE;
++              break;
++      case 6:
++              addr = LCDC_WIN67_HSIZE;
++              off = 0xfffff000;
++              winsize = hsize;
++              break;
++      case 7:
++              addr = LCDC_WIN67_HSIZE;
++              off = 0xff000fff;
++              winsize = hsize << LCDC_IMG_HSIZE;
++              break;
++      default:
++              addr = LCDC_WIN01_HSIZE;
++              off = 0xfffff000;
++              winsize = hsize;
++              break;
++      }
++      preCfg = sf_fb_lcdcread32(sf_crtc, addr) & off;
++      cfg = winsize | preCfg;
++      sf_fb_lcdcwrite32(sf_crtc, addr, cfg);
++      dev_dbg(sf_crtc->dev, "LCDC Win%d Src Hsize: %d\n", winNum, hsize);
++}
++
++static void lcdc_alphaVal_cfg(struct starfive_crtc *sf_crtc,
++                            int val1, int val2, int val3, int val4, int sel)
++{
++      u32 val = val1 |
++              val2 << LCDC_ALPHA2 |
++              val3 << LCDC_ALPHA3 |
++              val4 << LCDC_ALPHA4 |
++              sel << LCDC_01_ALPHA_SEL;
++      u32 preVal = sf_fb_lcdcread32(sf_crtc, LCDC_ALPHA_VALUE) & 0xfffb0000U;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_ALPHA_VALUE, preVal | val);
++      dev_dbg(sf_crtc->dev, "LCDC Alpha 1: %x, 2: %x, 3: %x, 4: %x\n", val1, val2, val3, val4);
++}
++
++static void lcdc_panel_cfg(struct starfive_crtc *sf_crtc,
++                         int buswid, int depth, int txcycle, int pixpcycle,
++                         int rgb565sel, int rgb888sel)
++{
++      u32 cfg = buswid |
++              depth << LCDC_COLOR_DEP |
++              txcycle << LCDC_TCYCLES |
++              pixpcycle << LCDC_PIXELS |
++              rgb565sel << LCDC_565RGB_SEL |
++              rgb888sel << LCDC_888RGB_SEL;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_PANELDATAFMT, cfg);
++      dev_dbg(sf_crtc->dev, "LCDC bus bit: :%d, pixDep: 0x%x, txCyle: %d, %dpix/cycle, RGB565 2cycle_%d, RGB888 3cycle_%d\n",
++              buswid, depth, txcycle, pixpcycle, rgb565sel, rgb888sel);
++}
++
++//winNum: 0-2
++static void lcdc_win02Addr_cfg(struct starfive_crtc *sf_crtc, int addr0, int addr1)
++{
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR0 + sf_crtc->winNum * 0x8, addr0);
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR1 + sf_crtc->winNum * 0x8, addr1);
++      dev_dbg(sf_crtc->dev, "LCDC Win%d Start Addr0: 0x%8x, Addr1: 0x%8x\n",
++                      sf_crtc->winNum, addr0, addr1);
++}
++
++void starfive_set_win_addr(struct starfive_crtc *sf_crtc, int addr)
++{
++      lcdc_win02Addr_cfg(sf_crtc, addr, 0x0);
++}
++
++void lcdc_enable_intr(struct starfive_crtc *sf_crtc)
++{
++      u32 cfg = ~(1U << LCDC_OUT_FRAME_END);
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, cfg);
++}
++
++void lcdc_disable_intr(struct starfive_crtc *sf_crtc)
++{
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, 0xff);
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_CLR, 0xff);
++}
++
++int lcdc_win_sel(struct starfive_crtc *sf_crtc, enum lcdc_in_mode sel)
++{
++      int winNum;
++
++      switch (sel) {
++      case LCDC_IN_LCD_AXI:
++              winNum = LCDC_WIN_0;
++              break;
++      case LCDC_IN_VPP2:
++              winNum = LCDC_WIN_0;
++              break;
++      case LCDC_IN_VPP1:
++              winNum = LCDC_WIN_2;
++              break;
++      case LCDC_IN_VPP0:
++              winNum = LCDC_WIN_1;
++              //mapconv_pp0_sel(sf_dev, 0x0);
++              break;
++      case LCDC_IN_MAPCONVERT:
++              winNum = LCDC_WIN_1;
++              //mapconv_pp0_sel(sf_dev, 0x1);
++              break;
++      default:
++              winNum = 2;
++      }
++
++      return winNum;
++}
++
++void lcdc_dsi_sel(struct starfive_crtc *sf_crtc)
++{
++      int temp;
++      u32 lcdcEn = 0x1;
++      u32 workMode = 0x1;
++      u32 cfg = lcdcEn | workMode << LCDC_WORK_MODE;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_GCTRL, cfg);
++      temp = starfive_lcdc_rstread32(sf_crtc, SRST_ASSERT0);
++      temp &= ~(0x1<<BIT_RST_DSI_DPI_PIX);
++      starfive_lcdc_rstwrite32(sf_crtc, SRST_ASSERT0, temp);
++}
++
++irqreturn_t lcdc_isr_handler(int this_irq, void *dev_id)
++{
++      struct starfive_crtc *sf_crtc = dev_id;
++      //u32 intr_status = sf_fb_lcdcread32(sf_crtc, LCDC_INT_STATUS);
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_CLR, 0xffffffff);
++
++      return IRQ_HANDLED;
++}
++
++void lcdc_int_cfg(struct starfive_crtc *sf_crtc, int mask)
++{
++      u32 cfg;
++
++      if (mask == 0x1)
++              cfg = 0xffffffff;
++      else
++              cfg = ~(1U << LCDC_OUT_FRAME_END); //only frame end interrupt mask
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, cfg);
++}
++
++void lcdc_config(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, int winNum)
++{
++      lcdc_mode_cfg(sf_crtc, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0);
++      lcdc_timing_cfg(sf_crtc, state, 0);
++      lcdc_desize_cfg(sf_crtc, state);
++      lcdc_rgb_dclk_cfg(sf_crtc, 0x1);
++
++      if (sf_crtc->pp_conn_lcdc < 0) //ddr->lcdc
++              lcdc_win02Addr_cfg(sf_crtc, sf_crtc->dma_addr, 0x0);
++
++      lcdc_win_cfgA(sf_crtc, state, winNum, 0x1, 0x0, 0x0, 0x0, 0x0);
++      lcdc_win_cfgB(sf_crtc, winNum, 0x0, 0x0, 0x0);
++      lcdc_win_cfgC(sf_crtc, winNum, 0xffffff);
++
++      lcdc_win_srcSize(sf_crtc, state, winNum);
++      lcdc_alphaVal_cfg(sf_crtc, 0xf, 0xf, 0xf, 0xf, 0x0);
++      lcdc_panel_cfg(sf_crtc, 0x3, 0x4, 0x0, 0x0, 0x0, 0x1);  //rgb888sel?
++}
++
++void lcdc_run(struct starfive_crtc *sf_crtc, uint32_t winMode, uint32_t lcdTrig)
++{
++      u32 runcfg = winMode << LCDC_EN_CFG_MODE | lcdTrig;
++
++      sf_fb_lcdcwrite32(sf_crtc, LCDC_SWITCH, runcfg);
++      dev_dbg(sf_crtc->dev, "Start run LCDC\n");
++}
++
++static int sf_fb_lcdc_clk_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
++{
++      u32 reg_val = 1485000 / state->mode.clock;
++      u32 tmp_val;
++
++      dev_dbg(sf_crtc->dev, "%s: reg_val = %u\n", __func__, reg_val);
++
++      switch (state->adjusted_mode.crtc_hdisplay) {
++      case 640:
++              tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
++              tmp_val &= ~(0x3F);
++              tmp_val |= (59 & 0x3F);
++              sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
++              break;
++      case 840:
++              tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
++              tmp_val &= ~(0x3F);
++              tmp_val |= (54 & 0x3F);
++              sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
++              break;
++      case 1024:
++              tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
++              tmp_val &= ~(0x3F);
++              tmp_val |= (30 & 0x3F);
++              sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
++              break;
++      case 1280:
++              tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
++              tmp_val &= ~(0x3F);
++              tmp_val |= (30 & 0x3F);
++              sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
++              break;
++      case 1440:
++              tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
++              tmp_val &= ~(0x3F);
++              tmp_val |= (30 & 0x3F);
++              sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
++              break;
++      case 1680:
++              tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
++              tmp_val &= ~(0x3F);
++              tmp_val |= (24 & 0x3F); //24 30MHZ
++              sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
++              break;
++      case 1920:
++              tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
++              tmp_val &= ~(0x3F);
++              tmp_val |= (10 & 0x3F); //20 30MHz , 15  40Mhz, 10 60Mhz
++              sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
++              break;
++      case 2048:
++              tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
++              tmp_val &= ~(0x3F);
++              tmp_val |= (10 & 0x3F);
++              sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
++              break;
++      default:
++              tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
++              tmp_val &= ~(0x3F);
++              tmp_val |= (reg_val & 0x3F);
++              sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
++      }
++
++      return 0;
++}
++
++static int sf_fb_lcdc_init(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
++{
++      int pp_id;
++      int lcd_in_pp;
++      int winNum;
++
++      pp_id = sf_crtc->pp_conn_lcdc;
++      if (pp_id < 0) {
++              dev_dbg(sf_crtc->dev, "DDR to LCDC\n");
++              lcd_in_pp = LCDC_IN_LCD_AXI;
++              winNum = lcdc_win_sel(sf_crtc, lcd_in_pp);
++              sf_crtc->winNum = winNum;
++              lcdc_config(sf_crtc, state, winNum);
++      } else {
++              dev_dbg(sf_crtc->dev, "DDR to VPP to LCDC\n");
++              lcd_in_pp = (pp_id == 0) ? LCDC_IN_VPP0 :
++                      ((pp_id == 1) ? LCDC_IN_VPP1 : LCDC_IN_VPP2);
++              winNum = lcdc_win_sel(sf_crtc, lcd_in_pp);
++              sf_crtc->winNum = winNum;
++              lcdc_config(sf_crtc, state, winNum);
++      }
++
++      return 0;
++}
++
++int starfive_lcdc_enable(struct starfive_crtc *sf_crtc)
++{
++      struct drm_crtc_state *state = sf_crtc->crtc.state;
++
++      lcdc_disable_intr(sf_crtc);
++
++      if (sf_fb_lcdc_clk_cfg(sf_crtc, state)) {
++              dev_err(sf_crtc->dev, "lcdc clock configure fail\n");
++              return -EINVAL;
++      }
++
++      if (sf_fb_lcdc_init(sf_crtc, state)) {
++              dev_err(sf_crtc->dev, "lcdc init fail\n");
++              return -EINVAL;
++      }
++
++      lcdc_run(sf_crtc, sf_crtc->winNum, LCDC_RUN);
++      lcdc_enable_intr(sf_crtc);
++
++      return 0;
++}
++
++MODULE_AUTHOR("StarFive Technology Co., Ltd.");
++MODULE_DESCRIPTION("loadable LCDC driver for StarFive");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_lcdc.h
+@@ -0,0 +1,160 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef __SF_FB_LCDC_H__
++#define __SF_FB_LCDC_H__
++
++#include "starfive_drm_crtc.h"
++
++enum lcdc_in_mode {
++      LCDC_IN_LCD_AXI = 0,
++      LCDC_IN_VPP2,
++      LCDC_IN_VPP1,
++      LCDC_IN_VPP0,
++      LCDC_IN_MAPCONVERT,
++};
++
++enum lcdc_win_num {
++      LCDC_WIN_0 = 0,
++      LCDC_WIN_1,
++      LCDC_WIN_2,
++      LCDC_WIN_3,
++      LCDC_WIN_4,
++      LCDC_WIN_5,
++};
++
++enum WIN_FMT {
++      WIN_FMT_RGB565 = 4,
++      WIN_FMT_xRGB1555,
++      WIN_FMT_xRGB4444,
++      WIN_FMT_xRGB8888,
++};
++
++#define LCDC_STOP     0
++#define LCDC_RUN      1
++
++//lcdc registers
++#define LCDC_SWITCH           0x0000
++#define LCDC_GCTRL            0x0004
++#define LCDC_INT_STATUS               0x0008
++#define LCDC_INT_MSK          0x000C
++#define LCDC_INT_CLR          0x0010
++#define LCDC_RGB_H_TMG                0x0014
++#define LCDC_RGB_V_TMG                0x0018
++#define LCDC_RGB_W_TMG                0x001C
++#define LCDC_RGB_DCLK         0x0020
++#define LCDC_M_CS_CTRL                0x0024
++#define LCDC_DeltaRGB_CFG     0x0028
++#define LCDC_BACKGROUD                0x002C
++#define LCDC_WIN0_CFG_A               0x0030
++#define LCDC_WIN0_CFG_B               0x0034
++#define LCDC_WIN0_CFG_C               0x0038
++#define LCDC_WIN1_CFG_A               0x003C
++#define LCDC_WIN1_CFG_B               0x0040
++#define LCDC_WIN1_CFG_C               0x0044
++#define LCDC_WIN2_CFG_A               0x0048
++#define LCDC_WIN2_CFG_B               0x004C
++#define LCDC_WIN2_CFG_C               0x0050
++#define LCDC_WIN3_CFG_A               0x0054
++#define LCDC_WIN3_CFG_B               0x0058
++#define LCDC_WIN3_CFG_C               0x005C
++#define LCDC_WIN01_HSIZE      0x0090
++#define LCDC_WIN23_HSIZE      0x0094
++#define LCDC_WIN45_HSIZE      0x0098
++#define LCDC_WIN67_HSIZE      0x009C
++#define LCDC_ALPHA_VALUE      0x00A0
++#define LCDC_PANELDATAFMT     0x00A4
++#define LCDC_WIN0STARTADDR0   0x00B8
++#define LCDC_WIN0STARTADDR1   0x00BC
++
++/* Definition controller bit for LCDC registers */
++//for LCDC_SWITCH
++#define LCDC_DTRANS_SWITCH            0
++#define LCDC_MPU_START                        1
++#define LCDC_EN_CFG_MODE              2
++//for LCDC_GCTRL
++#define LCDC_EN                               0
++#define LCDC_WORK_MODE                        1
++#define LCDC_A0_P                     4
++#define LCDC_ENABLE_P                 5
++#define LCDC_DOTCLK_P                 6
++#define LCDC_HSYNC_P                  7
++#define LCDC_VSYNC_P                  8
++#define LCDC_DITHER_EN                        9
++#define LCDC_R2Y_BPS                  10
++#define LCDC_MS_SEL                   11
++#define LCDC_TV_LCD_PATHSEL           12
++#define LCDC_INTERLACE                        13
++#define LCDC_CBCR_ORDER                       14
++#define LCDC_INT_SEL                  15
++#define LCDC_INT_FREQ                 24
++//for LCDC_INT_MSK
++#define LCDC_OUT_FRAME_END            5
++//for RGB_H_TMG,RGB_V_TMG,RGB_W_TMG
++#define LCDC_RGB_HBK                  0
++#define LCDC_RGB_HFP                  16
++#define LCDC_RGB_VBK                  0
++#define LCDC_RGB_VFP                  16
++#define LCDC_RGB_HPW                  0
++#define LCDC_RGB_VPW                  8
++#define LCDC_RGB_UNIT                 16
++//for BACKGROUD
++#define LCDC_BG_HSIZE                 0
++#define LCDC_BG_VSIZE                 12
++//for WINx_CFG_A/B/C
++#define LCDC_WIN_HSIZE                        0
++#define LCDC_WIN_VSIZE                        12
++#define LCDC_WIN_EN                   24
++#define LCDC_CC_EN                    25
++#define LCDC_CK_EN                    26
++#define LCDC_WIN_ISSEL                        27
++#define LCDC_WIN_PM                   28
++#define LCDC_WIN_CLK                  30
++#define LCDC_WIN_HPOS                 0
++#define LCDC_WIN_VPOS                 12
++#define LCDC_WIN_FMT                  24
++#define LCDC_WIN_ARGB_ORDER           27
++#define LCDC_WIN_CC                   0
++//for WINxx_HSIZE
++#define LCDC_IMG_HSIZE                        12
++//for LCDC_ALPHA_VALUE
++#define LCDC_ALPHA1                   0
++#define LCDC_ALPHA2                   4
++#define LCDC_ALPHA3                   8
++#define LCDC_ALPHA4                   12
++#define LCDC_A_GLBL_ALPHA             16
++#define LCDC_B_GLBL_ALPHA             17
++#define LCDC_01_ALPHA_SEL             18
++//for LCDC_PANELDATAFMT
++#define LCDC_BUS_W                    0
++#define LCDC_TCYCLES                  2
++#define LCDC_COLOR_DEP                        4
++#define LCDC_PIXELS                   7
++#define LCDC_332RGB_SEL                       8
++#define LCDC_444RGB_SEL                       9
++#define LCDC_666RGB_SEL                       12
++#define LCDC_565RGB_SEL                       16
++#define LCDC_888RGB_SEL                       18
++
++//sysrst registers
++#define SRST_ASSERT0          0x00
++#define SRST_STATUS0          0x04
++/* Definition controller bit for syd rst registers */
++#define BIT_RST_DSI_DPI_PIX   17
++
++void lcdc_enable_intr(struct starfive_crtc *sf_crtc);
++void lcdc_disable_intr(struct starfive_crtc *sf_crtc);
++irqreturn_t lcdc_isr_handler(int this_irq, void *dev_id);
++void lcdc_int_cfg(struct starfive_crtc *sf_crtc, int mask);
++void lcdc_config(struct starfive_crtc *sf_crtc,
++               struct drm_crtc_state *old_state,
++               int winNum);
++int lcdc_win_sel(struct starfive_crtc *sf_crtc, enum lcdc_in_mode sel);
++void lcdc_dsi_sel(struct starfive_crtc *sf_crtc);
++void lcdc_run(struct starfive_crtc *sf_crtc,
++            uint32_t winMode, uint32_t lcdTrig);
++void starfive_set_win_addr(struct starfive_crtc *sf_crtc, int addr);
++int starfive_lcdc_enable(struct starfive_crtc *sf_crtc);
++
++#endif
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_plane.c
+@@ -0,0 +1,226 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <drm/drm.h>
++#include <drm/drm_atomic.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_fourcc.h>
++#include <drm/drm_atomic_uapi.h>
++#include <drm/drm_plane_helper.h>
++#include <drm/drm_gem_framebuffer_helper.h>
++#include <drm/drm_gem_atomic_helper.h>
++#include "starfive_drm_crtc.h"
++#include "starfive_drm_plane.h"
++#include "starfive_drm_gem.h"
++#include "starfive_drm_lcdc.h"
++#include "starfive_drm_vpp.h"
++
++static const u32 formats[] = {
++      DRM_FORMAT_RGB565,
++      DRM_FORMAT_UYVY,
++      DRM_FORMAT_VYUY,
++      DRM_FORMAT_YUYV,
++      DRM_FORMAT_YVYU,
++
++      DRM_FORMAT_YUV420,
++      DRM_FORMAT_NV21,
++      DRM_FORMAT_NV12,
++
++      DRM_FORMAT_ARGB8888,
++      DRM_FORMAT_ABGR8888,
++};
++
++static void starfive_plane_destroy(struct drm_plane *plane)
++{
++      drm_plane_cleanup(plane);
++}
++
++static const struct drm_plane_funcs starfive_plane_funcs = {
++      .update_plane = drm_atomic_helper_update_plane,
++      .disable_plane = drm_atomic_helper_disable_plane,
++      .destroy = starfive_plane_destroy,
++      .set_property = NULL,
++      .reset = drm_atomic_helper_plane_reset,
++      .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
++      .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
++};
++
++static void starfive_plane_atomic_disable(struct drm_plane *plane,
++                                        struct drm_atomic_state *old_state)
++{
++}
++
++static int starfive_plane_atomic_check(struct drm_plane *plane,
++                              struct drm_atomic_state *state)
++{
++      struct drm_plane_state *new_plane_state =
++              drm_atomic_get_new_plane_state(state, plane);
++      struct drm_framebuffer *fb = new_plane_state->fb;
++      struct drm_crtc_state *crtc_state;
++
++      if (!fb)
++              return 0;
++
++      if (WARN_ON(!new_plane_state->crtc))
++              return 0;
++
++      /*
++      ret = starfive_drm_plane_check(state->crtc, plane,
++                                     to_starfive_plane_state(state));
++      if (ret)
++              return ret;
++      */
++
++      //crtc_state = drm_atomic_get_crtc_state(new_plane_state->state, new_plane_state->crtc);
++      crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);
++      if (IS_ERR(crtc_state))
++              return PTR_ERR(crtc_state);
++
++      return drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
++                              DRM_PLANE_HELPER_NO_SCALING,
++                              DRM_PLANE_HELPER_NO_SCALING,
++                              true, true);
++}
++
++static void starfive_plane_atomic_update(struct drm_plane *plane,
++                                       struct drm_atomic_state *old_state)
++{
++      struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(old_state,
++                                                                              plane);
++      struct drm_crtc *crtc = new_state->crtc;
++      struct drm_framebuffer *fb = new_state->fb;
++      //struct drm_plane_state *state = plane->state;
++      //struct drm_crtc *crtc = state->crtc;
++      //struct drm_framebuffer *fb = state->fb;
++
++      dma_addr_t dma_addr;
++      struct drm_gem_object *obj;
++      struct starfive_drm_gem_obj *starfive_obj;
++      unsigned int pitch, format;
++
++      struct starfive_crtc *sf_crtc = to_starfive_crtc(crtc);
++
++      if (!crtc || WARN_ON(!fb))
++              return;
++
++      //if (!plane->state->visible) {
++      if (!new_state->visible) {
++              starfive_plane_atomic_disable(plane, old_state);
++              return;
++      }
++
++      obj = fb->obj[0];
++      starfive_obj = to_starfive_gem_obj(obj);
++      dma_addr = starfive_obj->dma_addr;
++      pitch = fb->pitches[0];
++      format = fb->format->format;
++
++      //dma_addr += (plane->state->src.x1 >> 16) * fb->format->cpp[0];
++      //dma_addr += (plane->state->src.y1 >> 16) * pitch;
++      dma_addr += (new_state->src.x1 >> 16) * fb->format->cpp[0];
++      dma_addr += (new_state->src.y1 >> 16) * pitch;
++      if (sf_crtc->ddr_format != format) {
++              sf_crtc->ddr_format = format;
++              sf_crtc->ddr_format_change = true;
++      } else {
++              sf_crtc->ddr_format_change = false;
++      }
++
++      if (sf_crtc->dma_addr != dma_addr) {
++              sf_crtc->dma_addr = dma_addr;
++              sf_crtc->dma_addr_change = true;
++      } else {
++              sf_crtc->dma_addr_change = false;
++      }
++      sf_crtc->size = obj->size;
++}
++
++static int starfive_plane_atomic_async_check(struct drm_plane *plane,
++                              struct drm_atomic_state *state)
++{
++      struct drm_crtc_state *crtc_state;
++      struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
++                                                                               plane);
++
++      if (plane != new_plane_state->crtc->cursor)
++              return -EINVAL;
++
++      if (!plane->state)
++              return -EINVAL;
++
++      if (!plane->state->fb)
++              return -EINVAL;
++
++      //if (new_plane_state->state)
++      //   crtc_state = drm_atomic_get_existing_crtc_state(new_plane_state->state,
++      //                                                 new_plane_state->crtc);
++      //else /* Special case for asynchronous cursor updates. */
++      //  crtc_state = new_plane_state->crtc->state;
++
++      if (state)
++              crtc_state = drm_atomic_get_existing_crtc_state(state,
++                                                              new_plane_state->crtc);
++      else /* Special case for asynchronous cursor updates. */
++              //crtc_state = plane->crtc->state;
++              crtc_state = new_plane_state->crtc->state;
++
++      return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
++                              DRM_PLANE_HELPER_NO_SCALING,
++                              DRM_PLANE_HELPER_NO_SCALING,
++                              true, true);
++}
++
++static void starfive_plane_atomic_async_update(struct drm_plane *plane,
++                                             struct drm_atomic_state *new_state)
++{
++      struct drm_plane_state *new_plane_state =
++              drm_atomic_get_new_plane_state(new_state, plane);
++      struct starfive_crtc *crtcp = to_starfive_crtc(plane->state->crtc);
++
++      plane->state->crtc_x = new_plane_state->crtc_x;
++      plane->state->crtc_y = new_plane_state->crtc_y;
++      plane->state->crtc_h = new_plane_state->crtc_h;
++      plane->state->crtc_w = new_plane_state->crtc_w;
++      plane->state->src_x = new_plane_state->src_x;
++      plane->state->src_y = new_plane_state->src_y;
++      plane->state->src_h = new_plane_state->src_h;
++      plane->state->src_w = new_plane_state->src_w;
++      swap(plane->state->fb, new_plane_state->fb);
++
++      if (crtcp->is_enabled) {
++              starfive_plane_atomic_update(plane, new_state);
++              spin_lock(&crtcp->reg_lock);
++              starfive_crtc_hw_config_simple(crtcp);
++              spin_unlock(&crtcp->reg_lock);
++      }
++}
++
++static const struct drm_plane_helper_funcs starfive_plane_helper_funcs = {
++      .atomic_check = starfive_plane_atomic_check,
++      .atomic_update = starfive_plane_atomic_update,
++      //.prepare_fb = drm_gem_fb_prepare_fb,
++      .prepare_fb = drm_gem_plane_helper_prepare_fb,
++      .atomic_disable = starfive_plane_atomic_disable,
++      .atomic_async_check = starfive_plane_atomic_async_check,
++      .atomic_async_update = starfive_plane_atomic_async_update,
++};
++
++int starfive_plane_init(struct drm_device *dev,
++                      struct starfive_crtc *starfive_crtc,
++                      enum drm_plane_type type)
++{
++      int ret;
++
++      ret = drm_universal_plane_init(dev, starfive_crtc->planes, 0,
++                                     &starfive_plane_funcs, formats,
++                                     ARRAY_SIZE(formats), NULL, type, NULL);
++      if (ret) {
++              dev_err(dev->dev, "failed to initialize plane\n");
++              return ret;
++      }
++
++      drm_plane_helper_add(starfive_crtc->planes, &starfive_plane_helper_funcs);
++
++      return 0;
++}
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_plane.h
+@@ -0,0 +1,12 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef _STARFIVE_DRM_PLANE_H
++#define _STARFIVE_DRM_PLANE_H
++
++int starfive_plane_init(struct drm_device *dev,
++                      struct starfive_crtc *starfive_crtc,
++                      enum drm_plane_type type);
++
++#endif /* _STARFIVE_DRM_PLANE_H */
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.c
+@@ -0,0 +1,822 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#include <linux/module.h>
++#include <linux/delay.h>
++#include "starfive_drm_vpp.h"
++#include "starfive_drm_crtc.h"
++#include <soc/sifive/sifive_l2_cache.h>
++
++static inline void sf_set_clear(void __iomem *addr, u32 reg, u32 set, u32 clear)
++{
++      u32 value = ioread32(addr + reg);
++
++      value &= ~clear;
++      value |= set;
++      iowrite32(value, addr + reg);
++}
++
++static inline void sf_reg_status_wait(void __iomem *addr, u32 reg, u8 offset, u8 value)
++{
++      u32 temp;
++
++      do {
++              temp = ioread32(addr + reg) >> offset;
++              temp &= 0x01;
++      } while (temp != value);
++}
++
++static u32 sf_fb_sysread32(struct starfive_crtc *sf_crtc, u32 reg)
++{
++      return ioread32(sf_crtc->base_syscfg + reg);
++}
++
++static void sf_fb_syswrite32(struct starfive_crtc *sf_crtc, u32 reg, u32 val)
++{
++      iowrite32(val, sf_crtc->base_syscfg + reg);
++}
++
++static u32 sf_fb_vppread32(struct starfive_crtc *sf_crtc, int ppNum, u32 reg)
++{
++      void __iomem *base_vpp;
++
++      switch (ppNum) {
++      case 0:
++              base_vpp = sf_crtc->base_vpp0;
++              break;
++      case 1:
++              base_vpp = sf_crtc->base_vpp1;
++              break;
++      case 2:
++              base_vpp = sf_crtc->base_vpp2;
++              break;
++      default:
++              dev_err(sf_crtc->dev, "Err：invalid vpp Number!\n");
++              return 0;
++      }
++
++      return ioread32(base_vpp + reg);
++}
++
++static void sf_fb_vppwrite32(struct starfive_crtc *sf_crtc, int ppNum, u32 reg, u32 val)
++{
++      void __iomem *base_vpp;
++
++      switch (ppNum) {
++      case 0:
++              base_vpp = sf_crtc->base_vpp0;
++              break;
++      case 1:
++              base_vpp = sf_crtc->base_vpp1;
++              break;
++      case 2:
++              base_vpp = sf_crtc->base_vpp2;
++              break;
++      default:
++              dev_err(sf_crtc->dev, "Err：invalid vpp Number!\n");
++              return;
++      }
++      iowrite32(val, base_vpp + reg);
++}
++
++void mapconv_pp0_sel(struct starfive_crtc *sf_crtc, int sel)
++{
++      u32 temp;
++
++      temp = sf_fb_sysread32(sf_crtc, SYS_MAP_CONV);
++      temp &= ~(0x1);
++      temp |= (sel & 0x1);
++      sf_fb_syswrite32(sf_crtc, SYS_MAP_CONV, temp);
++}
++
++static void pp_output_cfg(struct starfive_crtc *sf_crtc,
++                        int ppNum, int outSel, int progInter, int desformat, int ptMode)
++{
++      int cfg = outSel | progInter << PP_INTERLACE |
++              desformat << PP_DES_FORMAT |
++              ptMode << PP_POINTER_MODE;
++      int preCfg = sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL1) & 0xffff8f0U;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL1, cfg | preCfg);
++      dev_dbg(sf_crtc->dev, "PP%d outSel: %d, outFormat: 0x%x, Out Interlace: %d, ptMode: %d\n",
++                      ppNum, outSel, desformat, progInter, ptMode);
++}
++
++static void pp_srcfmt_cfg(struct starfive_crtc *sf_crtc, int ppNum, int srcformat,
++                        int yuv420Inter, int yuv422_mode, int yuv420_mode, int argbOrd)
++{
++      int cfg = srcformat << PP_SRC_FORMAT_N |
++              yuv420Inter << PP_420_ITLC |
++              yuv422_mode << PP_SRC_422_YUV_POS |
++              yuv420_mode << PP_SRC_420_YUV_POS |
++              argbOrd << PP_SRC_ARGB_ORDER;
++      int preCfg = sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL1) & 0x83ffff0fU;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL1, cfg | preCfg);
++      dev_dbg(sf_crtc->dev, "PP%d Src Format: 0x%x, YUV420 Interlace: %d, YUV422: %d, YUV420: %d, ARGB Order: %d\n",
++                      ppNum, srcformat, yuv420Inter, yuv422_mode, yuv420_mode, argbOrd);
++}
++
++static void pp_r2yscal_bypass(struct starfive_crtc *sf_crtc,
++                            int ppNum, int r2yByp, int scalByp, int y2rByp)
++{
++      int bypass = (r2yByp | scalByp << 1 | y2rByp << 2) << PP_R2Y_BPS;
++      int preCfg = sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL1) & 0xffff8fffU;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL1, bypass | preCfg);
++      dev_dbg(sf_crtc->dev, "PP%d Bypass R2Y: %d, Y2R: %d, MainSacle: %d\n",
++                      ppNum, r2yByp, y2rByp, scalByp);
++}
++
++static void pp_argb_alpha(struct starfive_crtc *sf_crtc, int ppNum, int alpha)
++{
++      int preCfg = sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL1) & 0xff00ffffU;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL1, alpha << PP_ARGB_ALPHA | preCfg);
++      dev_dbg(sf_crtc->dev, "PP%d Alpha: 0x%4x\n", ppNum, alpha);
++}
++
++//rgbNum: 1-3
++static void pp_r2y_coeff(struct starfive_crtc *sf_crtc,
++                       int ppNum, int coefNum, int rcoef, int gcoef, int bcoef, int off)
++{
++      int rgcoeff = rcoef | gcoef << PP_COEF_G1;
++      int bcoefoff = bcoef | off << PP_OFFSET_1;
++      u32 addr1 = (coefNum - 1) * 0x8 + PP_R2Y_COEF1;
++      u32 addr2 = (coefNum - 1) * 0x8 + PP_R2Y_COEF2;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, addr1, rgcoeff);
++      sf_fb_vppwrite32(sf_crtc, ppNum, addr2, bcoefoff);
++      dev_dbg(sf_crtc->dev, "PP%d coefNum: %d, rCoef: 0x%4x, gCoef: 0x%4x, bCoef: 0x%4x, off: 0x%4x\n",
++                      ppNum, coefNum, rcoef, gcoef, bcoef, off);
++}
++
++static void pp_output_fmt_cfg(struct starfive_crtc *sf_crtc,
++                            int ppNum, int yuv420Inter, int yuv422_mode)
++{
++      int preCfg = sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL2) & 0xfffffffeU;
++
++      preCfg = preCfg |
++              yuv420Inter << PP_DES_420_ORDER |
++              yuv422_mode << PP_DES_422_ORDER;
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL2, preCfg);
++      dev_dbg(sf_crtc->dev, "PP%d Lock Transfer: %d\n", ppNum, yuv422_mode);
++}
++
++static void pp_lockTrans_cfg(struct starfive_crtc *sf_crtc, int ppNum, int lockTrans)
++{
++      int preCfg = sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL2) & 0xfffffffeU;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL2, lockTrans | preCfg);
++      dev_dbg(sf_crtc->dev, "PP%d Lock Transfer: %d\n", ppNum, lockTrans);
++}
++
++static void pp_int_interval_cfg(struct starfive_crtc *sf_crtc, int ppNum, int interval)
++{
++      int preCfg = sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL2) & 0xffff00ffU;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL2, interval << PP_INT_INTERVAL | preCfg);
++      dev_dbg(sf_crtc->dev, "PP%d Frame Interrupt interval: %d Frames\n", ppNum, interval);
++}
++
++static void pp_srcSize_cfg(struct starfive_crtc *sf_crtc, int ppNum, int hsize, int vsize)
++{
++      int size = hsize | vsize << PP_SRC_VSIZE;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_SIZE, size);
++      dev_dbg(sf_crtc->dev, "PP%d HSize: %d, VSize: %d\n", ppNum, hsize, vsize);
++}
++
++//0-no drop, 1-1/2, 2-1/4, down to 1/32
++static void pp_drop_cfg(struct starfive_crtc *sf_crtc, int ppNum, int hdrop, int vdrop)
++{
++      int drop = hdrop | vdrop << PP_DROP_VRATION;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_DROP_CTRL, drop);
++      dev_dbg(sf_crtc->dev, "PP%d HDrop: %d, VDrop: %d\n", ppNum, hdrop, vdrop);
++}
++
++static void pp_desSize_cfg(struct starfive_crtc *sf_crtc, int ppNum, int hsize, int vsize)
++{
++      int size = hsize | vsize << PP_DES_VSIZE;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_SIZE, size);
++      dev_dbg(sf_crtc->dev, "PP%d HSize: %d, VSize: %d\n", ppNum, hsize, vsize);
++}
++
++static void pp_desAddr_cfg(struct starfive_crtc *sf_crtc,
++                         int ppNum, int yaddr, int uaddr, int vaddr)
++{
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_Y_SA, yaddr);
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_U_SA, uaddr);
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_V_SA, vaddr);
++      dev_dbg(sf_crtc->dev, "PP%d des-Addr Y: 0x%8x, U: 0x%8x, V: 0x%8x\n",
++                      ppNum, yaddr, uaddr, vaddr);
++}
++
++static void pp_desOffset_cfg(struct starfive_crtc *sf_crtc,
++                           int ppNum, int yoff, int uoff, int voff)
++{
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_Y_OFS, yoff);
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_U_OFS, uoff);
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_V_OFS, voff);
++      dev_dbg(sf_crtc->dev, "PP%d des-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n",
++                      ppNum, yoff, uoff, voff);
++}
++
++void pp_intcfg(struct starfive_crtc *sf_crtc, int ppNum, int intMask)
++{
++      int intcfg = ~(0x1<<0);
++
++      if (intMask)
++              intcfg = 0xf;
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_MASK, intcfg);
++}
++
++//next source frame Y/RGB start address, ?
++void pp_srcAddr_next(struct starfive_crtc *sf_crtc, int ppNum, int ysa, int usa, int vsa)
++{
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_Y_SA_NXT, ysa);
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_U_SA_NXT, usa);
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_V_SA_NXT, vsa);
++      dev_dbg(sf_crtc->dev,
++                      "PP%d next Y startAddr: 0x%8x, U startAddr: 0x%8x, V startAddr: 0x%8x\n",
++                      ppNum, ysa, usa, vsa);
++}
++
++void pp_srcOffset_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yoff, int uoff, int voff)
++{
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_Y_OFS, yoff);
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_U_OFS, uoff);
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_V_OFS, voff);
++      dev_dbg(sf_crtc->dev, "PP%d src-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n",
++                      ppNum, yoff, uoff, voff);
++}
++
++void pp_nxtAddr_load(struct starfive_crtc *sf_crtc, int ppNum, int nxtPar, int nxtPos)
++{
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_LOAD_NXT_PAR, nxtPar | nxtPos);
++      dev_dbg(sf_crtc->dev, "PP%d next addrPointer: %d, %d set Regs\n", ppNum, nxtPar, nxtPos);
++}
++
++void pp_run(struct starfive_crtc *sf_crtc, int ppNum, int start)
++{
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_SWITCH, start);
++      //if (start)
++      //      dev_dbg(sf_crtc->dev, "Now start the PP%d\n\n", ppNum);
++}
++
++void pp1_enable_intr(struct starfive_crtc *sf_crtc)
++{
++      sf_fb_vppwrite32(sf_crtc, 1, PP_INT_MASK, 0x0);
++}
++
++void pp_enable_intr(struct starfive_crtc *sf_crtc, int ppNum)
++{
++      u32 cfg = 0xfffe;
++
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_MASK, cfg);
++}
++
++void pp_disable_intr(struct starfive_crtc *sf_crtc, int ppNum)
++{
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_MASK, 0xf);
++      sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_CLR, 0xf);
++}
++
++static void pp_srcfmt_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *src)
++{
++      switch (src->format) {
++      case COLOR_YUV422_YVYU:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_YVYU, 0x0, 0x0);
++              break;
++      case COLOR_YUV422_VYUY:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_VYUY, 0x0, 0x0);
++              break;
++      case COLOR_YUV422_YUYV:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_YUYV, 0x0, 0x0);
++              break;
++      case COLOR_YUV422_UYVY:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_UYVY, 0x0, 0x0);
++              break;
++      case COLOR_YUV420P:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420P, 0x0, 0, 0x0, 0x0);
++              break;
++      case COLOR_YUV420_NV21:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420I, 0x1, 0,
++                              COLOR_YUV420_NV21 - COLOR_YUV420_NV21, 0x0);
++              break;
++      case COLOR_YUV420_NV12:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420I, 0x1, 0,
++                              COLOR_YUV420_NV12 - COLOR_YUV420_NV21, 0x0);
++              break;
++      case COLOR_RGB888_ARGB:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0,
++                              0x0, COLOR_RGB888_ARGB - COLOR_RGB888_ARGB);
++              break;
++      case COLOR_RGB888_ABGR:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0,
++                              0x0, COLOR_RGB888_ABGR-COLOR_RGB888_ARGB);
++              break;
++      case COLOR_RGB888_RGBA:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0,
++                              0x0, COLOR_RGB888_RGBA-COLOR_RGB888_ARGB);
++              break;
++      case COLOR_RGB888_BGRA:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0,
++                              0x0, COLOR_RGB888_BGRA-COLOR_RGB888_ARGB);
++              break;
++      case COLOR_RGB565:
++              pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_RGB565, 0x0, 0x0, 0x0, 0x0);
++              break;
++      }
++}
++
++static void pp_dstfmt_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *dst)
++{
++      unsigned int outsel = 1;
++
++      if (dst->addr)
++              outsel = 0;
++
++      switch (dst->format) {
++      case COLOR_YUV422_YVYU:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
++              break;
++      case COLOR_YUV422_VYUY:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_VYUY);
++              break;
++      case COLOR_YUV422_YUYV:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YUYV);
++              break;
++      case COLOR_YUV422_UYVY:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
++              break;
++      case COLOR_YUV420P:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420P, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
++              break;
++      case COLOR_YUV420_NV21:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420I, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, COLOR_YUV420_NV21 - COLOR_YUV420_NV21, 0);
++              break;
++      case COLOR_YUV420_NV12:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420I, 0x0);///0x2, 0x0);
++              //pp_output_fmt_cfg(ppNum, COLOR_YUV420_NV12 - COLOR_YUV420_NV21, 0);
++              break;
++      case COLOR_RGB888_ARGB:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_ARGB888, 0x0);
++              //pp_output_fmt_cfg(ppNum, 0, 0);
++              break;
++      case COLOR_RGB888_ABGR:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_ABGR888, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
++              break;
++      case COLOR_RGB888_RGBA:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_RGBA888, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
++              break;
++      case COLOR_RGB888_BGRA:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_BGRA888, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
++              break;
++      case COLOR_RGB565:
++              pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_RGB565, 0x0);
++              pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
++              break;
++      }
++}
++
++static void pp_format_set(struct starfive_crtc *sf_crtc, int ppNum,
++                 struct pp_video_mode *src, struct pp_video_mode *dst)
++{
++      /* 1:bypass, 0:not bypass */
++      unsigned int scale_byp = 1;
++
++      pp_srcfmt_set(sf_crtc, ppNum, src);
++      pp_dstfmt_set(sf_crtc, ppNum, dst);
++
++      if (src->height != dst->height || src->width != dst->width)
++              scale_byp = 0;
++
++      if (src->format >= COLOR_RGB888_ARGB && dst->format <= COLOR_YUV420_NV12) {
++              /* rgb -> yuv-420 */
++              pp_r2yscal_bypass(sf_crtc, ppNum, NOT_BYPASS, scale_byp, BYPASS);
++              pp_r2y_coeff(sf_crtc, ppNum, 1, R2Y_COEF_R1, R2Y_COEF_G1, R2Y_COEF_B1, R2Y_OFFSET1);
++              pp_r2y_coeff(sf_crtc, ppNum, 2, R2Y_COEF_R2, R2Y_COEF_G2, R2Y_COEF_B2, R2Y_OFFSET2);
++              pp_r2y_coeff(sf_crtc, ppNum, 3, R2Y_COEF_R3, R2Y_COEF_G3, R2Y_COEF_B3, R2Y_OFFSET3);
++      } else if (src->format <= COLOR_YUV420_NV12 && dst->format >= COLOR_RGB888_ARGB) {
++              /* yuv-420 -> rgb */
++              pp_r2yscal_bypass(sf_crtc, ppNum, BYPASS, scale_byp, NOT_BYPASS);
++      } else if (src->format <= COLOR_YUV422_YVYU && dst->format <= COLOR_YUV420_NV12) {
++              /* yuv422 -> yuv420 */
++              pp_r2yscal_bypass(sf_crtc, ppNum, BYPASS, scale_byp, BYPASS);
++      } else {
++              /* rgb565->argb888 */
++              pp_r2yscal_bypass(sf_crtc, ppNum, BYPASS, scale_byp, BYPASS);
++      } //else if ((src->format >= COLOR_RGB888_ARGB) && (dst->format >= COLOR_RGB888_ARGB)) {
++              /* rgb -> rgb */
++              // pp_r2yscal_bypass(ppNum, BYPASS, scale_byp, BYPASS);
++      //}
++      pp_argb_alpha(sf_crtc, ppNum, 0xff);
++
++      if (dst->addr)
++              pp_lockTrans_cfg(sf_crtc, ppNum, SYS_BUS_OUTPUT);
++      else
++              pp_lockTrans_cfg(sf_crtc, ppNum, FIFO_OUTPUT);
++
++      pp_int_interval_cfg(sf_crtc, ppNum, 0x1);
++}
++
++static void pp_size_set(struct starfive_crtc *sf_crtc, int ppNum,
++                      struct pp_video_mode *src, struct pp_video_mode *dst)
++{
++      u32 srcAddr, dstaddr;
++      unsigned int size, y_rgb_ofst, uofst;
++      unsigned int v_uvofst = 0, next_y_rgb_addr = 0, next_u_addr = 0, next_v_addr = 0;
++      unsigned int i = 0;
++
++      pp_srcSize_cfg(sf_crtc, ppNum, src->width - 1, src->height - 1);
++      pp_drop_cfg(sf_crtc, ppNum, 0x0, 0x0);///0:no drop
++      pp_desSize_cfg(sf_crtc, ppNum, dst->width - 1, dst->height - 1);
++
++      srcAddr = src->addr + (i<<30); //PP_SRC_BASE_ADDR + (i<<30);
++      size = src->width * src->height;
++
++      if (src->format >= COLOR_RGB888_ARGB) {
++              next_y_rgb_addr = srcAddr;
++              next_u_addr = 0;
++              next_v_addr = 0;
++
++              y_rgb_ofst = 0;
++              uofst = 0;
++              v_uvofst = 0;
++              //pp_srcAddr_next(ppNum, srcAddr, 0, 0);
++              //pp_srcOffset_cfg(ppNum, 0x0, 0x0, 0x0);
++      } else {
++              if (src->format == COLOR_YUV420_NV21) {    //ok
++                      next_y_rgb_addr = srcAddr;
++                      next_u_addr = srcAddr+size+1;
++                      next_v_addr = srcAddr+size;
++                      y_rgb_ofst = 0;
++                      uofst = 0;
++                      v_uvofst = size;
++              } else if (src->format == COLOR_YUV420_NV12) {
++                      next_y_rgb_addr = srcAddr;
++                      next_u_addr = srcAddr+size;
++                      next_v_addr = srcAddr+size+1;
++                      y_rgb_ofst = 0;
++                      uofst = 0;
++                      v_uvofst = size;
++              } else if (src->format == COLOR_YUV420P) {
++                      next_y_rgb_addr = srcAddr;
++                      next_u_addr = srcAddr+size;
++                      next_v_addr = srcAddr+size*5/4;
++                      y_rgb_ofst = 0;
++                      uofst = 0;
++                      v_uvofst = 0;
++              } else if (src->format == COLOR_YUV422_YVYU) {   //ok
++                      next_y_rgb_addr = srcAddr;
++                      next_u_addr = srcAddr+1;
++                      next_v_addr = srcAddr+3;
++                      y_rgb_ofst = 0;
++                      uofst = 0;
++                      v_uvofst = 0;
++              } else if (src->format == COLOR_YUV422_VYUY) {   //ok
++                      next_y_rgb_addr = srcAddr+1;
++                      next_u_addr = srcAddr+2;
++                      next_v_addr = srcAddr;
++                      y_rgb_ofst = 0;
++                      uofst = 0;
++                      v_uvofst = 0;
++              } else if (src->format == COLOR_YUV422_YUYV) {   //ok
++                      next_y_rgb_addr = srcAddr;
++                      next_u_addr = srcAddr+1;
++                      next_v_addr = srcAddr+2;
++                      y_rgb_ofst = 0;
++                      uofst = 0;
++                      v_uvofst = 0;
++              } else if (src->format == COLOR_YUV422_UYVY) {  //ok
++                      next_y_rgb_addr = srcAddr+1;
++                      next_u_addr = srcAddr;
++                      next_v_addr = srcAddr+2;
++                      y_rgb_ofst = 0;
++                      uofst = 0;
++                      v_uvofst = 0;
++              }
++      }
++      pp_srcAddr_next(sf_crtc, ppNum, next_y_rgb_addr, next_u_addr, next_v_addr);
++      pp_srcOffset_cfg(sf_crtc, ppNum, y_rgb_ofst, uofst, v_uvofst);
++      /* source addr not change */
++      pp_nxtAddr_load(sf_crtc, ppNum, 0x1, (i & 0x1));
++
++      if (dst->addr) {
++              dstaddr = dst->addr;
++              size = dst->height*dst->width;
++              if (dst->format >= COLOR_RGB888_ARGB) {
++                      next_y_rgb_addr = dstaddr;
++                      next_u_addr = 0;
++                      next_v_addr = 0;
++                      y_rgb_ofst = 0;
++                      uofst = 0;
++                      v_uvofst = 0;
++              } else {
++                      if (dst->format == COLOR_YUV420_NV21) {
++                              /* yyyyvuvuvu */
++                              next_y_rgb_addr = dstaddr;
++                              next_u_addr = dstaddr+size;
++                              next_v_addr = 0;//dstaddr+size;
++                              y_rgb_ofst = 0;
++                              uofst = 0;
++                              v_uvofst = 0;
++                      } else if (dst->format == COLOR_YUV420_NV12) {
++                              /* yyyyuvuvuv */
++                              next_y_rgb_addr = dstaddr;
++                              next_u_addr = dstaddr+size;
++                              next_v_addr = dstaddr+size+1;
++                              y_rgb_ofst = 0;
++                              uofst = size;
++                              v_uvofst = 0;
++                      } else if (dst->format == COLOR_YUV420P) {
++                              next_y_rgb_addr = dstaddr;
++                              next_u_addr = dstaddr+size;
++                              next_v_addr = dstaddr+size*5/4;
++                              y_rgb_ofst = 0;
++                              uofst = 0;
++                              v_uvofst = 0;
++                      } else if (dst->format == COLOR_YUV422_YVYU) {
++                              next_y_rgb_addr = dstaddr;
++                              next_u_addr = dstaddr+1;
++                              next_v_addr = dstaddr+3;
++                              y_rgb_ofst = 0;
++                              uofst = 0;
++                              v_uvofst = 0;
++                      } else if (dst->format == COLOR_YUV422_VYUY) {
++                              next_y_rgb_addr = dstaddr+1;
++                              next_u_addr = dstaddr+2;
++                              next_v_addr = dstaddr;
++                              y_rgb_ofst = 0;
++                              uofst = 0;
++                              v_uvofst = 0;
++                      } else if (dst->format == COLOR_YUV422_YUYV) {
++                              next_y_rgb_addr = dstaddr;
++                              next_u_addr = dstaddr+1;
++                              next_v_addr = dstaddr+2;
++                              y_rgb_ofst = 0;
++                              uofst = 0;
++                              v_uvofst = 0;
++                      } else if (dst->format == COLOR_YUV422_UYVY) {
++                              next_y_rgb_addr = dstaddr+1;
++                              next_u_addr = dstaddr;
++                              next_v_addr = dstaddr+2;
++                              y_rgb_ofst = 0;
++                              uofst = 0;
++                              v_uvofst = 0;
++                      }
++              }
++              pp_desAddr_cfg(sf_crtc, ppNum, next_y_rgb_addr, next_u_addr, next_v_addr);
++              pp_desOffset_cfg(sf_crtc, ppNum, y_rgb_ofst, uofst, v_uvofst);
++      }
++}
++
++static void pp_config(struct starfive_crtc *sf_crtc, int ppNum,
++                    struct pp_video_mode *src, struct pp_video_mode *dst)
++{
++      //pp_disable_intr(sf_dev, ppNum);
++      pp_format_set(sf_crtc, ppNum, src, dst);
++      pp_size_set(sf_crtc, ppNum, src, dst);
++}
++
++irqreturn_t vpp1_isr_handler(int this_irq, void *dev_id)
++{
++      struct starfive_crtc *sf_crtc = dev_id;
++      u32 intr_status = 0;
++
++      intr_status = sf_fb_vppread32(sf_crtc, 1, PP_INT_STATUS);
++      sf_fb_vppwrite32(sf_crtc, 1, PP_INT_CLR, 0xf);
++      sifive_l2_flush64_range(sf_crtc->dma_addr, sf_crtc->size);
++
++      return IRQ_HANDLED;
++}
++
++static void starfive_pp_enable_intr(struct starfive_crtc *sf_crtc, int enable)
++{
++      int pp_id;
++
++      for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
++              if (sf_crtc->pp[pp_id].inited == 1) {
++                      if (enable)
++                              pp_enable_intr(sf_crtc, pp_id);
++                      else
++                              pp_disable_intr(sf_crtc, pp_id);
++              }
++      }
++}
++
++static int starfive_pp_video_mode_init(struct starfive_crtc *sf_crtc,
++                                     struct pp_video_mode *src,
++                                     struct pp_video_mode *dst,
++                                     int pp_id)
++{
++      if (!src || !dst) {
++              dev_err(sf_crtc->dev, "Invalid argument!\n");
++              return -EINVAL;
++      }
++
++      if (pp_id < PP_NUM && pp_id >= 0) {
++              src->format = sf_crtc->vpp_format;
++              src->width = sf_crtc->crtc.state->adjusted_mode.hdisplay;
++              src->height = sf_crtc->crtc.state->adjusted_mode.vdisplay;
++              src->addr = sf_crtc->dma_addr;
++              //src->addr = 0xa0000000;
++              dst->format = sf_crtc->pp[pp_id].dst.format;
++              dst->width = sf_crtc->crtc.state->adjusted_mode.hdisplay;
++              dst->height = sf_crtc->crtc.state->adjusted_mode.vdisplay;
++              if (sf_crtc->pp[pp_id].bus_out) /*out to ddr*/
++                      dst->addr = 0xfc000000;
++              else if (sf_crtc->pp[pp_id].fifo_out) /*out to lcdc*/
++                      dst->addr = 0;
++      } else {
++              dev_err(sf_crtc->dev, "pp_id %d is not support\n", pp_id);
++              return -EINVAL;
++      }
++
++      return 0;
++}
++
++static int starfive_pp_init(struct starfive_crtc *sf_crtc)
++{
++      int pp_id;
++      int ret = 0;
++      struct pp_video_mode src, dst;
++
++      for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
++              if (sf_crtc->pp[pp_id].inited == 1) {
++                      ret = starfive_pp_video_mode_init(sf_crtc, &src, &dst, pp_id);
++                      if (!ret)
++                              pp_config(sf_crtc, pp_id, &src, &dst);
++              }
++      }
++
++      return ret;
++}
++
++static int starfive_pp_run(struct starfive_crtc *sf_crtc)
++{
++      int pp_id;
++      int ret = 0;
++
++      for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
++              if (sf_crtc->pp[pp_id].inited == 1)
++                      pp_run(sf_crtc, pp_id, PP_RUN);
++      }
++
++      return ret;
++}
++
++int starfive_pp_enable(struct starfive_crtc *sf_crtc)
++{
++      starfive_pp_enable_intr(sf_crtc, PP_INTR_DISABLE);
++
++      if (starfive_pp_init(sf_crtc))
++              return -ENODEV;
++
++      starfive_pp_run(sf_crtc);
++      starfive_pp_enable_intr(sf_crtc, PP_INTR_ENABLE);
++
++      return 0;
++}
++
++int starfive_pp_update(struct starfive_crtc *sf_crtc)
++{
++      int pp_id;
++      int ret = 0;
++      struct pp_video_mode src, dst;
++
++      for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
++              if (sf_crtc->pp[pp_id].inited == 1) {
++                      ret = starfive_pp_video_mode_init(sf_crtc, &src, &dst, pp_id);
++                      if (!ret) {
++                              if (sf_crtc->ddr_format_change)
++                                      pp_format_set(sf_crtc, pp_id, &src, &dst);
++
++                              if (sf_crtc->dma_addr_change)
++                                      pp_size_set(sf_crtc, pp_id, &src, &dst);
++                      }
++              }
++      }
++
++      return 0;
++}
++
++int starfive_pp_get_2lcdc_id(struct starfive_crtc *sf_crtc)
++{
++      int pp_id;
++
++      for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
++              if (sf_crtc->pp[pp_id].inited == 1) {
++                      if (sf_crtc->pp[pp_id].fifo_out == 1 && !sf_crtc->pp[pp_id].bus_out)
++                              return pp_id;
++              }
++      }
++
++      if (pp_id == PP_NUM - 1)
++              dev_warn(sf_crtc->dev, "NO pp connect to LCDC\n");
++
++      return -ENODEV;
++}
++
++void dsitx_vout_init(struct starfive_crtc *sf_crtc)
++{
++      u32 temp;
++
++      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(23), BIT(23));
++      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 0);
++      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(24), BIT(24));
++      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 0);
++      sf_set_clear(sf_crtc->topclk, clk_disp_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->topclk, clk_vout_src_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(23));
++      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 1);
++      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(24));
++      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 1);
++      sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, BIT(31), BIT(31));
++
++      sf_set_clear(sf_crtc->base_rst, vout_rstgen_assert0_REG, ~0x1981ec, 0x1981ec);
++
++      do {
++              temp = ioread32(sf_crtc->base_rst + vout_rstgen_status0_REG);
++              temp &= 0x1981ec;
++      } while (temp != 0x1981ec);
++}
++
++void vout_reset(struct starfive_crtc *sf_crtc)
++{
++      u32 temp;
++
++      iowrite32(0xFFFFFFFF, sf_crtc->base_rst);
++
++      sf_set_clear(sf_crtc->topclk, clk_disp_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->topclk, clk_vout_src_ctrl_REG, BIT(31), BIT(31));
++
++      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(23));
++      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 1);
++
++      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(24));
++      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 1);
++
++      sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_mapconv_apb_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_mapconv_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_pixrawout_apb_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_pixrawout_axi_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_apb_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_pixclk_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, BIT(31), BIT(31));
++      sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, BIT(31), BIT(31));
++
++      sf_set_clear(sf_crtc->base_rst, vout_rstgen_assert0_REG, ~0x19bfff, 0x19bfff);
++      do {
++              temp = ioread32(sf_crtc->base_rst + vout_rstgen_status0_REG);
++              temp &= 0x19bfff;
++      } while (temp != 0x19bfff);
++}
++
++void vout_disable(struct starfive_crtc *sf_crtc)
++{
++      iowrite32(0xFFFFFFFF, sf_crtc->base_rst);
++
++      sf_set_clear(sf_crtc->topclk, clk_disp_axi_ctrl_REG, 0, BIT(31));
++      sf_set_clear(sf_crtc->topclk, clk_vout_src_ctrl_REG, 0, BIT(31));
++
++      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(23), BIT(23));
++      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 0);
++
++      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(24), BIT(24));
++      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 0);
++}
++
++MODULE_AUTHOR("StarFive Technology Co., Ltd.");
++MODULE_DESCRIPTION("loadable VPP driver for StarFive");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.h
+@@ -0,0 +1,213 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ */
++#ifndef __SF_FB_VPP_H__
++#define __SF_FB_VPP_H__
++
++#include "starfive_drm_crtc.h"
++
++#define PP_ID_0       0
++#define PP_ID_1       1
++#define PP_ID_2       2
++
++#define PP_NUM        3
++
++#define PP_STOP       0
++#define PP_RUN        1
++
++#define PP_INTR_ENABLE        1
++#define PP_INTR_DISABLE       0
++//PP coefficients
++#define R2Y_COEF_R1   77
++#define R2Y_COEF_G1   150
++#define R2Y_COEF_B1   29
++#define R2Y_OFFSET1   0
++#define R2Y_COEF_R2   (0x400|43)
++#define R2Y_COEF_G2   (0x400|85)
++#define R2Y_COEF_B2   128
++#define R2Y_OFFSET2   128
++#define R2Y_COEF_R3   128
++#define R2Y_COEF_G3   (0x400|107)
++#define R2Y_COEF_B3   (0x400|21)
++#define R2Y_OFFSET3   128
++
++//sys registers
++#define SYS_CONF_LCDC         0x00
++#define SYS_CONF_PP           0x04
++#define SYS_MAP_CONV          0x08
++
++//vout clk registers
++#define CLK_LCDC_OCLK_CTRL    0x14
++
++struct res_name {
++      char name[10];
++};
++
++enum PP_LCD_PATH {
++      SYS_BUS_OUTPUT = 0,
++      FIFO_OUTPUT = 1,
++};
++
++enum PP_COLOR_CONVERT_SCALE {
++      NOT_BYPASS = 0,
++      BYPASS,
++};
++
++enum PP_SRC_FORMAT {
++      PP_SRC_YUV420P = 0,
++      PP_SRC_YUV422,
++      PP_SRC_YUV420I,
++      PP_RESERVED,
++      PP_SRC_GRB888,
++      PP_SRC_RGB565,
++};
++
++enum PP_DST_FORMAT {
++      PP_DST_YUV420P = 0,
++      PP_DST_YUV422,
++      PP_DST_YUV420I,
++      PP_DST_RGBA888,
++      PP_DST_ARGB888,
++      PP_DST_RGB565,
++      PP_DST_ABGR888,
++      PP_DST_BGRA888,
++};
++
++
++struct pp_video_mode {
++      enum COLOR_FORMAT format;
++      unsigned int height;
++      unsigned int width;
++      unsigned int addr;
++};
++
++struct pp_mode {
++      char pp_id;
++      bool bus_out;   /*out to ddr*/
++      bool fifo_out;  /*out to lcdc*/
++      bool inited;
++      struct pp_video_mode src;
++      struct pp_video_mode dst;
++};
++
++//vpp registers
++#define PP_SWITCH             0x0000
++#define PP_CTRL1              0x0004
++#define PP_CTRL2              0x0008
++#define PP_SRC_SIZE           0x000C
++#define PP_DROP_CTRL          0x0010
++#define PP_DES_SIZE           0x0014
++#define PP_Scale_Hratio               0x0018
++#define PP_Scale_Vratio               0x001C
++#define PP_Scale_limit                0x0020
++#define PP_SRC_Y_SA_NXT               0x0024
++#define PP_SRC_U_SA_NXT               0x0028
++#define PP_SRC_V_SA_NXT               0x002c
++#define PP_LOAD_NXT_PAR               0x0030
++#define PP_SRC_Y_SA0          0x0034
++#define PP_SRC_U_SA0          0x0038
++#define PP_SRC_V_SA0          0x003c
++#define PP_SRC_Y_OFS          0x0040
++#define PP_SRC_U_OFS          0x0044
++#define PP_SRC_V_OFS          0x0048
++#define PP_SRC_Y_SA1          0x004C
++#define PP_SRC_U_SA1          0x0050
++#define PP_SRC_V_SA1          0x0054
++#define PP_DES_Y_SA           0x0058
++#define PP_DES_U_SA           0x005C
++#define PP_DES_V_SA           0x0060
++#define PP_DES_Y_OFS          0x0064
++#define PP_DES_U_OFS          0x0068
++#define PP_DES_V_OFS          0x006C
++#define PP_INT_STATUS         0x0070
++#define PP_INT_MASK           0x0074
++#define PP_INT_CLR            0x0078
++#define PP_R2Y_COEF1          0x007C
++#define PP_R2Y_COEF2          0x0080
++
++/* Definition controller bit for LCDC registers */
++//for PP_SWITCH
++#define PP_TRIG                       0
++//for PP_CTRL1
++#define PP_LCDPATH_EN         0
++#define PP_INTERLACE          1
++#define PP_POINTER_MODE               2
++#define PP_SRC_FORMAT_N               4
++#define PP_420_ITLC           7
++#define PP_DES_FORMAT         8
++#define PP_R2Y_BPS            12
++#define PP_MSCALE_BPS         13
++#define PP_Y2R_BPS            14
++#define PP_ARGB_ALPHA         16
++#define PP_UV_IN_ADD_128      24
++#define PP_UV_OUT_ADD_128     25
++#define PP_SRC_422_YUV_POS    26
++#define PP_SRC_420_YUV_POS    28
++#define PP_SRC_ARGB_ORDER     29
++//for PP_CTRL2
++#define PP_LOCK_EN            0
++#define PP_INT_INTERVAL               8
++#define PP_DES_422_ORDER      16
++#define PP_DES_420_ORDER      18
++//for PP_SRC_SIZE
++#define PP_SRC_HSIZE          0
++#define PP_SRC_VSIZE          16
++//for PP_DROP_CTRL
++#define PP_DROP_HRATION               0
++#define PP_DROP_VRATION               4
++//for PP_DES_SIZE
++#define PP_DES_HSIZE          0
++#define PP_DES_VSIZE          16
++//for PP_R2Y_COEF1
++#define PP_COEF_R1            0
++#define PP_COEF_G1            16
++//for PP_R2Y_COEF2
++#define PP_COEF_B1            0
++#define PP_OFFSET_1           16
++
++//for vout reg
++#define CLKGEN_BASE_ADDR      0x11800000
++
++#define clk_disp_axi_ctrl_REG                 0x1C0
++#define clk_vout_src_ctrl_REG                 0x1B4
++#define rstgen_assert1_REG                    0x4
++#define rstgen_status1_REG                    0x14
++#define vout_rstgen_assert0_REG                       0x0
++#define vout_rstgen_status0_REG                       0x4
++#define clk_vout_apb_ctrl_REG                 0x0
++#define clk_mapconv_apb_ctrl_REG              0x4
++#define clk_mapconv_axi_ctrl_REG              0x8
++#define clk_disp0_axi_ctrl_REG                        0xC
++#define clk_disp1_axi_ctrl_REG                        0x10
++#define clk_lcdc_oclk_ctrl_REG                        0x14
++#define clk_lcdc_axi_ctrl_REG                 0x18
++#define clk_vpp0_axi_ctrl_REG                 0x1C
++#define clk_vpp1_axi_ctrl_REG                 0x20
++#define clk_vpp2_axi_ctrl_REG                 0x24
++#define clk_pixrawout_apb_ctrl_REG            0x28
++#define clk_pixrawout_axi_ctrl_REG            0x2C
++#define clk_csi2tx_strm0_pixclk_ctrl_REG      0x30
++#define clk_csi2tx_strm0_apb_ctrl_REG         0x34
++#define clk_dsi_sys_clk_ctrl_REG              0x38
++#define clk_dsi_apb_ctrl_REG                  0x3C
++#define clk_ppi_tx_esc_clk_ctrl_REG           0x40
++
++void mapconv_pp0_sel(struct starfive_crtc *sf_crtc, int sel);
++void pp_srcAddr_next(struct starfive_crtc *sf_crtc, int ppNum, int ysa, int usa, int vsa);
++void pp_srcOffset_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yoff, int uoff, int voff);
++void pp_nxtAddr_load(struct starfive_crtc *sf_crtc, int ppNum, int nxtPar, int nxtPos);
++void pp_intcfg(struct starfive_crtc *sf_crtc, int ppNum, int intMask);
++irqreturn_t vpp1_isr_handler(int this_irq, void *dev_id);
++void pp1_enable_intr(struct starfive_crtc *sf_crtc);
++void pp_enable_intr(struct starfive_crtc *sf_crtc, int ppNum);
++void pp_disable_intr(struct starfive_crtc *sf_crtc, int ppNum);
++void pp_run(struct starfive_crtc *sf_crtc, int ppNum, int start);
++int starfive_pp_enable(struct starfive_crtc *sf_crtc);
++int starfive_pp_get_2lcdc_id(struct starfive_crtc *sf_crtc);
++int starfive_pp_update(struct starfive_crtc *sf_crtc);
++void vout_disable(struct starfive_crtc *sf_crtc);
++void vout_reset(struct starfive_crtc *sf_crtc);
++void dsitx_vout_init(struct starfive_crtc *sf_crtc);
++
++#endif

diff --git a/target/linux/visionfive/patches-5.15/0070-drm-i2c-tda998x-Hardcode-register-values-for-Starlig.patch b/target/linux/visionfive/patches-5.15/0070-drm-i2c-tda998x-Hardcode-register-values-for-Starlig.patch
new file mode 100644 (file)
index 0000000..796f57d
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0070-drm-i2c-tda998x-Hardcode-register-values-for-Starlig.patch
@@ -0,0 +1,36 @@
+From ee5b1a0313b7eaac59e91640defaed83abd43169 Mon Sep 17 00:00:00 2001
+From: "sw.multimedia" <sw.multimedia@starfivetech.com>
+Date: Tue, 31 Aug 2021 16:48:57 +0800
+Subject: [PATCH 70/84] drm/i2c/tda998x: Hardcode register values for Starlight
+
+A proper solution to this hack should be found.
+
+Signed-off-by: jack.zhu <jack.zhu@starfivetech.com>
+Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
+---
+ drivers/gpu/drm/i2c/tda998x_drv.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i2c/tda998x_drv.c
++++ b/drivers/gpu/drm/i2c/tda998x_drv.c
+@@ -1603,7 +1603,9 @@ static void tda998x_bridge_mode_set(stru
+               reg |= VIP_CNTRL_3_H_TGL;
+       if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+               reg |= VIP_CNTRL_3_V_TGL;
+-      reg_write(priv, REG_VIP_CNTRL_3, reg);
++      //reg_write(priv, REG_VIP_CNTRL_3, reg);
++      reg_write(priv, REG_VIP_CNTRL_3, 0x26);
++      reg_write(priv, REG_VIDFORMAT, 0x06);
+ 
+       reg_write(priv, REG_VIDFORMAT, 0x00);
+       reg_write16(priv, REG_REFPIX_MSB, ref_pix);
+@@ -1641,7 +1643,8 @@ static void tda998x_bridge_mode_set(stru
+               reg |= TBG_CNTRL_1_H_TGL;
+       if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+               reg |= TBG_CNTRL_1_V_TGL;
+-      reg_write(priv, REG_TBG_CNTRL_1, reg);
++      //reg_write(priv, REG_TBG_CNTRL_1, reg);
++      reg_write(priv, REG_TBG_CNTRL_1, 0x46);
+ 
+       /* must be last register set: */
+       reg_write(priv, REG_TBG_CNTRL_0, 0);

diff --git a/target/linux/visionfive/patches-5.15/0071-drm-starfive-crtc-Use-devm_platform_ioremap_resource.patch b/target/linux/visionfive/patches-5.15/0071-drm-starfive-crtc-Use-devm_platform_ioremap_resource.patch
new file mode 100644 (file)
index 0000000..34176d2
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0071-drm-starfive-crtc-Use-devm_platform_ioremap_resource.patch
@@ -0,0 +1,99 @@
+From 9438a0e5b99d4da67098aac4025fd0e91591a144 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Mon, 20 Sep 2021 21:09:40 +0200
+Subject: [PATCH 71/84] drm/starfive: crtc: Use
+ devm_platform_ioremap_resource_byname
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/gpu/drm/starfive/starfive_drm_crtc.c | 28 +++++++-------------
+ drivers/gpu/drm/starfive/starfive_drm_lcdc.c | 10 -------
+ drivers/gpu/drm/starfive/starfive_drm_vpp.h  |  4 ---
+ 3 files changed, 9 insertions(+), 33 deletions(-)
+
+--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
+@@ -21,20 +21,6 @@
+ #include "starfive_drm_vpp.h"
+ //#include <video/sys_comm_regs.h>
+ 
+-struct resource_name {
+-      char name[10];
+-};
+-
+-static const struct resource_name mem_res_name[] = {
+-      {"lcdc"},
+-      {"vpp0"},
+-      {"vpp1"},
+-      {"vpp2"},
+-      {"clk"},
+-      {"rst"},
+-      {"sys"}
+-};
+-
+ static inline struct drm_encoder *
+ starfive_head_atom_get_encoder(struct starfive_crtc *sf_crtc)
+ {
+@@ -313,13 +299,14 @@ int starfive_crtc_create(struct drm_devi
+ 
+ static int starfive_crtc_get_memres(struct platform_device *pdev, struct starfive_crtc *sf_crtc)
+ {
+-      struct device *dev = &pdev->dev;
++      static const char *const mem_res_name[] = {
++              "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys"
++      };
+       int i;
+ 
+       for (i = 0; i < ARRAY_SIZE(mem_res_name); i++) {
+-              const char *name = mem_res_name[i].name;
+-              struct resource *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+-              void __iomem *regs = devm_ioremap_resource(dev, res);
++              const char *name = mem_res_name[i];
++              void __iomem *regs = devm_platform_ioremap_resource_byname(pdev, name);
+ 
+               if (IS_ERR(regs))
+                       return PTR_ERR(regs);
+@@ -421,7 +408,10 @@ static int starfive_crtc_bind(struct dev
+ 
+       spin_lock_init(&crtcp->reg_lock);
+ 
+-      starfive_crtc_get_memres(pdev, crtcp);
++      ret = starfive_crtc_get_memres(pdev, crtcp);
++      if (ret)
++              return ret;
++
+       ret = starfive_parse_dt(dev, crtcp);
+ 
+       crtcp->pp_conn_lcdc = starfive_pp_get_2lcdc_id(crtcp);
+--- a/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
+@@ -7,16 +7,6 @@
+ #include "starfive_drm_lcdc.h"
+ #include "starfive_drm_vpp.h"
+ 
+-static const struct res_name mem_res_name[] = {
+-      {"lcdc"},
+-      {"vpp0"},
+-      {"vpp1"},
+-      {"vpp2"},
+-      {"clk"},
+-      {"rst"},
+-      {"sys"}
+-};
+-
+ static u32 sf_fb_clkread32(struct starfive_crtc *sf_crtc, u32 reg)
+ {
+       return ioread32(sf_crtc->base_clk + reg);
+--- a/drivers/gpu/drm/starfive/starfive_drm_vpp.h
++++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.h
+@@ -40,10 +40,6 @@
+ //vout clk registers
+ #define CLK_LCDC_OCLK_CTRL    0x14
+ 
+-struct res_name {
+-      char name[10];
+-};
+-
+ enum PP_LCD_PATH {
+       SYS_BUS_OUTPUT = 0,
+       FIFO_OUTPUT = 1,

diff --git a/target/linux/visionfive/patches-5.15/0072-drm-starfive-Use-clock-api.patch b/target/linux/visionfive/patches-5.15/0072-drm-starfive-Use-clock-api.patch
new file mode 100644 (file)
index 0000000..c729a3a
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0072-drm-starfive-Use-clock-api.patch
@@ -0,0 +1,122 @@
+From 581aebf17a117445620446811283196acfabd02d Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Mon, 20 Sep 2021 23:13:38 +0200
+Subject: [PATCH 72/84] drm/starfive: Use clock api
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/gpu/drm/starfive/starfive_drm_crtc.c | 18 +++++++++++++++++-
+ drivers/gpu/drm/starfive/starfive_drm_crtc.h |  4 +++-
+ drivers/gpu/drm/starfive/starfive_drm_vpp.c  | 13 +++++++------
+ drivers/gpu/drm/starfive/starfive_drm_vpp.h  |  5 -----
+ 4 files changed, 27 insertions(+), 13 deletions(-)
+
+--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
+@@ -329,12 +329,24 @@ static int starfive_crtc_get_memres(stru
+                       dev_err(&pdev->dev, "Could not match resource name\n");
+       }
+ 
+-      sf_crtc->topclk = ioremap(0x11800000, 0x10000);
+       sf_crtc->toprst = ioremap(0x11840000, 0x10000);
+ 
+       return 0;
+ }
+ 
++static int starfive_crtc_get_clks(struct platform_device *pdev, struct starfive_crtc *sf_crtc)
++{
++      struct clk_bulk_data clks[] = {
++              { .id = "disp_axi" },
++              { .id = "vout_src" },
++      };
++      int ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(clks), clks);
++
++      sf_crtc->clk_disp_axi = clks[0].clk;
++      sf_crtc->clk_vout_src = clks[1].clk;
++      return ret;
++}
++
+ static int starfive_parse_dt(struct device *dev, struct starfive_crtc *sf_crtc)
+ {
+       int ret;
+@@ -412,6 +424,10 @@ static int starfive_crtc_bind(struct dev
+       if (ret)
+               return ret;
+ 
++      ret = starfive_crtc_get_clks(pdev, crtcp);
++      if (ret)
++              return ret;
++
+       ret = starfive_parse_dt(dev, crtcp);
+ 
+       crtcp->pp_conn_lcdc = starfive_pp_get_2lcdc_id(crtcp);
+--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.h
++++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.h
+@@ -44,7 +44,9 @@ struct starfive_crtc {
+       void __iomem    *base_vpp2;     // 0x120c0000
+       void __iomem    *base_lcdc;     // 0x12000000
+ 
+-      void __iomem    *topclk;        // 0x11800000, 0x10000
++      struct clk *clk_disp_axi;
++      struct clk *clk_vout_src;
++
+       void __iomem    *toprst;        // 0x11840000, 0x10000
+ 
+       int             lcdc_irq;
+--- a/drivers/gpu/drm/starfive/starfive_drm_vpp.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.c
+@@ -2,6 +2,7 @@
+ /*
+  * Copyright (C) 2021 StarFive Technology Co., Ltd.
+  */
++#include <linux/clk.h>
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include "starfive_drm_vpp.h"
+@@ -739,8 +740,8 @@ void dsitx_vout_init(struct starfive_crt
+       sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 0);
+       sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(24), BIT(24));
+       sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 0);
+-      sf_set_clear(sf_crtc->topclk, clk_disp_axi_ctrl_REG, BIT(31), BIT(31));
+-      sf_set_clear(sf_crtc->topclk, clk_vout_src_ctrl_REG, BIT(31), BIT(31));
++      clk_prepare_enable(sf_crtc->clk_disp_axi);
++      clk_prepare_enable(sf_crtc->clk_vout_src);
+       sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(23));
+       sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 1);
+       sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(24));
+@@ -770,8 +771,8 @@ void vout_reset(struct starfive_crtc *sf
+ 
+       iowrite32(0xFFFFFFFF, sf_crtc->base_rst);
+ 
+-      sf_set_clear(sf_crtc->topclk, clk_disp_axi_ctrl_REG, BIT(31), BIT(31));
+-      sf_set_clear(sf_crtc->topclk, clk_vout_src_ctrl_REG, BIT(31), BIT(31));
++      clk_prepare_enable(sf_crtc->clk_disp_axi);
++      clk_prepare_enable(sf_crtc->clk_vout_src);
+ 
+       sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(23));
+       sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 1);
+@@ -807,8 +808,8 @@ void vout_disable(struct starfive_crtc *
+ {
+       iowrite32(0xFFFFFFFF, sf_crtc->base_rst);
+ 
+-      sf_set_clear(sf_crtc->topclk, clk_disp_axi_ctrl_REG, 0, BIT(31));
+-      sf_set_clear(sf_crtc->topclk, clk_vout_src_ctrl_REG, 0, BIT(31));
++      clk_disable_unprepare(sf_crtc->clk_disp_axi);
++      clk_disable_unprepare(sf_crtc->clk_vout_src);
+ 
+       sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(23), BIT(23));
+       sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 0);
+--- a/drivers/gpu/drm/starfive/starfive_drm_vpp.h
++++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.h
+@@ -162,11 +162,6 @@ struct pp_mode {
+ #define PP_COEF_B1            0
+ #define PP_OFFSET_1           16
+ 
+-//for vout reg
+-#define CLKGEN_BASE_ADDR      0x11800000
+-
+-#define clk_disp_axi_ctrl_REG                 0x1C0
+-#define clk_vout_src_ctrl_REG                 0x1B4
+ #define rstgen_assert1_REG                    0x4
+ #define rstgen_status1_REG                    0x14
+ #define vout_rstgen_assert0_REG                       0x0

diff --git a/target/linux/visionfive/patches-5.15/0073-drm-starfive-Use-reset-api.patch b/target/linux/visionfive/patches-5.15/0073-drm-starfive-Use-reset-api.patch
new file mode 100644 (file)
index 0000000..848a498
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0073-drm-starfive-Use-reset-api.patch
@@ -0,0 +1,165 @@
+From 39356b568e768d3b27bb3f7a0fc6108da1f3e083 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Mon, 20 Sep 2021 23:31:21 +0200
+Subject: [PATCH 73/84] drm/starfive: Use reset api
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/gpu/drm/starfive/starfive_drm_crtc.c | 20 +++++++++-
+ drivers/gpu/drm/starfive/starfive_drm_crtc.h |  3 +-
+ drivers/gpu/drm/starfive/starfive_drm_vpp.c  | 40 +++++---------------
+ drivers/gpu/drm/starfive/starfive_drm_vpp.h  |  2 -
+ 4 files changed, 30 insertions(+), 35 deletions(-)
+
+--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
+@@ -5,6 +5,7 @@
+ #include <linux/clk.h>
+ #include <linux/component.h>
+ #include <linux/of_device.h>
++#include <linux/reset.h>
+ #include <linux/delay.h>
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -329,8 +330,6 @@ static int starfive_crtc_get_memres(stru
+                       dev_err(&pdev->dev, "Could not match resource name\n");
+       }
+ 
+-      sf_crtc->toprst = ioremap(0x11840000, 0x10000);
+-
+       return 0;
+ }
+ 
+@@ -347,6 +346,19 @@ static int starfive_crtc_get_clks(struct
+       return ret;
+ }
+ 
++static int starfive_crtc_get_resets(struct platform_device *pdev, struct starfive_crtc *sf_crtc)
++{
++      struct reset_control_bulk_data resets[] = {
++              { .id = "disp_axi" },
++              { .id = "vout_src" },
++      };
++      int ret = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(resets), resets);
++
++      sf_crtc->rst_disp_axi = resets[0].rstc;
++      sf_crtc->rst_vout_src = resets[1].rstc;
++      return ret;
++}
++
+ static int starfive_parse_dt(struct device *dev, struct starfive_crtc *sf_crtc)
+ {
+       int ret;
+@@ -428,6 +440,10 @@ static int starfive_crtc_bind(struct dev
+       if (ret)
+               return ret;
+ 
++      ret = starfive_crtc_get_resets(pdev, crtcp);
++      if (ret)
++              return ret;
++
+       ret = starfive_parse_dt(dev, crtcp);
+ 
+       crtcp->pp_conn_lcdc = starfive_pp_get_2lcdc_id(crtcp);
+--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.h
++++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.h
+@@ -47,7 +47,8 @@ struct starfive_crtc {
+       struct clk *clk_disp_axi;
+       struct clk *clk_vout_src;
+ 
+-      void __iomem    *toprst;        // 0x11840000, 0x10000
++      struct reset_control *rst_disp_axi;
++      struct reset_control *rst_vout_src;
+ 
+       int             lcdc_irq;
+       int             vpp0_irq;
+--- a/drivers/gpu/drm/starfive/starfive_drm_vpp.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.c
+@@ -4,6 +4,7 @@
+  */
+ #include <linux/clk.h>
+ #include <linux/module.h>
++#include <linux/reset.h>
+ #include <linux/delay.h>
+ #include "starfive_drm_vpp.h"
+ #include "starfive_drm_crtc.h"
+@@ -18,16 +19,6 @@ static inline void sf_set_clear(void __i
+       iowrite32(value, addr + reg);
+ }
+ 
+-static inline void sf_reg_status_wait(void __iomem *addr, u32 reg, u8 offset, u8 value)
+-{
+-      u32 temp;
+-
+-      do {
+-              temp = ioread32(addr + reg) >> offset;
+-              temp &= 0x01;
+-      } while (temp != value);
+-}
+-
+ static u32 sf_fb_sysread32(struct starfive_crtc *sf_crtc, u32 reg)
+ {
+       return ioread32(sf_crtc->base_syscfg + reg);
+@@ -736,16 +727,13 @@ void dsitx_vout_init(struct starfive_crt
+ {
+       u32 temp;
+ 
+-      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(23), BIT(23));
+-      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 0);
+-      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(24), BIT(24));
+-      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 0);
++      reset_control_assert(sf_crtc->rst_vout_src);
++      reset_control_assert(sf_crtc->rst_disp_axi);
+       clk_prepare_enable(sf_crtc->clk_disp_axi);
+       clk_prepare_enable(sf_crtc->clk_vout_src);
+-      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(23));
+-      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 1);
+-      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(24));
+-      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 1);
++      reset_control_deassert(sf_crtc->rst_vout_src);
++      reset_control_deassert(sf_crtc->rst_disp_axi);
++
+       sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, BIT(31), BIT(31));
+       sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, BIT(31), BIT(31));
+       sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, BIT(31), BIT(31));
+@@ -773,12 +761,8 @@ void vout_reset(struct starfive_crtc *sf
+ 
+       clk_prepare_enable(sf_crtc->clk_disp_axi);
+       clk_prepare_enable(sf_crtc->clk_vout_src);
+-
+-      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(23));
+-      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 1);
+-
+-      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, 0, BIT(24));
+-      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 1);
++      reset_control_deassert(sf_crtc->rst_vout_src);
++      reset_control_deassert(sf_crtc->rst_disp_axi);
+ 
+       sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, BIT(31), BIT(31));
+       sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, BIT(31), BIT(31));
+@@ -810,12 +794,8 @@ void vout_disable(struct starfive_crtc *
+ 
+       clk_disable_unprepare(sf_crtc->clk_disp_axi);
+       clk_disable_unprepare(sf_crtc->clk_vout_src);
+-
+-      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(23), BIT(23));
+-      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 0);
+-
+-      sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, BIT(24), BIT(24));
+-      sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 0);
++      reset_control_assert(sf_crtc->rst_vout_src);
++      reset_control_assert(sf_crtc->rst_disp_axi);
+ }
+ 
+ MODULE_AUTHOR("StarFive Technology Co., Ltd.");
+--- a/drivers/gpu/drm/starfive/starfive_drm_vpp.h
++++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.h
+@@ -162,8 +162,6 @@ struct pp_mode {
+ #define PP_COEF_B1            0
+ #define PP_OFFSET_1           16
+ 
+-#define rstgen_assert1_REG                    0x4
+-#define rstgen_status1_REG                    0x14
+ #define vout_rstgen_assert0_REG                       0x0
+ #define vout_rstgen_status0_REG                       0x4
+ #define clk_vout_apb_ctrl_REG                 0x0

diff --git a/target/linux/visionfive/patches-5.15/0074-drm-starfive-Use-actual-clock-rate.patch b/target/linux/visionfive/patches-5.15/0074-drm-starfive-Use-actual-clock-rate.patch
new file mode 100644 (file)
index 0000000..d9ed5cc
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0074-drm-starfive-Use-actual-clock-rate.patch
@@ -0,0 +1,31 @@
+From ec6b6cf84e85943691174f14be0b819f573610a6 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Mon, 20 Sep 2021 23:49:31 +0200
+Subject: [PATCH 74/84] drm/starfive: Use actual clock rate
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/gpu/drm/starfive/starfive_drm_lcdc.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
+@@ -2,7 +2,9 @@
+ /*
+  * Copyright (C) 2021 StarFive Technology Co., Ltd.
+  */
++#include <linux/clk.h>
+ #include <linux/module.h>
++#include <linux/units.h>
+ #include <drm/drm_crtc.h>
+ #include "starfive_drm_lcdc.h"
+ #include "starfive_drm_vpp.h"
+@@ -394,7 +396,7 @@ void lcdc_run(struct starfive_crtc *sf_c
+ 
+ static int sf_fb_lcdc_clk_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
+ {
+-      u32 reg_val = 1485000 / state->mode.clock;
++      u32 reg_val = clk_get_rate(sf_crtc->clk_vout_src) / (state->mode.clock * HZ_PER_KHZ);
+       u32 tmp_val;
+ 
+       dev_dbg(sf_crtc->dev, "%s: reg_val = %u\n", __func__, reg_val);

diff --git a/target/linux/visionfive/patches-5.15/0075-WIP-drm-starfive-Support-DRM_FORMAT_XRGB8888.patch b/target/linux/visionfive/patches-5.15/0075-WIP-drm-starfive-Support-DRM_FORMAT_XRGB8888.patch
new file mode 100644 (file)
index 0000000..3b73508
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0075-WIP-drm-starfive-Support-DRM_FORMAT_XRGB8888.patch
@@ -0,0 +1,35 @@
+From 512c5da245a10f9cebe92661f0414195919e87a2 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Wed, 22 Sep 2021 16:35:15 +0200
+Subject: [PATCH 75/84] [WIP] drm/starfive: Support DRM_FORMAT_XRGB8888
+
+When creating dumb buffers with 32bpp and 24bit colour depth this is
+default mode return by drm_mode_legacy_fb_format. So we need to support
+this for common dumb buffers to just work.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/gpu/drm/starfive/starfive_drm_crtc.c  | 1 +
+ drivers/gpu/drm/starfive/starfive_drm_plane.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
+@@ -64,6 +64,7 @@ static int ddrfmt_to_ppfmt(struct starfi
+       case DRM_FORMAT_NV12:
+               sf_crtc->vpp_format = COLOR_YUV420_NV12;
+               break;
++      case DRM_FORMAT_XRGB8888:
+       case DRM_FORMAT_ARGB8888:
+               sf_crtc->vpp_format = COLOR_RGB888_ARGB;
+               break;
+--- a/drivers/gpu/drm/starfive/starfive_drm_plane.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_plane.c
+@@ -27,6 +27,7 @@ static const u32 formats[] = {
+       DRM_FORMAT_NV21,
+       DRM_FORMAT_NV12,
+ 
++      DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+ };

diff --git a/target/linux/visionfive/patches-5.15/0076-drm-starfive-Propagate-bridge-error-properly.patch b/target/linux/visionfive/patches-5.15/0076-drm-starfive-Propagate-bridge-error-properly.patch
new file mode 100644 (file)
index 0000000..cb46f9c
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0076-drm-starfive-Propagate-bridge-error-properly.patch
@@ -0,0 +1,25 @@
+From d78a242adca610f87a4e194fc005266d9e380181 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Wed, 20 Oct 2021 14:29:35 +0200
+Subject: [PATCH 76/84] drm/starfive: Propagate bridge error properly
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/gpu/drm/starfive/starfive_drm_encoder.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/starfive/starfive_drm_encoder.c
++++ b/drivers/gpu/drm/starfive/starfive_drm_encoder.c
+@@ -70,8 +70,10 @@ static int starfive_encoder_bind(struct
+ 
+       ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
+                       &tmp_panel, &tmp_bridge);
+-      if (ret)
+-              dev_err(dev, "endpoint returns %d\n", ret);
++      if (ret) {
++              dev_err_probe(dev, ret, "endpoint returns %d\n", ret);
++              goto err_bridge;
++      }
+ 
+       if (tmp_panel)
+               DRM_INFO("found panel on endpoint\n");

diff --git a/target/linux/visionfive/patches-5.15/0077-nvdla-add-NVDLA-driver.patch b/target/linux/visionfive/patches-5.15/0077-nvdla-add-NVDLA-driver.patch
new file mode 100644 (file)
index 0000000..5597a20
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0077-nvdla-add-NVDLA-driver.patch
@@ -0,0 +1,32767 @@
+From 03cca3f4e965bb2436911734926f8bab7fbe4649 Mon Sep 17 00:00:00 2001
+From: Farzad Farshchi <farzadfr@gmail.com>
+Date: Thu, 20 Sep 2018 19:08:27 -0500
+Subject: [PATCH 77/84] nvdla: add NVDLA driver
+
+Additional update from Prashant Gaikwad <pgaikwad@nvidia.com>
+Adapted for Linux 5.13 and the BeagleV Starlight board by
+<cybergaszcz@gmail.com>
+---
+ drivers/Kconfig                         |     2 +
+ drivers/Makefile                        |     1 +
+ drivers/nvdla/Kconfig                   |     5 +
+ drivers/nvdla/Makefile                  |    19 +
+ drivers/nvdla/bdma.c                    |   280 +
+ drivers/nvdla/cache.c                   |   253 +
+ drivers/nvdla/cdp.c                     |   384 +
+ drivers/nvdla/common.c                  |   324 +
+ drivers/nvdla/common.h                  |    47 +
+ drivers/nvdla/conv.c                    |   779 +
+ drivers/nvdla/dla_engine_internal.h     |   361 +
+ drivers/nvdla/engine.c                  |   262 +
+ drivers/nvdla/engine_data.c             |   303 +
+ drivers/nvdla/engine_debug.c            |   551 +
+ drivers/nvdla/engine_debug.h            |   129 +
+ drivers/nvdla/engine_isr.c              |   136 +
+ drivers/nvdla/include/dla_debug.h       |    94 +
+ drivers/nvdla/include/dla_engine.h      |    94 +
+ drivers/nvdla/include/dla_err.h         |    50 +
+ drivers/nvdla/include/dla_interface.h   |   886 ++
+ drivers/nvdla/include/dla_sched.h       |    74 +
+ drivers/nvdla/include/nvdla_interface.h |   327 +
+ drivers/nvdla/include/nvdla_ioctl.h     |   138 +
+ drivers/nvdla/include/nvdla_linux.h     |   153 +
+ drivers/nvdla/include/opendla.h         |    40 +
+ drivers/nvdla/include/opendla_initial.h | 16743 ++++++++++++++++++++++
+ drivers/nvdla/include/opendla_small.h   |  6433 +++++++++
+ drivers/nvdla/nvdla_core_callbacks.c    |   446 +
+ drivers/nvdla/nvdla_gem.c               |   475 +
+ drivers/nvdla/pdp.c                     |   528 +
+ drivers/nvdla/rubik.c                   |   292 +
+ drivers/nvdla/scheduler.c               |  1160 ++
+ drivers/nvdla/sdp.c                     |   817 ++
+ 33 files changed, 32586 insertions(+)
+ create mode 100644 drivers/nvdla/Kconfig
+ create mode 100644 drivers/nvdla/Makefile
+ create mode 100644 drivers/nvdla/bdma.c
+ create mode 100644 drivers/nvdla/cache.c
+ create mode 100644 drivers/nvdla/cdp.c
+ create mode 100644 drivers/nvdla/common.c
+ create mode 100644 drivers/nvdla/common.h
+ create mode 100644 drivers/nvdla/conv.c
+ create mode 100644 drivers/nvdla/dla_engine_internal.h
+ create mode 100644 drivers/nvdla/engine.c
+ create mode 100644 drivers/nvdla/engine_data.c
+ create mode 100644 drivers/nvdla/engine_debug.c
+ create mode 100644 drivers/nvdla/engine_debug.h
+ create mode 100644 drivers/nvdla/engine_isr.c
+ create mode 100644 drivers/nvdla/include/dla_debug.h
+ create mode 100644 drivers/nvdla/include/dla_engine.h
+ create mode 100644 drivers/nvdla/include/dla_err.h
+ create mode 100644 drivers/nvdla/include/dla_interface.h
+ create mode 100644 drivers/nvdla/include/dla_sched.h
+ create mode 100644 drivers/nvdla/include/nvdla_interface.h
+ create mode 100644 drivers/nvdla/include/nvdla_ioctl.h
+ create mode 100644 drivers/nvdla/include/nvdla_linux.h
+ create mode 100644 drivers/nvdla/include/opendla.h
+ create mode 100644 drivers/nvdla/include/opendla_initial.h
+ create mode 100644 drivers/nvdla/include/opendla_small.h
+ create mode 100644 drivers/nvdla/nvdla_core_callbacks.c
+ create mode 100644 drivers/nvdla/nvdla_gem.c
+ create mode 100644 drivers/nvdla/pdp.c
+ create mode 100644 drivers/nvdla/rubik.c
+ create mode 100644 drivers/nvdla/scheduler.c
+ create mode 100644 drivers/nvdla/sdp.c
+
+--- a/drivers/Kconfig
++++ b/drivers/Kconfig
+@@ -236,4 +236,6 @@ source "drivers/interconnect/Kconfig"
+ source "drivers/counter/Kconfig"
+ 
+ source "drivers/most/Kconfig"
++
++source "drivers/nvdla/Kconfig"
+ endmenu
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -187,3 +187,4 @@ obj-$(CONFIG_GNSS)         += gnss/
+ obj-$(CONFIG_INTERCONNECT)    += interconnect/
+ obj-$(CONFIG_COUNTER)         += counter/
+ obj-$(CONFIG_MOST)            += most/
++obj-$(CONFIG_NVDLA)           += nvdla/
+--- /dev/null
++++ b/drivers/nvdla/Kconfig
+@@ -0,0 +1,5 @@
++config NVDLA
++      bool "The NVIDIA Deep Learning Accelerator"
++      default n
++      depends on DRM
++      select DRM_GEM_CMA_HELPER
+--- /dev/null
++++ b/drivers/nvdla/Makefile
+@@ -0,0 +1,19 @@
++
++ccflags-$(CONFIG_NVDLA) += -I$(srctree)/$(src)
++ccflags-$(CONFIG_NVDLA) += -I$(srctree)/$(src)/include
++
++obj-$(CONFIG_NVDLA) += scheduler.o
++obj-$(CONFIG_NVDLA) += engine.o
++obj-$(CONFIG_NVDLA) += bdma.o
++obj-$(CONFIG_NVDLA) += conv.o
++obj-$(CONFIG_NVDLA) += sdp.o
++obj-$(CONFIG_NVDLA) += cdp.o
++obj-$(CONFIG_NVDLA) += pdp.o
++obj-$(CONFIG_NVDLA) += rubik.o
++obj-$(CONFIG_NVDLA) += cache.o
++obj-$(CONFIG_NVDLA) += common.o
++obj-$(CONFIG_NVDLA) += engine_data.o
++obj-$(CONFIG_NVDLA) += engine_isr.o
++obj-$(CONFIG_NVDLA) += engine_debug.o
++obj-$(CONFIG_NVDLA) += nvdla_core_callbacks.o
++obj-$(CONFIG_NVDLA) += nvdla_gem.o
+--- /dev/null
++++ b/drivers/nvdla/bdma.c
+@@ -0,0 +1,280 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_err.h>
++#include <dla_interface.h>
++
++#include "dla_engine_internal.h"
++#include "engine_debug.h"
++
++static const uint8_t map_mem[] = {
++      FIELD_ENUM(BDMA_CFG_CMD_0, SRC_RAM_TYPE, MC),
++      FIELD_ENUM(BDMA_CFG_CMD_0, SRC_RAM_TYPE, CVSRAM),
++};
++
++#if STAT_ENABLE
++void
++dla_bdma_stat_data(struct dla_processor *processor,
++                                      struct dla_processor_group *group)
++{
++      uint64_t end_time = 0;
++      struct dla_bdma_stat_desc *bdma_stat;
++
++      bdma_stat = &processor->stat_data_desc->bdma_stat;
++
++      end_time = dla_get_time_us();
++
++      if (group->id == (uint32_t)0) {
++              bdma_stat->read_stall = bdma_reg_read(STATUS_GRP0_READ_STALL);
++              bdma_stat->write_stall = bdma_reg_read(STATUS_GRP0_WRITE_STALL);
++      } else {
++              bdma_stat->read_stall = bdma_reg_read(STATUS_GRP1_READ_STALL);
++              bdma_stat->write_stall = bdma_reg_read(STATUS_GRP1_WRITE_STALL);
++      }
++      bdma_stat->runtime = (uint32_t)(end_time - group->start_time);
++}
++
++void
++dla_bdma_dump_stat(struct dla_processor *processor)
++{
++      struct dla_bdma_stat_desc *bdma_stat;
++
++      bdma_stat = &processor->stat_data_desc->bdma_stat;
++
++      dla_debug_bdma_stats(bdma_stat);
++}
++#endif /* STAT_ENABLE */
++
++void
++dla_bdma_set_producer(int32_t group_id, int32_t rdma_group_id)
++{
++      /**
++       * There is no producer bit for BDMA operation,
++       * interrupt pointer decides which outstanding request
++       * to use for this BDMA operation
++       */
++}
++
++int
++dla_bdma_enable(struct dla_processor_group *group)
++{
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_debug("Enter: %s\n", __func__);
++
++      if (group->surface_desc->bdma_surface.num_transfers == (uint16_t)0) {
++              group->events |= ((uint8_t)1 << DLA_EVENT_OP_COMPLETED);
++              goto exit;
++      }
++
++      if (engine->stat_enable == (uint32_t)1) {
++              bdma_reg_write(CFG_STATUS, FIELD_ENUM(BDMA_CFG_STATUS_0,
++                                                      STALL_COUNT_EN, YES));
++              group->start_time = dla_get_time_us();
++      }
++
++      /**
++       * Launch BDMA transfer
++       */
++      if (group->id == 0)
++              bdma_reg_write(CFG_LAUNCH0, FIELD_ENUM(BDMA_CFG_LAUNCH0_0,
++                                                      GRP0_LAUNCH, YES));
++      else
++              bdma_reg_write(CFG_LAUNCH1, FIELD_ENUM(BDMA_CFG_LAUNCH1_0,
++                                                      GRP1_LAUNCH, YES));
++
++exit:
++      dla_debug("Exit: %s\n", __func__);
++      return 0;
++}
++
++void
++dla_bdma_rdma_check(struct dla_processor_group *group)
++{
++      group->is_rdma_needed = 0;
++}
++
++/**
++ * Program BDMA slot for transfer
++ */
++static int32_t
++processor_bdma_program_slot(struct dla_bdma_surface_desc *bdma_surface,
++                              struct dla_bdma_transfer_desc *transfer)
++{
++      int32_t ret = 0;
++      uint64_t source_addr = 0;
++      uint64_t destination_addr = 0;
++      uint32_t high, low, reg;
++      uint8_t  bdma_free_slots = 0;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_debug("Enter: %s\n", __func__);
++
++      /* make sure there're enough free slots */
++      if (bdma_free_slots <= 0) {
++              do {
++                      reg = bdma_reg_read(STATUS);
++                      reg = (reg & MASK(BDMA_STATUS_0, FREE_SLOT)) >>
++                                      SHIFT(BDMA_STATUS_0, FREE_SLOT);
++              } while (reg == 0);
++              bdma_free_slots = (uint8_t)reg;
++      }
++
++      dla_get_dma_address(engine->driver_context, engine->task->task_data,
++                                              transfer->source_address,
++                                              (void *)&source_addr,
++                                              DESTINATION_DMA);
++      dla_get_dma_address(engine->driver_context, engine->task->task_data,
++                                              transfer->destination_address,
++                                              (void *)&destination_addr,
++                                              DESTINATION_DMA);
++
++      ASSERT_GOTO((transfer->line_repeat <= 8192),
++                              ret, ERR(INVALID_INPUT), exit);
++      ASSERT_GOTO((transfer->surface_repeat <= 8192),
++                              ret, ERR(INVALID_INPUT), exit);
++      ASSERT_GOTO((transfer->line_size % 32) == 0,
++                              ret, ERR(INVALID_INPUT), exit);
++      ASSERT_GOTO(transfer->source_line >= transfer->line_size,
++                              ret, ERR(INVALID_INPUT), exit);
++      ASSERT_GOTO(transfer->destination_line >= transfer->line_size,
++                              ret, ERR(INVALID_INPUT), exit);
++      ASSERT_GOTO(transfer->source_surface >=
++                      (transfer->source_line * transfer->line_repeat),
++                              ret, ERR(INVALID_INPUT), exit);
++      ASSERT_GOTO(transfer->destination_surface >=
++                      (transfer->destination_line * transfer->line_repeat),
++                              ret, ERR(INVALID_INPUT), exit);
++
++      /* config registers */
++      high = HIGH32BITS(source_addr);
++      low = LOW32BITS(source_addr);
++      bdma_reg_write(CFG_SRC_ADDR_LOW, low);
++      bdma_reg_write(CFG_SRC_ADDR_HIGH, high);
++      high = HIGH32BITS(destination_addr);
++      low = LOW32BITS(destination_addr);
++      bdma_reg_write(CFG_DST_ADDR_LOW, low);
++      bdma_reg_write(CFG_DST_ADDR_HIGH, high);
++      bdma_reg_write(CFG_LINE, (transfer->line_size >> 5) - 1);
++      reg = (map_mem[bdma_surface->source_type] <<
++                              SHIFT(BDMA_CFG_CMD_0, SRC_RAM_TYPE)) |
++              (map_mem[bdma_surface->destination_type] <<
++                              SHIFT(BDMA_CFG_CMD_0, DST_RAM_TYPE));
++      bdma_reg_write(CFG_CMD, reg);
++      bdma_reg_write(CFG_LINE_REPEAT, transfer->line_repeat - 1);
++      bdma_reg_write(CFG_SRC_LINE, transfer->source_line);
++      bdma_reg_write(CFG_DST_LINE, transfer->destination_line);
++      bdma_reg_write(CFG_SURF_REPEAT, transfer->surface_repeat - 1);
++      bdma_reg_write(CFG_SRC_SURF, transfer->source_surface);
++      bdma_reg_write(CFG_DST_SURF, transfer->destination_surface);
++      bdma_reg_write(CFG_OP, FIELD_ENUM(BDMA_CFG_OP_0, EN, ENABLE));
++
++      dla_debug("Exit: %s\n", __func__);
++
++exit:
++      RETURN(ret);
++}
++
++int
++dla_bdma_is_ready(struct dla_processor *processor,
++                          struct dla_processor_group *group)
++{
++      struct dla_processor_group *next_group;
++
++      next_group = &processor->groups[!group->id];
++
++      /**
++       * If another group is already programmed but not active then
++       * do not program this operation as BDMA does not really
++       * have shadow copies for groups. It will end programming
++       * same group. Wait for another group to get enabled.
++       */
++      if ((processor->group_status & (1 << next_group->id)) &&
++                                              !next_group->active)
++              return 0;
++
++      return 1;
++}
++
++void
++dla_bdma_dump_config(struct dla_processor_group *group)
++{
++      struct dla_bdma_op_desc *bdma_op;
++      struct dla_bdma_surface_desc *bdma_surface;
++
++      bdma_surface = &group->surface_desc->bdma_surface;
++      bdma_op = &group->operation_desc->bdma_op;
++
++      dla_debug_bdma_surface_desc(bdma_surface, group->roi_index);
++      dla_debug_bdma_op_desc(bdma_op, group->roi_index);
++}
++
++int
++dla_bdma_program(struct dla_processor_group *group)
++{
++      int32_t i;
++      int32_t ret = 0;
++      struct dla_bdma_surface_desc *bdma_surface;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_debug("Enter: %s\n", __func__);
++
++      if (!engine->config_data->bdma_enable) {
++              dla_error("BDMA is not supported for this configuration\n");
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      bdma_surface = &group->surface_desc->bdma_surface;
++
++      dla_debug("Num of transfers %u\n", bdma_surface->num_transfers);
++      if (bdma_surface->num_transfers == (uint16_t)0)
++              goto exit;
++
++      if (bdma_surface->num_transfers > NUM_MAX_BDMA_OPS) {
++              dla_error("Invalid number of transfers\n");
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      for (i = 0; i < bdma_surface->num_transfers; i++) {
++              ret = processor_bdma_program_slot(bdma_surface,
++                                      &bdma_surface->transfers[i]);
++              if (ret)
++                      goto exit;
++      }
++
++      dla_enable_intr(MASK(GLB_S_INTR_MASK_0, BDMA_DONE_MASK1) |
++                      MASK(GLB_S_INTR_MASK_0, BDMA_DONE_MASK0));
++
++exit:
++      dla_debug("Exit: %s\n", __func__);
++      RETURN(ret);
++}
+--- /dev/null
++++ b/drivers/nvdla/cache.c
+@@ -0,0 +1,253 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_engine.h>
++#include <dla_interface.h>
++
++#include "dla_engine_internal.h"
++
++#define DLA_OP_CACHE_SIZE (DLA_NUM_GROUPS * ((DLA_OP_NUM + 2) * 2))
++
++static struct dla_common_op_desc desc_cache[DLA_OP_NUM][DLA_OP_CACHE_SIZE];
++static int32_t desc_refcount[DLA_OP_NUM][DLA_OP_CACHE_SIZE];
++
++void
++dla_get_refcount(struct dla_common_op_desc *op_desc)
++{
++      int32_t i;
++      struct dla_common_op_desc *desc = NULL;
++
++      if (op_desc == NULL)
++              return;
++
++      if (op_desc->index == -1)
++              return;
++
++      desc = &desc_cache[op_desc->op_type][0];
++
++      for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
++              if (desc->index == op_desc->index &&
++                              desc->roi_index == op_desc->roi_index) {
++                      desc_refcount[op_desc->op_type][i]++;
++                      return;
++              }
++      }
++}
++
++struct dla_common_op_desc *
++dla_get_op_desc(struct dla_task *task, int16_t index,
++                      uint8_t op_type, uint8_t roi_index)
++{
++      int32_t i;
++      int32_t ret;
++      uint64_t op_base;
++      uint64_t dep_graph_addr;
++      struct dla_common_op_desc *desc = NULL;
++      struct dla_engine *engine = dla_get_engine();
++
++      if (index == -1) {
++              dla_debug("no desc get due to index==-1\n");
++              goto exit;
++      }
++
++      dep_graph_addr = (sizeof(struct dla_common_op_desc) *
++                              engine->network->num_operations * roi_index);
++
++      desc = &desc_cache[op_type][0];
++
++      for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
++              if (desc->index == index && desc->roi_index == roi_index) {
++                      if (desc->op_type != op_type) {
++                              dla_error("op_cache[op=%u] contains incorrect "
++                                              "entry of op[%u]\n", op_type,
++                                              desc->op_type);
++                              continue;
++                      }
++                      desc_refcount[op_type][i]++;
++                      goto exit;
++              }
++      }
++
++      desc = &desc_cache[op_type][0];
++
++      for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
++              if (desc->index == -1) {
++                      op_base = dep_graph_addr +
++                                      (sizeof(struct dla_common_op_desc) *
++                                      (uint64_t)index);
++                      ret = dla_data_read(engine->driver_context,
++                                      task->task_data,
++                                      task->dependency_graph_addr,
++                                      (void *)(desc),
++                                      sizeof(struct dla_common_op_desc),
++                                      op_base);
++                      if (ret) {
++                              desc = NULL;
++                              goto exit;
++                      }
++
++                      if (op_type != desc->op_type) {
++                              /*
++                               * op_type of entry read from DRAM should not
++                               * mismatch with given op_type. If they
++                               * mismatches, then wrong entry is fetched, so
++                               * report this issue by throwing error.
++                               */
++                              dla_error("Fetched [op_type=%u] from DRAM doesn't "
++                                      "match with op_type[%u]\n",
++                                      desc->op_type,
++                                      op_type);
++                              desc->op_type = op_type;
++                              desc->index = -1;
++                              desc->roi_index = -1;
++                              desc = NULL;
++                              goto exit;
++                      }
++
++                      desc->index = index;
++                      desc->roi_index = roi_index;
++
++                      /**
++                       * Refcount must be 0 if we are reading it first time
++                       * from DRAM
++                       */
++                      assert(desc_refcount[op_type][i] == 0);
++
++                      desc_refcount[op_type][i]++;
++                      goto exit;
++              }
++      }
++
++exit:
++      return desc;
++}
++
++static void
++dla_free_op_desc(struct dla_common_op_desc *op_desc)
++{
++      uint64_t op_base;
++      uint64_t dep_graph_addr;
++      struct dla_task *task;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_debug("Enter: %s op desc index %u ROI %d\n", __func__,
++                              op_desc->index, op_desc->roi_index);
++
++      task = engine->task;
++      dep_graph_addr = (sizeof(struct dla_common_op_desc) *
++                              engine->network->num_operations *
++                              op_desc->roi_index);
++
++      if (op_desc->index == -1)
++              goto exit;
++
++      if (op_desc == NULL)
++              goto exit;
++
++      /**
++       * TODO: keeping the depth value hardcoded as 0 for now,
++       * need to replace it once corresponding implementation is done.
++       */
++      op_base = (dep_graph_addr +
++                      (sizeof(struct dla_common_op_desc) *
++                      (uint64_t)op_desc->index));
++
++      /**
++       * Flush descriptor to DRAM
++       */
++      dla_data_write(engine->driver_context,
++                      task->task_data,
++                      (void *)op_desc,
++                      task->dependency_graph_addr,
++                      sizeof(struct dla_common_op_desc),
++                      op_base);
++
++      /**
++       * Release it
++       */
++      op_desc->index = -1;
++      op_desc->roi_index = -1;
++exit:
++      dla_debug("Exit: %s\n", __func__);
++}
++
++void
++dla_put_op_desc(struct dla_common_op_desc *op_desc)
++{
++      int32_t i;
++      struct dla_common_op_desc *desc;
++
++      if (op_desc == NULL)
++              return;
++
++      if (op_desc->index == -1)
++              return;
++
++      desc = &desc_cache[op_desc->op_type][0];
++
++      for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
++              if (desc->index == op_desc->index &&
++                              desc->roi_index == op_desc->roi_index) {
++                      /**
++                       * Refcount can't be 0 when we are trying to free it
++                       */
++                      assert(desc_refcount[op_desc->op_type][i] > 0);
++
++                      desc_refcount[op_desc->op_type][i]--;
++
++                      /**
++                       * Free desc if refcount is 0
++                       */
++                      if (desc_refcount[op_desc->op_type][i] == 0)
++                              dla_free_op_desc(op_desc);
++
++                      return;
++              }
++      }
++}
++
++void
++dla_init_op_cache(struct dla_engine *engine)
++{
++      int32_t i, j;
++      struct dla_common_op_desc *desc = &desc_cache[0][0];
++
++      dla_memset((uint8_t *)&desc_cache[0][0], 0, sizeof(desc_cache));
++      dla_memset((uint8_t *)&desc_refcount[0][0], 0, sizeof(desc_refcount));
++
++      for (i = 0; i < DLA_OP_NUM; i++) {
++              for (j = 0; j < DLA_OP_CACHE_SIZE; j++) {
++                      desc->index = -1;
++                      desc->roi_index = -1;
++                      desc->op_type = (uint8_t)i;
++                      desc++;
++              }
++      }
++}
+--- /dev/null
++++ b/drivers/nvdla/cdp.c
+@@ -0,0 +1,384 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_err.h>
++#include <dla_interface.h>
++
++#include "common.h"
++#include "dla_engine_internal.h"
++#include "engine_debug.h"
++
++static const uint8_t map_ram[] = {
++      FIELD_ENUM(CDP_RDMA_D_SRC_DMA_CFG_0, SRC_RAM_TYPE, MC),
++      FIELD_ENUM(CDP_RDMA_D_SRC_DMA_CFG_0, SRC_RAM_TYPE, CV),
++};
++
++static const uint8_t map_precision[] = {
++      FIELD_ENUM(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA, INT8),
++      FIELD_ENUM(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA, INT16),
++      FIELD_ENUM(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA, FP16),
++};
++
++static const uint8_t map_perf_dma[] = {
++      FIELD_ENUM(CDP_D_PERF_ENABLE_0, DMA_EN, DISABLE),
++      FIELD_ENUM(CDP_D_PERF_ENABLE_0, DMA_EN, ENABLE),
++};
++
++static const uint8_t map_perf_lut[] = {
++      FIELD_ENUM(CDP_D_PERF_ENABLE_0, LUT_EN, DISABLE),
++      FIELD_ENUM(CDP_D_PERF_ENABLE_0, LUT_EN, ENABLE),
++};
++
++#if STAT_ENABLE
++void
++dla_cdp_stat_data(struct dla_processor *processor,
++                                      struct dla_processor_group *group)
++{
++      uint64_t end_time = 0;
++      struct dla_cdp_stat_desc *cdp_stat;
++
++      cdp_stat = &processor->stat_data_desc->cdp_stat;
++
++      end_time = dla_get_time_us();
++
++      cdp_stat->write_stall = cdp_reg_read(D_PERF_WRITE_STALL);
++      cdp_stat->lut_uflow = cdp_reg_read(D_PERF_LUT_UFLOW);
++      cdp_stat->lut_oflow = cdp_reg_read(D_PERF_LUT_OFLOW);
++      cdp_stat->lut_hybrid = cdp_reg_read(D_PERF_LUT_HYBRID);
++      cdp_stat->lut_le_hit = cdp_reg_read(D_PERF_LUT_LE_HIT);
++      cdp_stat->lut_lo_hit = cdp_reg_read(D_PERF_LUT_LO_HIT);
++      cdp_stat->runtime = (uint32_t)(end_time - group->start_time);
++}
++
++void
++dla_cdp_dump_stat(struct dla_processor *processor)
++{
++      struct dla_cdp_stat_desc *cdp_stat;
++
++      cdp_stat = &processor->stat_data_desc->cdp_stat;
++
++      dla_debug_cdp_stats(cdp_stat);
++}
++#endif /* STAT_ENABLE */
++
++static uint32_t
++map_local_size(uint8_t local_size)
++{
++      return ((local_size-1)/2)-1;
++}
++
++void
++dla_cdp_set_producer(int32_t group_id, int32_t rdma_group_id)
++{
++      uint32_t reg;
++
++      /**
++       * set producer pointer for all sub-modules
++       */
++      reg = group_id << SHIFT(CDP_S_POINTER_0, PRODUCER);
++      cdp_reg_write(S_POINTER, reg);
++      reg = group_id << SHIFT(CDP_RDMA_S_POINTER_0, PRODUCER);
++      cdp_rdma_reg_write(S_POINTER, reg);
++}
++
++int
++dla_cdp_enable(struct dla_processor_group *group)
++{
++      uint32_t reg;
++      uint8_t perf_reg;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_debug("Enter: %s\n", __func__);
++
++      if (engine->stat_enable == (uint32_t)1) {
++              perf_reg = (map_perf_dma[1] <<
++                              SHIFT(CDP_D_PERF_ENABLE_0, DMA_EN)) |
++                      (map_perf_lut[1] <<
++                              SHIFT(CDP_D_PERF_ENABLE_0, LUT_EN));
++
++              cdp_reg_write(D_PERF_ENABLE, perf_reg);
++              group->start_time = dla_get_time_us();
++      }
++
++      /**
++       * enable all sub-modules
++       */
++      reg = FIELD_ENUM(CDP_RDMA_D_OP_ENABLE_0, OP_EN, ENABLE);
++      cdp_rdma_reg_write(D_OP_ENABLE, reg);
++      reg = FIELD_ENUM(CDP_D_OP_ENABLE_0, OP_EN, ENABLE);
++      cdp_reg_write(D_OP_ENABLE, reg);
++
++      dla_debug("Exit: %s\n", __func__);
++
++      RETURN(0);
++}
++
++void
++dla_cdp_rdma_check(struct dla_processor_group *group)
++{
++      group->is_rdma_needed = 1;
++}
++
++static int32_t
++processor_cdp_program(struct dla_processor_group *group)
++{
++      int32_t ret = 0;
++      uint32_t reg, high, low;
++      uint64_t input_address = 0;
++      uint64_t output_address = 0;
++      struct dla_lut_param lut;
++      struct dla_engine *engine = dla_get_engine();
++      struct dla_cdp_op_desc *cdp_op;
++      struct dla_cdp_surface_desc *cdp_surface;
++
++      dla_debug("Enter: %s\n", __func__);
++
++      cdp_op = &group->operation_desc->cdp_op;
++      cdp_surface = &group->surface_desc->cdp_surface;
++
++      /* Argument check */
++      if (cdp_surface->src_data.type == DLA_MEM_HW) {
++              dla_error("Invalid source memory type\n");
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++      if (cdp_surface->dst_data.type == DLA_MEM_HW) {
++              dla_error("Invalid destination memory type\n");
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      if (cdp_op->in_precision != cdp_op->out_precision) {
++              dla_error("CDP does not support precision conversion\n");
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      /* get the addresses from task descriptor */
++      ret = dla_read_input_address(&cdp_surface->src_data,
++                                              &input_address,
++                                              group->op_desc->index,
++                                              group->roi_index,
++                                              1);
++      if (ret)
++              goto exit;
++
++      dla_get_dma_cube_address(engine->driver_context,
++                              engine->task->task_data,
++                              cdp_surface->dst_data.address,
++                              cdp_surface->dst_data.offset,
++                              (void *)&output_address,
++                              DESTINATION_DMA);
++      if (cdp_op->lut_index >= 0) {
++              group->lut_index = cdp_op->lut_index;
++              dla_read_lut(engine, cdp_op->lut_index, (void *)&lut);
++              dla_debug_lut_params(&lut);
++      }
++
++      /* config CDP RDMA registers */
++      reg = ((cdp_surface->src_data.width - 1)
++              << SHIFT(CDP_RDMA_D_DATA_CUBE_WIDTH_0, WIDTH));
++      cdp_rdma_reg_write(D_DATA_CUBE_WIDTH, reg);
++
++      reg = ((cdp_surface->src_data.height - 1)
++              << SHIFT(CDP_RDMA_D_DATA_CUBE_HEIGHT_0, HEIGHT));
++      cdp_rdma_reg_write(D_DATA_CUBE_HEIGHT, reg);
++
++      reg = ((cdp_surface->src_data.channel - 1)
++              << SHIFT(CDP_RDMA_D_DATA_CUBE_CHANNEL_0, CHANNEL));
++      cdp_rdma_reg_write(D_DATA_CUBE_CHANNEL, reg);
++
++      high = HIGH32BITS(input_address);
++      low = LOW32BITS(input_address);
++      cdp_rdma_reg_write(D_SRC_BASE_ADDR_LOW, low);
++      cdp_rdma_reg_write(D_SRC_BASE_ADDR_HIGH, high);
++
++      cdp_rdma_reg_write(D_SRC_LINE_STRIDE,
++                      cdp_surface->src_data.line_stride);
++      cdp_rdma_reg_write(D_SRC_SURFACE_STRIDE,
++                      cdp_surface->src_data.surf_stride);
++
++      reg = (map_ram[cdp_surface->src_data.type]
++              << SHIFT(CDP_RDMA_D_SRC_DMA_CFG_0, SRC_RAM_TYPE));
++      cdp_rdma_reg_write(D_SRC_DMA_CFG, reg);
++
++      reg = (map_precision[cdp_op->in_precision]
++              << SHIFT(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA));
++      cdp_rdma_reg_write(D_DATA_FORMAT, reg);
++
++      /* config CDP */
++      if (cdp_op->lut_index >= 0)
++              update_lut(CDP_S_LUT_ACCESS_CFG_0, &lut, cdp_op->in_precision);
++
++      high = HIGH32BITS(output_address);
++      low = LOW32BITS(output_address);
++      cdp_reg_write(D_DST_BASE_ADDR_LOW, low);
++      cdp_reg_write(D_DST_BASE_ADDR_HIGH, high);
++
++      cdp_reg_write(D_DST_LINE_STRIDE, cdp_surface->dst_data.line_stride);
++      cdp_reg_write(D_DST_SURFACE_STRIDE, cdp_surface->dst_data.surf_stride);
++
++      reg = (map_ram[cdp_surface->dst_data.type]
++              << SHIFT(CDP_D_DST_DMA_CFG_0, DST_RAM_TYPE));
++      cdp_reg_write(D_DST_DMA_CFG, reg);
++
++      reg = (map_precision[cdp_op->in_precision]
++              << SHIFT(CDP_D_DATA_FORMAT_0, INPUT_DATA_TYPE));
++      cdp_reg_write(D_DATA_FORMAT, reg);
++
++      reg = (map_local_size(cdp_op->local_size)
++              << SHIFT(CDP_D_LRN_CFG_0, NORMALZ_LEN));
++      cdp_reg_write(D_LRN_CFG, reg);
++
++      reg = (cdp_op->in_cvt.offset
++              << SHIFT(CDP_D_DATIN_OFFSET_0, DATIN_OFFSET));
++      cdp_reg_write(D_DATIN_OFFSET, reg);
++
++      reg = (cdp_op->in_cvt.scale
++              << SHIFT(CDP_D_DATIN_SCALE_0, DATIN_SCALE));
++      cdp_reg_write(D_DATIN_SCALE, reg);
++
++      reg = (cdp_op->in_cvt.truncate
++              << SHIFT(CDP_D_DATIN_SHIFTER_0, DATIN_SHIFTER));
++      cdp_reg_write(D_DATIN_SHIFTER, reg);
++
++      reg = (cdp_op->out_cvt.offset
++              << SHIFT(CDP_D_DATOUT_OFFSET_0, DATOUT_OFFSET));
++      cdp_reg_write(D_DATOUT_OFFSET, reg);
++
++      reg = (cdp_op->out_cvt.scale
++              << SHIFT(CDP_D_DATOUT_SCALE_0, DATOUT_SCALE));
++      cdp_reg_write(D_DATOUT_SCALE, reg);
++
++      reg = (cdp_op->out_cvt.truncate
++              << SHIFT(CDP_D_DATOUT_SHIFTER_0, DATOUT_SHIFTER));
++      cdp_reg_write(D_DATOUT_SHIFTER, reg);
++
++      reg = ((cdp_op->bypass_sqsum ?
++              FIELD_ENUM(CDP_D_FUNC_BYPASS_0, SQSUM_BYPASS, ENABLE) :
++              FIELD_ENUM(CDP_D_FUNC_BYPASS_0, SQSUM_BYPASS, DISABLE)) <<
++              SHIFT(CDP_D_FUNC_BYPASS_0, SQSUM_BYPASS)) |
++              ((cdp_op->bypass_out_mul ?
++              FIELD_ENUM(CDP_D_FUNC_BYPASS_0, MUL_BYPASS, ENABLE) :
++              FIELD_ENUM(CDP_D_FUNC_BYPASS_0, MUL_BYPASS, DISABLE)) <<
++              SHIFT(CDP_D_FUNC_BYPASS_0, MUL_BYPASS));
++      cdp_reg_write(D_FUNC_BYPASS, reg);
++
++exit:
++      dla_debug("Exit: %s", __func__);
++      RETURN(ret);
++}
++
++int
++dla_cdp_is_ready(struct dla_processor *processor,
++               struct dla_processor_group *group)
++{
++      struct dla_processor_group *next_group;
++      struct dla_cdp_op_desc *cdp_op;
++
++      cdp_op = &group->operation_desc->cdp_op;
++      next_group = &processor->groups[!group->id];
++
++      /**
++       * Single LUT is shared between two CDP groups, need to make
++       * sure that usage does not conflict. Also, LUT write
++       * access is locked when CDP sub-engine is active, so delay
++       * writing LUT when another group is active.
++       */
++
++      /**
++       * if no LUT required for current group then it can be programmed
++       * without further checks
++       */
++      if (cdp_op->lut_index == -1)
++              return 1;
++
++      /**
++       * if same LUT is used for both groups then it can be programmed
++       * without more checks. Even if another group is active and LUT
++       * is locked, it would have been programmed by another group.
++       */
++      if (next_group->lut_index == cdp_op->lut_index)
++              return 1;
++
++      /**
++       * if LUT index of another group is not -1 means some LUT is programmed,
++       * then do not program current LUT as we already know current LUT is not
++       * -1 and neither same as another group.
++       */
++      if (next_group->lut_index != -1)
++              return 0;
++
++      /**
++       * if current group needs LUT different than another group and that
++       * group is not active then program it.
++       */
++      if (!next_group->active)
++              return 1;
++
++      /**
++       * if control is here it means current group is using LUT different than
++       * another group and that group is active. Wait for another group to
++       * become idle.
++       */
++
++      return 0;
++}
++
++void
++dla_cdp_dump_config(struct dla_processor_group *group)
++{
++      struct dla_cdp_op_desc *cdp_op;
++      struct dla_cdp_surface_desc *cdp_surface;
++
++      cdp_surface = &group->surface_desc->cdp_surface;
++      cdp_op = &group->operation_desc->cdp_op;
++
++      dla_debug_cdp_surface_desc(cdp_surface, group->roi_index);
++      dla_debug_cdp_op_desc(cdp_op, group->roi_index);
++}
++
++int
++dla_cdp_program(struct dla_processor_group *group)
++{
++      int32_t ret;
++
++      dla_debug("Enter: %s", __func__);
++      dla_enable_intr(MASK(GLB_S_INTR_MASK_0, CDP_DONE_MASK1) |
++                      MASK(GLB_S_INTR_MASK_0, CDP_DONE_MASK0));
++
++      ret = processor_cdp_program(group);
++      if (ret)
++              goto exit;
++
++exit:
++      dla_debug("Exit: %s", __func__);
++      RETURN(ret);
++}
+--- /dev/null
++++ b/drivers/nvdla/common.c
+@@ -0,0 +1,324 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_err.h>
++#include <dla_interface.h>
++
++#include "common.h"
++#include "dla_engine_internal.h"
++
++static const uint8_t map_lut_method[] = {
++      FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_LE_FUNCTION, EXPONENT),
++      FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_LE_FUNCTION, LINEAR)
++};
++static const uint8_t map_lut_out[] = {
++      FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_UFLOW_PRIORITY, LE),
++      FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_UFLOW_PRIORITY, LO)
++};
++
++static const uint16_t access_data_offset[] = {
++      CDP_S_LUT_ACCESS_DATA_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_ACCESS_DATA_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t lut_cfg_offset[] = {
++      CDP_S_LUT_CFG_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_CFG_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t lut_info_offset[] = {
++      CDP_S_LUT_INFO_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_INFO_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t le_start_offset[] = {
++      CDP_S_LUT_LE_START_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_LE_START_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t le_end_offset[] = {
++      CDP_S_LUT_LE_END_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_LE_END_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t lo_start_offset[] = {
++      CDP_S_LUT_LO_START_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_LO_START_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t lo_end_offset[] = {
++      CDP_S_LUT_LO_END_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_LO_END_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t le_slope_scale_offset[] = {
++      CDP_S_LUT_LE_SLOPE_SCALE_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_LE_SLOPE_SCALE_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t le_slope_shift_offset[] = {
++      CDP_S_LUT_LE_SLOPE_SHIFT_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_LE_SLOPE_SHIFT_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t lo_slope_scale_offset[] = {
++      CDP_S_LUT_LO_SLOPE_SCALE_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_LO_SLOPE_SCALE_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++static const uint16_t lo_slope_shift_offset[] = {
++      CDP_S_LUT_LO_SLOPE_SHIFT_0 - CDP_S_LUT_ACCESS_CFG_0,
++      SDP_S_LUT_LO_SLOPE_SHIFT_0 - SDP_S_LUT_ACCESS_CFG_0,
++};
++
++void update_lut(uint32_t reg_base, struct dla_lut_param *lut,
++                                                      uint8_t precision)
++{
++      int32_t i;
++      uint32_t reg;
++      uint32_t high, low;
++      int32_t is_sdp = reg_base == SDP_S_LUT_ACCESS_CFG_0;
++      struct dla_engine *engine = dla_get_engine();
++
++      /* program raw table */
++      reg = (FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID, LE)
++              << SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID)) |
++              (FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE, WRITE)
++              << SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE));
++      reg_write(reg_base, reg);
++
++      for (i = 0; i < (1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1; i++) {
++              dla_reg_write(engine->driver_context,
++                              reg_base + access_data_offset[is_sdp],
++                              lut->linear_exp_table[i]);
++      }
++
++      /* program density table */
++      reg = (FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID, LO)
++              << SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID)) |
++              (FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE, WRITE)
++              << SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE));
++      dla_reg_write(engine->driver_context, reg_base, reg);
++
++      for (i = 0; i < (1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1; i++) {
++              dla_reg_write(engine->driver_context,
++                              reg_base + access_data_offset[is_sdp],
++                              lut->linear_only_table[i]);
++      }
++
++      /* program other configurations */
++      reg = (map_lut_method[lut->method] <<
++              SHIFT(CDP_S_LUT_CFG_0, LUT_LE_FUNCTION)) |
++              (map_lut_out[lut->hybrid_priority] <<
++              SHIFT(CDP_S_LUT_CFG_0, LUT_HYBRID_PRIORITY)) |
++              (map_lut_out[lut->underflow_priority] <<
++              SHIFT(CDP_S_LUT_CFG_0, LUT_UFLOW_PRIORITY)) |
++              (map_lut_out[lut->overflow_priority] <<
++              SHIFT(CDP_S_LUT_CFG_0, LUT_OFLOW_PRIORITY));
++      dla_reg_write(engine->driver_context,
++                      reg_base + lut_cfg_offset[is_sdp], reg);
++
++      if (lut->method == FIELD_ENUM(CDP_S_LUT_CFG_0,
++                                      LUT_LE_FUNCTION, EXPONENT)) {
++              reg = ((((uint32_t)lut->linear_exp_offset.exp_offset) <<
++                      SHIFT(CDP_S_LUT_INFO_0, LUT_LE_INDEX_OFFSET))&
++              MASK(CDP_S_LUT_INFO_0, LUT_LE_INDEX_OFFSET)) |
++                      ((((uint32_t)lut->linear_only_offset.frac_bits) <<
++                      SHIFT(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT))&
++              MASK(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT));
++      } else {
++              reg = ((((uint32_t)lut->linear_exp_offset.frac_bits) <<
++                      SHIFT(CDP_S_LUT_INFO_0, LUT_LE_INDEX_SELECT))&
++              MASK(CDP_S_LUT_INFO_0, LUT_LE_INDEX_SELECT)) |
++                      ((((uint32_t)lut->linear_only_offset.frac_bits) <<
++                      SHIFT(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT))&
++              MASK(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT));
++      }
++      dla_reg_write(engine->driver_context,
++                      reg_base + lut_info_offset[is_sdp], reg);
++      high = HIGH32BITS(lut->linear_exp_start);
++      low = LOW32BITS(lut->linear_exp_start);
++      dla_reg_write(engine->driver_context,
++                      reg_base + le_start_offset[is_sdp], low);
++      if (!is_sdp)
++              dla_reg_write(engine->driver_context,
++                              reg_base + le_start_offset[is_sdp] + 4, high);
++
++      high = HIGH32BITS(lut->linear_exp_end);
++      low = LOW32BITS(lut->linear_exp_end);
++      dla_reg_write(engine->driver_context,
++                              reg_base + le_end_offset[is_sdp], low);
++      if (!is_sdp)
++              dla_reg_write(engine->driver_context,
++                              reg_base + le_end_offset[is_sdp] + 4, high);
++
++      high = HIGH32BITS(lut->linear_only_start);
++      low = LOW32BITS(lut->linear_only_start);
++      dla_reg_write(engine->driver_context,
++                              reg_base + lo_start_offset[is_sdp], low);
++      if (!is_sdp)
++              dla_reg_write(engine->driver_context,
++                              reg_base + lo_start_offset[is_sdp] + 4, high);
++
++      high = HIGH32BITS(lut->linear_only_end);
++      low = LOW32BITS(lut->linear_only_end);
++      dla_reg_write(engine->driver_context,
++                              reg_base + lo_end_offset[is_sdp], low);
++      if (!is_sdp)
++              dla_reg_write(engine->driver_context,
++                              reg_base + lo_end_offset[is_sdp] + 4, high);
++
++      if (precision == PRECISION_FP16) {
++              reg = (lut->linear_exp_underflow_slope.data_f <<
++                      SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
++                                      LUT_LE_SLOPE_UFLOW_SCALE)) |
++                      (lut->linear_exp_overflow_slope.data_f <<
++                      SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
++                                      LUT_LE_SLOPE_OFLOW_SCALE));
++              dla_reg_write(engine->driver_context,
++                              reg_base + le_slope_scale_offset[is_sdp], reg);
++
++              reg = (lut->linear_only_underflow_slope.data_f <<
++                      SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
++                                      LUT_LO_SLOPE_UFLOW_SCALE)) |
++                      (lut->linear_only_overflow_slope.data_f <<
++                      SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
++                                      LUT_LO_SLOPE_OFLOW_SCALE));
++              dla_reg_write(engine->driver_context,
++                              reg_base + lo_slope_scale_offset[is_sdp], reg);
++      } else {
++              union dla_slope *oslope;
++              union dla_slope *uslope;
++
++              uslope = &lut->linear_exp_underflow_slope;
++              oslope = &lut->linear_exp_overflow_slope;
++              reg = ((((uint32_t)uslope->data_i.scale)
++                      << SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
++                                      LUT_LE_SLOPE_UFLOW_SCALE))&
++                      MASK(CDP_S_LUT_LE_SLOPE_SCALE_0,
++                                      LUT_LE_SLOPE_UFLOW_SCALE)) |
++                      ((((uint32_t)oslope->data_i.scale)
++                      << SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
++                                      LUT_LE_SLOPE_OFLOW_SCALE))&
++                      MASK(CDP_S_LUT_LE_SLOPE_SCALE_0,
++                                      LUT_LE_SLOPE_OFLOW_SCALE));
++              dla_reg_write(engine->driver_context,
++                              reg_base + le_slope_scale_offset[is_sdp], reg);
++
++              reg = ((((uint32_t)uslope->data_i.shifter) <<
++                      SHIFT(CDP_S_LUT_LE_SLOPE_SHIFT_0,
++                                      LUT_LE_SLOPE_UFLOW_SHIFT))&
++                      MASK(CDP_S_LUT_LE_SLOPE_SHIFT_0,
++                                      LUT_LE_SLOPE_UFLOW_SHIFT)) |
++                      ((((uint32_t)oslope->data_i.shifter) <<
++                      SHIFT(CDP_S_LUT_LE_SLOPE_SHIFT_0,
++                                      LUT_LE_SLOPE_OFLOW_SHIFT))&
++                      MASK(CDP_S_LUT_LE_SLOPE_SHIFT_0,
++                                      LUT_LE_SLOPE_OFLOW_SHIFT));
++              dla_reg_write(engine->driver_context,
++                              reg_base + le_slope_shift_offset[is_sdp], reg);
++
++              uslope = &lut->linear_only_underflow_slope;
++              oslope = &lut->linear_only_overflow_slope;
++              reg = ((((uint32_t)uslope->data_i.scale) <<
++                      SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
++                                      LUT_LO_SLOPE_UFLOW_SCALE))&
++                      MASK(CDP_S_LUT_LO_SLOPE_SCALE_0,
++                                      LUT_LO_SLOPE_UFLOW_SCALE)) |
++                      ((((uint32_t)oslope->data_i.scale) <<
++                      SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
++                                      LUT_LO_SLOPE_OFLOW_SCALE))&
++                      MASK(CDP_S_LUT_LO_SLOPE_SCALE_0,
++                                      LUT_LO_SLOPE_OFLOW_SCALE));
++              dla_reg_write(engine->driver_context,
++                              reg_base + lo_slope_scale_offset[is_sdp], reg);
++              reg = ((((uint32_t)uslope->data_i.shifter) <<
++                      SHIFT(CDP_S_LUT_LO_SLOPE_SHIFT_0,
++                                      LUT_LO_SLOPE_UFLOW_SHIFT))&
++                      MASK(CDP_S_LUT_LO_SLOPE_SHIFT_0,
++                                      LUT_LO_SLOPE_UFLOW_SHIFT)) |
++                      ((((uint32_t)oslope->data_i.shifter) <<
++                      SHIFT(CDP_S_LUT_LO_SLOPE_SHIFT_0,
++                                      LUT_LO_SLOPE_OFLOW_SHIFT))&
++                      MASK(CDP_S_LUT_LO_SLOPE_SHIFT_0,
++                                      LUT_LO_SLOPE_OFLOW_SHIFT));
++              dla_reg_write(engine->driver_context,
++                              reg_base + lo_slope_shift_offset[is_sdp], reg);
++      }
++}
++
++int
++validate_data_cube(struct dla_data_cube src_data_cube,
++                      struct dla_data_cube dst_data_cube,
++                      uint8_t mem_type)
++{
++      int32_t ret = 0;
++
++      dla_trace("Enter: %s", __func__);
++
++      if ((src_data_cube.width > DCUBE_MAX_WIDTH) ||
++          (src_data_cube.height > DCUBE_MAX_HEIGHT) ||
++          (src_data_cube.channel > DCUBE_MAX_CHANNEL)) {
++              dla_error("Invalid SrcInput Cude[W: %u, H: %u, C: %u]",
++                              src_data_cube.width, src_data_cube.height,
++                              src_data_cube.channel);
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      if ((dst_data_cube.width > DCUBE_MAX_WIDTH) ||
++          (dst_data_cube.height > DCUBE_MAX_HEIGHT) ||
++          (dst_data_cube.channel > DCUBE_MAX_CHANNEL)) {
++              dla_error("Invalid DstInput Cude[W: %u, H: %u, C: %u]",
++                              dst_data_cube.width, dst_data_cube.height,
++                              dst_data_cube.channel);
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      if (src_data_cube.type > mem_type) {
++              dla_error("Invalid src_data.mem_type: %u\n", src_data_cube.type);
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      if (dst_data_cube.type > mem_type) {
++              dla_error("Invalid dst_data.mem_type: %u\n", dst_data_cube.type);
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
++
++int
++validate_precision(uint8_t precision, uint8_t map_precision)
++{
++      int32_t ret = 0;
++
++      if (precision >= map_precision) {
++              dla_error("Invalid precision: %u\n", precision);
++              ret = ERR(INVALID_INPUT);
++      }
++
++      RETURN(ret);
++}
+--- /dev/null
++++ b/drivers/nvdla/common.h
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __FIRMWARE_COMMON_H_
++#define __FIRMWARE_COMMON_H_
++
++#include <dla_interface.h>
++
++#define DCUBE_MAX_WIDTH               8192
++#define DCUBE_MAX_HEIGHT      8192
++#define DCUBE_MAX_CHANNEL     8192
++
++void update_lut(uint32_t reg_base,
++              struct dla_lut_param *lut,
++              uint8_t precision);
++int32_t validate_data_cube(struct dla_data_cube src_data_cube,
++                      struct dla_data_cube dst_data_cube,
++                      uint8_t mem_type);
++int32_t validate_precision(uint8_t precision,
++                      uint8_t map_precision);
++
++#endif /* __FIRMWARE_COMMON_H_ */
+--- /dev/null
++++ b/drivers/nvdla/conv.c
+@@ -0,0 +1,779 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_err.h>
++#include <dla_interface.h>
++
++#include "common.h"
++#include "dla_engine_internal.h"
++#include "engine_debug.h"
++
++static const uint8_t map_precision[] = {
++      FIELD_ENUM(CDMA_D_MISC_CFG_0, IN_PRECISION, INT8),
++      FIELD_ENUM(CDMA_D_MISC_CFG_0, IN_PRECISION, INT16),
++      FIELD_ENUM(CDMA_D_MISC_CFG_0, IN_PRECISION, FP16),
++};
++
++static const uint8_t map_conv[] = {
++      FIELD_ENUM(CACC_D_MISC_CFG_0, CONV_MODE, DIRECT),
++      FIELD_ENUM(CACC_D_MISC_CFG_0, CONV_MODE, WINOGRAD),
++};
++
++static const uint8_t map_weight_fmt[] = {
++      FIELD_ENUM(CSC_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT, UNCOMPRESSED),
++      FIELD_ENUM(CSC_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT, COMPRESSED),
++};
++
++static const uint8_t map_img_fmt[][2] = {
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_R8), 1},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_R10), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_R12), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_R16), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_R16_I), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_R16_F), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A16B16G16R16), 8},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_X16B16G16R16), 8},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A16B16G16R16_F), 8},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A16Y16U16V16), 8},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_V16U16Y16A16), 8},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A16Y16U16V16_F), 8},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A8B8G8R8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A8R8G8B8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_B8G8R8A8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_R8G8B8A8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_X8B8G8R8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_X8R8G8B8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_B8G8R8X8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_R8G8B8X8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A2B10G10R10), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A2R10G10B10), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_B10G10R10A2), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_R10G10B10A2), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A2Y10U10V10), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_V10U10Y10A2), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_A8Y8U8V8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_V8U8Y8A8), 4},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_Y8___U8V8_N444), 1},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_Y8___V8U8_N444), 1},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_Y10___U10V10_N444), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_Y10___V10U10_N444), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_Y12___U12V12_N444), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_Y12___V12U12_N444), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_Y16___U16V16_N444), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      PIXEL_FORMAT, T_Y16___V16U16_N444), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      DATAIN_FORMAT, FEATURE), 2},
++      {FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                      DATAIN_FORMAT, PIXEL), 1},
++};
++
++static const uint8_t map_pixel[] = {
++      FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0, PIXEL_MAPPING, PITCH_LINEAR),
++};
++
++static const uint8_t map_ram[] = {
++      FIELD_ENUM(CDMA_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, MCIF),
++      FIELD_ENUM(CDMA_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, CVIF),
++};
++
++static const uint8_t map_mean[] = {
++      FIELD_ENUM(CDMA_D_MEAN_FORMAT_0, MEAN_FORMAT, DISABLE),
++      FIELD_ENUM(CDMA_D_MEAN_FORMAT_0, MEAN_FORMAT, ENABLE),
++};
++
++#if STAT_ENABLE
++void
++dla_conv_stat_data(struct dla_processor *processor,
++                                      struct dla_processor_group *group)
++{
++      uint64_t end_time = 0;
++      struct dla_conv_stat_desc *conv_stat;
++
++      conv_stat = &processor->stat_data_desc->conv_stat;
++
++      end_time = dla_get_time_us();
++
++      conv_stat->data_read_stall = cdma_reg_read(D_PERF_DAT_READ_STALL);
++      conv_stat->weight_read_stall = cdma_reg_read(D_PERF_WT_READ_STALL);
++      conv_stat->data_read_latency = cdma_reg_read(D_PERF_DAT_READ_LATENCY);
++      conv_stat->weight_read_latency = cdma_reg_read(D_PERF_WT_READ_LATENCY);
++      conv_stat->nan_data_num = cdma_reg_read(D_NAN_INPUT_DATA_NUM);
++      conv_stat->nan_weight_num = cdma_reg_read(D_NAN_INPUT_WEIGHT_NUM);
++      conv_stat->inf_data_num = cdma_reg_read(D_INF_INPUT_DATA_NUM);
++      conv_stat->inf_weight_num = cdma_reg_read(D_INF_INPUT_WEIGHT_NUM);
++      conv_stat->saturation_count = cacc_reg_read(D_OUT_SATURATION);
++      conv_stat->runtime = (uint32_t)(end_time - group->start_time);
++}
++
++void
++dla_conv_dump_stat(struct dla_processor *processor)
++{
++      struct dla_conv_stat_desc *conv_stat;
++
++      conv_stat = &processor->stat_data_desc->conv_stat;
++
++      dla_debug_conv_stats(conv_stat);
++}
++#endif /* STAT_ENABLE */
++
++static uint32_t
++get_in_format(uint8_t format)
++{
++      uint32_t in_format = 0;
++
++      if (format >= FORMAT_T_R8 && format < FORMAT_FEATURE) {
++              in_format = FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                                              DATAIN_FORMAT, PIXEL);
++      } else if (format == FORMAT_FEATURE) {
++              in_format = FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
++                                              DATAIN_FORMAT, FEATURE);
++      } else {
++              assert(0);
++      }
++
++      return in_format;
++}
++
++void
++dla_conv_set_producer(int32_t group_id, int32_t rdma_group_id)
++{
++      uint32_t reg;
++
++      /* set producer pointer for all sub-modules */
++      reg = group_id << SHIFT(CACC_S_POINTER_0, PRODUCER);
++      cacc_reg_write(S_POINTER, reg);
++      cmac_a_reg_write(S_POINTER, reg);
++      cmac_b_reg_write(S_POINTER, reg);
++      csc_reg_write(S_POINTER, reg);
++      cdma_reg_write(S_POINTER, reg);
++}
++
++int
++dla_conv_enable(struct dla_processor_group *group)
++{
++      uint32_t reg;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_trace("Enter: %s", __func__);
++
++      do {
++              reg = cdma_reg_read(S_CBUF_FLUSH_STATUS);
++      } while (!(reg & MASK(CDMA_S_CBUF_FLUSH_STATUS_0, FLUSH_DONE)));
++
++      if (engine->stat_enable == (uint32_t)1) {
++              cdma_reg_write(D_PERF_ENABLE, 1);
++              group->start_time = dla_get_time_us();
++      }
++
++      /* enable all sub-modules */
++      reg = FIELD_ENUM(CACC_D_OP_ENABLE_0, OP_EN, ENABLE);
++      cacc_reg_write(D_OP_ENABLE, reg);
++      cmac_a_reg_write(D_OP_ENABLE, reg);
++      cmac_b_reg_write(D_OP_ENABLE, reg);
++      csc_reg_write(D_OP_ENABLE, reg);
++      cdma_reg_write(D_OP_ENABLE, reg);
++
++      dla_trace("Exit: %s", __func__);
++
++      RETURN(0);
++}
++
++void
++dla_conv_rdma_check(struct dla_processor_group *group)
++{
++      group->is_rdma_needed = 0;
++}
++
++static int32_t
++processor_conv_program(struct dla_processor_group *group)
++{
++      int32_t ret = 0;
++      uint32_t reg, high, low, shift, mask;
++      uint32_t stride_x, stride_y, pad_x, pad_y;
++      uint64_t weight_address = 0;
++      uint64_t wmb_address = 0;
++      uint64_t wgs_address = 0;
++      uint64_t input_address = 0;
++      uint64_t output_address = 0;
++      uint32_t atom_size = 0;
++      bool weight_compress_support = false;
++      struct dla_engine *engine = dla_get_engine();
++      struct dla_conv_op_desc *conv_op;
++      struct dla_conv_surface_desc *conv_surface;
++
++      dla_trace("Enter: %s", __func__);
++
++      weight_compress_support = engine->config_data->weight_compress_support;
++      atom_size = engine->config_data->atom_size;
++      conv_op = &group->operation_desc->conv_op;
++      conv_surface = &group->surface_desc->conv_surface;
++
++      if (conv_op->weight_format == WEIGHT_FORMAT_COMPRESSED) {
++              ASSERT_GOTO((weight_compress_support), ret, ERR(INVALID_INPUT), exit);
++              ASSERT_GOTO((conv_surface->wmb_data.address != -1),
++                      ret, ERR(INVALID_INPUT), exit);
++              dla_get_dma_cube_address(engine->driver_context,
++                                      engine->task->task_data,
++                                      conv_surface->wmb_data.address,
++                                      conv_surface->wmb_data.offset,
++                                      (void *)&wmb_address,
++                                      DESTINATION_DMA);
++              CHECK_ALIGN(wmb_address, atom_size);
++              CHECK_ALIGN(conv_surface->wmb_data.size, 128);
++
++              ASSERT_GOTO((conv_surface->wgs_data.address != -1),
++                      ret, ERR(INVALID_INPUT), exit);
++              dla_get_dma_cube_address(engine->driver_context,
++                                      engine->task->task_data,
++                                      conv_surface->wgs_data.address,
++                                      conv_surface->wgs_data.offset,
++                                      (void *)&wgs_address,
++                                      DESTINATION_DMA);
++              CHECK_ALIGN(wgs_address, atom_size);
++              CHECK_ALIGN(conv_surface->wgs_data.size, 4);
++      }
++
++      if (conv_surface->weight_data.address != -1) {
++              dla_get_dma_cube_address(engine->driver_context,
++                                      engine->task->task_data,
++                                      conv_surface->weight_data.address,
++                                      conv_surface->weight_data.offset,
++                                      (void *)&weight_address,
++                                      DESTINATION_DMA);
++              CHECK_ALIGN(weight_address, atom_size);
++              CHECK_ALIGN(conv_surface->weight_data.size, 128);
++      }
++
++      if (conv_surface->dst_data.address != -1) {
++              dla_get_dma_cube_address(engine->driver_context,
++                                      engine->task->task_data,
++                                      conv_surface->dst_data.address,
++                                      conv_surface->dst_data.offset,
++                                      (void *)&output_address,
++                                      DESTINATION_DMA);
++              CHECK_ALIGN(output_address, atom_size);
++              CHECK_ALIGN(conv_surface->dst_data.size, atom_size);
++              CHECK_ALIGN(conv_surface->dst_data.line_stride, atom_size);
++              CHECK_ALIGN(conv_surface->dst_data.surf_stride, atom_size);
++      }
++
++      ret = dla_read_input_address(&conv_surface->src_data, &input_address,
++                                      group->op_desc->index,
++                                      group->roi_index,
++                                      map_img_fmt[conv_op->data_format][1]);
++      if (ret)
++              goto exit;
++
++      CHECK_ALIGN(input_address, atom_size);
++
++      ASSERT_GOTO((conv_op->out_cvt.scale  == 1),
++              ret, ERR(INVALID_INPUT), exit);
++      ASSERT_GOTO((conv_op->out_cvt.offset == 0),
++              ret, ERR(INVALID_INPUT), exit);
++
++      /* check if the register group is idle */
++      reg = cacc_reg_read(S_STATUS);
++      mask = group->id ? MASK(CACC_S_STATUS_0, STATUS_1) :
++              MASK(CACC_S_STATUS_0, STATUS_0);
++      shift = group->id ? SHIFT(CACC_S_STATUS_0, STATUS_1) :
++              SHIFT(CACC_S_STATUS_0, STATUS_0);
++      reg = (reg & mask) >> shift;
++      ASSERT_GOTO((reg == FIELD_ENUM(CACC_S_STATUS_0, STATUS_0, IDLE)),
++              ret, ERR(INVALID_INPUT), exit);
++
++      reg = cmac_a_reg_read(S_STATUS);
++      mask = group->id ? MASK(CMAC_A_S_STATUS_0, STATUS_1) :
++        MASK(CMAC_A_S_STATUS_0, STATUS_0);
++      shift = group->id ? SHIFT(CMAC_A_S_STATUS_0, STATUS_1) :
++              SHIFT(CMAC_A_S_STATUS_0, STATUS_0);
++      reg = (reg & mask) >> shift;
++      ASSERT_GOTO((reg == FIELD_ENUM(CMAC_A_S_STATUS_0, STATUS_0, IDLE)),
++              ret, ERR(INVALID_INPUT), exit);
++
++      reg = cmac_b_reg_read(S_STATUS);
++      mask = group->id ? MASK(CMAC_B_S_STATUS_0, STATUS_1) :
++              MASK(CMAC_B_S_STATUS_0, STATUS_0);
++      shift = group->id ? SHIFT(CMAC_B_S_STATUS_0, STATUS_1) :
++              SHIFT(CMAC_B_S_STATUS_0, STATUS_0);
++      reg = (reg & mask) >> shift;
++      ASSERT_GOTO((reg == FIELD_ENUM(CMAC_B_S_STATUS_0, STATUS_0, IDLE)),
++              ret, ERR(INVALID_INPUT), exit);
++
++      reg = csc_reg_read(S_STATUS);
++      mask = group->id ? MASK(CSC_S_STATUS_0, STATUS_1) :
++              MASK(CSC_S_STATUS_0, STATUS_0);
++      shift = group->id ? SHIFT(CSC_S_STATUS_0, STATUS_1) :
++              SHIFT(CSC_S_STATUS_0, STATUS_0);
++      reg = (reg & mask) >> shift;
++      ASSERT_GOTO((reg == FIELD_ENUM(CSC_S_STATUS_0, STATUS_0, IDLE)),
++              ret, ERR(INVALID_INPUT), exit);
++
++      reg = cdma_reg_read(S_STATUS);
++      mask = group->id ? MASK(CDMA_S_STATUS_0, STATUS_1) :
++              MASK(CDMA_S_STATUS_0, STATUS_0);
++      shift = group->id ? SHIFT(CDMA_S_STATUS_0, STATUS_1) :
++              SHIFT(CDMA_S_STATUS_0, STATUS_0);
++      reg = (reg & mask) >> shift;
++      ASSERT_GOTO((reg == FIELD_ENUM(CDMA_S_STATUS_0, STATUS_0, IDLE)),
++              ret, ERR(INVALID_INPUT), exit);
++
++      /* reverse config each sub-module in CC */
++
++      /* CACC */
++      reg = (map_conv[conv_op->conv_mode]
++              << SHIFT(CACC_D_MISC_CFG_0, CONV_MODE)) |
++              (map_precision[conv_op->out_precision]
++              << SHIFT(CACC_D_MISC_CFG_0, PROC_PRECISION));
++      cacc_reg_write(D_MISC_CFG, reg);
++
++      reg = ((conv_surface->dst_data.width - 1)
++              << SHIFT(CACC_D_DATAOUT_SIZE_0_0, DATAOUT_WIDTH)) |
++              ((conv_surface->dst_data.height - 1)
++              << SHIFT(CACC_D_DATAOUT_SIZE_0_0, DATAOUT_HEIGHT));
++      cacc_reg_write(D_DATAOUT_SIZE_0, reg);
++
++      reg = ((conv_surface->dst_data.channel - 1)
++              << SHIFT(CACC_D_DATAOUT_SIZE_1_0, DATAOUT_CHANNEL));
++      cacc_reg_write(D_DATAOUT_SIZE_1, reg);
++
++      low = LOW32BITS(output_address);
++      cacc_reg_write(D_DATAOUT_ADDR, low);
++      cacc_reg_write(D_BATCH_NUMBER, conv_op->batch - 1);
++      cacc_reg_write(D_LINE_STRIDE, conv_surface->dst_data.line_stride);
++      cacc_reg_write(D_SURF_STRIDE, conv_surface->dst_data.surf_stride);
++
++      if (conv_surface->dst_data.width == 1 &&
++                              conv_surface->dst_data.height == 1) {
++              ASSERT_GOTO((((uint32_t)conv_surface->dst_data.line_stride ==
++                      (uint32_t)(conv_surface->dst_data.width * atom_size))),
++                      ret, ERR(INVALID_INPUT), exit);
++              reg = (CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE <<
++                              SHIFT(CACC_D_DATAOUT_MAP_0, LINE_PACKED));
++              reg |= (CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE <<
++                              SHIFT(CACC_D_DATAOUT_MAP_0, SURF_PACKED));
++      } else {
++              reg = (FIELD_ENUM(CACC_D_DATAOUT_MAP_0, LINE_PACKED, FALSE) <<
++                              SHIFT(CACC_D_DATAOUT_MAP_0, LINE_PACKED));
++              reg |= (FIELD_ENUM(CACC_D_DATAOUT_MAP_0, SURF_PACKED, FALSE) <<
++                              SHIFT(CACC_D_DATAOUT_MAP_0, SURF_PACKED));
++      }
++      cacc_reg_write(D_DATAOUT_MAP, reg);
++
++      cacc_reg_write(D_CLIP_CFG, conv_op->out_cvt.truncate);
++
++      /* CMAC */
++      reg = (map_conv[conv_op->conv_mode]
++              << SHIFT(CMAC_A_D_MISC_CFG_0, CONV_MODE)) |
++              (map_precision[conv_op->out_precision]
++              << SHIFT(CMAC_A_D_MISC_CFG_0, PROC_PRECISION));
++      cmac_a_reg_write(D_MISC_CFG, reg);
++      cmac_b_reg_write(D_MISC_CFG, reg);
++
++      /* CSC */
++      reg = (map_conv[conv_op->conv_mode]
++              << SHIFT(CSC_D_MISC_CFG_0, CONV_MODE)) |
++              (map_precision[conv_op->out_precision]
++              << SHIFT(CSC_D_MISC_CFG_0, IN_PRECISION)) |
++              (map_precision[conv_op->out_precision]
++              << SHIFT(CSC_D_MISC_CFG_0, PROC_PRECISION)) |
++              (conv_op->data_reuse
++              << SHIFT(CSC_D_MISC_CFG_0, DATA_REUSE)) |
++              (conv_op->weight_reuse
++              << SHIFT(CSC_D_MISC_CFG_0, WEIGHT_REUSE)) |
++              (conv_op->skip_data_rls
++              << SHIFT(CSC_D_MISC_CFG_0, SKIP_DATA_RLS)) |
++              (conv_op->skip_weight_rls
++              << SHIFT(CSC_D_MISC_CFG_0, SKIP_WEIGHT_RLS));
++      csc_reg_write(D_MISC_CFG, reg);
++
++      reg = (get_in_format(conv_op->data_format) <<
++              SHIFT(CSC_D_DATAIN_FORMAT_0, DATAIN_FORMAT));
++      csc_reg_write(D_DATAIN_FORMAT, reg);
++
++      reg = ((conv_op->input_width_csc - 1)
++              << SHIFT(CSC_D_DATAIN_SIZE_EXT_0_0, DATAIN_WIDTH_EXT)) |
++              ((conv_op->input_height_csc - 1)
++              << SHIFT(CSC_D_DATAIN_SIZE_EXT_0_0, DATAIN_HEIGHT_EXT));
++      csc_reg_write(D_DATAIN_SIZE_EXT_0, reg);
++
++      reg = ((conv_op->input_channel_csc - 1)
++              << SHIFT(CSC_D_DATAIN_SIZE_EXT_1_0, DATAIN_CHANNEL_EXT));
++      csc_reg_write(D_DATAIN_SIZE_EXT_1, reg);
++
++      reg = ((conv_op->batch - 1)
++              << SHIFT(CSC_D_BATCH_NUMBER_0, BATCHES));
++      csc_reg_write(D_BATCH_NUMBER, reg);
++      reg = ((conv_op->post_extension)
++              << SHIFT(CSC_D_POST_Y_EXTENSION_0, Y_EXTENSION));
++      csc_reg_write(D_POST_Y_EXTENSION, reg);
++
++      reg = ((conv_op->entry_per_slice - 1)
++              << SHIFT(CSC_D_ENTRY_PER_SLICE_0, ENTRIES));
++      csc_reg_write(D_ENTRY_PER_SLICE, reg);
++
++      reg = (map_weight_fmt[conv_op->weight_format]
++              << SHIFT(CSC_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT));
++      csc_reg_write(D_WEIGHT_FORMAT, reg);
++
++      reg = ((conv_op->kernel_width_csc - 1)
++              << SHIFT(CSC_D_WEIGHT_SIZE_EXT_0_0, WEIGHT_WIDTH_EXT)) |
++              ((conv_op->kernel_height_csc - 1)
++              << SHIFT(CSC_D_WEIGHT_SIZE_EXT_0_0, WEIGHT_HEIGHT_EXT));
++      csc_reg_write(D_WEIGHT_SIZE_EXT_0, reg);
++
++      reg = ((conv_op->kernel_channel_csc - 1)
++              << SHIFT(CSC_D_WEIGHT_SIZE_EXT_1_0, WEIGHT_CHANNEL_EXT)) |
++              ((conv_surface->dst_data.channel - 1)
++              << SHIFT(CSC_D_WEIGHT_SIZE_EXT_1_0, WEIGHT_KERNEL));
++      csc_reg_write(D_WEIGHT_SIZE_EXT_1, reg);
++
++      csc_reg_write(D_WEIGHT_BYTES, conv_surface->weight_data.size);
++      csc_reg_write(D_WMB_BYTES, conv_surface->wmb_data.size);
++
++      reg = ((conv_op->input_width_cmac - 1)
++              << SHIFT(CSC_D_DATAOUT_SIZE_0_0, DATAOUT_WIDTH)) |
++              ((conv_op->input_height_cmac - 1)
++              << SHIFT(CSC_D_DATAOUT_SIZE_0_0, DATAOUT_HEIGHT));
++      csc_reg_write(D_DATAOUT_SIZE_0, reg);
++
++      reg = ((conv_surface->dst_data.channel - 1)
++              << SHIFT(CSC_D_DATAOUT_SIZE_1_0, DATAOUT_CHANNEL));
++      csc_reg_write(D_DATAOUT_SIZE_1, reg);
++
++      reg = ((conv_surface->dst_data.width *
++                              conv_surface->dst_data.height - 1)
++              << SHIFT(CSC_D_ATOMICS_0, ATOMICS));
++      csc_reg_write(D_ATOMICS, reg);
++      reg = ((conv_op->release - 1)
++              << SHIFT(CSC_D_RELEASE_0, RLS_SLICES));
++      csc_reg_write(D_RELEASE, reg);
++
++      if (conv_op->conv_mode == CONV_MODE_DIRECT) {
++              stride_x = conv_op->conv_stride_x - 1;
++              stride_y = conv_op->conv_stride_y - 1;
++              pad_x = conv_op->pad_x_left;
++              pad_y = conv_op->pad_y_top;
++      } else {
++              stride_x = 0;
++              stride_y = 0;
++              pad_x = 0;
++              pad_y = 0;
++      }
++
++      reg = (stride_x
++              << SHIFT(CSC_D_CONV_STRIDE_EXT_0, CONV_X_STRIDE_EXT)) |
++              (stride_y
++              << SHIFT(CSC_D_CONV_STRIDE_EXT_0, CONV_Y_STRIDE_EXT));
++      csc_reg_write(D_CONV_STRIDE_EXT, reg);
++
++      reg = ((conv_op->dilation_x - 1)
++              << SHIFT(CSC_D_DILATION_EXT_0, X_DILATION_EXT)) |
++              ((conv_op->dilation_y - 1)
++              << SHIFT(CSC_D_DILATION_EXT_0, Y_DILATION_EXT));
++      csc_reg_write(D_DILATION_EXT, reg);
++
++      reg = (pad_x
++              << SHIFT(CSC_D_ZERO_PADDING_0, PAD_LEFT)) |
++              (pad_y
++              << SHIFT(CSC_D_ZERO_PADDING_0, PAD_TOP));
++      csc_reg_write(D_ZERO_PADDING, reg);
++
++      reg = (conv_op->pad_val
++              << SHIFT(CSC_D_ZERO_PADDING_VALUE_0, PAD_VALUE)) &
++              MASK(CSC_D_ZERO_PADDING_VALUE_0, PAD_VALUE);
++      csc_reg_write(D_ZERO_PADDING_VALUE, reg);
++
++      reg = ((conv_op->data_bank - 1)
++              << SHIFT(CSC_D_BANK_0, DATA_BANK)) |
++              ((conv_op->weight_bank - 1)
++              << SHIFT(CSC_D_BANK_0, WEIGHT_BANK));
++      csc_reg_write(D_BANK, reg);
++      csc_reg_write(D_PRA_CFG, conv_op->pra_truncate);
++
++      /* CBUF */
++      /* there's no CBUF register */
++
++      /* CDMA */
++      reg = (map_conv[conv_op->conv_mode]
++              << SHIFT(CDMA_D_MISC_CFG_0, CONV_MODE)) |
++              (map_precision[conv_op->in_precision]
++              << SHIFT(CDMA_D_MISC_CFG_0, IN_PRECISION)) |
++              (map_precision[conv_op->out_precision]
++              << SHIFT(CDMA_D_MISC_CFG_0, PROC_PRECISION)) |
++              (conv_op->data_reuse
++              << SHIFT(CDMA_D_MISC_CFG_0, DATA_REUSE)) |
++              (conv_op->weight_reuse
++              << SHIFT(CDMA_D_MISC_CFG_0, WEIGHT_REUSE)) |
++              (conv_op->skip_data_rls
++              << SHIFT(CDMA_D_MISC_CFG_0, SKIP_DATA_RLS)) |
++              (conv_op->skip_weight_rls
++              << SHIFT(CDMA_D_MISC_CFG_0, SKIP_WEIGHT_RLS));
++      cdma_reg_write(D_MISC_CFG, reg);
++
++      reg = (get_in_format(conv_op->data_format) <<
++              SHIFT(CDMA_D_DATAIN_FORMAT_0, DATAIN_FORMAT)) |
++              (map_img_fmt[conv_op->data_format][0]
++              << SHIFT(CDMA_D_DATAIN_FORMAT_0, PIXEL_FORMAT)) |
++              (map_pixel[conv_op->pixel_mapping]
++              << SHIFT(CDMA_D_DATAIN_FORMAT_0, PIXEL_MAPPING)) |
++              (conv_op->pixel_override
++              << SHIFT(CDMA_D_DATAIN_FORMAT_0, PIXEL_SIGN_OVERRIDE));
++      cdma_reg_write(D_DATAIN_FORMAT, reg);
++
++      reg = ((conv_surface->src_data.width - 1)
++              << SHIFT(CDMA_D_DATAIN_SIZE_0_0, DATAIN_WIDTH)) |
++              ((conv_surface->src_data.height - 1)
++              << SHIFT(CDMA_D_DATAIN_SIZE_0_0, DATAIN_HEIGHT));
++      cdma_reg_write(D_DATAIN_SIZE_0, reg);
++
++      reg = ((conv_surface->src_data.channel - 1)
++              << SHIFT(CDMA_D_DATAIN_SIZE_1_0, DATAIN_CHANNEL));
++      cdma_reg_write(D_DATAIN_SIZE_1, reg);
++
++      reg = ((conv_op->input_width_csc - 1)
++              << SHIFT(CDMA_D_DATAIN_SIZE_EXT_0_0, DATAIN_WIDTH_EXT)) |
++              ((conv_op->input_height_csc - 1)
++              << SHIFT(CDMA_D_DATAIN_SIZE_EXT_0_0, DATAIN_HEIGHT_EXT));
++      cdma_reg_write(D_DATAIN_SIZE_EXT_0, reg);
++
++      reg = (map_ram[conv_surface->src_data.type]
++              << SHIFT(CDMA_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE));
++      cdma_reg_write(D_DAIN_RAM_TYPE, reg);
++
++      high = HIGH32BITS(input_address);
++      low = LOW32BITS(input_address);
++      cdma_reg_write(D_DAIN_ADDR_HIGH_0, high);
++      cdma_reg_write(D_DAIN_ADDR_LOW_0, low);
++
++      high = HIGH32BITS((input_address + conv_surface->offset_u));
++      low = LOW32BITS(input_address + conv_surface->offset_u);
++      cdma_reg_write(D_DAIN_ADDR_HIGH_1, high);
++      cdma_reg_write(D_DAIN_ADDR_LOW_1, low);
++
++      cdma_reg_write(D_LINE_STRIDE, conv_surface->src_data.line_stride);
++      cdma_reg_write(D_SURF_STRIDE, conv_surface->src_data.surf_stride);
++      cdma_reg_write(D_LINE_UV_STRIDE, conv_surface->in_line_uv_stride);
++
++      reg = ((conv_surface->src_data.line_stride ==
++                      ((uint32_t)conv_surface->src_data.width * atom_size))
++              << SHIFT(CDMA_D_DAIN_MAP_0, LINE_PACKED));
++      reg |= ((conv_surface->src_data.surf_stride ==
++                      ((uint32_t)(conv_surface->src_data.width *
++                      conv_surface->src_data.height) * atom_size))
++              << SHIFT(CDMA_D_DAIN_MAP_0, SURF_PACKED));
++      cdma_reg_write(D_DAIN_MAP, reg);
++
++      reg = ((conv_op->batch - 1)
++              << SHIFT(CDMA_D_BATCH_NUMBER_0, BATCHES));
++      cdma_reg_write(D_BATCH_NUMBER, reg);
++
++      cdma_reg_write(D_BATCH_STRIDE, conv_op->batch_stride);
++
++      reg = ((conv_op->entry_per_slice - 1)
++              << SHIFT(CDMA_D_ENTRY_PER_SLICE_0, ENTRIES));
++      cdma_reg_write(D_ENTRY_PER_SLICE, reg);
++
++      reg = ((conv_op->fetch_grain - 1)
++              << SHIFT(CDMA_D_FETCH_GRAIN_0, GRAINS));
++      cdma_reg_write(D_FETCH_GRAIN, reg);
++
++      reg = (map_weight_fmt[conv_op->weight_format]
++              << SHIFT(CDMA_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT));
++      cdma_reg_write(D_WEIGHT_FORMAT, reg);
++
++      reg = ((conv_op->bytes_per_kernel - 1)
++              << SHIFT(CDMA_D_WEIGHT_SIZE_0_0, BYTE_PER_KERNEL));
++      cdma_reg_write(D_WEIGHT_SIZE_0, reg);
++
++      reg = ((conv_surface->dst_data.channel - 1)
++              << SHIFT(CDMA_D_WEIGHT_SIZE_1_0, WEIGHT_KERNEL));
++      cdma_reg_write(D_WEIGHT_SIZE_1, reg);
++
++      reg = (map_ram[conv_surface->weight_data.type]
++              << SHIFT(CDMA_D_WEIGHT_RAM_TYPE_0, WEIGHT_RAM_TYPE));
++      cdma_reg_write(D_WEIGHT_RAM_TYPE, reg);
++
++      high = HIGH32BITS(weight_address);
++      low = LOW32BITS(weight_address);
++      cdma_reg_write(D_WEIGHT_ADDR_HIGH, high);
++      cdma_reg_write(D_WEIGHT_ADDR_LOW, low);
++      cdma_reg_write(D_WEIGHT_BYTES, conv_surface->weight_data.size);
++
++      if (conv_op->weight_format == WEIGHT_FORMAT_COMPRESSED) {
++              high = HIGH32BITS(wgs_address);
++              low = LOW32BITS(wgs_address);
++              cdma_reg_write(D_WGS_ADDR_HIGH, high);
++              cdma_reg_write(D_WGS_ADDR_LOW, low);
++
++              high = HIGH32BITS(wmb_address);
++              low = LOW32BITS(wmb_address);
++              cdma_reg_write(D_WMB_ADDR_HIGH, high);
++              cdma_reg_write(D_WMB_ADDR_LOW, low);
++              cdma_reg_write(D_WMB_BYTES, conv_surface->wmb_data.size);
++      }
++
++      reg = (map_mean[conv_op->mean_format]
++              << SHIFT(CDMA_D_MEAN_FORMAT_0, MEAN_FORMAT));
++      cdma_reg_write(D_MEAN_FORMAT, reg);
++
++      if (conv_op->mean_format == MEAN_FORMAT_ENABLE) {
++              reg = ((conv_op->mean_ry
++                      << SHIFT(CDMA_D_MEAN_GLOBAL_0_0, MEAN_RY)) &
++                      MASK(CDMA_D_MEAN_GLOBAL_0_0, MEAN_RY)) |
++                      ((conv_op->mean_gu
++                      << SHIFT(CDMA_D_MEAN_GLOBAL_0_0, MEAN_GU)) &
++                      MASK(CDMA_D_MEAN_GLOBAL_0_0, MEAN_GU));
++              cdma_reg_write(D_MEAN_GLOBAL_0, reg);
++
++              reg = ((conv_op->mean_bv
++                      << SHIFT(CDMA_D_MEAN_GLOBAL_1_0, MEAN_BV))&
++                      MASK(CDMA_D_MEAN_GLOBAL_1_0, MEAN_BV)) |
++                      ((conv_op->mean_ax
++                      << SHIFT(CDMA_D_MEAN_GLOBAL_1_0, MEAN_AX))&
++                      MASK(CDMA_D_MEAN_GLOBAL_1_0, MEAN_AX));
++              cdma_reg_write(D_MEAN_GLOBAL_1, reg);
++      }
++
++      if (conv_op->in_cvt.enable) {
++              reg = ((FIELD_ENUM(CDMA_D_CVT_CFG_0, CVT_EN, ENABLE))
++                      << SHIFT(CDMA_D_CVT_CFG_0, CVT_EN)) |
++                      (conv_op->in_cvt.truncate
++                      << SHIFT(CDMA_D_CVT_CFG_0, CVT_TRUNCATE));
++              cdma_reg_write(D_CVT_CFG, reg);
++              cdma_reg_write(D_CVT_OFFSET, conv_op->in_cvt.offset);
++              cdma_reg_write(D_CVT_SCALE, conv_op->in_cvt.scale);
++      } else {
++              reg = ((FIELD_ENUM(CDMA_D_CVT_CFG_0, CVT_EN, DISABLE))
++                      << SHIFT(CDMA_D_CVT_CFG_0, CVT_EN));
++              cdma_reg_write(D_CVT_CFG, reg);
++      }
++
++      reg = ((conv_op->conv_stride_x - 1)
++              << SHIFT(CDMA_D_CONV_STRIDE_0, CONV_X_STRIDE)) |
++              ((conv_op->conv_stride_y - 1)
++              << SHIFT(CDMA_D_CONV_STRIDE_0, CONV_Y_STRIDE));
++      cdma_reg_write(D_CONV_STRIDE, reg);
++
++      reg = (conv_op->pad_x_left <<
++              SHIFT(CDMA_D_ZERO_PADDING_0, PAD_LEFT)) |
++              (conv_op->pad_x_right
++              << SHIFT(CDMA_D_ZERO_PADDING_0, PAD_RIGHT)) |
++              (conv_op->pad_y_top
++              << SHIFT(CDMA_D_ZERO_PADDING_0, PAD_TOP)) |
++              (conv_op->pad_y_bottom
++              << SHIFT(CDMA_D_ZERO_PADDING_0, PAD_BOTTOM));
++      cdma_reg_write(D_ZERO_PADDING,   reg);
++
++      reg = conv_op->pad_val <<
++              SHIFT(CDMA_D_ZERO_PADDING_VALUE_0, PAD_VALUE) &
++              MASK(CDMA_D_ZERO_PADDING_VALUE_0, PAD_VALUE);
++      cdma_reg_write(D_ZERO_PADDING_VALUE, reg);
++      reg = ((conv_op->weight_bank - 1)
++              << SHIFT(CDMA_D_BANK_0, WEIGHT_BANK)) |
++              ((conv_op->data_bank - 1)
++              << SHIFT(CDMA_D_BANK_0, DATA_BANK));
++      cdma_reg_write(D_BANK, reg);
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
++
++int
++dla_conv_is_ready(struct dla_processor *processor,
++                          struct dla_processor_group *group)
++{
++      return 1;
++}
++
++void
++dla_conv_dump_config(struct dla_processor_group *group)
++{
++      struct dla_conv_op_desc *conv_op;
++      struct dla_conv_surface_desc *conv_surface;
++
++      conv_surface = &group->surface_desc->conv_surface;
++      conv_op = &group->operation_desc->conv_op;
++
++      dla_debug_conv_surface_desc(conv_surface, group->roi_index);
++      dla_debug_conv_op_desc(conv_op, group->roi_index);
++}
++
++int
++dla_conv_program(struct dla_processor_group *group)
++{
++      int32_t ret;
++
++      dla_trace("Enter: %s", __func__);
++
++      ret = processor_conv_program(group);
++      if (ret)
++              goto exit;
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
+--- /dev/null
++++ b/drivers/nvdla/dla_engine_internal.h
+@@ -0,0 +1,361 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __FIRMWARE_DLA_ENGINE_INTERNAL_H_
++#define __FIRMWARE_DLA_ENGINE_INTERNAL_H_
++
++#include <opendla.h>
++#include <dla_engine.h>
++#include <dla_interface.h>
++#include <dla_debug.h>
++
++#include "nvdla_interface.h"
++
++#define BITS(num, range) ((((0xFFFFFFFF >> (31 - (1 ? range))) & \
++                      (0xFFFFFFFF << (0 ? range))) & num) >> \
++                      (0 ? range))
++#define HIGH32BITS(val64bit) ((uint32_t)(val64bit >> 32))
++#define LOW32BITS(val64bit) ((uint32_t)(val64bit))
++
++#ifdef MIN
++#undef MIN
++#endif /* MIN */
++
++#ifdef MAX
++#undef MAX
++#endif /* MAX */
++
++#define MIN(a, b) ((a) > (b) ? (b) : (a))
++#define MAX(a, b) ((a) > (b) ? (a) : (b))
++
++/*********************************************************/
++/******************** Utilities **************************/
++/*********************************************************/
++#ifdef DEBUG
++#define CHECK_ALIGN(val, align)                assert((val&(align-1)) == 0)
++#else
++#define CHECK_ALIGN(val, align)
++#endif /* DEBUG */
++
++#define MASK(reg, field)              (reg##_##field##_FIELD)
++#define FIELD_ENUM(r, f, e)           (r##_##f##_##e)
++#define SHIFT(reg, field)             (reg##_##field##_SHIFT)
++
++#define GLB_REG(name)                GLB_##name##_0
++#define MCIF_REG(name)               MCIF_##name##_0
++#define CVIF_REG(name)               CVIF_##name##_0
++#define BDMA_REG(name)               BDMA_##name##_0
++#define CDMA_REG(name)               CDMA_##name##_0
++#define CSC_REG(name)                CSC_##name##_0
++#define CMAC_A_REG(name)             CMAC_A_##name##_0
++#define CMAC_B_REG(name)             CMAC_B_##name##_0
++#define CACC_REG(name)               CACC_##name##_0
++#define SDP_RDMA_REG(name)           SDP_RDMA_##name##_0
++#define SDP_REG(name)                SDP_##name##_0
++#define PDP_RDMA_REG(name)           PDP_RDMA_##name##_0
++#define PDP_REG(name)                PDP_##name##_0
++#define CDP_RDMA_REG(name)           CDP_RDMA_##name##_0
++#define CDP_REG(name)                CDP_##name##_0
++#define RBK_REG(name)                RBK_##name##_0
++
++/* alias for register read for each sub-module */
++#define glb_reg_read(reg)           reg_read(GLB_REG(reg))
++#define bdma_reg_read(reg)          reg_read(BDMA_REG(reg))
++#define cdma_reg_read(reg)          reg_read(CDMA_REG(reg))
++#define csc_reg_read(reg)           reg_read(CSC_REG(reg))
++#define cmac_a_reg_read(reg)        reg_read(CMAC_A_REG(reg))
++#define cmac_b_reg_read(reg)        reg_read(CMAC_B_REG(reg))
++#define cacc_reg_read(reg)          reg_read(CACC_REG(reg))
++#define sdp_rdma_reg_read(reg)      reg_read(SDP_RDMA_REG(reg))
++#define sdp_reg_read(reg)           reg_read(SDP_REG(reg))
++#define pdp_rdma_reg_read(reg)      reg_read(PDP_RDMA_REG(reg))
++#define pdp_reg_read(reg)           reg_read(PDP_REG(reg))
++#define cdp_rdma_reg_read(reg)      reg_read(CDP_RDMA_REG(reg))
++#define cdp_reg_read(reg)           reg_read(CDP_REG(reg))
++#define rubik_reg_read(reg)         reg_read(RBK_REG(reg))
++
++/* alias for register write for each sub-module */
++#define glb_reg_write(reg, val)      reg_write(GLB_REG(reg), val)
++#define bdma_reg_write(reg, val)     reg_write(BDMA_REG(reg), val)
++#define cdma_reg_write(reg, val)     reg_write(CDMA_REG(reg), val)
++#define csc_reg_write(reg, val)      reg_write(CSC_REG(reg), val)
++#define cmac_a_reg_write(reg, val)   reg_write(CMAC_A_REG(reg), val)
++#define cmac_b_reg_write(reg, val)   reg_write(CMAC_B_REG(reg), val)
++#define cacc_reg_write(reg, val)     reg_write(CACC_REG(reg), val)
++#define sdp_rdma_reg_write(reg, val) reg_write(SDP_RDMA_REG(reg), val)
++#define sdp_reg_write(reg, val)      reg_write(SDP_REG(reg), val)
++#define pdp_rdma_reg_write(reg, val) reg_write(PDP_RDMA_REG(reg), val)
++#define pdp_reg_write(reg, val)      reg_write(PDP_REG(reg), val)
++#define cdp_rdma_reg_write(reg, val) reg_write(CDP_RDMA_REG(reg), val)
++#define cdp_reg_write(reg, val)      reg_write(CDP_REG(reg), val)
++#define rubik_reg_write(reg, val)    reg_write(RBK_REG(reg), val)
++
++void reg_write(uint32_t addr, uint32_t reg);
++uint32_t reg_read(uint32_t addr);
++
++/**
++ * Operation descriptor cache functions
++ */
++void
++dla_put_op_desc(struct dla_common_op_desc *op_desc);
++struct dla_common_op_desc
++*dla_get_op_desc(struct dla_task *task,
++                         int16_t index,
++                         uint8_t op_type,
++                         uint8_t roi_index);
++void
++dla_dump_op_desc(struct dla_common_op_desc *desc);
++void
++dla_get_refcount(struct dla_common_op_desc *op_desc);
++void
++dla_init_op_cache(struct dla_engine *engine);
++
++/**
++ * Operation completion handler
++ */
++int
++dla_op_completion(struct dla_processor *processor,
++                    struct dla_processor_group *group);
++
++int32_t
++dla_read_lut(struct dla_engine *engine, int16_t index, void *dst);
++int
++dla_enable_intr(uint32_t mask);
++int
++dla_disable_intr(uint32_t mask);
++int
++utils_get_free_group(struct dla_processor *processor,
++                      uint8_t *group_id,
++                      uint8_t *rdma_id);
++int32_t
++dla_get_dma_cube_address(void *driver_context,
++                                              void *task_data,
++                                              int16_t index,
++                                              uint32_t offset,
++                                              void *dst_ptr,
++                                              uint32_t destination);
++int
++dla_read_input_address(struct dla_data_cube *data,
++                     uint64_t *address,
++                     int16_t op_index,
++                     uint8_t roi_index,
++                     uint8_t bpp);
++
++/**
++ * BDMA operations
++ */
++void
++dla_bdma_set_producer(int32_t group_id, int32_t rdma_group_id);
++int
++dla_bdma_enable(struct dla_processor_group *group);
++int
++dla_bdma_program(struct dla_processor_group *group);
++int
++dla_bdma_is_ready(struct dla_processor *processor,
++                          struct dla_processor_group *group);
++void
++dla_bdma_dump_config(struct dla_processor_group *group);
++void
++dla_bdma_rdma_check(struct dla_processor_group *group);
++
++#if STAT_ENABLE
++void
++dla_bdma_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group);
++void
++dla_bdma_dump_stat(struct dla_processor *processor);
++
++#else
++static inline void
++dla_bdma_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group) {}
++static inline void
++dla_bdma_dump_stat(struct dla_processor *processor) {}
++#endif
++
++/**
++ * Convolution operations
++ */
++void
++dla_conv_set_producer(int32_t group_id, int32_t rdma_group_id);
++int
++dla_conv_enable(struct dla_processor_group *group);
++int
++dla_conv_program(struct dla_processor_group *group);
++int
++dla_conv_is_ready(struct dla_processor *processor,
++                          struct dla_processor_group *group);
++void
++dla_conv_dump_config(struct dla_processor_group *group);
++void
++dla_conv_rdma_check(struct dla_processor_group *group);
++
++#if STAT_ENABLE
++void
++dla_conv_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group);
++void
++dla_conv_dump_stat(struct dla_processor *processor);
++
++#else
++static inline void
++dla_conv_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group) {}
++static inline void
++dla_conv_dump_stat(struct dla_processor *processor) {}
++#endif /* STAT_ENABLE */
++
++/**
++ * SDP operations
++ */
++void
++dla_sdp_set_producer(int32_t group_id, int32_t rdma_group_id);
++int
++dla_sdp_enable(struct dla_processor_group *group);
++int
++dla_sdp_program(struct dla_processor_group *group);
++int
++dla_sdp_is_ready(struct dla_processor *processor,
++                         struct dla_processor_group *group);
++void
++dla_sdp_dump_config(struct dla_processor_group *group);
++void
++dla_sdp_rdma_check(struct dla_processor_group *group);
++
++#if STAT_ENABLE
++void
++dla_sdp_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group);
++void
++dla_sdp_dump_stat(struct dla_processor *processor);
++
++#else
++static inline void
++dla_sdp_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group) {}
++static inline void
++dla_sdp_dump_stat(struct dla_processor *processor) {}
++#endif
++
++/**
++ * PDP operations
++ */
++void
++dla_pdp_set_producer(int32_t group_id, int32_t rdma_group_id);
++int
++dla_pdp_enable(struct dla_processor_group *group);
++int
++dla_pdp_program(struct dla_processor_group *group);
++int
++dla_pdp_is_ready(struct dla_processor *processor,
++                         struct dla_processor_group *group);
++void
++dla_pdp_dump_config(struct dla_processor_group *group);
++void
++dla_pdp_rdma_check(struct dla_processor_group *group);
++
++#if STAT_ENABLE
++void
++dla_pdp_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group);
++void
++dla_pdp_dump_stat(struct dla_processor *processor);
++
++#else
++static inline void
++dla_pdp_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group) {}
++static inline void
++dla_pdp_dump_stat(struct dla_processor *processor) {}
++#endif
++
++/**
++ * CDP operations
++ */
++void
++dla_cdp_set_producer(int32_t group_id, int32_t rdma_group_id);
++int
++dla_cdp_enable(struct dla_processor_group *group);
++int
++dla_cdp_program(struct dla_processor_group *group);
++int
++dla_cdp_is_ready(struct dla_processor *processor,
++                         struct dla_processor_group *group);
++void
++dla_cdp_dump_config(struct dla_processor_group *group);
++void
++dla_cdp_rdma_check(struct dla_processor_group *group);
++
++#if STAT_ENABLE
++void
++dla_cdp_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group);
++void
++dla_cdp_dump_stat(struct dla_processor *processor);
++
++#else
++static inline void
++dla_cdp_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group) {}
++static inline void
++dla_cdp_dump_stat(struct dla_processor *processor) {}
++#endif
++
++/**
++ * RUBIK operations
++ */
++void
++dla_rubik_set_producer(int32_t group_id, int32_t rdma_group_id);
++int
++dla_rubik_enable(struct dla_processor_group *group);
++int
++dla_rubik_program(struct dla_processor_group *group);
++int
++dla_rubik_is_ready(struct dla_processor *processor,
++                           struct dla_processor_group *group);
++void
++dla_rubik_dump_config(struct dla_processor_group *group);
++void
++dla_rubik_rdma_check(struct dla_processor_group *group);
++
++#if STAT_ENABLE
++void
++dla_rubik_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group);
++void
++dla_rubik_dump_stat(struct dla_processor *processor);
++
++#else
++static inline void
++dla_rubik_stat_data(struct dla_processor *processor,
++                              struct dla_processor_group *group) {}
++static inline void
++dla_rubik_dump_stat(struct dla_processor *processor) {}
++#endif
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/engine.c
+@@ -0,0 +1,262 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_err.h>
++#include <dla_interface.h>
++
++#include "dla_engine_internal.h"
++#include "common.h"
++
++static const uint32_t map_rdma_ptr_addr[] = {
++      0xFFFFFFFF,
++      0xFFFFFFFF,
++      SDP_REG(RDMA_S_POINTER),
++      PDP_REG(RDMA_S_POINTER),
++      CDP_REG(RDMA_S_POINTER),
++      0xFFFFFFFF,
++};
++
++static const uint32_t map_sts_addr[] = {
++      BDMA_REG(STATUS),
++      CACC_REG(S_STATUS),
++      SDP_REG(S_STATUS),
++      PDP_REG(S_STATUS),
++      CDP_REG(S_STATUS),
++      RBK_REG(S_STATUS),
++};
++
++static const uint32_t map_ptr_addr[] = {
++      BDMA_REG(STATUS),
++      CACC_REG(S_POINTER),
++      SDP_REG(S_POINTER),
++      PDP_REG(S_POINTER),
++      CDP_REG(S_POINTER),
++      RBK_REG(S_POINTER),
++};
++
++int32_t dla_enable_intr(uint32_t mask)
++{
++      uint32_t reg = glb_reg_read(S_INTR_MASK);
++
++      reg = reg & (~mask);
++      glb_reg_write(S_INTR_MASK, reg);
++
++      RETURN(0);
++}
++
++int32_t dla_disable_intr(uint32_t mask)
++{
++      uint32_t reg = glb_reg_read(S_INTR_MASK);
++
++      reg = reg | mask;
++      glb_reg_write(S_INTR_MASK, reg);
++
++      RETURN(0);
++}
++
++uint8_t bdma_grp_sts[2] = {
++      FIELD_ENUM(BDMA_STATUS_0, IDLE, YES),
++      FIELD_ENUM(BDMA_STATUS_0, IDLE, YES)
++};
++
++struct dla_roi_desc roi_desc;
++
++/**
++ * Get DMA data cube address
++ */
++int32_t
++dla_get_dma_cube_address(void *driver_context, void *task_data,
++                                      int16_t index, uint32_t offset, void *dst_ptr,
++                                      uint32_t destination)
++{
++      int32_t ret = 0;
++      uint64_t *pdst = (uint64_t *)dst_ptr;
++       ret = dla_get_dma_address(driver_context, task_data, index,
++                                                              dst_ptr, destination);
++      if (ret)
++              goto exit;
++
++      pdst[0] += offset;
++
++exit:
++      return ret;
++}
++
++/**
++ * Read input buffer address
++ *
++ * For input layer, in case of static ROI this address is read
++ * from address list and index is specified in data cube. In case
++ * dynamic ROI, it has to be read depending on ROI information
++ * and using surface address
++ *
++ * For all other layers, this address is read from address list
++ * using index specified in data cube
++ */
++int
++dla_read_input_address(struct dla_data_cube *data,
++                     uint64_t *address,
++                     int16_t op_index,
++                     uint8_t roi_index,
++                     uint8_t bpp)
++{
++      uint64_t roi_desc_addr;
++      int32_t ret = ERR(INVALID_INPUT);
++      struct dla_engine *en = dla_get_engine();
++
++      /**
++       * If memory type is HW then no address required
++       */
++      if (data->type == DLA_MEM_HW) {
++              ret = 0;
++              goto exit;
++      }
++
++      /**
++       * If address list index is not -1 means this address has to
++       * be read from address list
++       */
++      if (data->address != -1) {
++
++              /**
++               * But if other parameters indicate that this is input layer
++               * for dynamic ROI then it is an error
++               */
++              if (en->network->dynamic_roi &&
++                      en->network->input_layer == op_index)
++                      goto exit;
++              ret = dla_get_dma_cube_address(en->driver_context,
++                                              en->task->task_data,
++                                              data->address,
++                                              data->offset,
++                                              (void *)address,
++                                              DESTINATION_DMA);
++              goto exit;
++      }
++
++      /**
++       * Check if it is dynamic ROI and this is input layer
++       */
++      if (en->network->dynamic_roi && en->network->input_layer == op_index) {
++              if (!en->task->surface_addr)
++                      goto exit;
++
++              /* Calculate address of ROI descriptor in array */
++              roi_desc_addr = en->task->roi_array_addr;
++
++              /* Read ROI descriptor */
++              ret = dla_data_read(en->driver_context,
++                              en->task->task_data,
++                              roi_desc_addr,
++                              (void *)&roi_desc,
++                              sizeof(roi_desc),
++                              sizeof(struct dla_roi_array_desc) +
++                              roi_index * sizeof(struct dla_roi_desc));
++              if (ret)
++                      goto exit;
++
++              /* Calculate ROI address */
++              *address = en->task->surface_addr;
++              *address += (roi_desc.top * data->line_stride) +
++                                              (bpp * roi_desc.left);
++      }
++
++exit:
++      RETURN(ret);
++}
++
++int
++utils_get_free_group(struct dla_processor *processor,
++                   uint8_t *group_id,
++                   uint8_t *rdma_id)
++{
++      int32_t ret = 0;
++      uint32_t pointer;
++      uint32_t hw_consumer_ptr;
++      uint32_t hw_rdma_ptr;
++
++      hw_rdma_ptr = 0;
++
++      if (processor->op_type == DLA_OP_BDMA) {
++              pointer = reg_read(map_ptr_addr[processor->op_type]);
++              hw_consumer_ptr = ((pointer & MASK(BDMA_STATUS_0, GRP0_BUSY)) >>
++                              SHIFT(BDMA_STATUS_0, GRP0_BUSY)) ==
++                              FIELD_ENUM(BDMA_STATUS_0, GRP0_BUSY, YES) ?
++                              1 : 0;
++      } else {
++              pointer = reg_read(map_ptr_addr[processor->op_type]);
++              hw_consumer_ptr = (pointer & MASK(CDP_S_POINTER_0, CONSUMER)) >>
++                              SHIFT(CDP_S_POINTER_0, CONSUMER);
++
++              /**
++               * Read current consumer pointer for RDMA only if processor
++               * has RDMA module
++               */
++              if (map_rdma_ptr_addr[processor->op_type] != 0xFFFFFFFF) {
++                      pointer =
++                      reg_read(map_rdma_ptr_addr[processor->op_type]);
++                      hw_rdma_ptr = (pointer &
++                                      MASK(CDP_S_POINTER_0, CONSUMER)) >>
++                                      SHIFT(CDP_S_POINTER_0, CONSUMER);
++              }
++      }
++
++      /**
++       * If both processors are programmed then exit
++       */
++      if (processor->group_status == 0x3) {
++              ret = ERR(PROCESSOR_BUSY);
++              goto exit;
++      }
++
++      if (!processor->group_status)
++              /**
++               * If both groups are idle then use consumer pointer
++               */
++              *group_id = hw_consumer_ptr;
++      else
++              /**
++               * Here it is assumed that only one group is idle or busy
++               * and hence right shift will work to get correct
++               * group id
++               */
++              *group_id = !(processor->group_status >> 1);
++
++      /**
++       * If both groups are idle then read group id from pointer
++       */
++      if (!processor->rdma_status)
++              *rdma_id = hw_rdma_ptr;
++      else
++              *rdma_id = !(processor->rdma_status >> 1);
++
++exit:
++      RETURN(ret);
++}
+--- /dev/null
++++ b/drivers/nvdla/engine_data.c
+@@ -0,0 +1,303 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <nvdla_interface.h>
++#include <dla_interface.h>
++
++#include "dla_engine_internal.h"
++
++static union dla_operation_container operation_desc[DLA_OP_NUM][DLA_NUM_GROUPS];
++static union dla_surface_container surface_desc[DLA_OP_NUM][DLA_NUM_GROUPS];
++
++static struct dla_task global_task;
++
++static struct dla_engine engine = {
++      .processors[DLA_OP_BDMA] = {
++              .name = "BDMA",
++              .op_type = DLA_OP_BDMA,
++              .program = dla_bdma_program,
++              .enable = dla_bdma_enable,
++              .set_producer = dla_bdma_set_producer,
++              .is_ready = dla_bdma_is_ready,
++              .dump_config = dla_bdma_dump_config,
++              .rdma_check = dla_bdma_rdma_check,
++              .get_stat_data = dla_bdma_stat_data,
++              .dump_stat = dla_bdma_dump_stat,
++              .consumer_ptr = 0,
++              .roi_index = 0,
++              .group_status = 0,
++              .rdma_status = 0,
++              .last_group = 1,
++              .groups[0] = {
++                      .id = 0,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_BDMA][0],
++                      .surface_desc = &surface_desc[DLA_OP_BDMA][0],
++              },
++              .groups[1] = {
++                      .id = 1,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_BDMA][1],
++                      .surface_desc = &surface_desc[DLA_OP_BDMA][1],
++              },
++      },
++      .processors[DLA_OP_CONV] = {
++              .name = "Convolution",
++              .op_type = DLA_OP_CONV,
++              .program = dla_conv_program,
++              .enable = dla_conv_enable,
++              .set_producer = dla_conv_set_producer,
++              .is_ready = dla_conv_is_ready,
++              .dump_config = dla_conv_dump_config,
++              .rdma_check = dla_conv_rdma_check,
++              .get_stat_data = dla_conv_stat_data,
++              .dump_stat = dla_conv_dump_stat,
++              .consumer_ptr = 0,
++              .roi_index = 0,
++              .group_status = 0,
++              .rdma_status = 0,
++              .last_group = 1,
++              .groups[0] = {
++                      .id = 0,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_CONV][0],
++                      .surface_desc = &surface_desc[DLA_OP_CONV][0],
++              },
++              .groups[1] = {
++                      .id = 1,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_CONV][1],
++                      .surface_desc = &surface_desc[DLA_OP_CONV][1],
++              },
++      },
++      .processors[DLA_OP_SDP] = {
++              .name = "SDP",
++              .op_type = DLA_OP_SDP,
++              .program = dla_sdp_program,
++              .enable = dla_sdp_enable,
++              .set_producer = dla_sdp_set_producer,
++              .is_ready = dla_sdp_is_ready,
++              .dump_config = dla_sdp_dump_config,
++              .rdma_check = dla_sdp_rdma_check,
++              .get_stat_data = dla_sdp_stat_data,
++              .dump_stat = dla_sdp_dump_stat,
++              .consumer_ptr = 0,
++              .roi_index = 0,
++              .group_status = 0,
++              .rdma_status = 0,
++              .last_group = 1,
++              .groups[0] = {
++                      .id = 0,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_SDP][0],
++                      .surface_desc = &surface_desc[DLA_OP_SDP][0],
++              },
++              .groups[1] = {
++                      .id = 1,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_SDP][1],
++                      .surface_desc = &surface_desc[DLA_OP_SDP][1],
++              },
++      },
++      .processors[DLA_OP_PDP] = {
++              .name = "PDP",
++              .op_type = DLA_OP_PDP,
++              .program = dla_pdp_program,
++              .enable = dla_pdp_enable,
++              .set_producer = dla_pdp_set_producer,
++              .is_ready = dla_pdp_is_ready,
++              .dump_config = dla_pdp_dump_config,
++              .rdma_check = dla_pdp_rdma_check,
++              .get_stat_data = dla_pdp_stat_data,
++              .dump_stat = dla_pdp_dump_stat,
++              .consumer_ptr = 0,
++              .roi_index = 0,
++              .group_status = 0,
++              .rdma_status = 0,
++              .last_group = 1,
++              .groups[0] = {
++                      .id = 0,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_PDP][0],
++                      .surface_desc = &surface_desc[DLA_OP_PDP][0],
++              },
++              .groups[1] = {
++                      .id = 1,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_PDP][1],
++                      .surface_desc = &surface_desc[DLA_OP_PDP][1],
++              },
++      },
++      .processors[DLA_OP_CDP] = {
++              .name = "CDP",
++              .op_type = DLA_OP_CDP,
++              .program = dla_cdp_program,
++              .enable = dla_cdp_enable,
++              .set_producer = dla_cdp_set_producer,
++              .is_ready = dla_cdp_is_ready,
++              .dump_config = dla_cdp_dump_config,
++              .rdma_check = dla_cdp_rdma_check,
++              .get_stat_data = dla_cdp_stat_data,
++              .dump_stat = dla_cdp_dump_stat,
++              .consumer_ptr = 0,
++              .roi_index = 0,
++              .group_status = 0,
++              .rdma_status = 0,
++              .last_group = 1,
++              .groups[0] = {
++                      .id = 0,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_CDP][0],
++                      .surface_desc = &surface_desc[DLA_OP_CDP][0],
++              },
++              .groups[1] = {
++                      .id = 1,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_CDP][1],
++                      .surface_desc = &surface_desc[DLA_OP_CDP][1],
++              },
++      },
++
++      .processors[DLA_OP_RUBIK] = {
++              .name = "RUBIK",
++              .op_type = DLA_OP_RUBIK,
++              .program = dla_rubik_program,
++              .enable = dla_rubik_enable,
++              .set_producer = dla_rubik_set_producer,
++              .is_ready = dla_rubik_is_ready,
++              .dump_config = dla_rubik_dump_config,
++              .rdma_check = dla_rubik_rdma_check,
++              .get_stat_data = dla_rubik_stat_data,
++              .dump_stat = dla_rubik_dump_stat,
++              .consumer_ptr = 0,
++              .roi_index = 0,
++              .group_status = 0,
++              .rdma_status = 0,
++              .last_group = 1,
++              .groups[0] = {
++                      .id = 0,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_RUBIK][0],
++                      .surface_desc = &surface_desc[DLA_OP_RUBIK][0],
++              },
++              .groups[1] = {
++                      .id = 1,
++                      .rdma_id = 0,
++                      .active = 0,
++                      .events = 0,
++                      .roi_index = 0,
++                      .is_rdma_needed = 0,
++                      .lut_index = -1,
++                      .operation_desc = &operation_desc[DLA_OP_RUBIK][1],
++                      .surface_desc = &surface_desc[DLA_OP_RUBIK][1],
++              },
++      },
++
++};
++
++struct dla_engine *dla_get_engine(void)
++{
++      return &engine;
++}
++
++int32_t dla_register_driver(void **engine_context, void *driver_context)
++{
++      *engine_context = &engine;
++      engine.task = &global_task;
++      engine.driver_context = driver_context;
++      engine.task->task_data = NULL;
++
++      dla_init_op_cache(&engine);
++
++      RETURN(0);
++}
++
++uint32_t reg_read(uint32_t addr)
++{
++      return dla_reg_read(engine.driver_context, addr);
++}
++
++void reg_write(uint32_t addr, uint32_t reg)
++{
++      dla_reg_write(engine.driver_context, addr, reg);
++}
+--- /dev/null
++++ b/drivers/nvdla/engine_debug.c
+@@ -0,0 +1,551 @@
++/*
++ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <dla_debug.h>
++#include <dla_interface.h>
++#include <dla_sched.h>
++
++#include "engine_debug.h"
++
++#if DEBUG_NETWORK_DATA
++
++void
++dla_debug_network_desc(struct dla_network_desc *nd)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW dla_network_desc\n");
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("op desc index      = %d\n", nd->operation_desc_index);
++      dla_debug("surface desc index = %d\n", nd->surface_desc_index);
++      dla_debug("dep graph index    = %d\n", nd->dependency_graph_index);
++      dla_debug("lut data index     = %d\n", nd->lut_data_index);
++      dla_debug("stat_list_index    = %d\n", nd->stat_list_index);
++      dla_debug("roi array index    = %d\n", nd->roi_array_index);
++      dla_debug("surface index      = %d\n", nd->surface_index);
++      dla_debug("num rois           = %u\n", nd->num_rois);
++      dla_debug("num ops            = %u\n", nd->num_operations);
++      dla_debug("num luts           = %u\n", nd->num_luts);
++      dla_debug("num addr           = %u\n", nd->num_addresses);
++      dla_debug("input layer        = %u\n", nd->input_layer);
++      dla_debug("dynamic roi        = %u\n", nd->dynamic_roi);
++}
++
++static void
++dla_debug_bdma_transfer(struct dla_bdma_transfer_desc *tr, int32_t id)
++{
++      dla_debug("transfer[%d]            = [ dla_bdma_transfer_desc =>\n", id);
++      dla_debug("    source_address      = %x\n", tr->source_address);
++      dla_debug("    destination_address = %x\n", tr->destination_address);
++      dla_debug("    line_size           = %x\n", tr->line_size);
++      dla_debug("    line_repeat         = %x\n", tr->line_repeat);
++      dla_debug("    source_line         = %x\n", tr->source_line);
++      dla_debug("    destination_line    = %x\n", tr->destination_line);
++      dla_debug("    surface_repeat      = %x\n", tr->surface_repeat);
++      dla_debug("    source_surface      = %x\n", tr->source_surface);
++      dla_debug("    destination_surface = %x\n", tr->destination_surface);
++}
++
++void
++dla_debug_bdma_surface_desc(struct dla_bdma_surface_desc *desc, int32_t roi)
++{
++      int32_t i;
++
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_bdma_surface_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("source_type      = %u\n", desc->source_type);
++      dla_debug("destination_type = %u\n", desc->destination_type);
++      dla_debug("num_transfers    = %u\n", desc->num_transfers);
++      for (i = 0; i < desc->num_transfers; i++)
++              dla_debug_bdma_transfer(&desc->transfers[i], i);
++}
++
++void
++dla_debug_bdma_op_desc(struct dla_bdma_op_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_bdma_op_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("num_transfers    = %u\n", desc->num_transfers);
++}
++
++void
++dla_debug_address_info(struct dla_task *tk)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW address list\n");
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("task base address        = %llu\n", tk->base);
++      dla_debug("op desc address          = %llu\n", tk->operation_desc_addr);
++      dla_debug("surface desc address     = %llu\n", tk->surface_desc_addr);
++      dla_debug("dependency graph address = %llu\n", tk->dependency_graph_addr);
++      dla_debug("LUT data address         = %llu\n", tk->lut_data_addr);
++      dla_debug("stat address             = %llu\n", tk->stat_data_addr);
++      dla_debug("ROI array address        = %llu\n", tk->roi_array_addr);
++      dla_debug("surface address          = %llu\n", tk->surface_addr);
++}
++
++void
++dla_debug_op_desc(struct dla_common_op_desc *desc, int32_t roi)
++{
++      int32_t i;
++
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_common_op_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("[%p] Operation index %d ROI %d dep_count %d type %d\n",
++                      (unsigned int *)desc, desc->index, desc->roi_index,
++                      desc->dependency_count, desc->op_type);
++      dla_debug("consumers = [ dla_consumer =>\n");
++      for (i = 0; i < DLA_OP_NUM; i++)
++              dla_debug(" [ %d %d ]", desc->consumers[i].index,
++                                      desc->consumers[i].event);
++      dla_debug("]");
++      dla_debug("fused_parent = [ dla_consumer =>\n");
++      dla_debug(" [ %d %d ]", desc->fused_parent.index,
++                                      desc->fused_parent.event);
++      dla_debug("]");
++}
++
++static void
++dla_debug_data_cube(struct dla_data_cube *cube)
++{
++      dla_debug("    type          = %u\n", cube->type);
++      dla_debug("    address       = %d\n", cube->address);
++      dla_debug("    width         = %x\n", cube->width);
++      dla_debug("    height        = %x\n", cube->height);
++      dla_debug("    channel       = %x\n", cube->channel);
++      dla_debug("    size          = %u\n", cube->size);
++      dla_debug("    line_stride   = %u\n", cube->line_stride);
++      dla_debug("    surf_stride   = %u\n", cube->surf_stride);
++      dla_debug("    plane_stride  = %u\n", cube->plane_stride);
++      dla_debug("]");
++}
++
++static void
++dla_debug_converter(struct dla_cvt_param *cvt)
++{
++      dla_debug("[ scale = %d, truncate = %u, enable = %u, offset = %d ]\n",
++                      cvt->scale, cvt->truncate, cvt->enable, cvt->offset);
++}
++
++static void
++dla_debug_float_data(struct dla_float_data *float_data)
++{
++      dla_debug("[ scale = %d, shifter = %d ]\n",
++                      float_data->scale, float_data->shifter);
++}
++
++static void
++dla_debug_dla_slope(union dla_slope *slope)
++{
++      dla_debug("    data_i =\n");
++      dla_debug_float_data(&slope->data_i);
++      dla_debug("    data_f = %u\n", slope->data_f);
++}
++
++static void
++dla_debug_lut_offset(union dla_lut_offset *offset)
++{
++      dla_debug("    exp_offset = %d\n", offset->exp_offset);
++      dla_debug("    frac_bits  = %d\n", offset->frac_bits);
++}
++
++void
++dla_debug_lut_params(struct dla_lut_param *lut_param)
++{
++      int32_t i, j;
++
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW dla_lut_param\n");
++      dla_debug("---------------------------------------------------------\n");
++
++      dla_debug("linear_exp_table            = [\n");
++      for (i = 0; i < (1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1; i++)
++              dla_debug(" %u", lut_param->linear_exp_table[i]);
++      dla_debug("]");
++
++      dla_debug("linear_only_table           = [\n");
++      for (j = 0; j < (1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1; j++)
++              dla_debug(" %u\n", lut_param->linear_only_table[j]);
++      dla_debug("]\n");
++
++      dla_debug("linear_exp_offset           =\n");
++      dla_debug_lut_offset(&lut_param->linear_exp_offset);
++      dla_debug("linear_only_offset          =\n");
++      dla_debug_lut_offset(&lut_param->linear_only_offset);
++      dla_debug("linear_exp_start            = %llu\n",
++                              lut_param->linear_exp_start);
++      dla_debug("linear_exp_end            = %llu\n",
++                              lut_param->linear_exp_end);
++      dla_debug("linear_only_start           = %llu\n",
++                              lut_param->linear_only_start);
++      dla_debug("linear_only_end           = %llu\n",
++                              lut_param->linear_only_end);
++      dla_debug("linear_exp_underflow_slope  =\n");
++      dla_debug_dla_slope(&lut_param->linear_exp_underflow_slope);
++      dla_debug("linear_exp_overflow_slope   =\n");
++      dla_debug_dla_slope(&lut_param->linear_exp_overflow_slope);
++      dla_debug("linear_only_underflow_slope =\n");
++      dla_debug_dla_slope(&lut_param->linear_only_underflow_slope);
++      dla_debug("linear_only_overflow_slope  =\n");
++      dla_debug_dla_slope(&lut_param->linear_only_overflow_slope);
++      dla_debug("hybrid_priority             = %u\n",
++                              lut_param->hybrid_priority);
++      dla_debug("underflow_priority          = %u\n",
++                              lut_param->underflow_priority);
++      dla_debug("overflow_priority           = %u\n",
++                              lut_param->overflow_priority);
++      dla_debug("method                      = %u\n",
++                              lut_param->method);
++}
++
++void
++dla_debug_bdma_stats(struct dla_bdma_stat_desc *stat)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW STATS: dla_bdma_stat_desc\n");
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("read_stall   = %u\n", stat->read_stall);
++      dla_debug("write_stall  = %u\n", stat->write_stall);
++      dla_debug("runtime      = %u\n", stat->runtime);
++}
++
++void
++dla_debug_conv_surface_desc(struct dla_conv_surface_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_conv_surface_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("weight_data         = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->weight_data);
++      dla_debug("wmb_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->wmb_data);
++      dla_debug("wgs_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->wgs_data);
++      dla_debug("src_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->src_data);
++      dla_debug("dst_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->dst_data);
++      dla_debug("offset_u            = %lld\n", desc->offset_u);
++      dla_debug("in_line_uv_stride   = %u\n", desc->in_line_uv_stride);
++}
++
++void
++dla_debug_conv_op_desc(struct dla_conv_op_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_conv_op_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("conv_mode          = %u\n", desc->conv_mode);
++      dla_debug("data_reuse         = %u\n", desc->data_reuse);
++      dla_debug("weight_reuse       = %u\n", desc->weight_reuse);
++      dla_debug("skip_data_rls      = %u\n", desc->skip_data_rls);
++      dla_debug("skip_weight_rls    = %u\n", desc->skip_weight_rls);
++      dla_debug("entry_per_slice    = %u\n", desc->entry_per_slice);
++      dla_debug("data_format        = %u\n", desc->data_format);
++      dla_debug("pixel_mapping      = %u\n", desc->pixel_mapping);
++      dla_debug("fetch_grain        = %u\n", desc->fetch_grain);
++      dla_debug("batch              = %u\n", desc->batch);
++      dla_debug("weight_format      = %u\n", desc->weight_format);
++      dla_debug("data_bank          = %u\n", desc->data_bank);
++      dla_debug("weight_bank        = %u\n", desc->weight_bank);
++      dla_debug("batch_stride       = %u\n", desc->batch_stride);
++      dla_debug("post_extension     = %u\n", desc->post_extension);
++      dla_debug("pixel_override     = %u\n", desc->pixel_override);
++      dla_debug("release            = %u\n", desc->release);
++      dla_debug("input_width_csc    = %u\n", desc->input_width_csc);
++      dla_debug("input_height_csc   = %u\n", desc->input_height_csc);
++      dla_debug("input_channel_csc  = %u\n", desc->input_channel_csc);
++      dla_debug("kernel_width_csc   = %u\n", desc->kernel_width_csc);
++      dla_debug("kernel_height_csc  = %u\n", desc->kernel_height_csc);
++      dla_debug("kernel_channel_csc = %u\n", desc->kernel_channel_csc);
++      dla_debug("input_width_cmac   = %u\n", desc->input_width_cmac);
++      dla_debug("input_height_cmac  = %u\n", desc->input_height_cmac);
++      dla_debug("bytes_per_kernel   = %u\n", desc->bytes_per_kernel);
++      dla_debug("mean_ry            = %d\n", desc->mean_ry);
++      dla_debug("mean_gu            = %d\n", desc->mean_gu);
++      dla_debug("mean_bv            = %d\n", desc->mean_bv);
++      dla_debug("mean_ax            = %d\n", desc->mean_ax);
++      dla_debug("mean_format        = %u\n", desc->mean_format);
++      dla_debug("conv_stride_x      = %u\n", desc->conv_stride_x);
++      dla_debug("conv_stride_y      = %u\n", desc->conv_stride_y);
++      dla_debug("pad_x_left         = %u\n", desc->pad_x_left);
++      dla_debug("pad_x_right        = %u\n", desc->pad_x_right);
++      dla_debug("pad_y_top          = %u\n", desc->pad_y_top);
++      dla_debug("pad_y_bottom       = %u\n", desc->pad_y_bottom);
++      dla_debug("dilation_x         = %u\n", desc->dilation_x);
++      dla_debug("dilation_y         = %u\n", desc->dilation_y);
++      dla_debug("pra_truncate       = %u\n", desc->pra_truncate);
++      dla_debug("in_precision       = %u\n", desc->in_precision);
++      dla_debug("out_precision      = %u\n", desc->out_precision);
++      dla_debug("pad_val            = %d\n", desc->pad_val);
++      dla_debug("in_cvt             =\n");
++      dla_debug_converter(&desc->in_cvt);
++      dla_debug("out_cvt            =\n");
++      dla_debug_converter(&desc->out_cvt);
++}
++
++void
++dla_debug_conv_stats(struct dla_conv_stat_desc *stat)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW STATS: dla_conv_stat_desc\n");
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("data_read_stall      = %u\n", stat->data_read_stall);
++      dla_debug("weight_read_stall    = %u\n", stat->weight_read_stall);
++      dla_debug("data_read_latency    = %u\n", stat->data_read_latency);
++      dla_debug("weight_read_latency  = %u\n", stat->weight_read_latency);
++      dla_debug("saturation_count     = %u\n", stat->saturation_count);
++      dla_debug("nan_data_num         = %u\n", stat->nan_data_num);
++      dla_debug("nan_weight_num       = %u\n", stat->nan_weight_num);
++      dla_debug("inf_data_num         = %u\n", stat->inf_data_num);
++      dla_debug("inf_weight_num       = %u\n", stat->inf_weight_num);
++      dla_debug("runtime              = %u\n", stat->runtime);
++}
++
++void
++dla_debug_pdp_surface_desc(struct dla_pdp_surface_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_pdp_surface_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("src_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->src_data);
++      dla_debug("dst_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->dst_data);
++}
++
++void
++dla_debug_pdp_op_desc(struct dla_pdp_op_desc *desc, int32_t roi)
++{
++      int32_t i;
++
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_pdp_op_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("precision               = %u\n", desc->precision);
++      dla_debug("padding_value           = [\n");
++      for (i = 0; i < PDP_PAD_VAL_NUM; i++)
++              dla_debug(" %d\n", desc->padding_value[i]);
++      dla_debug("]\n");
++      dla_debug("split_num               = %u\n", desc->split_num);
++      dla_debug("partial_in_width_first  = %u\n",
++                                      desc->partial_in_width_first);
++      dla_debug("partial_in_width_mid    = %u\n", desc->partial_in_width_mid);
++      dla_debug("partial_in_width_last   = %u\n", desc->partial_in_width_last);
++      dla_debug("partial_width_first     = %u\n", desc->partial_width_first);
++      dla_debug("partial_width_mid       = %u\n", desc->partial_width_mid);
++      dla_debug("partial_width_last      = %u\n", desc->partial_width_last);
++      dla_debug("pool_mode               = %u\n", desc->pool_mode);
++      dla_debug("pool_width              = %u\n", desc->pool_width);
++      dla_debug("pool_height             = %u\n", desc->pool_height);
++      dla_debug("stride_x                = %u\n", desc->stride_x);
++      dla_debug("stride_y                = %u\n", desc->stride_y);
++      dla_debug("pad_left                = %u\n", desc->pad_left);
++      dla_debug("pad_right               = %u\n", desc->pad_right);
++      dla_debug("pad_top                 = %u\n", desc->pad_top);
++      dla_debug("pad_bottom              = %u\n", desc->pad_bottom);
++}
++
++void
++dla_debug_pdp_stats(struct dla_pdp_stat_desc *stat)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW STATS: dla_pdp_stat_desc\n");
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("inf_input_num   = %u\n", stat->inf_input_num);
++      dla_debug("nan_input_num   = %u\n", stat->nan_input_num);
++      dla_debug("nan_output_num  = %u\n", stat->nan_output_num);
++      dla_debug("write_stall     = %u\n", stat->write_stall);
++      dla_debug("runtime         = %u\n", stat->runtime);
++}
++
++void
++dla_debug_cdp_surface_desc(struct dla_cdp_surface_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_cdp_surface_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("src_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->src_data);
++      dla_debug("dst_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->dst_data);
++}
++
++void
++dla_debug_cdp_op_desc(struct dla_cdp_op_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_cdp_op_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("in_precision      = %u\n", desc->in_precision);
++      dla_debug("out_precision     = %u\n", desc->out_precision);
++      dla_debug("lut_index         = %d\n", desc->lut_index);
++      dla_debug("in_cvt             =\n");
++      dla_debug_converter(&desc->in_cvt);
++      dla_debug("out_cvt             =\n");
++      dla_debug_converter(&desc->out_cvt);
++      dla_debug("local_size        = %u\n", desc->local_size);
++      dla_debug("bypass_sqsum      = %u\n", desc->bypass_sqsum);
++      dla_debug("bypass_out_mul    = %u\n", desc->bypass_out_mul);
++}
++
++void
++dla_debug_cdp_stats(struct dla_cdp_stat_desc *stat)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW STATS: dla_cdp_stat_desc\n");
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("nan_input_num     = %u\n", stat->nan_input_num);
++      dla_debug("inf_input_num     = %u\n", stat->inf_input_num);
++      dla_debug("nan_output_num    = %u\n", stat->nan_output_num);
++      dla_debug("write_stall       = %u\n", stat->write_stall);
++      dla_debug("lut_uflow         = %u\n", stat->lut_uflow);
++      dla_debug("lut_oflow         = %u\n", stat->lut_oflow);
++      dla_debug("lut_hybrid        = %u\n", stat->lut_hybrid);
++      dla_debug("lut_le_hit        = %u\n", stat->lut_le_hit);
++      dla_debug("lut_lo_hit        = %u\n", stat->lut_lo_hit);
++      dla_debug("saturation_count  = %u\n", stat->saturation_count);
++      dla_debug("runtime           = %u\n", stat->runtime);
++}
++
++void
++dla_debug_rubik_surface_desc(struct dla_rubik_surface_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_rubik_surface_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("src_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->src_data);
++      dla_debug("dst_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->dst_data);
++}
++
++void
++dla_debug_rubik_op_desc(struct dla_rubik_op_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_rubik_op_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("mode       = %u\n", desc->mode);
++      dla_debug("precision  = %u\n", desc->precision);
++      dla_debug("stride_x   = %u\n", desc->stride_x);
++      dla_debug("stride_y   = %u\n", desc->stride_y);
++}
++
++void
++dla_debug_rubik_stats(struct dla_rubik_stat_desc *stat)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW STATS: dla_rubik_stat_desc\n");
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("read_stall   = %u\n", stat->read_stall);
++      dla_debug("write_stall  = %u\n", stat->write_stall);
++      dla_debug("runtime      = %u\n", stat->runtime);
++}
++
++static void
++dla_debug_sdp_op(struct dla_sdp_op *sdp_op)
++{
++      dla_debug("    enable         = %u\n", sdp_op->enable);
++      dla_debug("    alu_type       = %u\n", sdp_op->alu_type);
++      dla_debug("    type           = %u\n", sdp_op->type);
++      dla_debug("    mode           = %u\n", sdp_op->mode);
++      dla_debug("    act            = %u\n", sdp_op->act);
++      dla_debug("    shift_value    = %u\n", sdp_op->shift_value);
++      dla_debug("    truncate       = %u\n", sdp_op->truncate);
++      dla_debug("    precision      = %u\n", sdp_op->precision);
++      dla_debug("    alu_operand    = %d\n", sdp_op->alu_operand);
++      dla_debug("    mul_operand    = %d\n", sdp_op->mul_operand);
++      dla_debug("cvt.alu_cvt          =\n");
++      dla_debug_converter(&sdp_op->cvt.alu_cvt);
++      dla_debug("cvt.mul_cvt          =\n");
++      dla_debug_converter(&sdp_op->cvt.mul_cvt);
++      dla_debug("]\n");
++}
++
++void
++dla_debug_sdp_surface_desc(struct dla_sdp_surface_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_sdp_surface_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("src_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->src_data);
++      dla_debug("x1_data             = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->x1_data);
++      dla_debug("x2_data             = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->x2_data);
++      dla_debug("y_data              = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->y_data);
++      dla_debug("dst_data            = [ dla_data_cube =>\n");
++      dla_debug_data_cube(&desc->dst_data);
++}
++
++void
++dla_debug_sdp_op_desc(struct dla_sdp_op_desc *desc, int32_t roi)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW ROI[%d]: dla_sdp_op_desc\n", roi);
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("src_precision    = %u\n", desc->src_precision);
++      dla_debug("dst_precision    = %u\n", desc->dst_precision);
++      dla_debug("lut_index        = %d\n", desc->lut_index);
++      dla_debug("out_cvt          =\n");
++      dla_debug_converter(&desc->out_cvt);
++      dla_debug("conv_mode        = %u\n", desc->conv_mode);
++      dla_debug("batch_num        = %u\n", desc->batch_num);
++      dla_debug("batch_stride     = %u\n", desc->batch_stride);
++      dla_debug("x1_op            = [ dla_sdp_op =>\n");
++      dla_debug_sdp_op(&desc->x1_op);
++      dla_debug("x2_op            = [ dla_sdp_op =>\n");
++      dla_debug_sdp_op(&desc->x2_op);
++      dla_debug("y_op             = [ dla_sdp_op =>\n");
++      dla_debug_sdp_op(&desc->y_op);
++}
++
++void
++dla_debug_sdp_stats(struct dla_sdp_stat_desc *stat)
++{
++      dla_debug("*********************************************************\n");
++      dla_debug("NVDLA FW STATS: dla_sdp_stat_desc\n");
++      dla_debug("---------------------------------------------------------\n");
++      dla_debug("nan_input_num     = %u\n", stat->nan_input_num);
++      dla_debug("inf_input_num     = %u\n", stat->inf_input_num);
++      dla_debug("nan_output_num    = %u\n", stat->nan_output_num);
++      dla_debug("wdma_write_stall  = %u\n", stat->wdma_write_stall);
++      dla_debug("lut_underflow     = %u\n", stat->lut_underflow);
++      dla_debug("lut_overflow      = %u\n", stat->lut_overflow);
++      dla_debug("lut_hybrid        = %u\n", stat->lut_hybrid);
++      dla_debug("lut_le_hit        = %u\n", stat->lut_le_hit);
++      dla_debug("lut_lo_hit        = %u\n", stat->lut_lo_hit);
++      dla_debug("saturation_count  = %u\n", stat->saturation_count);
++      dla_debug("runtime           = %u\n", stat->runtime);
++}
++#endif /* DEBUG_NETWORK_DATA */
+--- /dev/null
++++ b/drivers/nvdla/engine_debug.h
+@@ -0,0 +1,129 @@
++/*
++ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __FIRMWARE_ENGINE_DEBUG_H_
++#define __FIRMWARE_ENGINE_DEBUG_H_
++
++#include <dla_debug.h>
++#include <dla_interface.h>
++
++#if DEBUG_NETWORK_DATA
++void
++dla_debug_op_desc(struct dla_common_op_desc *desc, int32_t roi);
++void
++dla_debug_network_desc(struct dla_network_desc *network_desc);
++void
++dla_debug_address_info(struct dla_task *task);
++void
++dla_debug_bdma_surface_desc(struct dla_bdma_surface_desc *desc, int32_t roi);
++void
++dla_debug_bdma_op_desc(struct dla_bdma_op_desc *desc, int32_t roi);
++void
++dla_debug_bdma_stats(struct dla_bdma_stat_desc *stat);
++void
++dla_debug_conv_surface_desc(struct dla_conv_surface_desc *desc, int32_t roi);
++void
++dla_debug_conv_op_desc(struct dla_conv_op_desc *desc, int32_t roi);
++void
++dla_debug_conv_stats(struct dla_conv_stat_desc *stat);
++void
++dla_debug_sdp_op_desc(struct dla_sdp_op_desc *desc, int32_t roi);
++void
++dla_debug_sdp_surface_desc(struct dla_sdp_surface_desc *desc, int32_t roi);
++void
++dla_debug_sdp_stats(struct dla_sdp_stat_desc *stat);
++void
++dla_debug_pdp_surface_desc(struct dla_pdp_surface_desc *desc, int32_t roi);
++void
++dla_debug_pdp_op_desc(struct dla_pdp_op_desc *desc, int32_t roi);
++void
++dla_debug_pdp_stats(struct dla_pdp_stat_desc *stat);
++void
++dla_debug_cdp_surface_desc(struct dla_cdp_surface_desc *desc, int32_t roi);
++void
++dla_debug_cdp_op_desc(struct dla_cdp_op_desc *desc, int32_t roi);
++void
++dla_debug_cdp_stats(struct dla_cdp_stat_desc *stat);
++void
++dla_debug_rubik_op_desc(struct dla_rubik_op_desc *desc, int32_t roi);
++void
++dla_debug_rubik_surface_desc(struct dla_rubik_surface_desc *desc, int32_t roi);
++void
++dla_debug_rubik_stats(struct dla_rubik_stat_desc *stat);
++void
++dla_debug_lut_params(struct dla_lut_param *lut_param);
++
++#else
++
++static inline void
++dla_debug_op_desc(struct dla_common_op_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_network_desc(struct dla_network_desc *network_desc) {}
++static inline void
++dla_debug_address_info(struct dla_task *task) {}
++static inline void
++dla_debug_bdma_surface_desc(struct dla_bdma_surface_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_bdma_op_desc(struct dla_bdma_op_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_bdma_stats(struct dla_bdma_stat_desc *stat) {}
++static inline void
++dla_debug_conv_surface_desc(struct dla_conv_surface_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_conv_op_desc(struct dla_conv_op_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_conv_stats(struct dla_conv_stat_desc *stat) {}
++static inline void
++dla_debug_sdp_op_desc(struct dla_sdp_op_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_sdp_surface_desc(struct dla_sdp_surface_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_sdp_stats(struct dla_sdp_stat_desc *stat) {}
++static inline void
++dla_debug_pdp_surface_desc(struct dla_pdp_surface_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_pdp_op_desc(struct dla_pdp_op_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_pdp_stats(struct dla_pdp_stat_desc *stat) {}
++static inline void
++dla_debug_cdp_surface_desc(struct dla_cdp_surface_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_cdp_op_desc(struct dla_cdp_op_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_cdp_stats(struct dla_cdp_stat_desc *stat) {}
++static inline void
++dla_debug_rubik_op_desc(struct dla_rubik_op_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_rubik_surface_desc(struct dla_rubik_surface_desc *desc, int32_t roi) {}
++static inline void
++dla_debug_rubik_stats(struct dla_rubik_stat_desc *stat) {}
++static inline void
++dla_debug_lut_params(struct dla_lut_param *lut_param) {}
++
++#endif /* DEBUG_NETWORK_DATA */
++#endif /* __FIRMWARE_ENGINE_DEBUG_H_ */
+--- /dev/null
++++ b/drivers/nvdla/engine_isr.c
+@@ -0,0 +1,136 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_engine.h>
++#include <dla_interface.h>
++
++#include "dla_engine_internal.h"
++
++int32_t dla_isr_handler(void *engine_data)
++{
++      uint32_t mask;
++      uint32_t reg;
++      struct dla_processor *processor = NULL;
++      struct dla_processor_group *group;
++      struct dla_engine *engine = (struct dla_engine *)engine_data;
++
++      mask = glb_reg_read(S_INTR_MASK);
++      reg = glb_reg_read(S_INTR_STATUS);
++
++      dla_trace("Enter: dla_isr_handler, reg:%x, mask:%x\n", reg, mask);
++      if (reg & MASK(GLB_S_INTR_STATUS_0, CACC_DONE_STATUS0)) {
++              processor = &engine->processors[DLA_OP_CONV];
++              group = &processor->groups[0];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, CACC_DONE_STATUS1)) {
++              processor = &engine->processors[DLA_OP_CONV];
++              group = &processor->groups[1];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, SDP_DONE_STATUS0)) {
++              processor = &engine->processors[DLA_OP_SDP];
++              group = &processor->groups[0];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, SDP_DONE_STATUS1)) {
++              processor = &engine->processors[DLA_OP_SDP];
++              group = &processor->groups[1];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, CDP_DONE_STATUS0)) {
++              processor = &engine->processors[DLA_OP_CDP];
++              group = &processor->groups[0];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, CDP_DONE_STATUS1)) {
++              processor = &engine->processors[DLA_OP_CDP];
++              group = &processor->groups[1];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, RUBIK_DONE_STATUS0)) {
++              processor = &engine->processors[DLA_OP_RUBIK];
++              group = &processor->groups[0];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, RUBIK_DONE_STATUS1)) {
++              processor = &engine->processors[DLA_OP_RUBIK];
++              group = &processor->groups[1];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, PDP_DONE_STATUS0)) {
++              processor = &engine->processors[DLA_OP_PDP];
++              group = &processor->groups[0];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, PDP_DONE_STATUS1)) {
++              processor = &engine->processors[DLA_OP_PDP];
++              group = &processor->groups[1];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, BDMA_DONE_STATUS0)) {
++              processor = &engine->processors[DLA_OP_BDMA];
++              group = &processor->groups[0];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, BDMA_DONE_STATUS1)) {
++              processor = &engine->processors[DLA_OP_BDMA];
++              group = &processor->groups[1];
++              group->events |= (1 << DLA_EVENT_OP_COMPLETED);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_DAT_DONE_STATUS0)) {
++              processor = &engine->processors[DLA_OP_CONV];
++              group = &processor->groups[0];
++              group->events |= (1 << DLA_EVENT_CDMA_DT_DONE);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_DAT_DONE_STATUS1)) {
++              processor = &engine->processors[DLA_OP_CONV];
++              group = &processor->groups[1];
++              group->events |= (1 << DLA_EVENT_CDMA_DT_DONE);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_WT_DONE_STATUS0)) {
++              processor = &engine->processors[DLA_OP_CONV];
++              group = &processor->groups[0];
++              group->events |= (1 << DLA_EVENT_CDMA_WT_DONE);
++      }
++      if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_WT_DONE_STATUS1)) {
++              processor = &engine->processors[DLA_OP_CONV];
++              group = &processor->groups[1];
++              group->events |= (1 << DLA_EVENT_CDMA_WT_DONE);
++      }
++
++      glb_reg_write(S_INTR_STATUS, reg);
++
++      mask = glb_reg_read(S_INTR_MASK);
++      reg = glb_reg_read(S_INTR_STATUS);
++
++      dla_trace("Exit: dla_isr_handler, reg:%x, mask:%x\n", reg, mask);
++      RETURN(0);
++}
+--- /dev/null
++++ b/drivers/nvdla/include/dla_debug.h
+@@ -0,0 +1,94 @@
++/*
++ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __FIRMWARE_DLA_DEBUG_H_
++#define __FIRMWARE_DLA_DEBUG_H_
++
++#define STRINGIFY(s) #s
++#define DEFER_STRINGIFY(s) STRINGIFY(s)
++#define FILELINE DEFER_STRINGIFY(__LINE__)
++#define FILENAME DEFER_STRINGIFY(__FILE__)
++
++#define LOG_EVENT_BDMA_SHIFT          0U
++#define LOG_EVENT_CONV_SHIFT          4U
++#define LOG_EVENT_SDP_SHIFT           8U
++#define LOG_EVENT_PDP_SHIFT           12U
++#define LOG_EVENT_CDP_SHIFT           16U
++#define LOG_EVENT_RBK_SHIFT           20U
++#define LOG_EVENT_GROUP_SHIFT         24U
++#define LOG_EVENT_ROI_SHIFT           28U
++
++#define LOG_TASK_START                        1
++#define LOG_TASK_END                  2
++#define LOG_READ_OP_CONFIG_START      3
++#define LOG_READ_OP_CONFIG_END                4
++#define LOG_READ_SURF_CONFIG_START    5
++#define LOG_READ_SURF_CONFIG_END      6
++#define LOG_PROGRAM_START             7
++#define LOG_PROGRAM_END                       8
++#define LOG_OPERATION_START           9
++#define LOG_OPERATION_END             10
++
++#define LOG_EVENT(roi, group, processor, event)
++
++/**
++ * Used to enable/disable reading stat registers
++ */
++#define STAT_ENABLE           1
++
++/**
++ * Used to print debug network data
++ */
++#define DEBUG_NETWORK_DATA            0
++
++#define pr_dump_stack(format, ...)
++#define dla_trace(format, ...)
++
++#define assert(condition)
++
++#define RETURN(err) { return (err); }
++
++#define DEBUG_ASSERT
++
++#ifdef DEBUG_ASSERT
++#define ASSERT_GOTO(_condition, _ret, _err_value, _goto)      \
++do {                                                          \
++      if (!(_condition)) {                                    \
++              dla_error("Assertion Fail(" FILENAME FILELINE "):" \
++                                      STRINGIFY(_condition)); \
++              _ret = _err_value;                              \
++              goto _goto;                                     \
++      } else {                                                \
++              _ret = 0;                                       \
++      }                                                       \
++} while (0)
++#else
++#define ASSERT_GOTO(_condition, _ret, _err_value, _goto) assert(condition)
++#endif /* DEBUG_ASSERT */
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/include/dla_engine.h
+@@ -0,0 +1,94 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __DLA_ENGINE_H_
++#define __DLA_ENGINE_H_
++
++#include <dla_interface.h>
++#include <dla_sched.h>
++
++struct dla_processor_group {
++      uint8_t id;
++      uint8_t rdma_id;
++      uint8_t active;
++      uint8_t events;
++      uint8_t roi_index;
++      uint8_t is_rdma_needed;
++      uint8_t pending;
++      int32_t lut_index;
++      uint8_t programming;
++      uint64_t start_time;
++
++      struct dla_common_op_desc *op_desc;
++      struct dla_common_op_desc *consumers[DLA_OP_NUM];
++      struct dla_common_op_desc *fused_parent;
++      union dla_operation_container *operation_desc;
++      union dla_surface_container *surface_desc;
++};
++
++struct dla_processor {
++      const char *name;
++      uint8_t op_type;
++      uint8_t consumer_ptr;
++      uint8_t roi_index;
++      uint8_t group_status;
++      uint8_t rdma_status;
++      uint8_t last_group;
++
++      struct dla_common_op_desc *tail_op;
++      struct dla_processor_group groups[DLA_NUM_GROUPS];
++      union dla_stat_container *stat_data_desc;
++
++      int32_t (*is_ready)(struct dla_processor *processor,
++                                struct dla_processor_group *group);
++      int32_t (*enable)(struct dla_processor_group *group);
++      int32_t (*program)(struct dla_processor_group *group);
++      void (*set_producer)(int32_t group_id, int32_t rdma_id);
++      void (*dump_config)(struct dla_processor_group *group);
++      void (*rdma_check)(struct dla_processor_group *group);
++      void (*get_stat_data)(struct dla_processor *processor,
++                              struct dla_processor_group *group);
++      void (*dump_stat)(struct dla_processor *processor);
++};
++
++struct dla_engine {
++      struct dla_task *task;
++      struct dla_config *config_data;
++      struct dla_network_desc *network;
++      struct dla_processor processors[DLA_OP_NUM];
++
++      uint16_t num_proc_hwl;
++      int32_t status;
++      uint32_t stat_enable;
++
++      void *driver_context;
++};
++
++struct dla_engine *dla_get_engine(void);
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/include/dla_err.h
+@@ -0,0 +1,50 @@
++/*
++ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __FIRMWARE_DLA_ERR_H_
++#define __FIRMWARE_DLA_ERR_H_
++
++#define ERR(code) -DLA_ERR_##code
++
++#define DLA_ERR_NONE                  0
++#define DLA_ERR_INVALID_METHOD                1
++#define DLA_ERR_INVALID_TASK          2
++#define DLA_ERR_INVALID_INPUT         3
++#define DLA_ERR_INVALID_FALC_DMA      4
++#define DLA_ERR_INVALID_QUEUE         5
++#define DLA_ERR_INVALID_PREACTION     6
++#define DLA_ERR_INVALID_POSTACTION    7
++#define DLA_ERR_NO_MEM                        8
++#define DLA_ERR_INVALID_DESC_VER      9
++#define DLA_ERR_INVALID_ENGINE_ID     10
++#define DLA_ERR_INVALID_REGION                11
++#define DLA_ERR_PROCESSOR_BUSY                12
++#define DLA_ERR_RETRY                 13
++#define DLA_ERR_TASK_STATUS_MISMATCH  14
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/include/dla_interface.h
+@@ -0,0 +1,886 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __FIRMWARE_DLA_INTERFACE_H_
++#define __FIRMWARE_DLA_INTERFACE_H_
++
++#include <nvdla_interface.h>
++
++/**
++ * @ingroup Processors
++ * @name DLA Processors
++ * Processor modules in DLA engine. Each processor has it's
++ * own operation a.k.a. HW layer. Network is formed using
++ * graph of these operations
++ * @{
++ */
++#define DLA_OP_BDMA           0
++#define DLA_OP_CONV           1
++#define DLA_OP_SDP            2
++#define DLA_OP_PDP            3
++#define DLA_OP_CDP            4
++#define DLA_OP_RUBIK          5
++/** @} */
++
++/**
++ * @ingroup Processors
++ * @name Maximum number of processors
++ * @brief DLA ash 6 processors
++ * @{
++ */
++#define DLA_OP_NUM            6
++/** @} */
++
++/**
++ * @ingroup Processors
++ * @name Number of groups
++ * @brief Each processor has 2 groups of registers
++ * @{
++ */
++#define DLA_NUM_GROUPS                2
++/** @} */
++
++/**
++ * Network descriptor
++ *
++ * Contains all information to execute a network
++ *
++ * @op_head: Index of first operation of each type in operations list
++ * @num_rois: Number of ROIs
++ * @num_operations: Number of operations in one list
++ * @num_luts: Number of LUTs
++ */
++struct dla_network_desc {
++      int16_t operation_desc_index;
++      int16_t surface_desc_index;
++
++      int16_t dependency_graph_index;
++      int16_t lut_data_index;
++
++      int16_t roi_array_index;
++      int16_t surface_index;
++
++      int16_t stat_list_index;
++      int16_t reserved1;
++
++      int16_t op_head[DLA_OP_NUM];
++
++      uint16_t num_rois;
++      uint16_t num_operations;
++
++      uint16_t num_luts;
++      uint16_t num_addresses;
++
++      int16_t input_layer;
++      uint8_t dynamic_roi;
++      uint8_t reserved0;
++} __packed __aligned(4);
++
++/**
++ * @name Memory types
++ * @brief DLA engnine can read/write to/from 3 memory types
++ * @{
++ */
++#define DLA_MEM_MC                    0 /* External DRAM */
++#define DLA_MEM_CV                    1 /* CV-SRAM */
++#define DLA_MEM_HW                    2 /* DLA sub-module */
++/** @} */
++
++/**
++ * @ingroup Events
++ * @name Operation events
++ * @brief Different events triggered by an operations
++ * @{
++ */
++#define DLA_EVENT_OP_COMPLETED                1
++#define DLA_EVENT_OP_PROGRAMMED               2
++#define DLA_EVENT_OP_ENABLED          3
++#define DLA_EVENT_CDMA_WT_DONE                4
++#define DLA_EVENT_CDMA_DT_DONE                5
++/** @} */
++
++struct dla_consumer {
++      int16_t index; /* the index of dla_common_op_desc in dep_graph_addr */
++      uint8_t event;
++      uint8_t res;
++} __packed __aligned(4);
++
++struct dla_common_op_desc {
++      int16_t index; /* set by ucode */
++      int8_t roi_index;
++      uint8_t op_type;
++
++      uint8_t dependency_count;
++      uint8_t reserved0[3];
++
++      struct dla_consumer consumers[DLA_OP_NUM];
++      struct dla_consumer fused_parent;
++} __packed __aligned(4);
++
++struct dla_roi_array_desc {
++      uint32_t array_length;
++
++      uint32_t array_reserved;
++} __packed __aligned(4);
++
++struct dla_roi_desc {
++      uint32_t left;
++
++      uint32_t top;
++
++      uint32_t right;
++
++      uint32_t bottom;
++} __packed __aligned(4);
++
++/**
++ * @ingroup BDMA
++ * @name Maximum BDMA transfers
++ * @brief BDMA supports multiple transfers in operation. This indicates
++ *        maximum number of transfers possible in one operation.
++ * @{
++ */
++#define NUM_MAX_BDMA_OPS      20
++/** @} */
++
++struct dla_bdma_transfer_desc {
++      int16_t source_address;
++      int16_t destination_address;
++
++      uint32_t line_size;
++
++      uint32_t line_repeat;
++
++      uint32_t source_line;
++
++      uint32_t destination_line;
++
++      uint32_t surface_repeat;
++
++      uint32_t source_surface;
++
++      uint32_t destination_surface;
++} __packed __aligned(4);
++
++struct dla_bdma_surface_desc {
++      uint8_t source_type;
++      uint8_t destination_type;
++      uint16_t num_transfers;
++
++      struct dla_bdma_transfer_desc transfers[NUM_MAX_BDMA_OPS];
++} __packed __aligned(4);
++
++struct dla_bdma_op_desc {
++      uint16_t num_transfers;
++      uint16_t reserved0;
++} __packed __aligned(4);
++
++struct dla_bdma_stat_desc {
++      uint32_t read_stall;
++      uint32_t write_stall;
++      uint32_t runtime;
++} __packed __aligned(4);
++
++/**
++ * @ingroup Convolution
++ * @name Convolution mode
++ * @brief Convolution modes support by DLA
++ * @{
++ */
++#define CONV_MODE_DIRECT      0
++#define CONV_MODE_WINOGRAD    1
++/** @} */
++
++/**
++ * @ingroup Processors
++ * @name Precision BPE mapping
++ * @brief Precision formats and Bit Per Elements mapping
++ * @{
++ */
++#define BPE_PRECISION_INT8            1
++#define BPE_PRECISION_INT16           2
++#define BPE_PRECISION_FP16            2
++/** @} */
++
++
++/**
++ * @ingroup Processors
++ * @name Precision types
++ * @brief Precision formats supported by DLA engine
++ * @{
++ */
++#define PRECISION_INT8                0
++#define PRECISION_INT16               1
++#define PRECISION_FP16                2
++/** @} */
++
++/**
++ * @ingroup Processors
++ * @name Data formats
++ * @brief Data formats supported by DLA engine
++ * @{
++ */
++#define FORMAT_T_R8                   0
++#define FORMAT_T_R10                  1
++#define FORMAT_T_R12                  2
++#define FORMAT_T_R16                  3
++#define FORMAT_T_R16_I                        4
++#define FORMAT_T_R16_F                        5
++#define FORMAT_T_A16B16G16R16         6
++#define FORMAT_T_X16B16G16R16         7
++#define FORMAT_T_A16B16G16R16_F               8
++#define FORMAT_T_A16Y16U16V16         9
++#define FORMAT_T_V16U16Y16A16         10
++#define FORMAT_T_A16Y16U16V16_F               11
++#define FORMAT_T_A8B8G8R8             12
++#define FORMAT_T_A8R8G8B8             13
++#define FORMAT_T_B8G8R8A8             14
++#define FORMAT_T_R8G8B8A8             15
++#define FORMAT_T_X8B8G8R8             16
++#define FORMAT_T_X8R8G8B8             17
++#define FORMAT_T_B8G8R8X8             18
++#define FORMAT_T_R8G8B8X8             19
++#define FORMAT_T_A2B10G10R10          20
++#define FORMAT_T_A2R10G10B10          21
++#define FORMAT_T_B10G10R10A2          22
++#define FORMAT_T_R10G10B10A2          23
++#define FORMAT_T_A2Y10U10V10          24
++#define FORMAT_T_V10U10Y10A2          25
++#define FORMAT_T_A8Y8U8V8                     26
++#define FORMAT_T_V8U8Y8A8                     27
++#define FORMAT_T_Y8___U8V8_N444               28
++#define FORMAT_T_Y8___V8U8_N444               29
++#define FORMAT_T_Y10___U10V10_N444    30
++#define FORMAT_T_Y10___V10U10_N444    31
++#define FORMAT_T_Y12___U12V12_N444    32
++#define FORMAT_T_Y12___V12U12_N444    33
++#define FORMAT_T_Y16___U16V16_N444    34
++#define FORMAT_T_Y16___V16U16_N444    35
++#define FORMAT_FEATURE                        36
++/** @} */
++
++/**
++ * @ingroup Convolution
++ * @name Pixel mapping
++ * @brief Pixel mapping formats supported for image input in Convolution
++ * @{
++ */
++#define MAP_PITCH_LINEAR              0
++/** @} */
++
++/**
++ * @ingroup Convolution
++ * @name Weight formats
++ * @brief Weight data formats supported in Convolution
++ * @{
++ */
++#define WEIGHT_FORMAT_UNCOMPRESSED    0
++#define WEIGHT_FORMAT_COMPRESSED      1
++/** @} */
++
++/**
++ * @ingroup Convolution
++ * @name Mean data format
++ * @brief Mean data formats supported in Convolution
++ * @{
++ */
++#define MEAN_FORMAT_DISABLE     0
++#define MEAN_FORMAT_ENABLE      1
++/** @} */
++
++struct dla_cvt_param {
++      int16_t  scale;
++      uint8_t  truncate;
++      uint8_t  enable;
++
++      int32_t  offset;
++} __packed __aligned(4);
++
++struct dla_data_cube {
++      uint16_t type; /* dla_mem_type */
++      int16_t address; /* offset to the actual IOVA in task.address_list */
++
++      uint32_t offset; /* offset within address */
++      uint32_t size;
++
++      /* cube dimensions */
++      uint16_t width;
++      uint16_t height;
++
++      uint16_t channel;
++      uint16_t reserved0;
++
++      /* stride information */
++      uint32_t line_stride;
++      uint32_t surf_stride;
++
++      /* For Rubik only */
++      uint32_t plane_stride;
++} __packed __aligned(4);
++
++#define PIXEL_OVERRIDE_UINT 0
++#define PIXEL_OVERRIDE_INT  1
++
++struct dla_conv_surface_desc {
++      /* Data cube */
++      struct dla_data_cube weight_data;
++      struct dla_data_cube wmb_data;
++      struct dla_data_cube wgs_data;
++      struct dla_data_cube src_data;
++      struct dla_data_cube dst_data;
++
++      /**
++       * u_addr = input_data.source_addr + offset_u
++       * this field should be set when YUV is not interleave format
++       *
++       */
++      int64_t offset_u;
++
++      /* line stride for 2nd plane, must be 32bytes aligned */
++      uint32_t in_line_uv_stride;
++} __packed __aligned(4);
++
++struct dla_conv_op_desc {
++      /* Performance parameters */
++
++      /* dla_conv_mode */
++      uint8_t conv_mode;
++      uint8_t data_reuse;
++      uint8_t weight_reuse;
++      uint8_t skip_data_rls;
++
++      uint8_t skip_weight_rls;
++      uint8_t reserved0;
++      uint16_t entry_per_slice;
++
++      /* dla_data_format */
++      uint8_t data_format;
++      /* dla_pixel_mapping */
++      uint8_t pixel_mapping;
++      /* number of free slices before fetch */
++      uint16_t fetch_grain;
++
++      uint8_t reserved_b[8];
++
++      /* batch_num */
++      uint8_t batch;
++      /* dla_weight_format */
++      uint8_t weight_format;
++      uint8_t data_bank;
++      uint8_t weight_bank;
++
++      /* the offset in bytes of each data cube in a batch */
++      uint32_t batch_stride;
++
++      uint8_t post_extension;
++      uint8_t pixel_override;
++      /* number of slices need to be released */
++      uint16_t release;
++
++       /* The input cube dimension for CSC */
++      uint16_t input_width_csc;
++      uint16_t input_height_csc;
++
++      uint16_t input_channel_csc;
++      uint16_t kernel_width_csc;
++
++      uint16_t kernel_height_csc;
++      uint16_t kernel_channel_csc;
++
++      /* The input cube dimension for CMAC */
++      uint16_t input_width_cmac;
++      uint16_t input_height_cmac;
++
++      /* actual size in bytes */
++      uint32_t bytes_per_kernel;
++
++      /* Algorithm parameters */
++
++      int16_t mean_ry; /* mean value for red in RGB or Y in YUV */
++      int16_t mean_gu; /* mean value for green in RGB or U in YUV */
++
++      int16_t mean_bv; /* mean value for blue in RGB or V in YUV */
++      int16_t mean_ax;
++
++      uint8_t mean_format; /* dla_mean_format */
++      uint8_t conv_stride_x;
++      uint8_t conv_stride_y;
++      uint8_t pad_x_left;
++
++      uint8_t pad_x_right;
++      uint8_t pad_y_top;
++      uint8_t pad_y_bottom;
++      uint8_t dilation_x;
++
++      uint8_t dilation_y;
++      uint8_t reserved2[2];
++
++      /* Precision parameters */
++      uint8_t pra_truncate;
++
++      uint8_t in_precision;
++      /* The output precision from CONV, it's the MAC processing precison */
++      uint8_t out_precision;
++      int16_t pad_val;
++
++      /* input converter parameters */
++      struct dla_cvt_param in_cvt;
++      /* output converter parameters, support truncate only */
++      struct dla_cvt_param out_cvt;
++
++} __packed __aligned(4);
++
++struct dla_conv_stat_desc {
++      uint32_t data_read_stall;
++      uint32_t weight_read_stall;
++      uint32_t data_read_latency;
++      uint32_t weight_read_latency;
++      uint32_t saturation_count;
++      uint32_t nan_data_num;
++      uint32_t nan_weight_num;
++      uint32_t inf_data_num;
++      uint32_t inf_weight_num;
++      uint32_t runtime;
++} __packed __aligned(4);
++
++/**
++ * @ingroup SDP
++ * @name Activation functions
++ * @brief Activation functions supported in SDP
++ * @{
++ */
++#define ACTIVATION_NONE               0
++#define ACTIVATION_RELU               1
++#define ACTIVATION_LUT                2
++#define ACTIVATION_PRELU      3
++/** @} */
++
++/**
++ * @ingroup LUT
++ * @name LUT size
++ * @brief LUT sizes for linear and exponentila LUT
++ * @{
++ */
++#define LUT_LINEAR_EXP_TABLE_ENTRY_LOG2               6
++#define LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2      8
++/** @} */
++
++/**
++ * @ingroup LUT
++ * @name LUT types
++ * @brief DLA supports two types of LUT, linear and exonential
++ * @{
++ */
++#define LUT_LINEAR_EXP_TABLE          0
++#define LUT_LINEAR_ONLY_TABLE         1
++/** @} */
++
++/**
++ * @ingroup LUT
++ * @name LUT methods
++ * @brief DLA supports two types of LUT, linear and exonential
++ * @{
++ */
++#define LUT_METHOD_EXPONENTIAL                0
++#define LUT_METHOD_LINEAR             1
++/** @} */
++
++/**
++ * @ingroup LUT
++ * @name LUT
++ * @brief DLA supports two types of LUT, linear and exonential
++ * @{
++ */
++#define LUT_PRI_LINEAR_EXP            0
++#define LUT_PRI_LINEAR_ONLY           1
++/** @} */
++
++union dla_lut_offset {
++      /**
++       * Number should be substracted on log domain before look up
++       * exponetial table it has the same definition as hardware
++       * thus input scaling should also take into account when
++       * set this field.
++       */
++      int8_t exp_offset;
++      /**
++       * Number of bits should be right shift before looking
++       * up linear table
++       */
++      int8_t frac_bits;
++      uint16_t reserved0;
++};
++
++/**
++ * This struct is used to represent floating point values by INT
++ * suppose we have a float point number fp_x, it will be represented
++ * as:
++ *
++ * fp_x = scale_int_x>>(shifter_x)
++ *
++ * This is very useful for INT pipeline;
++ */
++struct dla_float_data {
++      int16_t scale;
++      int8_t shifter;
++      uint8_t reserved0;
++} __packed __aligned(4);
++
++/**
++ * For INT pipeline, we use the struct above to represent a floating number;
++ * For FP16 pipeline, we should store the FP16 encoded value into a uint16_t
++ * container
++ */
++union dla_slope {
++      struct dla_float_data data_i;
++
++      uint16_t data_f;
++};
++
++struct dla_lut_param {
++      /**
++       * value of expression ((1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1) is 65,
++       * ((1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1) is 257, and int16_t is of
++       * 2Byte. And below two statement's combined memory size is 644 Byte.
++       *
++       * NOTE: below two declaration combined size should always be multiple
++       * of 4.
++       */
++      int16_t linear_exp_table[(1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1];
++      int16_t linear_only_table[(1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1];
++
++      union dla_lut_offset linear_exp_offset;
++      union dla_lut_offset linear_only_offset;
++
++      /**
++       * The start and end point of raw table,
++       * valid when raw_method=LINEAR only
++       */
++      uint64_t linear_exp_start;
++      uint64_t linear_exp_end;
++      uint64_t linear_only_start;
++      uint64_t linear_only_end;
++
++      union dla_slope linear_exp_underflow_slope;
++      union dla_slope linear_exp_overflow_slope;
++      union dla_slope linear_only_underflow_slope;
++      union dla_slope linear_only_overflow_slope;
++
++      /**
++       * dla_lut_priority, when both lut are hit(or one overflow,
++       * the other underflow), which one should be selected as output
++       */
++      uint8_t hybrid_priority;
++      uint8_t underflow_priority;
++      uint8_t overflow_priority;
++      uint8_t method; /* dla_lut_method */
++} __packed __aligned(4);
++
++struct dla_sdp_surface_desc {
++      /* Data cube */
++      /* source input cube, available when SDP working on offline mode */
++      struct dla_data_cube src_data;
++
++      /* X1 input cube */
++      struct dla_data_cube x1_data;
++
++      /* X2 input cube */
++      struct dla_data_cube x2_data;
++
++      /* Y input cube */
++      struct dla_data_cube y_data;
++
++      /* Output cube */
++      struct dla_data_cube dst_data;
++} __packed __aligned(4);
++
++#define SDP_OP_NONE           0
++#define SDP_OP_MUL            1
++#define SDP_OP_ADD            2
++#define SDP_OP_BOTH           3
++
++#define SDP_ALU_OP_MAX                0
++#define SDP_ALU_OP_MIN                1
++#define SDP_ALU_OP_SUM                2
++#define SDP_ALU_OP_EQL                3
++
++#define SDP_OP_PER_LAYER      0
++#define SDP_OP_PER_KERNEL     1
++#define SDP_OP_PER_POINT      2
++
++struct dla_sdp_cvt {
++      struct dla_cvt_param alu_cvt;
++      struct dla_cvt_param mul_cvt;
++} __packed __aligned(4);
++
++struct dla_sdp_op {
++      uint8_t enable;
++      uint8_t alu_type; /* dla_sdp_alu_op_type */
++      uint8_t type; /* dla_sdp_op_type */
++      uint8_t mode; /* dla_sdp_op_mode */
++
++      uint8_t act; /* dla_act_type */
++      uint8_t shift_value; /* left shift */
++      uint8_t truncate;
++      uint8_t precision;
++
++      int32_t alu_operand;
++      int32_t mul_operand;
++
++      struct dla_sdp_cvt  cvt;
++} __packed __aligned(4);
++
++struct dla_sdp_op_desc {
++      /* Precision parameters */
++      /* dla_precision */
++      uint8_t src_precision;
++      uint8_t dst_precision;
++      int16_t lut_index;
++
++      struct dla_cvt_param out_cvt;
++
++      /* Performance parameters */
++      /* dla_conv_mode */
++      uint8_t conv_mode;
++      uint8_t batch_num;
++      uint16_t reserved0;
++
++      uint32_t batch_stride;  /* will be used when batch_num > 1 */
++
++      /* Algorithm parameters */
++      struct dla_sdp_op x1_op;
++      struct dla_sdp_op x2_op;
++      struct dla_sdp_op y_op;
++} __packed __aligned(4);
++
++struct dla_sdp_stat_desc {
++      uint32_t nan_input_num;
++      uint32_t inf_input_num;
++      uint32_t nan_output_num;
++      uint32_t wdma_write_stall;
++      uint32_t lut_underflow;
++      uint32_t lut_overflow;
++      uint32_t lut_hybrid;
++      uint32_t lut_le_hit;
++      uint32_t lut_lo_hit;
++      uint32_t saturation_count;
++      uint32_t runtime;
++} __packed __aligned(4);
++
++#define POOL_MODE_AVG         0
++#define POOL_MODE_MAX         1
++#define POOL_MODE_MIN         2
++
++#define POOL_SIZE_1           0
++#define POOL_SIZE_2           1
++#define POOL_SIZE_3           2
++#define POOL_SIZE_4           3
++#define POOL_SIZE_5           4
++#define POOL_SIZE_6           5
++#define POOL_SIZE_7           6
++#define POOL_SIZE_8           7
++
++#define PDP_PAD_VAL_NUM       7
++
++struct dla_pdp_surface_desc {
++      /* Data cube */
++      struct dla_data_cube src_data;
++
++      struct dla_data_cube dst_data;
++} __packed __aligned(4);
++
++struct dla_pdp_op_desc {
++      /* Performance parameters */
++      uint16_t  partial_in_width_first;
++      uint16_t  partial_in_width_mid;
++
++      uint16_t  partial_in_width_last;
++      uint16_t  partial_width_first;
++
++      uint16_t  partial_width_mid;
++      uint16_t  partial_width_last;
++
++      uint8_t   split_num;
++
++      /* Algorithm parameters */
++      uint8_t  pool_mode; /* dla_pool_mode */
++      uint8_t  pool_width; /* dla_pool_width */
++      uint8_t  pool_height; /* dla_pool_height */
++
++      uint8_t  stride_x;
++      uint8_t  stride_y;
++
++      /**
++       * The left/right padding size,
++       * pad_right might be less than pad_left
++       */
++      uint8_t  pad_left;
++      uint8_t  pad_right;
++
++      /* The top/bottom padding size */
++      uint8_t  pad_top;
++      uint8_t  pad_bottom;
++
++      /* Precision parameters */
++      uint8_t  precision; /* dla_precision */
++      uint8_t  reserved0;
++      /**
++       * if input has non-zero "offset", this value should be set
++       * There'll be 7 different paddding values, the relationship between
++       * those versions are:
++       * padding_value[0] = -offset*scaling;
++       * padding_value[1] = 2*padding_value[0]
++       * padding_value[2] = 3*padding_value[0]
++       * ...
++       * The purpose is to avoid ucode implement FP16
++       * multiplier(for FP16 mode)
++       */
++      int32_t  padding_value[PDP_PAD_VAL_NUM];
++} __packed __aligned(4);
++
++struct dla_pdp_stat_desc {
++      uint32_t inf_input_num;
++      uint32_t nan_input_num;
++      uint32_t nan_output_num;
++      uint32_t write_stall;
++      uint32_t runtime;
++} __packed __aligned(4);
++
++struct dla_cdp_surface_desc {
++      /* Data cube */
++      struct dla_data_cube src_data;
++
++      struct dla_data_cube dst_data;
++} __packed __aligned(4);
++
++struct dla_cdp_op_desc {
++      /* Precision parameters */
++
++      /* dla_precision */
++      uint8_t  in_precision;
++      uint8_t  out_precision;
++      int16_t  lut_index;
++
++      struct dla_cvt_param in_cvt;
++      struct dla_cvt_param out_cvt;
++
++      /* Performance parameters */
++
++      /* Algorithm parameters */
++      uint8_t  local_size;
++      uint8_t  bypass_sqsum;
++      uint8_t  bypass_out_mul;
++      uint8_t  reserved0;
++} __packed __aligned(4);
++
++struct dla_cdp_stat_desc {
++      uint32_t nan_input_num;
++      uint32_t inf_input_num;
++      uint32_t nan_output_num;
++      uint32_t write_stall;
++      uint32_t lut_uflow;
++      uint32_t lut_oflow;
++      uint32_t lut_hybrid;
++      uint32_t lut_le_hit;
++      uint32_t lut_lo_hit;
++      uint32_t saturation_count;
++      uint32_t runtime;
++} __packed __aligned(4);
++
++struct dla_rubik_surface_desc {
++      /* Data cube */
++      struct dla_data_cube src_data;
++
++      struct dla_data_cube dst_data;
++} __packed __aligned(4);
++
++/* rubik mode */
++#define RUBIK_MODE_CONTRACT   0
++#define RUBIK_MODE_SPLIT      1
++#define RUBIK_MODE_MERGE      2
++
++struct dla_rubik_op_desc {
++      /* Precision parameters */
++      uint8_t mode;
++      uint8_t precision;
++      uint8_t stride_x;
++      uint8_t stride_y;
++} __packed __aligned(4);
++
++struct dla_rubik_stat_desc {
++      uint32_t read_stall;
++      uint32_t write_stall;
++      uint32_t runtime;
++} __packed __aligned(4);
++
++union dla_surface_container {
++      struct dla_bdma_surface_desc bdma_surface;
++      struct dla_conv_surface_desc conv_surface;
++      struct dla_sdp_surface_desc sdp_surface;
++      struct dla_pdp_surface_desc pdp_surface;
++      struct dla_cdp_surface_desc cdp_surface;
++      struct dla_rubik_surface_desc rubik_surface;
++};
++
++union dla_operation_container {
++      struct dla_bdma_op_desc bdma_op;
++      struct dla_conv_op_desc conv_op;
++      struct dla_sdp_op_desc sdp_op;
++      struct dla_pdp_op_desc pdp_op;
++      struct dla_cdp_op_desc cdp_op;
++      struct dla_rubik_op_desc rubik_op;
++};
++
++union dla_stat_container {
++      struct dla_bdma_stat_desc bdma_stat;
++      struct dla_conv_stat_desc conv_stat;
++      struct dla_sdp_stat_desc sdp_stat;
++      struct dla_pdp_stat_desc pdp_stat;
++      struct dla_cdp_stat_desc cdp_stat;
++      struct dla_rubik_stat_desc rubik_stat;
++};
++
++/**
++ * status notifier structure
++ *
++ * @address: 64-bit timestamp representing the time at which
++ * the notifier was written
++ * @status_engine: status work captured from HW engine
++ * @subframe: NA
++ * @status_task: status word as configured from an action list
++ */
++struct dla_task_status {
++      uint64_t timestamp;
++
++      uint32_t status_engine;
++
++      uint16_t subframe;
++      uint16_t status_task;
++} __packed __aligned(4);
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/include/dla_sched.h
+@@ -0,0 +1,74 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __DLA_SCHED_H_
++#define __DLA_SCHED_H_
++
++struct dla_task {
++      /* platform specific data to communicate with portability layer */
++      void *task_data;
++      /* task state */
++      uint32_t state;
++      /* Task base address */
++      uint64_t base;
++      /* start address of a list of dla_operation_container */
++      uint64_t operation_desc_addr;
++      /* start address of a list of dla_surface_container */
++      uint64_t surface_desc_addr;
++      /* start address of a list of dla_common_op_desc */
++      uint64_t dependency_graph_addr;
++      /* start address of a list of dla_lut_param */
++      uint64_t lut_data_addr;
++      /*
++       * start address of a list of dla_roi_desc,
++       * the first one is dla_roi_array_desc
++       * valid when network.dynamic_roi is true
++       */
++      uint64_t roi_array_addr;
++      /* start address of a list of dla_surface_container */
++      uint64_t surface_addr;
++      /* start address of a list of dla_stat_container */
++      uint64_t stat_data_addr;
++} __packed __aligned(256);
++
++/**
++ * @brief                     Configuration parameters supported by the engine
++ *
++ * atom_size                  Memory smallest access size
++ * bdma_enable                        Defines whether bdma is supported
++ * rubik_enable                       Defines whether rubik is supported
++ * weight_compress_support    Defines whether weight data compression is supported
++ */
++struct dla_config {
++      uint32_t atom_size;
++      bool bdma_enable;
++      bool rubik_enable;
++      bool weight_compress_support;
++};
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/include/nvdla_interface.h
+@@ -0,0 +1,327 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __NVDLA_INTERFACE_H_
++#define __NVDLA_INTERFACE_H_
++
++#include <linux/types.h>
++
++/**
++ * @brief                     Register driver to firmware
++ *
++ * Implementation in firmware, called by portability layer
++ *
++ * This function must be called once during boot to initialize DLA
++ * engine scheduler and register driver with firmware before submitting
++ * any task. Pass pointer to driver context in @param driver_context
++ * which is passed as param when firmware calls any function
++ * of portability layer. It also updates pointer to engine context
++ * which must be passed in any function call to firmware after this point.
++ *
++ * @param engine_context      Pointer to engine specific data
++ * @param driver_context      Pointer to driver specific data
++ *
++ * @return                    0 on success and negative on error
++ */
++int32_t dla_register_driver(void **engine_context, void *driver_context);
++
++/**
++ * @brief                     Interrupt handler
++ *
++ * Implementation in firmware, called by portability layer
++ *
++ * This function is called when DLA interrupt is received. Portability layer
++ * should register it's own handler using the mechanism supported by that platform
++ * and call this function from the handler. Call to this function must be
++ * protected by lock to prevent handling interrupt when firmware is programming
++ * layers in process context.
++ *
++ * @param engine_context      Engine specific data received in dla_register_driver
++ *
++ * @return                    0 on success and negative on error
++ */
++int32_t dla_isr_handler(void *engine_context);
++
++/**
++ * @brief                     Process events recorded in interrupt handler
++ *
++ * Implementation in firmware, called by portability layer
++ *
++ * Interrupt handler just records events and does not process those events.
++ * Portability layer must call this function in thread/process context after
++ * interrupt handler is done.
++ *
++ * @param engine_context      Engine specific data received in dla_register_driver
++ * @param task_complete               Pointer to parameter to indicate task complete,
++                              firmare writes 1 to it if all layers are processed.
++ *
++ * @return                    0 on success and negative on error
++ *
++ */
++int32_t dla_process_events(void *engine_context, uint32_t *task_complete);
++
++/**
++ * @brief                     Clear task from firmware
++ *
++ * Implementation in firmware, called by portability layer
++ *
++ * This function resets engine scheduler state including op descriptor cache,
++ * error values, sub-engine status, events etc and clears previous task state
++ * from firmware. This function can be called by portability layer after
++ * task completion. It is not mandatory to call it but calling it will
++ * ensure clean state before next task execution.
++ *
++ * @param engine_context      Engine specific data received in dla_register_driver
++ *
++ * @return                    0 on success and negative on error
++ *
++ */
++void dla_clear_task(void *engine_context);
++
++/**
++ * @brief                     Execute task
++ *
++ * Implementation in firmware, called by portability layer
++ *
++ * This function initializes sub-engines and starts task execution. Further
++ * programming and layer scheduling is triggered by events received from
++ * hardware.
++ *
++ * @param engine_context      Engine specific data received in dla_register_driver
++ * @param task_data           Task specific data to be passed when reading task info
++ * @param config_data         Configuration data to be passed
++ *
++ * @return                    0 on success and negative on error
++ *
++ */
++int32_t dla_execute_task(void *engine_context, void *task_data, void *config_data);
++
++/**
++ * @brief                     Register read
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Read DLA HW register. Portability layer is responsible to use correct
++ * base address and for any IO mapping if required.
++ *
++ * @param engine_context      Driver specific data received in dla_register_driver
++ * @param addr                        Register offset
++ *
++ * @return                    Register value
++ *
++ */
++uint32_t dla_reg_read(void *driver_context, uint32_t addr);
++
++/**
++ * @brief                     Register write
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Write DLA HW registr. Portability layer is responsible to use correct
++ * base address and for any IO mapping if required.
++ *
++ * @param driver_context      Driver specific data received in dla_register_driver
++ * @param addr                        Register offset
++ * @param reg                 Value to write
++ *
++ */
++void dla_reg_write(void *driver_context, uint32_t addr, uint32_t reg);
++
++/**
++ * @brief                     Read data from DMA mapped memory in local buffer
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * This function reads data from buffers passed by UMD in local memory.
++ * Addresses for buffers passed by are shared in address list and network
++ * descriptor contains index in address list for those buffers. Firmware
++ * reads this data from buffer shared by UMD into local buffer to consume
++ * the information.
++ *
++ * @param driver_context      Driver specific data received in dla_register_driver
++ * @param task_data           Task specific data received in dla_execute_task
++ * @param src                 Index in address list
++ * @param dst                 Pointer to local memory
++ * @param size                        Size of data to copy
++ * @param offset              Offset from start of UMD buffer
++ *
++ * @return                    0 on success and negative on error
++ *
++ */
++int32_t dla_data_read(void *driver_context, void *task_data,
++                              uint64_t src, void *dst,
++                              uint32_t size, uint64_t offset);
++
++/**
++ * @brief                     Write data to DMA mapped memory from local buffer
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * This function writes data from local buffer to buffer passed by UMD.
++ * Addresses for buffers passed by are shared in address list and network
++ * descriptor contains index in address list for those buffers. Firmware
++ * writes this data to buffer shared by UMD from local buffer to update
++ * the information.
++ *
++ * @param driver_context      Driver specific data received in dla_register_driver
++ * @param task_data           Task specific data received in dla_execute_task
++ * @param src                 Pointer to local memory
++ * @param dst                 Index in address list
++ * @param size                        Size of data to copy
++ * @param offset              Offset from start of UMD buffer
++ *
++ * @return                    0 on success and negative on error
++ *
++ */
++int32_t dla_data_write(void *driver_context, void *task_data,
++                              void *src, uint64_t dst,
++                              uint32_t size, uint64_t offset);
++
++/* Destination for DMA buffer */
++#define DESTINATION_PROCESSOR 0
++#define DESTINATION_DMA               1
++
++/**
++ * @brief                     Read DMA address
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Some buffers shared by UMD are accessed by processor responsible for
++ * programming DLA HW. It would be companion micro-controller in case of
++ * headed config while main CPU in case of headless config. Also, some
++ * buffers are accessed by DLA DMA engines inside sub-engines. This function
++ * should return proper address accessible by destination user depending
++ * on config.
++ *
++ * @param driver_context      Driver specific data received in dla_register_driver
++ * @param task_data           Task specific data received in dla_execute_task
++ * @param index                       Index in address list
++ * @param dst_ptr             Pointer to update address
++ * @param destination         Destination user for DMA address
++ *
++ * @return                    0 on success and negative on error
++ *
++ */
++int32_t dla_get_dma_address(void *driver_context, void *task_data,
++                                      int16_t index, void *dst_ptr,
++                                      uint32_t destination);
++
++/**
++ * @brief                     Read time value in micro-seconds
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Read system time in micro-seconds
++ *
++ * @return                    Time value in micro-seconds
++ *
++ */
++int64_t dla_get_time_us(void);
++
++/**
++ * @brief                     Print debug message
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Print debug message to console
++ *
++ * @param str                 Format string and variable arguments
++ *
++ */
++void dla_debug(const char *str, ...);
++
++/**
++ * @brief                     Print information message
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Print information message to console
++ *
++ * @param str                 Format string and variable arguments
++ *
++ */
++void dla_info(const char *str, ...);
++
++/**
++ * @brief                     Print warning message
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Print warning message to console
++ *
++ * @param str                 Format string and variable arguments
++ *
++ */
++void dla_warn(const char *str, ...);
++
++/**
++ * @brief                     Print error message
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Print error message to console
++ *
++ * @param str                 Format string and variable arguments
++ *
++ */
++void dla_error(const char *str, ...);
++
++/**
++ * @brief                     Fill memory region
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Fills the first len bytes of the memory area pointed to by src
++ * with the constant byte ch.
++ *
++ * @param src                 Memory area address
++ * @param ch                  Byte to fill
++ * @param len                 Length of memory area to fill
++ *
++ * @return                    Memory area address
++ *
++ */
++void *dla_memset(void *src, int ch, uint64_t len);
++
++/**
++ * @brief                     Copy memory
++ *
++ * Implementation in portability layer, called by firmware
++ *
++ * Copies len bytes from memory area src to memory area dest.
++ *
++ * @param dest                        Destination memory area address
++ * @param src                 Source memory area address
++ * @param len                 Length of memory area to copy
++ *
++ * @return                    Destination memory area address
++ *
++ */
++void *dla_memcpy(void *dest, const void *src, uint64_t len);
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/include/nvdla_ioctl.h
+@@ -0,0 +1,138 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License version 2
++ * as published by the Free Software Foundation; or, when distributed
++ * separately from the Linux kernel or incorporated into other
++ * software packages, subject to the following license:
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __LINUX_NVDLA_IOCTL_H
++#define __LINUX_NVDLA_IOCTL_H
++
++#include <linux/ioctl.h>
++#include <linux/types.h>
++
++#if !defined(__KERNEL__)
++#define __user
++#endif
++
++/**
++ * struct nvdla_mem_handle structure for memory handles
++ *
++ * @handle            handle to DMA buffer allocated in userspace
++ * @reserved          Reserved for padding
++ * @offset            offset in bytes from start address of buffer
++ *
++ */
++struct nvdla_mem_handle {
++      __u32 handle;
++      __u32 reserved;
++      __u64 offset;
++};
++
++/**
++ * struct nvdla_ioctl_submit_task structure for single task information
++ *
++ * @num_addresses             total number of entries in address_list
++ * @reserved                  Reserved for padding
++ * @address_list              pointer to array of struct nvdla_mem_handle
++ *
++ */
++struct nvdla_ioctl_submit_task {
++#define NVDLA_MAX_BUFFERS_PER_TASK (6144)
++      __u32 num_addresses;
++#define NVDLA_NO_TIMEOUT    (0xffffffff)
++      __u32 timeout;
++      __u64 address_list;
++};
++
++/**
++ * struct nvdla_submit_args structure for task submit
++ *
++ * @tasks             pointer to array of struct nvdla_ioctl_submit_task
++ * @num_tasks         number of entries in tasks
++ * @flags             flags for task submit, no flags defined yet
++ * @version           version of task structure
++ *
++ */
++struct nvdla_submit_args {
++      __u64 tasks;
++      __u16 num_tasks;
++#define NVDLA_MAX_TASKS_PER_SUBMIT    24
++#define NVDLA_SUBMIT_FLAGS_ATOMIC     (1 << 0)
++      __u16 flags;
++      __u32 version;
++};
++
++/**
++ * struct nvdla_gem_create_args for allocating DMA buffer through GEM
++ *
++ * @handle            handle updated by kernel after allocation
++ * @flags             implementation specific flags
++ * @size              size of buffer to allocate
++ */
++struct nvdla_gem_create_args {
++      __u32 handle;
++      __u32 flags;
++      __u64 size;
++};
++
++/**
++ * struct nvdla_gem_map_offset_args for mapping DMA buffer
++ *
++ * @handle            handle of the buffer
++ * @reserved          reserved for padding
++ * @offset            offset updated by kernel after mapping
++ */
++struct nvdla_gem_map_offset_args {
++      __u32 handle;
++      __u32 reserved;
++      __u64 offset;
++};
++
++/**
++ * struct nvdla_gem_destroy_args for destroying DMA buffer
++ *
++ * @handle            handle of the buffer
++ */
++struct nvdla_gem_destroy_args {
++      __u32 handle;
++};
++
++#define DRM_NVDLA_SUBMIT              0x00
++#define DRM_NVDLA_GEM_CREATE          0x01
++#define DRM_NVDLA_GEM_MMAP            0x02
++#define DRM_NVDLA_GEM_DESTROY         0x03
++
++#define DRM_IOCTL_NVDLA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_SUBMIT, struct nvdla_submit_args)
++#define DRM_IOCTL_NVDLA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_GEM_CREATE, struct nvdla_gem_create_args)
++#define DRM_IOCTL_NVDLA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_GEM_MMAP, struct nvdla_gem_map_offset_args)
++#define DRM_IOCTL_NVDLA_GEM_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_GEM_DESTROY, struct nvdla_gem_destroy_args)
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/include/nvdla_linux.h
+@@ -0,0 +1,153 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License version 2
++ * as published by the Free Software Foundation; or, when distributed
++ * separately from the Linux kernel or incorporated into other
++ * software packages, subject to the following license:
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __LINUX_NVDLA_LINUX_H_
++#define __LINUX_NVDLA_LINUX_H_
++
++#include <linux/completion.h>
++#include <linux/device.h>
++#include <linux/kref.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++
++/**
++ * @brief                     Task information submitted from user space
++ *
++ * ref                                Reference count for task
++ * num_addresses              Number of addresses in address list
++ * nvdla_dev                  Pointer to NVDLA device
++ * address_list                       Address list
++ * file                               DRM file instance
++ */
++struct nvdla_task {
++      struct kref ref;
++      uint32_t num_addresses;
++      struct nvdla_device *nvdla_dev;
++      struct nvdla_mem_handle *address_list;
++      struct drm_file *file;
++};
++
++/**
++ * @brief                     Configuration parameters supported by the engine
++ *
++ * atom_size                  Memory smallest access size
++ * bdma_enable                        Defines whether bdma is supported
++ * rubik_enable                       Defines whether rubik is supported
++ * weight_compress_support    Defines whether weight data compression is supported
++ */
++struct nvdla_config
++{
++      uint32_t atom_size;
++      bool bdma_enable;
++      bool rubik_enable;
++      bool weight_compress_support;
++};
++
++/**
++ * @brief                     NVDLA device
++ *
++ * irq                                Interrupt number associated with this device
++ * ref                                Reference count for device
++ * base                               IO mapped base address for device
++ * nvdla_lock                 Spinlock used for synchronization
++ * drm                                DRM device instance
++ * task                               Pointer to task in execution
++ * config_data                        Pointer to the configuration data
++ * pdev                               Pointer to NVDLA platform device
++ * event_notifier             Completion object used to wait for events from HW
++ * engine_context             Private data passed from engine in dla_engine_init
++ */
++struct nvdla_device {
++      int32_t irq;
++      struct kref ref;
++      void __iomem *base;
++      spinlock_t nvdla_lock;
++      struct drm_device *drm;
++      struct nvdla_task *task;
++      struct nvdla_config *config_data;
++      struct platform_device *pdev;
++      struct completion event_notifier;
++
++      void *engine_context;
++};
++
++/**
++ * @brief                     Submit task
++ *
++ * This function submits task to NVDLA engine.
++ *
++ * @param nvdla_dev           Pointer to NVDLA device
++ * @param task                        Pointer to task
++ * @return                    0 on success and negative on error
++ *
++ */
++int32_t nvdla_task_submit(struct nvdla_device *nvdla_dev, struct nvdla_task *task);
++
++/**
++ * @brief                     Get DMA address
++ *
++ * This function gets DMA address for given fd
++ *
++ * @param dev                 DRM device instance
++ * @param file                        DRM file instance
++ * @param fd                  File desriptor for DMA buffer
++ * @param addr                        Pointer to update DMA address
++ * @return                    0 on success and negative on error
++ *
++ */
++int32_t nvdla_gem_dma_addr(struct drm_device *dev, struct drm_file *file,
++                                      uint32_t fd, dma_addr_t *addr);
++
++/**
++ * @brief                     DRM probe
++ *
++ * Probe function for DRM device
++ *
++ * @param nvdla_dev           NVDLA device pointer
++ * @return                    0 on success and negative on error
++ *
++ */
++int32_t nvdla_drm_probe(struct nvdla_device *nvdla_dev);
++
++/**
++ * @brief                     DRM remove
++ *
++ * Remove function for DRM device
++ *
++ * @param nvdla_dev           NVDLA device pointer
++ *
++ */
++void nvdla_drm_remove(struct nvdla_device *nvdla_dev);
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/include/opendla.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __OPENDLA_H_
++#define __OPENDLA_H_
++
++#define DLA_2_CONFIG
++
++#ifdef DLA_2_CONFIG
++#include <opendla_small.h>
++#else
++#include <opendla_initial.h>
++#endif
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/include/opendla_initial.h
+@@ -0,0 +1,16743 @@
++/*
++ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __ARNVDLA_H_
++#define __ARNVDLA_H_
++
++// Register GLB_S_NVDLA_HW_VERSION_0
++#define GLB_S_NVDLA_HW_VERSION_0                           (_MK_ADDR_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_SECURE                                    (0x0)
++#define GLB_S_NVDLA_HW_VERSION_0_DUAL                                      (0x0)
++#define GLB_S_NVDLA_HW_VERSION_0_SCR                                         (0)
++#define GLB_S_NVDLA_HW_VERSION_0_WORD_COUNT                                (0x1)
++#define GLB_S_NVDLA_HW_VERSION_0_RESET_VAL            (_MK_MASK_CONST(0x303031))
++#define GLB_S_NVDLA_HW_VERSION_0_RESET_MASK           (_MK_MASK_CONST(0xffffff))
++#define GLB_S_NVDLA_HW_VERSION_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_READ_MASK            (_MK_MASK_CONST(0xffffff))
++#define GLB_S_NVDLA_HW_VERSION_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT                (_MK_SHIFT_CONST(0))
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_FIELD \
++      (_MK_FIELD_CONST(0xff, GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT))
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_RANGE                               (7:0)
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_WOFFSET                             (0x0)
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_DEFAULT            (_MK_MASK_CONST(0x31))
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_DEFAULT_MASK       (_MK_MASK_CONST(0xff))
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT                (_MK_SHIFT_CONST(8))
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_FIELD \
++      (_MK_FIELD_CONST(0xffff, GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT))
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_RANGE                              (23:8)
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_WOFFSET                             (0x0)
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_DEFAULT          (_MK_MASK_CONST(0x3030))
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register GLB_S_INTR_MASK_0
++#define GLB_S_INTR_MASK_0                                  (_MK_ADDR_CONST(0x4))
++#define GLB_S_INTR_MASK_0_SECURE                                           (0x0)
++#define GLB_S_INTR_MASK_0_DUAL                                             (0x0)
++#define GLB_S_INTR_MASK_0_SCR                                                (0)
++#define GLB_S_INTR_MASK_0_WORD_COUNT                                       (0x1)
++#define GLB_S_INTR_MASK_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_RESET_MASK                  (_MK_MASK_CONST(0x3f03ff))
++#define GLB_S_INTR_MASK_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_READ_MASK                   (_MK_MASK_CONST(0x3f03ff))
++#define GLB_S_INTR_MASK_0_WRITE_MASK                  (_MK_MASK_CONST(0x3f03ff))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT              (_MK_SHIFT_CONST(0))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_RANGE                             (0:0)
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_WOFFSET                           (0x0)
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_DEFAULT           (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT              (_MK_SHIFT_CONST(1))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_RANGE                             (1:1)
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_WOFFSET                           (0x0)
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_DEFAULT           (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT              (_MK_SHIFT_CONST(2))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_RANGE                             (2:2)
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_WOFFSET                           (0x0)
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_DEFAULT           (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT              (_MK_SHIFT_CONST(3))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_RANGE                             (3:3)
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_WOFFSET                           (0x0)
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_DEFAULT           (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT              (_MK_SHIFT_CONST(4))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_RANGE                             (4:4)
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_WOFFSET                           (0x0)
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_DEFAULT           (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT              (_MK_SHIFT_CONST(5))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_RANGE                             (5:5)
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_WOFFSET                           (0x0)
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_DEFAULT           (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT             (_MK_SHIFT_CONST(6))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_RANGE                            (6:6)
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_WOFFSET                          (0x0)
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT             (_MK_SHIFT_CONST(7))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_RANGE                            (7:7)
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_WOFFSET                          (0x0)
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT            (_MK_SHIFT_CONST(8))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_RANGE                           (8:8)
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_WOFFSET                         (0x0)
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_DEFAULT         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT            (_MK_SHIFT_CONST(9))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_RANGE                           (9:9)
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_WOFFSET                         (0x0)
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_DEFAULT         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT        (_MK_SHIFT_CONST(16))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_RANGE                      (16:16)
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_WOFFSET                      (0x0)
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT        (_MK_SHIFT_CONST(17))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_RANGE                      (17:17)
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_WOFFSET                      (0x0)
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT         (_MK_SHIFT_CONST(18))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_RANGE                       (18:18)
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_WOFFSET                       (0x0)
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT         (_MK_SHIFT_CONST(19))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_RANGE                       (19:19)
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_WOFFSET                       (0x0)
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT            (_MK_SHIFT_CONST(20))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_RANGE                          (20:20)
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_WOFFSET                          (0x0)
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT            (_MK_SHIFT_CONST(21))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_RANGE                          (21:21)
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_WOFFSET                          (0x0)
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register GLB_S_INTR_SET_0
++#define GLB_S_INTR_SET_0                                   (_MK_ADDR_CONST(0x8))
++#define GLB_S_INTR_SET_0_SECURE                                            (0x0)
++#define GLB_S_INTR_SET_0_DUAL                                              (0x0)
++#define GLB_S_INTR_SET_0_SCR                                                 (0)
++#define GLB_S_INTR_SET_0_WORD_COUNT                                        (0x1)
++#define GLB_S_INTR_SET_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_RESET_MASK                   (_MK_MASK_CONST(0x3f03ff))
++#define GLB_S_INTR_SET_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_READ_MASK                         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_WRITE_MASK                   (_MK_MASK_CONST(0x3f03ff))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT                (_MK_SHIFT_CONST(0))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_RANGE                               (0:0)
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_WOFFSET                             (0x0)
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_DEFAULT             (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT                (_MK_SHIFT_CONST(1))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_RANGE                               (1:1)
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_WOFFSET                             (0x0)
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_DEFAULT             (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT                (_MK_SHIFT_CONST(2))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_RANGE                               (2:2)
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_WOFFSET                             (0x0)
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_DEFAULT             (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT                (_MK_SHIFT_CONST(3))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_RANGE                               (3:3)
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_WOFFSET                             (0x0)
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_DEFAULT             (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT                (_MK_SHIFT_CONST(4))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_RANGE                               (4:4)
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_WOFFSET                             (0x0)
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_DEFAULT             (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT                (_MK_SHIFT_CONST(5))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_RANGE                               (5:5)
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_WOFFSET                             (0x0)
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_DEFAULT             (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT               (_MK_SHIFT_CONST(6))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_RANGE                              (6:6)
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_WOFFSET                            (0x0)
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_DEFAULT            (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT               (_MK_SHIFT_CONST(7))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_RANGE                              (7:7)
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_WOFFSET                            (0x0)
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_DEFAULT            (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT              (_MK_SHIFT_CONST(8))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_RANGE                             (8:8)
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_WOFFSET                           (0x0)
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_DEFAULT           (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT              (_MK_SHIFT_CONST(9))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_RANGE                             (9:9)
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_WOFFSET                           (0x0)
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_DEFAULT           (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT          (_MK_SHIFT_CONST(16))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_RANGE                        (16:16)
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_WOFFSET                        (0x0)
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT          (_MK_SHIFT_CONST(17))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_RANGE                        (17:17)
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_WOFFSET                        (0x0)
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_DEFAULT        (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT           (_MK_SHIFT_CONST(18))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_RANGE                         (18:18)
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_WOFFSET                         (0x0)
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_DEFAULT         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT           (_MK_SHIFT_CONST(19))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_RANGE                         (19:19)
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_WOFFSET                         (0x0)
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_DEFAULT         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT              (_MK_SHIFT_CONST(20))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_RANGE                            (20:20)
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_WOFFSET                            (0x0)
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_DEFAULT            (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT              (_MK_SHIFT_CONST(21))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_RANGE                            (21:21)
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_WOFFSET                            (0x0)
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_DEFAULT            (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register GLB_S_INTR_STATUS_0
++#define GLB_S_INTR_STATUS_0                                (_MK_ADDR_CONST(0xc))
++#define GLB_S_INTR_STATUS_0_SECURE                                         (0x0)
++#define GLB_S_INTR_STATUS_0_DUAL                                           (0x0)
++#define GLB_S_INTR_STATUS_0_SCR                                              (0)
++#define GLB_S_INTR_STATUS_0_WORD_COUNT                                     (0x1)
++#define GLB_S_INTR_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_RESET_MASK                (_MK_MASK_CONST(0x3f03ff))
++#define GLB_S_INTR_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_READ_MASK                 (_MK_MASK_CONST(0x3f03ff))
++#define GLB_S_INTR_STATUS_0_WRITE_MASK                (_MK_MASK_CONST(0x3f03ff))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT          (_MK_SHIFT_CONST(0))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_RANGE                         (0:0)
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_WOFFSET                       (0x0)
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT          (_MK_SHIFT_CONST(1))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_RANGE                         (1:1)
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_WOFFSET                       (0x0)
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT          (_MK_SHIFT_CONST(2))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_RANGE                         (2:2)
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_WOFFSET                       (0x0)
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT          (_MK_SHIFT_CONST(3))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_RANGE                         (3:3)
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_WOFFSET                       (0x0)
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT          (_MK_SHIFT_CONST(4))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_RANGE                         (4:4)
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_WOFFSET                       (0x0)
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT          (_MK_SHIFT_CONST(5))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_RANGE                         (5:5)
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_WOFFSET                       (0x0)
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_DEFAULT       (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT         (_MK_SHIFT_CONST(6))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_RANGE                        (6:6)
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_WOFFSET                      (0x0)
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT         (_MK_SHIFT_CONST(7))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_RANGE                        (7:7)
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_WOFFSET                      (0x0)
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT        (_MK_SHIFT_CONST(8))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_RANGE                       (8:8)
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_WOFFSET                     (0x0)
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_DEFAULT     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT        (_MK_SHIFT_CONST(9))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_RANGE                       (9:9)
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_WOFFSET                     (0x0)
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_DEFAULT     (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT    (_MK_SHIFT_CONST(16))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_RANGE                  (16:16)
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_WOFFSET                  (0x0)
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT    (_MK_SHIFT_CONST(17))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_RANGE                  (17:17)
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_WOFFSET                  (0x0)
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT     (_MK_SHIFT_CONST(18))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_RANGE                   (18:18)
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_WOFFSET                   (0x0)
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT     (_MK_SHIFT_CONST(19))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_RANGE                   (19:19)
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_WOFFSET                   (0x0)
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT        (_MK_SHIFT_CONST(20))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_RANGE                      (20:20)
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_WOFFSET                      (0x0)
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT        (_MK_SHIFT_CONST(21))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_FIELD \
++      (_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_RANGE                      (21:21)
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_WOFFSET                      (0x0)
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_DEFAULT      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register MCIF_CFG_RD_WEIGHT_0_0
++#define MCIF_CFG_RD_WEIGHT_0_0                          (_MK_ADDR_CONST(0x2000))
++#define MCIF_CFG_RD_WEIGHT_0_0_SECURE                                      (0x0)
++#define MCIF_CFG_RD_WEIGHT_0_0_DUAL                                        (0x0)
++#define MCIF_CFG_RD_WEIGHT_0_0_SCR                                           (0)
++#define MCIF_CFG_RD_WEIGHT_0_0_WORD_COUNT                                  (0x1)
++#define MCIF_CFG_RD_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define MCIF_CFG_RD_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_RD_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_RANGE                        (7:0)
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_WOFFSET                      (0x0)
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_RANGE                        (15:8)
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_WOFFSET                       (0x0)
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_RANGE                       (23:16)
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_WOFFSET                       (0x0)
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_RANGE                       (31:24)
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_WOFFSET                       (0x0)
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register MCIF_CFG_RD_WEIGHT_1_0
++#define MCIF_CFG_RD_WEIGHT_1_0                          (_MK_ADDR_CONST(0x2004))
++#define MCIF_CFG_RD_WEIGHT_1_0_SECURE                                      (0x0)
++#define MCIF_CFG_RD_WEIGHT_1_0_DUAL                                        (0x0)
++#define MCIF_CFG_RD_WEIGHT_1_0_SCR                                           (0)
++#define MCIF_CFG_RD_WEIGHT_1_0_WORD_COUNT                                  (0x1)
++#define MCIF_CFG_RD_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define MCIF_CFG_RD_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_RD_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT        (_MK_SHIFT_CONST(0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_RANGE                       (7:0)
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_WOFFSET                     (0x0)
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT     (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT        (_MK_SHIFT_CONST(8))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_RANGE                      (15:8)
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_WOFFSET                     (0x0)
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT     (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT       (_MK_SHIFT_CONST(16))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_RANGE                     (23:16)
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_WOFFSET                     (0x0)
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT     (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT    (_MK_SHIFT_CONST(24))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD \
++      (_MK_FIELD_CONST(0xff, \
++      MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_RANGE                  (31:24)
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_WOFFSET                  (0x0)
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT \
++      (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register MCIF_CFG_RD_WEIGHT_2_0
++#define MCIF_CFG_RD_WEIGHT_2_0                          (_MK_ADDR_CONST(0x2008))
++#define MCIF_CFG_RD_WEIGHT_2_0_SECURE                                      (0x0)
++#define MCIF_CFG_RD_WEIGHT_2_0_DUAL                                        (0x0)
++#define MCIF_CFG_RD_WEIGHT_2_0_SCR                                           (0)
++#define MCIF_CFG_RD_WEIGHT_2_0_WORD_COUNT                                  (0x1)
++#define MCIF_CFG_RD_WEIGHT_2_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define MCIF_CFG_RD_WEIGHT_2_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_RD_WEIGHT_2_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT      (_MK_SHIFT_CONST(0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD \
++      (_MK_FIELD_CONST(0xff, \
++      MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_RANGE                     (7:0)
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_WOFFSET                   (0x0)
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT \
++      (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(8))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_RANGE                        (15:8)
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_WOFFSET                       (0x0)
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_RANGE                     (23:16)
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_WOFFSET                     (0x0)
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_RANGE                     (31:24)
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_WOFFSET                     (0x0)
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register MCIF_CFG_WR_WEIGHT_0_0
++#define MCIF_CFG_WR_WEIGHT_0_0                          (_MK_ADDR_CONST(0x200c))
++#define MCIF_CFG_WR_WEIGHT_0_0_SECURE                                      (0x0)
++#define MCIF_CFG_WR_WEIGHT_0_0_DUAL                                        (0x0)
++#define MCIF_CFG_WR_WEIGHT_0_0_SCR                                           (0)
++#define MCIF_CFG_WR_WEIGHT_0_0_WORD_COUNT                                  (0x1)
++#define MCIF_CFG_WR_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define MCIF_CFG_WR_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_WR_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_RANGE                        (7:0)
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_WOFFSET                      (0x0)
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_RANGE                        (15:8)
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_WOFFSET                       (0x0)
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_RANGE                       (23:16)
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_WOFFSET                       (0x0)
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_RANGE                       (31:24)
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_WOFFSET                       (0x0)
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register MCIF_CFG_WR_WEIGHT_1_0
++#define MCIF_CFG_WR_WEIGHT_1_0                          (_MK_ADDR_CONST(0x2010))
++#define MCIF_CFG_WR_WEIGHT_1_0_SECURE                                      (0x0)
++#define MCIF_CFG_WR_WEIGHT_1_0_DUAL                                        (0x0)
++#define MCIF_CFG_WR_WEIGHT_1_0_SCR                                           (0)
++#define MCIF_CFG_WR_WEIGHT_1_0_WORD_COUNT                                  (0x1)
++#define MCIF_CFG_WR_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define MCIF_CFG_WR_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_WR_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_RANGE                         (7:0)
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_WOFFSET                       (0x0)
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT        (_MK_SHIFT_CONST(8))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_RANGE                      (15:8)
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_WOFFSET                     (0x0)
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT     (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_RANGE                     (23:16)
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_WOFFSET                     (0x0)
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_RANGE                     (31:24)
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_WOFFSET                     (0x0)
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register MCIF_CFG_OUTSTANDING_CNT_0
++#define MCIF_CFG_OUTSTANDING_CNT_0                      (_MK_ADDR_CONST(0x2014))
++#define MCIF_CFG_OUTSTANDING_CNT_0_SECURE                                  (0x0)
++#define MCIF_CFG_OUTSTANDING_CNT_0_DUAL                                    (0x0)
++#define MCIF_CFG_OUTSTANDING_CNT_0_SCR                                       (0)
++#define MCIF_CFG_OUTSTANDING_CNT_0_WORD_COUNT                              (0x1)
++#define MCIF_CFG_OUTSTANDING_CNT_0_RESET_VAL            (_MK_MASK_CONST(0xffff))
++#define MCIF_CFG_OUTSTANDING_CNT_0_RESET_MASK           (_MK_MASK_CONST(0xffff))
++#define MCIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_OUTSTANDING_CNT_0_READ_MASK            (_MK_MASK_CONST(0xffff))
++#define MCIF_CFG_OUTSTANDING_CNT_0_WRITE_MASK           (_MK_MASK_CONST(0xffff))
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT          (_MK_SHIFT_CONST(0))
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT))
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_RANGE                         (7:0)
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_WOFFSET                       (0x0)
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT          (_MK_SHIFT_CONST(8))
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD \
++      (_MK_FIELD_CONST(0xff, MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT))
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_RANGE                        (15:8)
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_WOFFSET                       (0x0)
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register MCIF_STATUS_0
++#define MCIF_STATUS_0                                   (_MK_ADDR_CONST(0x2018))
++#define MCIF_STATUS_0_SECURE                                               (0x0)
++#define MCIF_STATUS_0_DUAL                                                 (0x0)
++#define MCIF_STATUS_0_SCR                                                    (0)
++#define MCIF_STATUS_0_WORD_COUNT                                           (0x1)
++#define MCIF_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x100))
++#define MCIF_STATUS_0_RESET_MASK                         (_MK_MASK_CONST(0x100))
++#define MCIF_STATUS_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
++#define MCIF_STATUS_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
++#define MCIF_STATUS_0_READ_MASK                          (_MK_MASK_CONST(0x100))
++#define MCIF_STATUS_0_WRITE_MASK                           (_MK_MASK_CONST(0x0))
++#define MCIF_STATUS_0_IDLE_SHIFT                            (_MK_SHIFT_CONST(8))
++#define MCIF_STATUS_0_IDLE_FIELD \
++      (_MK_FIELD_CONST(0x1, MCIF_STATUS_0_IDLE_SHIFT))
++#define MCIF_STATUS_0_IDLE_RANGE                                           (8:8)
++#define MCIF_STATUS_0_IDLE_WOFFSET                                         (0x0)
++#define MCIF_STATUS_0_IDLE_DEFAULT                         (_MK_MASK_CONST(0x1))
++#define MCIF_STATUS_0_IDLE_DEFAULT_MASK                    (_MK_MASK_CONST(0x1))
++#define MCIF_STATUS_0_IDLE_SW_DEFAULT                      (_MK_MASK_CONST(0x0))
++#define MCIF_STATUS_0_IDLE_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define MCIF_STATUS_0_IDLE_PARITY_PROTECTION               (_MK_MASK_CONST(0x0))
++#define MCIF_STATUS_0_IDLE_PLATFORM_DEPENDENT              (_MK_MASK_CONST(0x1))
++#define MCIF_STATUS_0_IDLE_INIT_ENUM                                       (YES)
++#define MCIF_STATUS_0_IDLE_NO                                (_MK_ENUM_CONST(0))
++#define MCIF_STATUS_0_IDLE_YES                               (_MK_ENUM_CONST(1))
++
++
++// Register CVIF_CFG_RD_WEIGHT_0_0
++#define CVIF_CFG_RD_WEIGHT_0_0                          (_MK_ADDR_CONST(0x3000))
++#define CVIF_CFG_RD_WEIGHT_0_0_SECURE                                      (0x0)
++#define CVIF_CFG_RD_WEIGHT_0_0_DUAL                                        (0x0)
++#define CVIF_CFG_RD_WEIGHT_0_0_SCR                                           (0)
++#define CVIF_CFG_RD_WEIGHT_0_0_WORD_COUNT                                  (0x1)
++#define CVIF_CFG_RD_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define CVIF_CFG_RD_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_RD_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_RANGE                        (7:0)
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_WOFFSET                      (0x0)
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_RANGE                        (15:8)
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_WOFFSET                       (0x0)
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_RANGE                       (23:16)
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_WOFFSET                       (0x0)
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_RANGE                       (31:24)
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_WOFFSET                       (0x0)
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CVIF_CFG_RD_WEIGHT_1_0
++#define CVIF_CFG_RD_WEIGHT_1_0                          (_MK_ADDR_CONST(0x3004))
++#define CVIF_CFG_RD_WEIGHT_1_0_SECURE                                      (0x0)
++#define CVIF_CFG_RD_WEIGHT_1_0_DUAL                                        (0x0)
++#define CVIF_CFG_RD_WEIGHT_1_0_SCR                                           (0)
++#define CVIF_CFG_RD_WEIGHT_1_0_WORD_COUNT                                  (0x1)
++#define CVIF_CFG_RD_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define CVIF_CFG_RD_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_RD_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT        (_MK_SHIFT_CONST(0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_RANGE                       (7:0)
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_WOFFSET                     (0x0)
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT     (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT        (_MK_SHIFT_CONST(8))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_RANGE                      (15:8)
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_WOFFSET                     (0x0)
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT     (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT       (_MK_SHIFT_CONST(16))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_RANGE                     (23:16)
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_WOFFSET                     (0x0)
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT     (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT    (_MK_SHIFT_CONST(24))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD \
++      (_MK_FIELD_CONST(0xff, \
++      CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_RANGE                  (31:24)
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_WOFFSET                  (0x0)
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT \
++      (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CVIF_CFG_RD_WEIGHT_2_0
++#define CVIF_CFG_RD_WEIGHT_2_0                          (_MK_ADDR_CONST(0x3008))
++#define CVIF_CFG_RD_WEIGHT_2_0_SECURE                                      (0x0)
++#define CVIF_CFG_RD_WEIGHT_2_0_DUAL                                        (0x0)
++#define CVIF_CFG_RD_WEIGHT_2_0_SCR                                           (0)
++#define CVIF_CFG_RD_WEIGHT_2_0_WORD_COUNT                                  (0x1)
++#define CVIF_CFG_RD_WEIGHT_2_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define CVIF_CFG_RD_WEIGHT_2_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_RD_WEIGHT_2_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT      (_MK_SHIFT_CONST(0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD \
++      (_MK_FIELD_CONST(0xff, \
++      CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_RANGE                     (7:0)
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_WOFFSET                   (0x0)
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT \
++      (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(8))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_RANGE                        (15:8)
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_WOFFSET                       (0x0)
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_RANGE                     (23:16)
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_WOFFSET                     (0x0)
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_RANGE                     (31:24)
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_WOFFSET                     (0x0)
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CVIF_CFG_WR_WEIGHT_0_0
++#define CVIF_CFG_WR_WEIGHT_0_0                          (_MK_ADDR_CONST(0x300c))
++#define CVIF_CFG_WR_WEIGHT_0_0_SECURE                                      (0x0)
++#define CVIF_CFG_WR_WEIGHT_0_0_DUAL                                        (0x0)
++#define CVIF_CFG_WR_WEIGHT_0_0_SCR                                           (0)
++#define CVIF_CFG_WR_WEIGHT_0_0_WORD_COUNT                                  (0x1)
++#define CVIF_CFG_WR_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define CVIF_CFG_WR_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_WR_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_RANGE                        (7:0)
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_WOFFSET                      (0x0)
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_RANGE                        (15:8)
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_WOFFSET                       (0x0)
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_RANGE                       (23:16)
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_WOFFSET                       (0x0)
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_RANGE                       (31:24)
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_WOFFSET                       (0x0)
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CVIF_CFG_WR_WEIGHT_1_0
++#define CVIF_CFG_WR_WEIGHT_1_0                          (_MK_ADDR_CONST(0x3010))
++#define CVIF_CFG_WR_WEIGHT_1_0_SECURE                                      (0x0)
++#define CVIF_CFG_WR_WEIGHT_1_0_DUAL                                        (0x0)
++#define CVIF_CFG_WR_WEIGHT_1_0_SCR                                           (0)
++#define CVIF_CFG_WR_WEIGHT_1_0_WORD_COUNT                                  (0x1)
++#define CVIF_CFG_WR_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
++#define CVIF_CFG_WR_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_WR_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_RANGE                         (7:0)
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_WOFFSET                       (0x0)
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT        (_MK_SHIFT_CONST(8))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_RANGE                      (15:8)
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_WOFFSET                     (0x0)
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT     (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_RANGE                     (23:16)
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_WOFFSET                     (0x0)
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_RANGE                     (31:24)
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_WOFFSET                     (0x0)
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CVIF_CFG_OUTSTANDING_CNT_0
++#define CVIF_CFG_OUTSTANDING_CNT_0                      (_MK_ADDR_CONST(0x3014))
++#define CVIF_CFG_OUTSTANDING_CNT_0_SECURE                                  (0x0)
++#define CVIF_CFG_OUTSTANDING_CNT_0_DUAL                                    (0x0)
++#define CVIF_CFG_OUTSTANDING_CNT_0_SCR                                       (0)
++#define CVIF_CFG_OUTSTANDING_CNT_0_WORD_COUNT                              (0x1)
++#define CVIF_CFG_OUTSTANDING_CNT_0_RESET_VAL            (_MK_MASK_CONST(0xffff))
++#define CVIF_CFG_OUTSTANDING_CNT_0_RESET_MASK           (_MK_MASK_CONST(0xffff))
++#define CVIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_OUTSTANDING_CNT_0_READ_MASK            (_MK_MASK_CONST(0xffff))
++#define CVIF_CFG_OUTSTANDING_CNT_0_WRITE_MASK           (_MK_MASK_CONST(0xffff))
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT          (_MK_SHIFT_CONST(0))
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT))
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_RANGE                         (7:0)
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_WOFFSET                       (0x0)
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT          (_MK_SHIFT_CONST(8))
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD \
++      (_MK_FIELD_CONST(0xff, CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT))
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_RANGE                        (15:8)
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_WOFFSET                       (0x0)
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CVIF_STATUS_0
++#define CVIF_STATUS_0                                   (_MK_ADDR_CONST(0x3018))
++#define CVIF_STATUS_0_SECURE                                               (0x0)
++#define CVIF_STATUS_0_DUAL                                                 (0x0)
++#define CVIF_STATUS_0_SCR                                                    (0)
++#define CVIF_STATUS_0_WORD_COUNT                                           (0x1)
++#define CVIF_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x100))
++#define CVIF_STATUS_0_RESET_MASK                         (_MK_MASK_CONST(0x100))
++#define CVIF_STATUS_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
++#define CVIF_STATUS_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
++#define CVIF_STATUS_0_READ_MASK                          (_MK_MASK_CONST(0x100))
++#define CVIF_STATUS_0_WRITE_MASK                           (_MK_MASK_CONST(0x0))
++#define CVIF_STATUS_0_IDLE_SHIFT                            (_MK_SHIFT_CONST(8))
++#define CVIF_STATUS_0_IDLE_FIELD \
++      (_MK_FIELD_CONST(0x1, CVIF_STATUS_0_IDLE_SHIFT))
++#define CVIF_STATUS_0_IDLE_RANGE                                           (8:8)
++#define CVIF_STATUS_0_IDLE_WOFFSET                                         (0x0)
++#define CVIF_STATUS_0_IDLE_DEFAULT                         (_MK_MASK_CONST(0x1))
++#define CVIF_STATUS_0_IDLE_DEFAULT_MASK                    (_MK_MASK_CONST(0x1))
++#define CVIF_STATUS_0_IDLE_SW_DEFAULT                      (_MK_MASK_CONST(0x0))
++#define CVIF_STATUS_0_IDLE_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define CVIF_STATUS_0_IDLE_PARITY_PROTECTION               (_MK_MASK_CONST(0x0))
++#define CVIF_STATUS_0_IDLE_PLATFORM_DEPENDENT              (_MK_MASK_CONST(0x1))
++#define CVIF_STATUS_0_IDLE_INIT_ENUM                                       (YES)
++#define CVIF_STATUS_0_IDLE_NO                                (_MK_ENUM_CONST(0))
++#define CVIF_STATUS_0_IDLE_YES                               (_MK_ENUM_CONST(1))
++
++
++// Register BDMA_CFG_SRC_ADDR_LOW_0
++#define BDMA_CFG_SRC_ADDR_LOW_0                         (_MK_ADDR_CONST(0x4000))
++#define BDMA_CFG_SRC_ADDR_LOW_0_SECURE                                     (0x0)
++#define BDMA_CFG_SRC_ADDR_LOW_0_DUAL                                       (0x0)
++#define BDMA_CFG_SRC_ADDR_LOW_0_SCR                                          (0)
++#define BDMA_CFG_SRC_ADDR_LOW_0_WORD_COUNT                                 (0x1)
++#define BDMA_CFG_SRC_ADDR_LOW_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT                   (_MK_SHIFT_CONST(5))
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT))
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_RANGE                                 (31:5)
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_WOFFSET                                (0x0)
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_DEFAULT                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_DEFAULT_MASK     (_MK_MASK_CONST(0x7ffffff))
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_SRC_ADDR_HIGH_0
++#define BDMA_CFG_SRC_ADDR_HIGH_0                        (_MK_ADDR_CONST(0x4004))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_SECURE                                    (0x0)
++#define BDMA_CFG_SRC_ADDR_HIGH_0_DUAL                                      (0x0)
++#define BDMA_CFG_SRC_ADDR_HIGH_0_SCR                                         (0)
++#define BDMA_CFG_SRC_ADDR_HIGH_0_WORD_COUNT                                (0x1)
++#define BDMA_CFG_SRC_ADDR_HIGH_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT                   (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_RANGE                                 (31:0)
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_WOFFSET                                (0x0)
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_DEFAULT                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_DEFAULT_MASK    (_MK_MASK_CONST(0xffffffff))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_DST_ADDR_LOW_0
++#define BDMA_CFG_DST_ADDR_LOW_0                         (_MK_ADDR_CONST(0x4008))
++#define BDMA_CFG_DST_ADDR_LOW_0_SECURE                                     (0x0)
++#define BDMA_CFG_DST_ADDR_LOW_0_DUAL                                       (0x0)
++#define BDMA_CFG_DST_ADDR_LOW_0_SCR                                          (0)
++#define BDMA_CFG_DST_ADDR_LOW_0_WORD_COUNT                                 (0x1)
++#define BDMA_CFG_DST_ADDR_LOW_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_LOW_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_DST_ADDR_LOW_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_LOW_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_LOW_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_DST_ADDR_LOW_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT                   (_MK_SHIFT_CONST(5))
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT))
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_RANGE                                 (31:5)
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_WOFFSET                                (0x0)
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_DEFAULT                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_DEFAULT_MASK     (_MK_MASK_CONST(0x7ffffff))
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_DST_ADDR_HIGH_0
++#define BDMA_CFG_DST_ADDR_HIGH_0                        (_MK_ADDR_CONST(0x400c))
++#define BDMA_CFG_DST_ADDR_HIGH_0_SECURE                                    (0x0)
++#define BDMA_CFG_DST_ADDR_HIGH_0_DUAL                                      (0x0)
++#define BDMA_CFG_DST_ADDR_HIGH_0_SCR                                         (0)
++#define BDMA_CFG_DST_ADDR_HIGH_0_WORD_COUNT                                (0x1)
++#define BDMA_CFG_DST_ADDR_HIGH_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_HIGH_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
++#define BDMA_CFG_DST_ADDR_HIGH_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_HIGH_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_HIGH_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
++#define BDMA_CFG_DST_ADDR_HIGH_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT                   (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT))
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_RANGE                                 (31:0)
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_WOFFSET                                (0x0)
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_DEFAULT                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_DEFAULT_MASK    (_MK_MASK_CONST(0xffffffff))
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_LINE_0
++#define BDMA_CFG_LINE_0                                 (_MK_ADDR_CONST(0x4010))
++#define BDMA_CFG_LINE_0_SECURE                                             (0x0)
++#define BDMA_CFG_LINE_0_DUAL                                               (0x0)
++#define BDMA_CFG_LINE_0_SCR                                                  (0)
++#define BDMA_CFG_LINE_0_WORD_COUNT                                         (0x1)
++#define BDMA_CFG_LINE_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_0_RESET_MASK                      (_MK_MASK_CONST(0x1fff))
++#define BDMA_CFG_LINE_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_0_READ_MASK                       (_MK_MASK_CONST(0x1fff))
++#define BDMA_CFG_LINE_0_WRITE_MASK                      (_MK_MASK_CONST(0x1fff))
++#define BDMA_CFG_LINE_0_SIZE_SHIFT                          (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_LINE_0_SIZE_FIELD \
++      (_MK_FIELD_CONST(0x1fff, BDMA_CFG_LINE_0_SIZE_SHIFT))
++#define BDMA_CFG_LINE_0_SIZE_RANGE                                        (12:0)
++#define BDMA_CFG_LINE_0_SIZE_WOFFSET                                       (0x0)
++#define BDMA_CFG_LINE_0_SIZE_DEFAULT                       (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_0_SIZE_DEFAULT_MASK               (_MK_MASK_CONST(0x1fff))
++#define BDMA_CFG_LINE_0_SIZE_SW_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_0_SIZE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_0_SIZE_PARITY_PROTECTION             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_0_SIZE_PLATFORM_DEPENDENT            (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_CMD_0
++#define BDMA_CFG_CMD_0                                  (_MK_ADDR_CONST(0x4014))
++#define BDMA_CFG_CMD_0_SECURE                                              (0x0)
++#define BDMA_CFG_CMD_0_DUAL                                                (0x0)
++#define BDMA_CFG_CMD_0_SCR                                                   (0)
++#define BDMA_CFG_CMD_0_WORD_COUNT                                          (0x1)
++#define BDMA_CFG_CMD_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_RESET_MASK                          (_MK_MASK_CONST(0x3))
++#define BDMA_CFG_CMD_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_READ_MASK                           (_MK_MASK_CONST(0x3))
++#define BDMA_CFG_CMD_0_WRITE_MASK                          (_MK_MASK_CONST(0x3))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT                   (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_RANGE                                  (0:0)
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_WOFFSET                                (0x0)
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_DEFAULT                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_CVSRAM                   (_MK_ENUM_CONST(0))
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_MC                       (_MK_ENUM_CONST(1))
++
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT                   (_MK_SHIFT_CONST(1))
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT))
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_RANGE                                  (1:1)
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_WOFFSET                                (0x0)
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_DEFAULT                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_CVSRAM                   (_MK_ENUM_CONST(0))
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_MC                       (_MK_ENUM_CONST(1))
++
++
++// Register BDMA_CFG_LINE_REPEAT_0
++#define BDMA_CFG_LINE_REPEAT_0                          (_MK_ADDR_CONST(0x4018))
++#define BDMA_CFG_LINE_REPEAT_0_SECURE                                      (0x0)
++#define BDMA_CFG_LINE_REPEAT_0_DUAL                                        (0x0)
++#define BDMA_CFG_LINE_REPEAT_0_SCR                                           (0)
++#define BDMA_CFG_LINE_REPEAT_0_WORD_COUNT                                  (0x1)
++#define BDMA_CFG_LINE_REPEAT_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_REPEAT_0_RESET_MASK             (_MK_MASK_CONST(0xffffff))
++#define BDMA_CFG_LINE_REPEAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_REPEAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_REPEAT_0_READ_MASK              (_MK_MASK_CONST(0xffffff))
++#define BDMA_CFG_LINE_REPEAT_0_WRITE_MASK             (_MK_MASK_CONST(0xffffff))
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT                 (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_FIELD \
++      (_MK_FIELD_CONST(0xffffff, BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT))
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_RANGE                               (23:0)
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_WOFFSET                              (0x0)
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_DEFAULT              (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_DEFAULT_MASK    (_MK_MASK_CONST(0xffffff))
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_SRC_LINE_0
++#define BDMA_CFG_SRC_LINE_0                             (_MK_ADDR_CONST(0x401c))
++#define BDMA_CFG_SRC_LINE_0_SECURE                                         (0x0)
++#define BDMA_CFG_SRC_LINE_0_DUAL                                           (0x0)
++#define BDMA_CFG_SRC_LINE_0_SCR                                              (0)
++#define BDMA_CFG_SRC_LINE_0_WORD_COUNT                                     (0x1)
++#define BDMA_CFG_SRC_LINE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_LINE_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_SRC_LINE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_LINE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_LINE_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_SRC_LINE_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
++#define BDMA_CFG_SRC_LINE_0_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT))
++#define BDMA_CFG_SRC_LINE_0_STRIDE_RANGE                                  (31:5)
++#define BDMA_CFG_SRC_LINE_0_STRIDE_WOFFSET                                 (0x0)
++#define BDMA_CFG_SRC_LINE_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_LINE_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
++#define BDMA_CFG_SRC_LINE_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_LINE_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_LINE_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_LINE_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_DST_LINE_0
++#define BDMA_CFG_DST_LINE_0                             (_MK_ADDR_CONST(0x4020))
++#define BDMA_CFG_DST_LINE_0_SECURE                                         (0x0)
++#define BDMA_CFG_DST_LINE_0_DUAL                                           (0x0)
++#define BDMA_CFG_DST_LINE_0_SCR                                              (0)
++#define BDMA_CFG_DST_LINE_0_WORD_COUNT                                     (0x1)
++#define BDMA_CFG_DST_LINE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_LINE_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_DST_LINE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_LINE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_LINE_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_DST_LINE_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_DST_LINE_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
++#define BDMA_CFG_DST_LINE_0_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_LINE_0_STRIDE_SHIFT))
++#define BDMA_CFG_DST_LINE_0_STRIDE_RANGE                                  (31:5)
++#define BDMA_CFG_DST_LINE_0_STRIDE_WOFFSET                                 (0x0)
++#define BDMA_CFG_DST_LINE_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_LINE_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
++#define BDMA_CFG_DST_LINE_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_LINE_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_LINE_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_LINE_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_SURF_REPEAT_0
++#define BDMA_CFG_SURF_REPEAT_0                          (_MK_ADDR_CONST(0x4024))
++#define BDMA_CFG_SURF_REPEAT_0_SECURE                                      (0x0)
++#define BDMA_CFG_SURF_REPEAT_0_DUAL                                        (0x0)
++#define BDMA_CFG_SURF_REPEAT_0_SCR                                           (0)
++#define BDMA_CFG_SURF_REPEAT_0_WORD_COUNT                                  (0x1)
++#define BDMA_CFG_SURF_REPEAT_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SURF_REPEAT_0_RESET_MASK             (_MK_MASK_CONST(0xffffff))
++#define BDMA_CFG_SURF_REPEAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SURF_REPEAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SURF_REPEAT_0_READ_MASK              (_MK_MASK_CONST(0xffffff))
++#define BDMA_CFG_SURF_REPEAT_0_WRITE_MASK             (_MK_MASK_CONST(0xffffff))
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT                 (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_FIELD \
++      (_MK_FIELD_CONST(0xffffff, BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT))
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_RANGE                               (23:0)
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_WOFFSET                              (0x0)
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_DEFAULT              (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_DEFAULT_MASK    (_MK_MASK_CONST(0xffffff))
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_SRC_SURF_0
++#define BDMA_CFG_SRC_SURF_0                             (_MK_ADDR_CONST(0x4028))
++#define BDMA_CFG_SRC_SURF_0_SECURE                                         (0x0)
++#define BDMA_CFG_SRC_SURF_0_DUAL                                           (0x0)
++#define BDMA_CFG_SRC_SURF_0_SCR                                              (0)
++#define BDMA_CFG_SRC_SURF_0_WORD_COUNT                                     (0x1)
++#define BDMA_CFG_SRC_SURF_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_SURF_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_SRC_SURF_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_SURF_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_SURF_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_SRC_SURF_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
++#define BDMA_CFG_SRC_SURF_0_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT))
++#define BDMA_CFG_SRC_SURF_0_STRIDE_RANGE                                  (31:5)
++#define BDMA_CFG_SRC_SURF_0_STRIDE_WOFFSET                                 (0x0)
++#define BDMA_CFG_SRC_SURF_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_SURF_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
++#define BDMA_CFG_SRC_SURF_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_SURF_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_SURF_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_SRC_SURF_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_DST_SURF_0
++#define BDMA_CFG_DST_SURF_0                             (_MK_ADDR_CONST(0x402c))
++#define BDMA_CFG_DST_SURF_0_SECURE                                         (0x0)
++#define BDMA_CFG_DST_SURF_0_DUAL                                           (0x0)
++#define BDMA_CFG_DST_SURF_0_SCR                                              (0)
++#define BDMA_CFG_DST_SURF_0_WORD_COUNT                                     (0x1)
++#define BDMA_CFG_DST_SURF_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_SURF_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_DST_SURF_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_SURF_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_SURF_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_DST_SURF_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define BDMA_CFG_DST_SURF_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
++#define BDMA_CFG_DST_SURF_0_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_SURF_0_STRIDE_SHIFT))
++#define BDMA_CFG_DST_SURF_0_STRIDE_RANGE                                  (31:5)
++#define BDMA_CFG_DST_SURF_0_STRIDE_WOFFSET                                 (0x0)
++#define BDMA_CFG_DST_SURF_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_SURF_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
++#define BDMA_CFG_DST_SURF_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_SURF_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_SURF_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_DST_SURF_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_CFG_OP_0
++#define BDMA_CFG_OP_0                                   (_MK_ADDR_CONST(0x4030))
++#define BDMA_CFG_OP_0_SECURE                                               (0x0)
++#define BDMA_CFG_OP_0_DUAL                                                 (0x0)
++#define BDMA_CFG_OP_0_SCR                                                    (0)
++#define BDMA_CFG_OP_0_WORD_COUNT                                           (0x1)
++#define BDMA_CFG_OP_0_RESET_VAL                            (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_OP_0_RESET_MASK                           (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_OP_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_OP_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_OP_0_READ_MASK                            (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_OP_0_WRITE_MASK                           (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_OP_0_EN_SHIFT                              (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_OP_0_EN_FIELD    (_MK_FIELD_CONST(0x1, BDMA_CFG_OP_0_EN_SHIFT))
++#define BDMA_CFG_OP_0_EN_RANGE                                             (0:0)
++#define BDMA_CFG_OP_0_EN_WOFFSET                                           (0x0)
++#define BDMA_CFG_OP_0_EN_DEFAULT                           (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_OP_0_EN_DEFAULT_MASK                      (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_OP_0_EN_SW_DEFAULT                        (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_OP_0_EN_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_OP_0_EN_PARITY_PROTECTION                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_OP_0_EN_PLATFORM_DEPENDENT                (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_OP_0_EN_DISABLE                             (_MK_ENUM_CONST(0))
++#define BDMA_CFG_OP_0_EN_ENABLE                              (_MK_ENUM_CONST(1))
++
++
++// Register BDMA_CFG_LAUNCH0_0
++#define BDMA_CFG_LAUNCH0_0                              (_MK_ADDR_CONST(0x4034))
++#define BDMA_CFG_LAUNCH0_0_SECURE                                          (0x0)
++#define BDMA_CFG_LAUNCH0_0_DUAL                                            (0x0)
++#define BDMA_CFG_LAUNCH0_0_SCR                                               (0)
++#define BDMA_CFG_LAUNCH0_0_WORD_COUNT                                      (0x1)
++#define BDMA_CFG_LAUNCH0_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH0_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH0_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH0_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH0_0_READ_MASK                       (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH0_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT                (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_FIELD \
++      (_MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_RANGE                               (0:0)
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_WOFFSET                             (0x0)
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_DEFAULT             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_NO                    (_MK_ENUM_CONST(0))
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_YES                   (_MK_ENUM_CONST(1))
++
++
++// Register BDMA_CFG_LAUNCH1_0
++#define BDMA_CFG_LAUNCH1_0                              (_MK_ADDR_CONST(0x4038))
++#define BDMA_CFG_LAUNCH1_0_SECURE                                          (0x0)
++#define BDMA_CFG_LAUNCH1_0_DUAL                                            (0x0)
++#define BDMA_CFG_LAUNCH1_0_SCR                                               (0)
++#define BDMA_CFG_LAUNCH1_0_WORD_COUNT                                      (0x1)
++#define BDMA_CFG_LAUNCH1_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH1_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH1_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH1_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH1_0_READ_MASK                       (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH1_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT                (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_FIELD \
++      (_MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_RANGE                               (0:0)
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_WOFFSET                             (0x0)
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_DEFAULT             (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_NO                    (_MK_ENUM_CONST(0))
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_YES                   (_MK_ENUM_CONST(1))
++
++
++// Register BDMA_CFG_STATUS_0
++#define BDMA_CFG_STATUS_0                               (_MK_ADDR_CONST(0x403c))
++#define BDMA_CFG_STATUS_0_SECURE                                           (0x0)
++#define BDMA_CFG_STATUS_0_DUAL                                             (0x0)
++#define BDMA_CFG_STATUS_0_SCR                                                (0)
++#define BDMA_CFG_STATUS_0_WORD_COUNT                                       (0x1)
++#define BDMA_CFG_STATUS_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_STATUS_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_STATUS_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_STATUS_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_STATUS_0_READ_MASK                        (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_STATUS_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT              (_MK_SHIFT_CONST(0))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_RANGE                             (0:0)
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_WOFFSET                           (0x0)
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_DEFAULT           (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_INIT_ENUM                          (NO)
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_NO                  (_MK_ENUM_CONST(0))
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_YES                 (_MK_ENUM_CONST(1))
++
++
++// Register BDMA_STATUS_0
++#define BDMA_STATUS_0                                   (_MK_ADDR_CONST(0x4040))
++#define BDMA_STATUS_0_SECURE                                               (0x0)
++#define BDMA_STATUS_0_DUAL                                                 (0x0)
++#define BDMA_STATUS_0_SCR                                                    (0)
++#define BDMA_STATUS_0_WORD_COUNT                                           (0x1)
++#define BDMA_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x114))
++#define BDMA_STATUS_0_RESET_MASK                         (_MK_MASK_CONST(0x7ff))
++#define BDMA_STATUS_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_READ_MASK                          (_MK_MASK_CONST(0x7ff))
++#define BDMA_STATUS_0_WRITE_MASK                           (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_FREE_SLOT_SHIFT                       (_MK_SHIFT_CONST(0))
++#define BDMA_STATUS_0_FREE_SLOT_FIELD \
++      (_MK_FIELD_CONST(0xff, BDMA_STATUS_0_FREE_SLOT_SHIFT))
++#define BDMA_STATUS_0_FREE_SLOT_RANGE                                      (7:0)
++#define BDMA_STATUS_0_FREE_SLOT_WOFFSET                                    (0x0)
++#define BDMA_STATUS_0_FREE_SLOT_DEFAULT                   (_MK_MASK_CONST(0x14))
++#define BDMA_STATUS_0_FREE_SLOT_DEFAULT_MASK              (_MK_MASK_CONST(0xff))
++#define BDMA_STATUS_0_FREE_SLOT_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_FREE_SLOT_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_FREE_SLOT_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_FREE_SLOT_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++
++#define BDMA_STATUS_0_IDLE_SHIFT                            (_MK_SHIFT_CONST(8))
++#define BDMA_STATUS_0_IDLE_FIELD \
++      (_MK_FIELD_CONST(0x1, BDMA_STATUS_0_IDLE_SHIFT))
++#define BDMA_STATUS_0_IDLE_RANGE                                           (8:8)
++#define BDMA_STATUS_0_IDLE_WOFFSET                                         (0x0)
++#define BDMA_STATUS_0_IDLE_DEFAULT                         (_MK_MASK_CONST(0x1))
++#define BDMA_STATUS_0_IDLE_DEFAULT_MASK                    (_MK_MASK_CONST(0x1))
++#define BDMA_STATUS_0_IDLE_SW_DEFAULT                      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_IDLE_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_IDLE_PARITY_PROTECTION               (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_IDLE_PLATFORM_DEPENDENT              (_MK_MASK_CONST(0x1))
++#define BDMA_STATUS_0_IDLE_INIT_ENUM                                       (YES)
++#define BDMA_STATUS_0_IDLE_NO                                (_MK_ENUM_CONST(0))
++#define BDMA_STATUS_0_IDLE_YES                               (_MK_ENUM_CONST(1))
++
++#define BDMA_STATUS_0_GRP0_BUSY_SHIFT                       (_MK_SHIFT_CONST(9))
++#define BDMA_STATUS_0_GRP0_BUSY_FIELD \
++      (_MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP0_BUSY_SHIFT))
++#define BDMA_STATUS_0_GRP0_BUSY_RANGE                                      (9:9)
++#define BDMA_STATUS_0_GRP0_BUSY_WOFFSET                                    (0x0)
++#define BDMA_STATUS_0_GRP0_BUSY_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_GRP0_BUSY_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
++#define BDMA_STATUS_0_GRP0_BUSY_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_GRP0_BUSY_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_GRP0_BUSY_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_GRP0_BUSY_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define BDMA_STATUS_0_GRP0_BUSY_INIT_ENUM                                   (NO)
++#define BDMA_STATUS_0_GRP0_BUSY_NO                           (_MK_ENUM_CONST(0))
++#define BDMA_STATUS_0_GRP0_BUSY_YES                          (_MK_ENUM_CONST(1))
++
++#define BDMA_STATUS_0_GRP1_BUSY_SHIFT                      (_MK_SHIFT_CONST(10))
++#define BDMA_STATUS_0_GRP1_BUSY_FIELD \
++      (_MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP1_BUSY_SHIFT))
++#define BDMA_STATUS_0_GRP1_BUSY_RANGE                                    (10:10)
++#define BDMA_STATUS_0_GRP1_BUSY_WOFFSET                                    (0x0)
++#define BDMA_STATUS_0_GRP1_BUSY_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_GRP1_BUSY_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
++#define BDMA_STATUS_0_GRP1_BUSY_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_GRP1_BUSY_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_GRP1_BUSY_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_0_GRP1_BUSY_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define BDMA_STATUS_0_GRP1_BUSY_INIT_ENUM                                   (NO)
++#define BDMA_STATUS_0_GRP1_BUSY_NO                           (_MK_ENUM_CONST(0))
++#define BDMA_STATUS_0_GRP1_BUSY_YES                          (_MK_ENUM_CONST(1))
++
++
++// Register BDMA_STATUS_GRP0_READ_STALL_0
++#define BDMA_STATUS_GRP0_READ_STALL_0                   (_MK_ADDR_CONST(0x4044))
++#define BDMA_STATUS_GRP0_READ_STALL_0_SECURE                               (0x0)
++#define BDMA_STATUS_GRP0_READ_STALL_0_DUAL                                 (0x0)
++#define BDMA_STATUS_GRP0_READ_STALL_0_SCR                                    (0)
++#define BDMA_STATUS_GRP0_READ_STALL_0_WORD_COUNT                           (0x1)
++#define BDMA_STATUS_GRP0_READ_STALL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_READ_STALL_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP0_READ_STALL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_READ_STALL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_READ_STALL_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP0_READ_STALL_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT           (_MK_SHIFT_CONST(0))
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT))
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_RANGE                         (31:0)
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_WOFFSET                        (0x0)
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_DEFAULT        (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_STATUS_GRP0_WRITE_STALL_0
++#define BDMA_STATUS_GRP0_WRITE_STALL_0                  (_MK_ADDR_CONST(0x4048))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_SECURE                              (0x0)
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_DUAL                                (0x0)
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_SCR                                   (0)
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_WORD_COUNT                          (0x1)
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_WRITE_MASK          (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT          (_MK_SHIFT_CONST(0))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_RANGE                        (31:0)
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_WOFFSET                       (0x0)
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_STATUS_GRP1_READ_STALL_0
++#define BDMA_STATUS_GRP1_READ_STALL_0                   (_MK_ADDR_CONST(0x404c))
++#define BDMA_STATUS_GRP1_READ_STALL_0_SECURE                               (0x0)
++#define BDMA_STATUS_GRP1_READ_STALL_0_DUAL                                 (0x0)
++#define BDMA_STATUS_GRP1_READ_STALL_0_SCR                                    (0)
++#define BDMA_STATUS_GRP1_READ_STALL_0_WORD_COUNT                           (0x1)
++#define BDMA_STATUS_GRP1_READ_STALL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_READ_STALL_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP1_READ_STALL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_READ_STALL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_READ_STALL_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP1_READ_STALL_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT           (_MK_SHIFT_CONST(0))
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT))
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_RANGE                         (31:0)
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_WOFFSET                        (0x0)
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_DEFAULT        (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register BDMA_STATUS_GRP1_WRITE_STALL_0
++#define BDMA_STATUS_GRP1_WRITE_STALL_0                  (_MK_ADDR_CONST(0x4050))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_SECURE                              (0x0)
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_DUAL                                (0x0)
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_SCR                                   (0)
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_WORD_COUNT                          (0x1)
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_WRITE_MASK          (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT          (_MK_SHIFT_CONST(0))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_RANGE                        (31:0)
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_WOFFSET                       (0x0)
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_S_STATUS_0
++#define CDMA_S_STATUS_0                                 (_MK_ADDR_CONST(0x5000))
++#define CDMA_S_STATUS_0_SECURE                                             (0x0)
++#define CDMA_S_STATUS_0_DUAL                                               (0x0)
++#define CDMA_S_STATUS_0_SCR                                                  (0)
++#define CDMA_S_STATUS_0_WORD_COUNT                                         (0x1)
++#define CDMA_S_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_RESET_MASK                     (_MK_MASK_CONST(0x30003))
++#define CDMA_S_STATUS_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_READ_MASK                      (_MK_MASK_CONST(0x30003))
++#define CDMA_S_STATUS_0_WRITE_MASK                         (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_STATUS_0_SHIFT                      (_MK_SHIFT_CONST(0))
++#define CDMA_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_0_SHIFT))
++#define CDMA_S_STATUS_0_STATUS_0_RANGE                                     (1:0)
++#define CDMA_S_STATUS_0_STATUS_0_WOFFSET                                   (0x0)
++#define CDMA_S_STATUS_0_STATUS_0_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
++#define CDMA_S_STATUS_0_STATUS_0_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CDMA_S_STATUS_0_STATUS_0_INIT_ENUM                                (IDLE)
++#define CDMA_S_STATUS_0_STATUS_0_IDLE                        (_MK_ENUM_CONST(0))
++#define CDMA_S_STATUS_0_STATUS_0_RUNNING                     (_MK_ENUM_CONST(1))
++#define CDMA_S_STATUS_0_STATUS_0_PENDING                     (_MK_ENUM_CONST(2))
++
++#define CDMA_S_STATUS_0_STATUS_1_SHIFT                     (_MK_SHIFT_CONST(16))
++#define CDMA_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_1_SHIFT))
++#define CDMA_S_STATUS_0_STATUS_1_RANGE                                   (17:16)
++#define CDMA_S_STATUS_0_STATUS_1_WOFFSET                                   (0x0)
++#define CDMA_S_STATUS_0_STATUS_1_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
++#define CDMA_S_STATUS_0_STATUS_1_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CDMA_S_STATUS_0_STATUS_1_INIT_ENUM                                (IDLE)
++#define CDMA_S_STATUS_0_STATUS_1_IDLE                        (_MK_ENUM_CONST(0))
++#define CDMA_S_STATUS_0_STATUS_1_RUNNING                     (_MK_ENUM_CONST(1))
++#define CDMA_S_STATUS_0_STATUS_1_PENDING                     (_MK_ENUM_CONST(2))
++
++
++// Register CDMA_S_POINTER_0
++#define CDMA_S_POINTER_0                                (_MK_ADDR_CONST(0x5004))
++#define CDMA_S_POINTER_0_SECURE                                            (0x0)
++#define CDMA_S_POINTER_0_DUAL                                              (0x0)
++#define CDMA_S_POINTER_0_SCR                                                 (0)
++#define CDMA_S_POINTER_0_WORD_COUNT                                        (0x1)
++#define CDMA_S_POINTER_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_RESET_MASK                    (_MK_MASK_CONST(0x10001))
++#define CDMA_S_POINTER_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_READ_MASK                     (_MK_MASK_CONST(0x10001))
++#define CDMA_S_POINTER_0_WRITE_MASK                        (_MK_MASK_CONST(0x1))
++#define CDMA_S_POINTER_0_PRODUCER_SHIFT                     (_MK_SHIFT_CONST(0))
++#define CDMA_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_PRODUCER_SHIFT))
++#define CDMA_S_POINTER_0_PRODUCER_RANGE                                    (0:0)
++#define CDMA_S_POINTER_0_PRODUCER_WOFFSET                                  (0x0)
++#define CDMA_S_POINTER_0_PRODUCER_DEFAULT                  (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
++#define CDMA_S_POINTER_0_PRODUCER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
++#define CDMA_S_POINTER_0_PRODUCER_INIT_ENUM                            (GROUP_0)
++#define CDMA_S_POINTER_0_PRODUCER_GROUP_0                    (_MK_ENUM_CONST(0))
++#define CDMA_S_POINTER_0_PRODUCER_GROUP_1                    (_MK_ENUM_CONST(1))
++
++#define CDMA_S_POINTER_0_CONSUMER_SHIFT                    (_MK_SHIFT_CONST(16))
++#define CDMA_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_CONSUMER_SHIFT))
++#define CDMA_S_POINTER_0_CONSUMER_RANGE                                  (16:16)
++#define CDMA_S_POINTER_0_CONSUMER_WOFFSET                                  (0x0)
++#define CDMA_S_POINTER_0_CONSUMER_DEFAULT                  (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
++#define CDMA_S_POINTER_0_CONSUMER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
++#define CDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
++#define CDMA_S_POINTER_0_CONSUMER_INIT_ENUM                            (GROUP_0)
++#define CDMA_S_POINTER_0_CONSUMER_GROUP_0                    (_MK_ENUM_CONST(0))
++#define CDMA_S_POINTER_0_CONSUMER_GROUP_1                    (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_S_ARBITER_0
++#define CDMA_S_ARBITER_0                                (_MK_ADDR_CONST(0x5008))
++#define CDMA_S_ARBITER_0_SECURE                                            (0x0)
++#define CDMA_S_ARBITER_0_DUAL                                              (0x0)
++#define CDMA_S_ARBITER_0_SCR                                                 (0)
++#define CDMA_S_ARBITER_0_WORD_COUNT                                        (0x1)
++#define CDMA_S_ARBITER_0_RESET_VAL                     (_MK_MASK_CONST(0x3000f))
++#define CDMA_S_ARBITER_0_RESET_MASK                    (_MK_MASK_CONST(0xf000f))
++#define CDMA_S_ARBITER_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_S_ARBITER_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define CDMA_S_ARBITER_0_READ_MASK                     (_MK_MASK_CONST(0xf000f))
++#define CDMA_S_ARBITER_0_WRITE_MASK                    (_MK_MASK_CONST(0xf000f))
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT                   (_MK_SHIFT_CONST(0))
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_FIELD \
++      (_MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT))
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_RANGE                                  (3:0)
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_WOFFSET                                (0x0)
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_DEFAULT                (_MK_MASK_CONST(0xf))
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_DEFAULT_MASK           (_MK_MASK_CONST(0xf))
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++#define CDMA_S_ARBITER_0_ARB_WMB_SHIFT                     (_MK_SHIFT_CONST(16))
++#define CDMA_S_ARBITER_0_ARB_WMB_FIELD \
++      (_MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WMB_SHIFT))
++#define CDMA_S_ARBITER_0_ARB_WMB_RANGE                                   (19:16)
++#define CDMA_S_ARBITER_0_ARB_WMB_WOFFSET                                   (0x0)
++#define CDMA_S_ARBITER_0_ARB_WMB_DEFAULT                   (_MK_MASK_CONST(0x3))
++#define CDMA_S_ARBITER_0_ARB_WMB_DEFAULT_MASK              (_MK_MASK_CONST(0xf))
++#define CDMA_S_ARBITER_0_ARB_WMB_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDMA_S_ARBITER_0_ARB_WMB_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_S_ARBITER_0_ARB_WMB_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CDMA_S_ARBITER_0_ARB_WMB_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_S_CBUF_FLUSH_STATUS_0
++#define CDMA_S_CBUF_FLUSH_STATUS_0                      (_MK_ADDR_CONST(0x500c))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_SECURE                                  (0x0)
++#define CDMA_S_CBUF_FLUSH_STATUS_0_DUAL                                    (0x0)
++#define CDMA_S_CBUF_FLUSH_STATUS_0_SCR                                       (0)
++#define CDMA_S_CBUF_FLUSH_STATUS_0_WORD_COUNT                              (0x1)
++#define CDMA_S_CBUF_FLUSH_STATUS_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_RESET_MASK              (_MK_MASK_CONST(0x1))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_READ_MASK               (_MK_MASK_CONST(0x1))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_WRITE_MASK              (_MK_MASK_CONST(0x0))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_RANGE                        (0:0)
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_WOFFSET                      (0x0)
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_OP_ENABLE_0
++#define CDMA_D_OP_ENABLE_0                              (_MK_ADDR_CONST(0x5010))
++#define CDMA_D_OP_ENABLE_0_SECURE                                          (0x0)
++#define CDMA_D_OP_ENABLE_0_DUAL                                            (0x0)
++#define CDMA_D_OP_ENABLE_0_SCR                                               (0)
++#define CDMA_D_OP_ENABLE_0_WORD_COUNT                                      (0x1)
++#define CDMA_D_OP_ENABLE_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define CDMA_D_OP_ENABLE_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
++#define CDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define CDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_OP_ENABLE_0_READ_MASK                       (_MK_MASK_CONST(0x1))
++#define CDMA_D_OP_ENABLE_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
++#define CDMA_D_OP_ENABLE_0_OP_EN_SHIFT                      (_MK_SHIFT_CONST(0))
++#define CDMA_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define CDMA_D_OP_ENABLE_0_OP_EN_RANGE                                     (0:0)
++#define CDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                                   (0x0)
++#define CDMA_D_OP_ENABLE_0_OP_EN_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define CDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                             (DISABLE)
++#define CDMA_D_OP_ENABLE_0_OP_EN_DISABLE                     (_MK_ENUM_CONST(0))
++#define CDMA_D_OP_ENABLE_0_OP_EN_ENABLE                      (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_D_MISC_CFG_0
++#define CDMA_D_MISC_CFG_0                               (_MK_ADDR_CONST(0x5014))
++#define CDMA_D_MISC_CFG_0_SECURE                                           (0x0)
++#define CDMA_D_MISC_CFG_0_DUAL                                             (0x0)
++#define CDMA_D_MISC_CFG_0_SCR                                                (0)
++#define CDMA_D_MISC_CFG_0_WORD_COUNT                                       (0x1)
++#define CDMA_D_MISC_CFG_0_RESET_VAL                     (_MK_MASK_CONST(0x1100))
++#define CDMA_D_MISC_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x11113301))
++#define CDMA_D_MISC_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x11113301))
++#define CDMA_D_MISC_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x11113301))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT                   (_MK_SHIFT_CONST(0))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_RANGE                                  (0:0)
++#define CDMA_D_MISC_CFG_0_CONV_MODE_WOFFSET                                (0x0)
++#define CDMA_D_MISC_CFG_0_CONV_MODE_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                           (DIRECT)
++#define CDMA_D_MISC_CFG_0_CONV_MODE_DIRECT                   (_MK_ENUM_CONST(0))
++#define CDMA_D_MISC_CFG_0_CONV_MODE_WINOGRAD                 (_MK_ENUM_CONST(1))
++
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT                (_MK_SHIFT_CONST(8))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_RANGE                               (9:8)
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_WOFFSET                             (0x0)
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_DEFAULT             (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_DEFAULT_MASK        (_MK_MASK_CONST(0x3))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_INIT_ENUM                         (INT16)
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT8                  (_MK_ENUM_CONST(0))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT16                 (_MK_ENUM_CONST(1))
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_FP16                  (_MK_ENUM_CONST(2))
++
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT             (_MK_SHIFT_CONST(12))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_RANGE                           (13:12)
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                           (0x0)
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_DEFAULT           (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK      (_MK_MASK_CONST(0x3))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                       (INT16)
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT8                (_MK_ENUM_CONST(0))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT16               (_MK_ENUM_CONST(1))
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FP16                (_MK_ENUM_CONST(2))
++
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT                 (_MK_SHIFT_CONST(16))
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT))
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_RANGE                               (16:16)
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_WOFFSET                               (0x0)
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_INIT_ENUM                         (DISABLE)
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_DISABLE                 (_MK_ENUM_CONST(0))
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_ENABLE                  (_MK_ENUM_CONST(1))
++
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT               (_MK_SHIFT_CONST(20))
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT))
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_RANGE                             (20:20)
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_WOFFSET                             (0x0)
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_INIT_ENUM                       (DISABLE)
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE               (_MK_ENUM_CONST(0))
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE                (_MK_ENUM_CONST(1))
++
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT              (_MK_SHIFT_CONST(24))
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT))
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_RANGE                            (24:24)
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_WOFFSET                            (0x0)
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_INIT_ENUM                      (DISABLE)
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE              (_MK_ENUM_CONST(0))
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE               (_MK_ENUM_CONST(1))
++
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT            (_MK_SHIFT_CONST(28))
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT))
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_RANGE                          (28:28)
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_WOFFSET                          (0x0)
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_INIT_ENUM                    (DISABLE)
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE            (_MK_ENUM_CONST(0))
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE             (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_D_DATAIN_FORMAT_0
++#define CDMA_D_DATAIN_FORMAT_0                          (_MK_ADDR_CONST(0x5018))
++#define CDMA_D_DATAIN_FORMAT_0_SECURE                                      (0x0)
++#define CDMA_D_DATAIN_FORMAT_0_DUAL                                        (0x0)
++#define CDMA_D_DATAIN_FORMAT_0_SCR                                           (0)
++#define CDMA_D_DATAIN_FORMAT_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_DATAIN_FORMAT_0_RESET_VAL                 (_MK_MASK_CONST(0xc00))
++#define CDMA_D_DATAIN_FORMAT_0_RESET_MASK             (_MK_MASK_CONST(0x113f01))
++#define CDMA_D_DATAIN_FORMAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_READ_MASK              (_MK_MASK_CONST(0x113f01))
++#define CDMA_D_DATAIN_FORMAT_0_WRITE_MASK             (_MK_MASK_CONST(0x113f01))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT          (_MK_SHIFT_CONST(0))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_RANGE                         (0:0)
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_WOFFSET                       (0x0)
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_INIT_ENUM                 (FEATURE)
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE         (_MK_ENUM_CONST(0))
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL           (_MK_ENUM_CONST(1))
++
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT           (_MK_SHIFT_CONST(8))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_FIELD \
++      (_MK_FIELD_CONST(0x3f, CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_RANGE                         (13:8)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_WOFFSET                        (0x0)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_DEFAULT        (_MK_MASK_CONST(0xc))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_INIT_ENUM               (T_A8B8G8R8)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8             (_MK_ENUM_CONST(0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10            (_MK_ENUM_CONST(1))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R12            (_MK_ENUM_CONST(2))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16            (_MK_ENUM_CONST(3))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_I          (_MK_ENUM_CONST(4))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_F          (_MK_ENUM_CONST(5))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16 \
++      (_MK_ENUM_CONST(6))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X16B16G16R16 \
++      (_MK_ENUM_CONST(7))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16_F \
++      (_MK_ENUM_CONST(8))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16 \
++      (_MK_ENUM_CONST(9))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V16U16Y16A16 \
++      (_MK_ENUM_CONST(10))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16_F \
++      (_MK_ENUM_CONST(11))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8B8G8R8      (_MK_ENUM_CONST(12))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8R8G8B8      (_MK_ENUM_CONST(13))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8A8      (_MK_ENUM_CONST(14))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8A8      (_MK_ENUM_CONST(15))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8B8G8R8      (_MK_ENUM_CONST(16))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8R8G8B8      (_MK_ENUM_CONST(17))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8X8      (_MK_ENUM_CONST(18))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8X8      (_MK_ENUM_CONST(19))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2B10G10R10 \
++      (_MK_ENUM_CONST(20))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2R10G10B10 \
++      (_MK_ENUM_CONST(21))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B10G10R10A2 \
++      (_MK_ENUM_CONST(22))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10G10B10A2 \
++      (_MK_ENUM_CONST(23))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2Y10U10V10 \
++      (_MK_ENUM_CONST(24))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V10U10Y10A2 \
++      (_MK_ENUM_CONST(25))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8Y8U8V8      (_MK_ENUM_CONST(26))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V8U8Y8A8      (_MK_ENUM_CONST(27))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___U8V8_N444 \
++      (_MK_ENUM_CONST(28))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___V8U8_N444 \
++      (_MK_ENUM_CONST(29))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___U10V10_N444 \
++      (_MK_ENUM_CONST(30))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___V10U10_N444 \
++      (_MK_ENUM_CONST(31))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___U12V12_N444 \
++      (_MK_ENUM_CONST(32))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___V12U12_N444 \
++      (_MK_ENUM_CONST(33))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___U16V16_N444 \
++      (_MK_ENUM_CONST(34))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___V16U16_N444 \
++      (_MK_ENUM_CONST(35))
++
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT         (_MK_SHIFT_CONST(16))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RANGE                       (16:16)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_WOFFSET                       (0x0)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_INIT_ENUM            (PITCH_LINEAR)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PITCH_LINEAR    (_MK_ENUM_CONST(0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RESERVED_LINEAR \
++      (_MK_ENUM_CONST(1))
++
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT \
++      (_MK_SHIFT_CONST(20))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_RANGE                 (20:20)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_WOFFSET                 (0x0)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_INIT_ENUM      (UNSIGNED_INT)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_UNSIGNED_INT \
++      (_MK_ENUM_CONST(0))
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SIGNED_INT \
++      (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_D_DATAIN_SIZE_0_0
++#define CDMA_D_DATAIN_SIZE_0_0                          (_MK_ADDR_CONST(0x501c))
++#define CDMA_D_DATAIN_SIZE_0_0_SECURE                                      (0x0)
++#define CDMA_D_DATAIN_SIZE_0_0_DUAL                                        (0x0)
++#define CDMA_D_DATAIN_SIZE_0_0_SCR                                           (0)
++#define CDMA_D_DATAIN_SIZE_0_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_DATAIN_SIZE_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_RESET_MASK           (_MK_MASK_CONST(0x1fff1fff))
++#define CDMA_D_DATAIN_SIZE_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_READ_MASK            (_MK_MASK_CONST(0x1fff1fff))
++#define CDMA_D_DATAIN_SIZE_0_0_WRITE_MASK           (_MK_MASK_CONST(0x1fff1fff))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT           (_MK_SHIFT_CONST(0))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_RANGE                         (12:0)
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_WOFFSET                        (0x0)
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT         (_MK_SHIFT_CONST(16))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_RANGE                       (28:16)
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_WOFFSET                       (0x0)
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_DATAIN_SIZE_1_0
++#define CDMA_D_DATAIN_SIZE_1_0                          (_MK_ADDR_CONST(0x5020))
++#define CDMA_D_DATAIN_SIZE_1_0_SECURE                                      (0x0)
++#define CDMA_D_DATAIN_SIZE_1_0_DUAL                                        (0x0)
++#define CDMA_D_DATAIN_SIZE_1_0_SCR                                           (0)
++#define CDMA_D_DATAIN_SIZE_1_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_DATAIN_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_DATAIN_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_DATAIN_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT))
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_RANGE                       (12:0)
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_WOFFSET                      (0x0)
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_DATAIN_SIZE_EXT_0_0
++#define CDMA_D_DATAIN_SIZE_EXT_0_0                      (_MK_ADDR_CONST(0x5024))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_SECURE                                  (0x0)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DUAL                                    (0x0)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_SCR                                       (0)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_WORD_COUNT                              (0x1)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_RESET_MASK       (_MK_MASK_CONST(0x1fff1fff))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_READ_MASK        (_MK_MASK_CONST(0x1fff1fff))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_WRITE_MASK       (_MK_MASK_CONST(0x1fff1fff))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_RANGE                 (12:0)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_WOFFSET                (0x0)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT \
++      (_MK_SHIFT_CONST(16))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_RANGE               (28:16)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_WOFFSET               (0x0)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_PIXEL_OFFSET_0
++#define CDMA_D_PIXEL_OFFSET_0                           (_MK_ADDR_CONST(0x5028))
++#define CDMA_D_PIXEL_OFFSET_0_SECURE                                       (0x0)
++#define CDMA_D_PIXEL_OFFSET_0_DUAL                                         (0x0)
++#define CDMA_D_PIXEL_OFFSET_0_SCR                                            (0)
++#define CDMA_D_PIXEL_OFFSET_0_WORD_COUNT                                   (0x1)
++#define CDMA_D_PIXEL_OFFSET_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_RESET_MASK               (_MK_MASK_CONST(0x7001f))
++#define CDMA_D_PIXEL_OFFSET_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_READ_MASK                (_MK_MASK_CONST(0x7001f))
++#define CDMA_D_PIXEL_OFFSET_0_WRITE_MASK               (_MK_MASK_CONST(0x7001f))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT          (_MK_SHIFT_CONST(0))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0x1f, CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_RANGE                         (4:0)
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_WOFFSET                       (0x0)
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT         (_MK_SHIFT_CONST(16))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0x7, CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_RANGE                       (18:16)
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_WOFFSET                       (0x0)
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_DAIN_RAM_TYPE_0
++#define CDMA_D_DAIN_RAM_TYPE_0                          (_MK_ADDR_CONST(0x502c))
++#define CDMA_D_DAIN_RAM_TYPE_0_SECURE                                      (0x0)
++#define CDMA_D_DAIN_RAM_TYPE_0_DUAL                                        (0x0)
++#define CDMA_D_DAIN_RAM_TYPE_0_SCR                                           (0)
++#define CDMA_D_DAIN_RAM_TYPE_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_DAIN_RAM_TYPE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_RAM_TYPE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
++#define CDMA_D_DAIN_RAM_TYPE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_RAM_TYPE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_RAM_TYPE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
++#define CDMA_D_DAIN_RAM_TYPE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT        (_MK_SHIFT_CONST(0))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_RANGE                       (0:0)
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_WOFFSET                     (0x0)
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_INIT_ENUM                  (CVIF)
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF          (_MK_ENUM_CONST(0))
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF          (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_D_DAIN_ADDR_HIGH_0_0
++#define CDMA_D_DAIN_ADDR_HIGH_0_0                       (_MK_ADDR_CONST(0x5030))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_SECURE                                   (0x0)
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DUAL                                     (0x0)
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_SCR                                        (0)
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_WORD_COUNT                               (0x1)
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_RESET_MASK        (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_READ_MASK         (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_RANGE                (31:0)
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_WOFFSET               (0x0)
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_DAIN_ADDR_LOW_0_0
++#define CDMA_D_DAIN_ADDR_LOW_0_0                        (_MK_ADDR_CONST(0x5034))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_SECURE                                    (0x0)
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DUAL                                      (0x0)
++#define CDMA_D_DAIN_ADDR_LOW_0_0_SCR                                         (0)
++#define CDMA_D_DAIN_ADDR_LOW_0_0_WORD_COUNT                                (0x1)
++#define CDMA_D_DAIN_ADDR_LOW_0_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT    (_MK_SHIFT_CONST(5))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_RANGE                  (31:5)
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_WOFFSET                 (0x0)
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_DAIN_ADDR_HIGH_1_0
++#define CDMA_D_DAIN_ADDR_HIGH_1_0                       (_MK_ADDR_CONST(0x5038))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_SECURE                                   (0x0)
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DUAL                                     (0x0)
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_SCR                                        (0)
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_WORD_COUNT                               (0x1)
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_RESET_MASK        (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_READ_MASK         (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_RANGE                (31:0)
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_WOFFSET               (0x0)
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_DAIN_ADDR_LOW_1_0
++#define CDMA_D_DAIN_ADDR_LOW_1_0                        (_MK_ADDR_CONST(0x503c))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_SECURE                                    (0x0)
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DUAL                                      (0x0)
++#define CDMA_D_DAIN_ADDR_LOW_1_0_SCR                                         (0)
++#define CDMA_D_DAIN_ADDR_LOW_1_0_WORD_COUNT                                (0x1)
++#define CDMA_D_DAIN_ADDR_LOW_1_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT    (_MK_SHIFT_CONST(5))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_RANGE                  (31:5)
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_WOFFSET                 (0x0)
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_LINE_STRIDE_0
++#define CDMA_D_LINE_STRIDE_0                            (_MK_ADDR_CONST(0x5040))
++#define CDMA_D_LINE_STRIDE_0_SECURE                                        (0x0)
++#define CDMA_D_LINE_STRIDE_0_DUAL                                          (0x0)
++#define CDMA_D_LINE_STRIDE_0_SCR                                             (0)
++#define CDMA_D_LINE_STRIDE_0_WORD_COUNT                                    (0x1)
++#define CDMA_D_LINE_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_STRIDE_0_RESET_MASK             (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_LINE_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_STRIDE_0_READ_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_LINE_STRIDE_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT))
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_RANGE                            (31:5)
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_WOFFSET                           (0x0)
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_LINE_UV_STRIDE_0
++#define CDMA_D_LINE_UV_STRIDE_0                         (_MK_ADDR_CONST(0x5044))
++#define CDMA_D_LINE_UV_STRIDE_0_SECURE                                     (0x0)
++#define CDMA_D_LINE_UV_STRIDE_0_DUAL                                       (0x0)
++#define CDMA_D_LINE_UV_STRIDE_0_SCR                                          (0)
++#define CDMA_D_LINE_UV_STRIDE_0_WORD_COUNT                                 (0x1)
++#define CDMA_D_LINE_UV_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_UV_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_LINE_UV_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_UV_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_UV_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_LINE_UV_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT        (_MK_SHIFT_CONST(5))
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT))
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_RANGE                      (31:5)
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_WOFFSET                     (0x0)
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_SURF_STRIDE_0
++#define CDMA_D_SURF_STRIDE_0                            (_MK_ADDR_CONST(0x5048))
++#define CDMA_D_SURF_STRIDE_0_SECURE                                        (0x0)
++#define CDMA_D_SURF_STRIDE_0_DUAL                                          (0x0)
++#define CDMA_D_SURF_STRIDE_0_SCR                                             (0)
++#define CDMA_D_SURF_STRIDE_0_WORD_COUNT                                    (0x1)
++#define CDMA_D_SURF_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CDMA_D_SURF_STRIDE_0_RESET_MASK             (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_SURF_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CDMA_D_SURF_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDMA_D_SURF_STRIDE_0_READ_MASK              (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_SURF_STRIDE_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT))
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_RANGE                            (31:5)
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_WOFFSET                           (0x0)
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_DAIN_MAP_0
++#define CDMA_D_DAIN_MAP_0                               (_MK_ADDR_CONST(0x504c))
++#define CDMA_D_DAIN_MAP_0_SECURE                                           (0x0)
++#define CDMA_D_DAIN_MAP_0_DUAL                                             (0x0)
++#define CDMA_D_DAIN_MAP_0_SCR                                                (0)
++#define CDMA_D_DAIN_MAP_0_WORD_COUNT                                       (0x1)
++#define CDMA_D_DAIN_MAP_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_RESET_MASK                   (_MK_MASK_CONST(0x10001))
++#define CDMA_D_DAIN_MAP_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_READ_MASK                    (_MK_MASK_CONST(0x10001))
++#define CDMA_D_DAIN_MAP_0_WRITE_MASK                   (_MK_MASK_CONST(0x10001))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT                 (_MK_SHIFT_CONST(0))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_RANGE                                (0:0)
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_WOFFSET                              (0x0)
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_INIT_ENUM                          (FALSE)
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FALSE                  (_MK_ENUM_CONST(0))
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_TRUE                   (_MK_ENUM_CONST(1))
++
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT                (_MK_SHIFT_CONST(16))
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT))
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_RANGE                              (16:16)
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_WOFFSET                              (0x0)
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_INIT_ENUM                          (FALSE)
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FALSE                  (_MK_ENUM_CONST(0))
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_TRUE                   (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_D_RESERVED_X_CFG_0
++#define CDMA_D_RESERVED_X_CFG_0                         (_MK_ADDR_CONST(0x5050))
++#define CDMA_D_RESERVED_X_CFG_0_SECURE                                     (0x0)
++#define CDMA_D_RESERVED_X_CFG_0_DUAL                                       (0x0)
++#define CDMA_D_RESERVED_X_CFG_0_SCR                                          (0)
++#define CDMA_D_RESERVED_X_CFG_0_WORD_COUNT                                 (0x1)
++#define CDMA_D_RESERVED_X_CFG_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_RESET_MASK           (_MK_MASK_CONST(0x3ff03ff))
++#define CDMA_D_RESERVED_X_CFG_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_READ_MASK            (_MK_MASK_CONST(0x3ff03ff))
++#define CDMA_D_RESERVED_X_CFG_0_WRITE_MASK           (_MK_MASK_CONST(0x3ff03ff))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT          (_MK_SHIFT_CONST(0))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_FIELD \
++      (_MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_RANGE                         (9:0)
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_WOFFSET                       (0x0)
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT      (_MK_SHIFT_CONST(16))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_RANGE                    (25:16)
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_WOFFSET                    (0x0)
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_RESERVED_Y_CFG_0
++#define CDMA_D_RESERVED_Y_CFG_0                         (_MK_ADDR_CONST(0x5054))
++#define CDMA_D_RESERVED_Y_CFG_0_SECURE                                     (0x0)
++#define CDMA_D_RESERVED_Y_CFG_0_DUAL                                       (0x0)
++#define CDMA_D_RESERVED_Y_CFG_0_SCR                                          (0)
++#define CDMA_D_RESERVED_Y_CFG_0_WORD_COUNT                                 (0x1)
++#define CDMA_D_RESERVED_Y_CFG_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_RESET_MASK            (_MK_MASK_CONST(0x1f0007))
++#define CDMA_D_RESERVED_Y_CFG_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_READ_MASK             (_MK_MASK_CONST(0x1f0007))
++#define CDMA_D_RESERVED_Y_CFG_0_WRITE_MASK            (_MK_MASK_CONST(0x1f0007))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT            (_MK_SHIFT_CONST(0))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x7, CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_RANGE                           (2:0)
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_WOFFSET                         (0x0)
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_DEFAULT_MASK    (_MK_MASK_CONST(0x7))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT          (_MK_SHIFT_CONST(16))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_FIELD \
++      (_MK_FIELD_CONST(0x1f, CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_RANGE                        (20:16)
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_WOFFSET                        (0x0)
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_BATCH_NUMBER_0
++#define CDMA_D_BATCH_NUMBER_0                           (_MK_ADDR_CONST(0x5058))
++#define CDMA_D_BATCH_NUMBER_0_SECURE                                       (0x0)
++#define CDMA_D_BATCH_NUMBER_0_DUAL                                         (0x0)
++#define CDMA_D_BATCH_NUMBER_0_SCR                                            (0)
++#define CDMA_D_BATCH_NUMBER_0_WORD_COUNT                                   (0x1)
++#define CDMA_D_BATCH_NUMBER_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_NUMBER_0_RESET_MASK                  (_MK_MASK_CONST(0x1f))
++#define CDMA_D_BATCH_NUMBER_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_NUMBER_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_NUMBER_0_READ_MASK                   (_MK_MASK_CONST(0x1f))
++#define CDMA_D_BATCH_NUMBER_0_WRITE_MASK                  (_MK_MASK_CONST(0x1f))
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT                 (_MK_SHIFT_CONST(0))
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_FIELD \
++      (_MK_FIELD_CONST(0x1f, CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT))
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_RANGE                                (4:0)
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_WOFFSET                              (0x0)
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_BATCH_STRIDE_0
++#define CDMA_D_BATCH_STRIDE_0                           (_MK_ADDR_CONST(0x505c))
++#define CDMA_D_BATCH_STRIDE_0_SECURE                                       (0x0)
++#define CDMA_D_BATCH_STRIDE_0_DUAL                                         (0x0)
++#define CDMA_D_BATCH_STRIDE_0_SCR                                            (0)
++#define CDMA_D_BATCH_STRIDE_0_WORD_COUNT                                   (0x1)
++#define CDMA_D_BATCH_STRIDE_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_STRIDE_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_BATCH_STRIDE_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_STRIDE_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_STRIDE_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_BATCH_STRIDE_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT            (_MK_SHIFT_CONST(5))
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT))
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_RANGE                          (31:5)
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_WOFFSET                         (0x0)
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_ENTRY_PER_SLICE_0
++#define CDMA_D_ENTRY_PER_SLICE_0                        (_MK_ADDR_CONST(0x5060))
++#define CDMA_D_ENTRY_PER_SLICE_0_SECURE                                    (0x0)
++#define CDMA_D_ENTRY_PER_SLICE_0_DUAL                                      (0x0)
++#define CDMA_D_ENTRY_PER_SLICE_0_SCR                                         (0)
++#define CDMA_D_ENTRY_PER_SLICE_0_WORD_COUNT                                (0x1)
++#define CDMA_D_ENTRY_PER_SLICE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_ENTRY_PER_SLICE_0_RESET_MASK              (_MK_MASK_CONST(0xfff))
++#define CDMA_D_ENTRY_PER_SLICE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDMA_D_ENTRY_PER_SLICE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_D_ENTRY_PER_SLICE_0_READ_MASK               (_MK_MASK_CONST(0xfff))
++#define CDMA_D_ENTRY_PER_SLICE_0_WRITE_MASK              (_MK_MASK_CONST(0xfff))
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT              (_MK_SHIFT_CONST(0))
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD \
++      (_MK_FIELD_CONST(0xfff, CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT))
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_RANGE                            (11:0)
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_WOFFSET                           (0x0)
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT_MASK    (_MK_MASK_CONST(0xfff))
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_FETCH_GRAIN_0
++#define CDMA_D_FETCH_GRAIN_0                            (_MK_ADDR_CONST(0x5064))
++#define CDMA_D_FETCH_GRAIN_0_SECURE                                        (0x0)
++#define CDMA_D_FETCH_GRAIN_0_DUAL                                          (0x0)
++#define CDMA_D_FETCH_GRAIN_0_SCR                                             (0)
++#define CDMA_D_FETCH_GRAIN_0_WORD_COUNT                                    (0x1)
++#define CDMA_D_FETCH_GRAIN_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CDMA_D_FETCH_GRAIN_0_RESET_MASK                  (_MK_MASK_CONST(0xfff))
++#define CDMA_D_FETCH_GRAIN_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CDMA_D_FETCH_GRAIN_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDMA_D_FETCH_GRAIN_0_READ_MASK                   (_MK_MASK_CONST(0xfff))
++#define CDMA_D_FETCH_GRAIN_0_WRITE_MASK                  (_MK_MASK_CONST(0xfff))
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT                   (_MK_SHIFT_CONST(0))
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_FIELD \
++      (_MK_FIELD_CONST(0xfff, CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT))
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_RANGE                                 (11:0)
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_WOFFSET                                (0x0)
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_DEFAULT_MASK         (_MK_MASK_CONST(0xfff))
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WEIGHT_FORMAT_0
++#define CDMA_D_WEIGHT_FORMAT_0                          (_MK_ADDR_CONST(0x5068))
++#define CDMA_D_WEIGHT_FORMAT_0_SECURE                                      (0x0)
++#define CDMA_D_WEIGHT_FORMAT_0_DUAL                                        (0x0)
++#define CDMA_D_WEIGHT_FORMAT_0_SCR                                           (0)
++#define CDMA_D_WEIGHT_FORMAT_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_WEIGHT_FORMAT_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_FORMAT_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_FORMAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_FORMAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_FORMAT_0_READ_MASK                   (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_FORMAT_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT          (_MK_SHIFT_CONST(0))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_RANGE                         (0:0)
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_WOFFSET                       (0x0)
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_INIT_ENUM            (UNCOMPRESSED)
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED    (_MK_ENUM_CONST(0))
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED      (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_D_WEIGHT_SIZE_0_0
++#define CDMA_D_WEIGHT_SIZE_0_0                          (_MK_ADDR_CONST(0x506c))
++#define CDMA_D_WEIGHT_SIZE_0_0_SECURE                                      (0x0)
++#define CDMA_D_WEIGHT_SIZE_0_0_DUAL                                        (0x0)
++#define CDMA_D_WEIGHT_SIZE_0_0_SCR                                           (0)
++#define CDMA_D_WEIGHT_SIZE_0_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_WEIGHT_SIZE_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_0_0_RESET_MASK              (_MK_MASK_CONST(0x3ffff))
++#define CDMA_D_WEIGHT_SIZE_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_0_0_READ_MASK               (_MK_MASK_CONST(0x3ffff))
++#define CDMA_D_WEIGHT_SIZE_0_0_WRITE_MASK              (_MK_MASK_CONST(0x3ffff))
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT        (_MK_SHIFT_CONST(0))
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_FIELD \
++      (_MK_FIELD_CONST(0x3ffff, \
++      CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT))
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_RANGE                      (17:0)
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_WOFFSET                     (0x0)
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ffff))
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WEIGHT_SIZE_1_0
++#define CDMA_D_WEIGHT_SIZE_1_0                          (_MK_ADDR_CONST(0x5070))
++#define CDMA_D_WEIGHT_SIZE_1_0_SECURE                                      (0x0)
++#define CDMA_D_WEIGHT_SIZE_1_0_DUAL                                        (0x0)
++#define CDMA_D_WEIGHT_SIZE_1_0_SCR                                           (0)
++#define CDMA_D_WEIGHT_SIZE_1_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_WEIGHT_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_WEIGHT_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_WEIGHT_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT          (_MK_SHIFT_CONST(0))
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT))
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_RANGE                        (12:0)
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_WOFFSET                       (0x0)
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WEIGHT_RAM_TYPE_0
++#define CDMA_D_WEIGHT_RAM_TYPE_0                        (_MK_ADDR_CONST(0x5074))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_SECURE                                    (0x0)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_DUAL                                      (0x0)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_SCR                                         (0)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WORD_COUNT                                (0x1)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT      (_MK_SHIFT_CONST(0))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_RANGE                     (0:0)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_WOFFSET                   (0x0)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_INIT_ENUM                (CVIF)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_CVIF        (_MK_ENUM_CONST(0))
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_MCIF        (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_D_WEIGHT_ADDR_HIGH_0
++#define CDMA_D_WEIGHT_ADDR_HIGH_0                       (_MK_ADDR_CONST(0x5078))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_SECURE                                   (0x0)
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_DUAL                                     (0x0)
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_SCR                                        (0)
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WORD_COUNT                               (0x1)
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_RESET_MASK        (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_READ_MASK         (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT    (_MK_SHIFT_CONST(0))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_RANGE                  (31:0)
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_WOFFSET                 (0x0)
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WEIGHT_ADDR_LOW_0
++#define CDMA_D_WEIGHT_ADDR_LOW_0                        (_MK_ADDR_CONST(0x507c))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_SECURE                                    (0x0)
++#define CDMA_D_WEIGHT_ADDR_LOW_0_DUAL                                      (0x0)
++#define CDMA_D_WEIGHT_ADDR_LOW_0_SCR                                         (0)
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WORD_COUNT                                (0x1)
++#define CDMA_D_WEIGHT_ADDR_LOW_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT      (_MK_SHIFT_CONST(5))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_RANGE                    (31:5)
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_WOFFSET                   (0x0)
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WEIGHT_BYTES_0
++#define CDMA_D_WEIGHT_BYTES_0                           (_MK_ADDR_CONST(0x5080))
++#define CDMA_D_WEIGHT_BYTES_0_SECURE                                       (0x0)
++#define CDMA_D_WEIGHT_BYTES_0_DUAL                                         (0x0)
++#define CDMA_D_WEIGHT_BYTES_0_SCR                                            (0)
++#define CDMA_D_WEIGHT_BYTES_0_WORD_COUNT                                   (0x1)
++#define CDMA_D_WEIGHT_BYTES_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_BYTES_0_RESET_MASK            (_MK_MASK_CONST(0xffffff80))
++#define CDMA_D_WEIGHT_BYTES_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_BYTES_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_BYTES_0_READ_MASK             (_MK_MASK_CONST(0xffffff80))
++#define CDMA_D_WEIGHT_BYTES_0_WRITE_MASK            (_MK_MASK_CONST(0xffffff80))
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT            (_MK_SHIFT_CONST(7))
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD \
++      (_MK_FIELD_CONST(0x1ffffff, \
++      CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT))
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_RANGE                          (31:7)
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_WOFFSET                         (0x0)
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1ffffff))
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WGS_ADDR_HIGH_0
++#define CDMA_D_WGS_ADDR_HIGH_0                          (_MK_ADDR_CONST(0x5084))
++#define CDMA_D_WGS_ADDR_HIGH_0_SECURE                                      (0x0)
++#define CDMA_D_WGS_ADDR_HIGH_0_DUAL                                        (0x0)
++#define CDMA_D_WGS_ADDR_HIGH_0_SCR                                           (0)
++#define CDMA_D_WGS_ADDR_HIGH_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_WGS_ADDR_HIGH_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_HIGH_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WGS_ADDR_HIGH_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_HIGH_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_HIGH_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WGS_ADDR_HIGH_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT          (_MK_SHIFT_CONST(0))
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT))
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_RANGE                        (31:0)
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_WOFFSET                       (0x0)
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WGS_ADDR_LOW_0
++#define CDMA_D_WGS_ADDR_LOW_0                           (_MK_ADDR_CONST(0x5088))
++#define CDMA_D_WGS_ADDR_LOW_0_SECURE                                       (0x0)
++#define CDMA_D_WGS_ADDR_LOW_0_DUAL                                         (0x0)
++#define CDMA_D_WGS_ADDR_LOW_0_SCR                                            (0)
++#define CDMA_D_WGS_ADDR_LOW_0_WORD_COUNT                                   (0x1)
++#define CDMA_D_WGS_ADDR_LOW_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_LOW_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_WGS_ADDR_LOW_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_LOW_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_LOW_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_WGS_ADDR_LOW_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT            (_MK_SHIFT_CONST(5))
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT))
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_RANGE                          (31:5)
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_WOFFSET                         (0x0)
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WMB_ADDR_HIGH_0
++#define CDMA_D_WMB_ADDR_HIGH_0                          (_MK_ADDR_CONST(0x508c))
++#define CDMA_D_WMB_ADDR_HIGH_0_SECURE                                      (0x0)
++#define CDMA_D_WMB_ADDR_HIGH_0_DUAL                                        (0x0)
++#define CDMA_D_WMB_ADDR_HIGH_0_SCR                                           (0)
++#define CDMA_D_WMB_ADDR_HIGH_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_WMB_ADDR_HIGH_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_HIGH_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WMB_ADDR_HIGH_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_HIGH_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_HIGH_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WMB_ADDR_HIGH_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT          (_MK_SHIFT_CONST(0))
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT))
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_RANGE                        (31:0)
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_WOFFSET                       (0x0)
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WMB_ADDR_LOW_0
++#define CDMA_D_WMB_ADDR_LOW_0                           (_MK_ADDR_CONST(0x5090))
++#define CDMA_D_WMB_ADDR_LOW_0_SECURE                                       (0x0)
++#define CDMA_D_WMB_ADDR_LOW_0_DUAL                                         (0x0)
++#define CDMA_D_WMB_ADDR_LOW_0_SCR                                            (0)
++#define CDMA_D_WMB_ADDR_LOW_0_WORD_COUNT                                   (0x1)
++#define CDMA_D_WMB_ADDR_LOW_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_LOW_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_WMB_ADDR_LOW_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_LOW_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_LOW_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_WMB_ADDR_LOW_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT            (_MK_SHIFT_CONST(5))
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT))
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_RANGE                          (31:5)
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_WOFFSET                         (0x0)
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_WMB_BYTES_0
++#define CDMA_D_WMB_BYTES_0                              (_MK_ADDR_CONST(0x5094))
++#define CDMA_D_WMB_BYTES_0_SECURE                                          (0x0)
++#define CDMA_D_WMB_BYTES_0_DUAL                                            (0x0)
++#define CDMA_D_WMB_BYTES_0_SCR                                               (0)
++#define CDMA_D_WMB_BYTES_0_WORD_COUNT                                      (0x1)
++#define CDMA_D_WMB_BYTES_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_BYTES_0_RESET_MASK                (_MK_MASK_CONST(0xfffff80))
++#define CDMA_D_WMB_BYTES_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_BYTES_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_BYTES_0_READ_MASK                 (_MK_MASK_CONST(0xfffff80))
++#define CDMA_D_WMB_BYTES_0_WRITE_MASK                (_MK_MASK_CONST(0xfffff80))
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT                  (_MK_SHIFT_CONST(7))
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_FIELD \
++      (_MK_FIELD_CONST(0x1fffff, CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT))
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_RANGE                                (27:7)
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_WOFFSET                               (0x0)
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_DEFAULT_MASK     (_MK_MASK_CONST(0x1fffff))
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_MEAN_FORMAT_0
++#define CDMA_D_MEAN_FORMAT_0                            (_MK_ADDR_CONST(0x5098))
++#define CDMA_D_MEAN_FORMAT_0_SECURE                                        (0x0)
++#define CDMA_D_MEAN_FORMAT_0_DUAL                                          (0x0)
++#define CDMA_D_MEAN_FORMAT_0_SCR                                             (0)
++#define CDMA_D_MEAN_FORMAT_0_WORD_COUNT                                    (0x1)
++#define CDMA_D_MEAN_FORMAT_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_FORMAT_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
++#define CDMA_D_MEAN_FORMAT_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_FORMAT_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_FORMAT_0_READ_MASK                     (_MK_MASK_CONST(0x1))
++#define CDMA_D_MEAN_FORMAT_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT              (_MK_SHIFT_CONST(0))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_RANGE                             (0:0)
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_WOFFSET                           (0x0)
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_INIT_ENUM                     (DISABLE)
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DISABLE             (_MK_ENUM_CONST(0))
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_ENABLE              (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_D_MEAN_GLOBAL_0_0
++#define CDMA_D_MEAN_GLOBAL_0_0                          (_MK_ADDR_CONST(0x509c))
++#define CDMA_D_MEAN_GLOBAL_0_0_SECURE                                      (0x0)
++#define CDMA_D_MEAN_GLOBAL_0_0_DUAL                                        (0x0)
++#define CDMA_D_MEAN_GLOBAL_0_0_SCR                                           (0)
++#define CDMA_D_MEAN_GLOBAL_0_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_MEAN_GLOBAL_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_MEAN_GLOBAL_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_MEAN_GLOBAL_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT                (_MK_SHIFT_CONST(0))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_RANGE                              (15:0)
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_WOFFSET                             (0x0)
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT               (_MK_SHIFT_CONST(16))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_RANGE                             (31:16)
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_WOFFSET                             (0x0)
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_MEAN_GLOBAL_1_0
++#define CDMA_D_MEAN_GLOBAL_1_0                          (_MK_ADDR_CONST(0x50a0))
++#define CDMA_D_MEAN_GLOBAL_1_0_SECURE                                      (0x0)
++#define CDMA_D_MEAN_GLOBAL_1_0_DUAL                                        (0x0)
++#define CDMA_D_MEAN_GLOBAL_1_0_SCR                                           (0)
++#define CDMA_D_MEAN_GLOBAL_1_0_WORD_COUNT                                  (0x1)
++#define CDMA_D_MEAN_GLOBAL_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_MEAN_GLOBAL_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_MEAN_GLOBAL_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT                (_MK_SHIFT_CONST(0))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_RANGE                              (15:0)
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_WOFFSET                             (0x0)
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT               (_MK_SHIFT_CONST(16))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_RANGE                             (31:16)
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_WOFFSET                             (0x0)
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_CVT_CFG_0
++#define CDMA_D_CVT_CFG_0                                (_MK_ADDR_CONST(0x50a4))
++#define CDMA_D_CVT_CFG_0_SECURE                                            (0x0)
++#define CDMA_D_CVT_CFG_0_DUAL                                              (0x0)
++#define CDMA_D_CVT_CFG_0_SCR                                                 (0)
++#define CDMA_D_CVT_CFG_0_WORD_COUNT                                        (0x1)
++#define CDMA_D_CVT_CFG_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x3f1))
++#define CDMA_D_CVT_CFG_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x3f1))
++#define CDMA_D_CVT_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x3f1))
++#define CDMA_D_CVT_CFG_0_CVT_EN_SHIFT                       (_MK_SHIFT_CONST(0))
++#define CDMA_D_CVT_CFG_0_CVT_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_CVT_CFG_0_CVT_EN_SHIFT))
++#define CDMA_D_CVT_CFG_0_CVT_EN_RANGE                                      (0:0)
++#define CDMA_D_CVT_CFG_0_CVT_EN_WOFFSET                                    (0x0)
++#define CDMA_D_CVT_CFG_0_CVT_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_CVT_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
++#define CDMA_D_CVT_CFG_0_CVT_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_CVT_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_CVT_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_CVT_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define CDMA_D_CVT_CFG_0_CVT_EN_INIT_ENUM                              (DISABLE)
++#define CDMA_D_CVT_CFG_0_CVT_EN_DISABLE                      (_MK_ENUM_CONST(0))
++#define CDMA_D_CVT_CFG_0_CVT_EN_ENABLE                       (_MK_ENUM_CONST(1))
++
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT                 (_MK_SHIFT_CONST(4))
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_FIELD \
++      (_MK_FIELD_CONST(0x3f, CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT))
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_RANGE                                (9:4)
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_WOFFSET                              (0x0)
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_DEFAULT_MASK        (_MK_MASK_CONST(0x3f))
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_CVT_OFFSET_0
++#define CDMA_D_CVT_OFFSET_0                             (_MK_ADDR_CONST(0x50a8))
++#define CDMA_D_CVT_OFFSET_0_SECURE                                         (0x0)
++#define CDMA_D_CVT_OFFSET_0_DUAL                                           (0x0)
++#define CDMA_D_CVT_OFFSET_0_SCR                                              (0)
++#define CDMA_D_CVT_OFFSET_0_WORD_COUNT                                     (0x1)
++#define CDMA_D_CVT_OFFSET_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_OFFSET_0_RESET_MASK                  (_MK_MASK_CONST(0xffff))
++#define CDMA_D_CVT_OFFSET_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_OFFSET_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_OFFSET_0_READ_MASK                   (_MK_MASK_CONST(0xffff))
++#define CDMA_D_CVT_OFFSET_0_WRITE_MASK                  (_MK_MASK_CONST(0xffff))
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT                (_MK_SHIFT_CONST(0))
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT))
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_RANGE                              (15:0)
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_WOFFSET                             (0x0)
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_CVT_SCALE_0
++#define CDMA_D_CVT_SCALE_0                              (_MK_ADDR_CONST(0x50ac))
++#define CDMA_D_CVT_SCALE_0_SECURE                                          (0x0)
++#define CDMA_D_CVT_SCALE_0_DUAL                                            (0x0)
++#define CDMA_D_CVT_SCALE_0_SCR                                               (0)
++#define CDMA_D_CVT_SCALE_0_WORD_COUNT                                      (0x1)
++#define CDMA_D_CVT_SCALE_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_SCALE_0_RESET_MASK                   (_MK_MASK_CONST(0xffff))
++#define CDMA_D_CVT_SCALE_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_SCALE_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_SCALE_0_READ_MASK                    (_MK_MASK_CONST(0xffff))
++#define CDMA_D_CVT_SCALE_0_WRITE_MASK                   (_MK_MASK_CONST(0xffff))
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT                  (_MK_SHIFT_CONST(0))
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT))
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_RANGE                                (15:0)
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_WOFFSET                               (0x0)
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_DEFAULT_MASK       (_MK_MASK_CONST(0xffff))
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_CONV_STRIDE_0
++#define CDMA_D_CONV_STRIDE_0                            (_MK_ADDR_CONST(0x50b0))
++#define CDMA_D_CONV_STRIDE_0_SECURE                                        (0x0)
++#define CDMA_D_CONV_STRIDE_0_DUAL                                          (0x0)
++#define CDMA_D_CONV_STRIDE_0_SCR                                             (0)
++#define CDMA_D_CONV_STRIDE_0_WORD_COUNT                                    (0x1)
++#define CDMA_D_CONV_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_RESET_MASK                (_MK_MASK_CONST(0x70007))
++#define CDMA_D_CONV_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_READ_MASK                 (_MK_MASK_CONST(0x70007))
++#define CDMA_D_CONV_STRIDE_0_WRITE_MASK                (_MK_MASK_CONST(0x70007))
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT            (_MK_SHIFT_CONST(0))
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT))
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_RANGE                           (2:0)
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_WOFFSET                         (0x0)
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_DEFAULT_MASK    (_MK_MASK_CONST(0x7))
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT           (_MK_SHIFT_CONST(16))
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT))
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_RANGE                         (18:16)
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_WOFFSET                         (0x0)
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_DEFAULT_MASK    (_MK_MASK_CONST(0x7))
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_ZERO_PADDING_0
++#define CDMA_D_ZERO_PADDING_0                           (_MK_ADDR_CONST(0x50b4))
++#define CDMA_D_ZERO_PADDING_0_SECURE                                       (0x0)
++#define CDMA_D_ZERO_PADDING_0_DUAL                                         (0x0)
++#define CDMA_D_ZERO_PADDING_0_SCR                                            (0)
++#define CDMA_D_ZERO_PADDING_0_WORD_COUNT                                   (0x1)
++#define CDMA_D_ZERO_PADDING_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_RESET_MASK            (_MK_MASK_CONST(0x3f1f3f1f))
++#define CDMA_D_ZERO_PADDING_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_READ_MASK             (_MK_MASK_CONST(0x3f1f3f1f))
++#define CDMA_D_ZERO_PADDING_0_WRITE_MASK            (_MK_MASK_CONST(0x3f1f3f1f))
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT                (_MK_SHIFT_CONST(0))
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT))
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_RANGE                               (4:0)
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_WOFFSET                             (0x0)
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT_MASK       (_MK_MASK_CONST(0x1f))
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT               (_MK_SHIFT_CONST(8))
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_FIELD \
++      (_MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT))
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_RANGE                             (13:8)
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_WOFFSET                            (0x0)
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_DEFAULT_MASK      (_MK_MASK_CONST(0x3f))
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT                (_MK_SHIFT_CONST(16))
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_FIELD \
++      (_MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT))
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_RANGE                              (20:16)
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_WOFFSET                              (0x0)
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT             (_MK_SHIFT_CONST(24))
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_FIELD \
++      (_MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT))
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_RANGE                           (29:24)
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_WOFFSET                           (0x0)
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_DEFAULT_MASK     (_MK_MASK_CONST(0x3f))
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_ZERO_PADDING_VALUE_0
++#define CDMA_D_ZERO_PADDING_VALUE_0                     (_MK_ADDR_CONST(0x50b8))
++#define CDMA_D_ZERO_PADDING_VALUE_0_SECURE                                 (0x0)
++#define CDMA_D_ZERO_PADDING_VALUE_0_DUAL                                   (0x0)
++#define CDMA_D_ZERO_PADDING_VALUE_0_SCR                                      (0)
++#define CDMA_D_ZERO_PADDING_VALUE_0_WORD_COUNT                             (0x1)
++#define CDMA_D_ZERO_PADDING_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
++#define CDMA_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
++#define CDMA_D_ZERO_PADDING_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT))
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_RANGE                       (15:0)
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_WOFFSET                      (0x0)
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_BANK_0
++#define CDMA_D_BANK_0                                   (_MK_ADDR_CONST(0x50bc))
++#define CDMA_D_BANK_0_SECURE                                               (0x0)
++#define CDMA_D_BANK_0_DUAL                                                 (0x0)
++#define CDMA_D_BANK_0_SCR                                                    (0)
++#define CDMA_D_BANK_0_WORD_COUNT                                           (0x1)
++#define CDMA_D_BANK_0_RESET_VAL                            (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_RESET_MASK                       (_MK_MASK_CONST(0xf000f))
++#define CDMA_D_BANK_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_READ_MASK                        (_MK_MASK_CONST(0xf000f))
++#define CDMA_D_BANK_0_WRITE_MASK                       (_MK_MASK_CONST(0xf000f))
++#define CDMA_D_BANK_0_DATA_BANK_SHIFT                       (_MK_SHIFT_CONST(0))
++#define CDMA_D_BANK_0_DATA_BANK_FIELD \
++      (_MK_FIELD_CONST(0xf, CDMA_D_BANK_0_DATA_BANK_SHIFT))
++#define CDMA_D_BANK_0_DATA_BANK_RANGE                                      (3:0)
++#define CDMA_D_BANK_0_DATA_BANK_WOFFSET                                    (0x0)
++#define CDMA_D_BANK_0_DATA_BANK_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_DATA_BANK_DEFAULT_MASK               (_MK_MASK_CONST(0xf))
++#define CDMA_D_BANK_0_DATA_BANK_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_DATA_BANK_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_DATA_BANK_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_DATA_BANK_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++
++#define CDMA_D_BANK_0_WEIGHT_BANK_SHIFT                    (_MK_SHIFT_CONST(16))
++#define CDMA_D_BANK_0_WEIGHT_BANK_FIELD \
++      (_MK_FIELD_CONST(0xf, CDMA_D_BANK_0_WEIGHT_BANK_SHIFT))
++#define CDMA_D_BANK_0_WEIGHT_BANK_RANGE                                  (19:16)
++#define CDMA_D_BANK_0_WEIGHT_BANK_WOFFSET                                  (0x0)
++#define CDMA_D_BANK_0_WEIGHT_BANK_DEFAULT                  (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_WEIGHT_BANK_DEFAULT_MASK             (_MK_MASK_CONST(0xf))
++#define CDMA_D_BANK_0_WEIGHT_BANK_SW_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_WEIGHT_BANK_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_WEIGHT_BANK_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
++#define CDMA_D_BANK_0_WEIGHT_BANK_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_NAN_FLUSH_TO_ZERO_0
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0                      (_MK_ADDR_CONST(0x50c0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SECURE                                  (0x0)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_DUAL                                    (0x0)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SCR                                       (0)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_WORD_COUNT                              (0x1)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_RESET_MASK              (_MK_MASK_CONST(0x1))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_READ_MASK               (_MK_MASK_CONST(0x1))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_WRITE_MASK              (_MK_MASK_CONST(0x1))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT        (_MK_SHIFT_CONST(0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_RANGE                       (0:0)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_WOFFSET                     (0x0)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_INIT_ENUM               (DISABLE)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE       (_MK_ENUM_CONST(0))
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE        (_MK_ENUM_CONST(1))
++
++
++// Register CDMA_D_NAN_INPUT_DATA_NUM_0
++#define CDMA_D_NAN_INPUT_DATA_NUM_0                     (_MK_ADDR_CONST(0x50c4))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_SECURE                                 (0x0)
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_DUAL                                   (0x0)
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_SCR                                      (0)
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_WORD_COUNT                             (0x1)
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT      (_MK_SHIFT_CONST(0))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_RANGE                    (31:0)
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_WOFFSET                   (0x0)
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_NAN_INPUT_WEIGHT_NUM_0
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0                   (_MK_ADDR_CONST(0x50c8))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SECURE                               (0x0)
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_DUAL                                 (0x0)
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SCR                                    (0)
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_WORD_COUNT                           (0x1)
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_RANGE                (31:0)
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_WOFFSET               (0x0)
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_INF_INPUT_DATA_NUM_0
++#define CDMA_D_INF_INPUT_DATA_NUM_0                     (_MK_ADDR_CONST(0x50cc))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_SECURE                                 (0x0)
++#define CDMA_D_INF_INPUT_DATA_NUM_0_DUAL                                   (0x0)
++#define CDMA_D_INF_INPUT_DATA_NUM_0_SCR                                      (0)
++#define CDMA_D_INF_INPUT_DATA_NUM_0_WORD_COUNT                             (0x1)
++#define CDMA_D_INF_INPUT_DATA_NUM_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT      (_MK_SHIFT_CONST(0))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_RANGE                    (31:0)
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_WOFFSET                   (0x0)
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_INF_INPUT_WEIGHT_NUM_0
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0                   (_MK_ADDR_CONST(0x50d0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SECURE                               (0x0)
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_DUAL                                 (0x0)
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SCR                                    (0)
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_WORD_COUNT                           (0x1)
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_RANGE                (31:0)
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_WOFFSET               (0x0)
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_PERF_ENABLE_0
++#define CDMA_D_PERF_ENABLE_0                            (_MK_ADDR_CONST(0x50d4))
++#define CDMA_D_PERF_ENABLE_0_SECURE                                        (0x0)
++#define CDMA_D_PERF_ENABLE_0_DUAL                                          (0x0)
++#define CDMA_D_PERF_ENABLE_0_SCR                                             (0)
++#define CDMA_D_PERF_ENABLE_0_WORD_COUNT                                    (0x1)
++#define CDMA_D_PERF_ENABLE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_ENABLE_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
++#define CDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_ENABLE_0_READ_MASK                     (_MK_MASK_CONST(0x1))
++#define CDMA_D_PERF_ENABLE_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT                   (_MK_SHIFT_CONST(0))
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT))
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_RANGE                                  (0:0)
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_WOFFSET                                (0x0)
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_PERF_DAT_READ_STALL_0
++#define CDMA_D_PERF_DAT_READ_STALL_0                    (_MK_ADDR_CONST(0x50d8))
++#define CDMA_D_PERF_DAT_READ_STALL_0_SECURE                                (0x0)
++#define CDMA_D_PERF_DAT_READ_STALL_0_DUAL                                  (0x0)
++#define CDMA_D_PERF_DAT_READ_STALL_0_SCR                                     (0)
++#define CDMA_D_PERF_DAT_READ_STALL_0_WORD_COUNT                            (0x1)
++#define CDMA_D_PERF_DAT_READ_STALL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_STALL_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_DAT_READ_STALL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_STALL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_STALL_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_DAT_READ_STALL_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT     (_MK_SHIFT_CONST(0))
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT))
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_RANGE                   (31:0)
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_WOFFSET                  (0x0)
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_PERF_WT_READ_STALL_0
++#define CDMA_D_PERF_WT_READ_STALL_0                     (_MK_ADDR_CONST(0x50dc))
++#define CDMA_D_PERF_WT_READ_STALL_0_SECURE                                 (0x0)
++#define CDMA_D_PERF_WT_READ_STALL_0_DUAL                                   (0x0)
++#define CDMA_D_PERF_WT_READ_STALL_0_SCR                                      (0)
++#define CDMA_D_PERF_WT_READ_STALL_0_WORD_COUNT                             (0x1)
++#define CDMA_D_PERF_WT_READ_STALL_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_STALL_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_WT_READ_STALL_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_STALL_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_STALL_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_WT_READ_STALL_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT       (_MK_SHIFT_CONST(0))
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT))
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_RANGE                     (31:0)
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_WOFFSET                    (0x0)
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_PERF_DAT_READ_LATENCY_0
++#define CDMA_D_PERF_DAT_READ_LATENCY_0                  (_MK_ADDR_CONST(0x50e0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_SECURE                              (0x0)
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DUAL                                (0x0)
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_SCR                                   (0)
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_WORD_COUNT                          (0x1)
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_WRITE_MASK          (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_RANGE               (31:0)
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_WOFFSET              (0x0)
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_PERF_WT_READ_LATENCY_0
++#define CDMA_D_PERF_WT_READ_LATENCY_0                   (_MK_ADDR_CONST(0x50e4))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_SECURE                               (0x0)
++#define CDMA_D_PERF_WT_READ_LATENCY_0_DUAL                                 (0x0)
++#define CDMA_D_PERF_WT_READ_LATENCY_0_SCR                                    (0)
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WORD_COUNT                           (0x1)
++#define CDMA_D_PERF_WT_READ_LATENCY_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_RANGE                 (31:0)
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_WOFFSET                (0x0)
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDMA_D_CYA_0
++#define CDMA_D_CYA_0                                    (_MK_ADDR_CONST(0x50e8))
++#define CDMA_D_CYA_0_SECURE                                                (0x0)
++#define CDMA_D_CYA_0_DUAL                                                  (0x0)
++#define CDMA_D_CYA_0_SCR                                                     (0)
++#define CDMA_D_CYA_0_WORD_COUNT                                            (0x1)
++#define CDMA_D_CYA_0_RESET_VAL                             (_MK_MASK_CONST(0x0))
++#define CDMA_D_CYA_0_RESET_MASK                     (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_CYA_0_SW_DEFAULT_VAL                        (_MK_MASK_CONST(0x0))
++#define CDMA_D_CYA_0_SW_DEFAULT_MASK                       (_MK_MASK_CONST(0x0))
++#define CDMA_D_CYA_0_READ_MASK                      (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_CYA_0_WRITE_MASK                     (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_CYA_0_CYA_SHIFT                              (_MK_SHIFT_CONST(0))
++#define CDMA_D_CYA_0_CYA_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, CDMA_D_CYA_0_CYA_SHIFT))
++#define CDMA_D_CYA_0_CYA_RANGE                                            (31:0)
++#define CDMA_D_CYA_0_CYA_WOFFSET                                           (0x0)
++#define CDMA_D_CYA_0_CYA_DEFAULT                           (_MK_MASK_CONST(0x0))
++#define CDMA_D_CYA_0_CYA_DEFAULT_MASK               (_MK_MASK_CONST(0xffffffff))
++#define CDMA_D_CYA_0_CYA_SW_DEFAULT                        (_MK_MASK_CONST(0x0))
++#define CDMA_D_CYA_0_CYA_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define CDMA_D_CYA_0_CYA_PARITY_PROTECTION                 (_MK_MASK_CONST(0x0))
++#define CDMA_D_CYA_0_CYA_PLATFORM_DEPENDENT                (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_S_STATUS_0
++#define CSC_S_STATUS_0                                  (_MK_ADDR_CONST(0x6000))
++#define CSC_S_STATUS_0_SECURE                                              (0x0)
++#define CSC_S_STATUS_0_DUAL                                                (0x0)
++#define CSC_S_STATUS_0_SCR                                                   (0)
++#define CSC_S_STATUS_0_WORD_COUNT                                          (0x1)
++#define CSC_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
++#define CSC_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
++#define CSC_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
++#define CSC_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_0_SHIFT))
++#define CSC_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
++#define CSC_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
++#define CSC_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define CSC_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define CSC_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
++#define CSC_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
++#define CSC_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
++#define CSC_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
++
++#define CSC_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
++#define CSC_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_1_SHIFT))
++#define CSC_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
++#define CSC_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
++#define CSC_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define CSC_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define CSC_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define CSC_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
++#define CSC_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
++#define CSC_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
++#define CSC_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
++
++
++// Register CSC_S_POINTER_0
++#define CSC_S_POINTER_0                                 (_MK_ADDR_CONST(0x6004))
++#define CSC_S_POINTER_0_SECURE                                             (0x0)
++#define CSC_S_POINTER_0_DUAL                                               (0x0)
++#define CSC_S_POINTER_0_SCR                                                  (0)
++#define CSC_S_POINTER_0_WORD_COUNT                                         (0x1)
++#define CSC_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
++#define CSC_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
++#define CSC_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
++#define CSC_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
++#define CSC_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_S_POINTER_0_PRODUCER_SHIFT))
++#define CSC_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
++#define CSC_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
++#define CSC_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define CSC_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CSC_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
++#define CSC_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define CSC_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++#define CSC_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
++#define CSC_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_S_POINTER_0_CONSUMER_SHIFT))
++#define CSC_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
++#define CSC_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
++#define CSC_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define CSC_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CSC_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CSC_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
++#define CSC_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define CSC_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++
++// Register CSC_D_OP_ENABLE_0
++#define CSC_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0x6008))
++#define CSC_D_OP_ENABLE_0_SECURE                                           (0x0)
++#define CSC_D_OP_ENABLE_0_DUAL                                             (0x0)
++#define CSC_D_OP_ENABLE_0_SCR                                                (0)
++#define CSC_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
++#define CSC_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define CSC_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
++#define CSC_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define CSC_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define CSC_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
++#define CSC_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
++#define CSC_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
++#define CSC_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define CSC_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
++#define CSC_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
++#define CSC_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define CSC_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
++#define CSC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CSC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CSC_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define CSC_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define CSC_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
++#define CSC_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
++#define CSC_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
++
++
++// Register CSC_D_MISC_CFG_0
++#define CSC_D_MISC_CFG_0                                (_MK_ADDR_CONST(0x600c))
++#define CSC_D_MISC_CFG_0_SECURE                                            (0x0)
++#define CSC_D_MISC_CFG_0_DUAL                                              (0x0)
++#define CSC_D_MISC_CFG_0_SCR                                                 (0)
++#define CSC_D_MISC_CFG_0_WORD_COUNT                                        (0x1)
++#define CSC_D_MISC_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x1100))
++#define CSC_D_MISC_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x11113301))
++#define CSC_D_MISC_CFG_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x11113301))
++#define CSC_D_MISC_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x11113301))
++#define CSC_D_MISC_CFG_0_CONV_MODE_SHIFT                    (_MK_SHIFT_CONST(0))
++#define CSC_D_MISC_CFG_0_CONV_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_CONV_MODE_SHIFT))
++#define CSC_D_MISC_CFG_0_CONV_MODE_RANGE                                   (0:0)
++#define CSC_D_MISC_CFG_0_CONV_MODE_WOFFSET                                 (0x0)
++#define CSC_D_MISC_CFG_0_CONV_MODE_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                            (DIRECT)
++#define CSC_D_MISC_CFG_0_CONV_MODE_DIRECT                    (_MK_ENUM_CONST(0))
++#define CSC_D_MISC_CFG_0_CONV_MODE_WINOGRAD                  (_MK_ENUM_CONST(1))
++
++#define CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT                 (_MK_SHIFT_CONST(8))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_RANGE                                (9:8)
++#define CSC_D_MISC_CFG_0_IN_PRECISION_WOFFSET                              (0x0)
++#define CSC_D_MISC_CFG_0_IN_PRECISION_DEFAULT              (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_INIT_ENUM                          (INT16)
++#define CSC_D_MISC_CFG_0_IN_PRECISION_INT8                   (_MK_ENUM_CONST(0))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_INT16                  (_MK_ENUM_CONST(1))
++#define CSC_D_MISC_CFG_0_IN_PRECISION_FP16                   (_MK_ENUM_CONST(2))
++
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT              (_MK_SHIFT_CONST(12))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_RANGE                            (13:12)
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                            (0x0)
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT            (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK       (_MK_MASK_CONST(0x3))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                        (INT16)
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT8                 (_MK_ENUM_CONST(0))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT16                (_MK_ENUM_CONST(1))
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_FP16                 (_MK_ENUM_CONST(2))
++
++#define CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT                  (_MK_SHIFT_CONST(16))
++#define CSC_D_MISC_CFG_0_DATA_REUSE_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT))
++#define CSC_D_MISC_CFG_0_DATA_REUSE_RANGE                                (16:16)
++#define CSC_D_MISC_CFG_0_DATA_REUSE_WOFFSET                                (0x0)
++#define CSC_D_MISC_CFG_0_DATA_REUSE_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_DATA_REUSE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_DATA_REUSE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_DATA_REUSE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_DATA_REUSE_INIT_ENUM                          (DISABLE)
++#define CSC_D_MISC_CFG_0_DATA_REUSE_DISABLE                  (_MK_ENUM_CONST(0))
++#define CSC_D_MISC_CFG_0_DATA_REUSE_ENABLE                   (_MK_ENUM_CONST(1))
++
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT                (_MK_SHIFT_CONST(20))
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT))
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_RANGE                              (20:20)
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_WOFFSET                              (0x0)
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_INIT_ENUM                        (DISABLE)
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE                (_MK_ENUM_CONST(0))
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE                 (_MK_ENUM_CONST(1))
++
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT               (_MK_SHIFT_CONST(24))
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT))
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_RANGE                             (24:24)
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_WOFFSET                             (0x0)
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_INIT_ENUM                       (DISABLE)
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE               (_MK_ENUM_CONST(0))
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE                (_MK_ENUM_CONST(1))
++
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT             (_MK_SHIFT_CONST(28))
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT))
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_RANGE                           (28:28)
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_WOFFSET                           (0x0)
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_INIT_ENUM                     (DISABLE)
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE             (_MK_ENUM_CONST(0))
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE              (_MK_ENUM_CONST(1))
++
++
++// Register CSC_D_DATAIN_FORMAT_0
++#define CSC_D_DATAIN_FORMAT_0                           (_MK_ADDR_CONST(0x6010))
++#define CSC_D_DATAIN_FORMAT_0_SECURE                                       (0x0)
++#define CSC_D_DATAIN_FORMAT_0_DUAL                                         (0x0)
++#define CSC_D_DATAIN_FORMAT_0_SCR                                            (0)
++#define CSC_D_DATAIN_FORMAT_0_WORD_COUNT                                   (0x1)
++#define CSC_D_DATAIN_FORMAT_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_FORMAT_0_RESET_MASK                   (_MK_MASK_CONST(0x1))
++#define CSC_D_DATAIN_FORMAT_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_FORMAT_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_FORMAT_0_READ_MASK                    (_MK_MASK_CONST(0x1))
++#define CSC_D_DATAIN_FORMAT_0_WRITE_MASK                   (_MK_MASK_CONST(0x1))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT           (_MK_SHIFT_CONST(0))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_RANGE                          (0:0)
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_WOFFSET                        (0x0)
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_INIT_ENUM                  (FEATURE)
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE          (_MK_ENUM_CONST(0))
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL            (_MK_ENUM_CONST(1))
++
++
++// Register CSC_D_DATAIN_SIZE_EXT_0_0
++#define CSC_D_DATAIN_SIZE_EXT_0_0                       (_MK_ADDR_CONST(0x6014))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_SECURE                                   (0x0)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DUAL                                     (0x0)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_SCR                                        (0)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_WORD_COUNT                               (0x1)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_RESET_MASK        (_MK_MASK_CONST(0x1fff1fff))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_READ_MASK         (_MK_MASK_CONST(0x1fff1fff))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff1fff))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT    (_MK_SHIFT_CONST(0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_RANGE                  (12:0)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_WOFFSET                 (0x0)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT \
++      (_MK_SHIFT_CONST(16))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_RANGE                (28:16)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_WOFFSET                (0x0)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_DATAIN_SIZE_EXT_1_0
++#define CSC_D_DATAIN_SIZE_EXT_1_0                       (_MK_ADDR_CONST(0x6018))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_SECURE                                   (0x0)
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DUAL                                     (0x0)
++#define CSC_D_DATAIN_SIZE_EXT_1_0_SCR                                        (0)
++#define CSC_D_DATAIN_SIZE_EXT_1_0_WORD_COUNT                               (0x1)
++#define CSC_D_DATAIN_SIZE_EXT_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_RESET_MASK            (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_READ_MASK             (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_WRITE_MASK            (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_RANGE                (12:0)
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_WOFFSET               (0x0)
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_BATCH_NUMBER_0
++#define CSC_D_BATCH_NUMBER_0                            (_MK_ADDR_CONST(0x601c))
++#define CSC_D_BATCH_NUMBER_0_SECURE                                        (0x0)
++#define CSC_D_BATCH_NUMBER_0_DUAL                                          (0x0)
++#define CSC_D_BATCH_NUMBER_0_SCR                                             (0)
++#define CSC_D_BATCH_NUMBER_0_WORD_COUNT                                    (0x1)
++#define CSC_D_BATCH_NUMBER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CSC_D_BATCH_NUMBER_0_RESET_MASK                   (_MK_MASK_CONST(0x1f))
++#define CSC_D_BATCH_NUMBER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CSC_D_BATCH_NUMBER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CSC_D_BATCH_NUMBER_0_READ_MASK                    (_MK_MASK_CONST(0x1f))
++#define CSC_D_BATCH_NUMBER_0_WRITE_MASK                   (_MK_MASK_CONST(0x1f))
++#define CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT                  (_MK_SHIFT_CONST(0))
++#define CSC_D_BATCH_NUMBER_0_BATCHES_FIELD \
++      (_MK_FIELD_CONST(0x1f, CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT))
++#define CSC_D_BATCH_NUMBER_0_BATCHES_RANGE                                 (4:0)
++#define CSC_D_BATCH_NUMBER_0_BATCHES_WOFFSET                               (0x0)
++#define CSC_D_BATCH_NUMBER_0_BATCHES_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CSC_D_BATCH_NUMBER_0_BATCHES_DEFAULT_MASK         (_MK_MASK_CONST(0x1f))
++#define CSC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CSC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CSC_D_BATCH_NUMBER_0_BATCHES_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define CSC_D_BATCH_NUMBER_0_BATCHES_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_POST_Y_EXTENSION_0
++#define CSC_D_POST_Y_EXTENSION_0                        (_MK_ADDR_CONST(0x6020))
++#define CSC_D_POST_Y_EXTENSION_0_SECURE                                    (0x0)
++#define CSC_D_POST_Y_EXTENSION_0_DUAL                                      (0x0)
++#define CSC_D_POST_Y_EXTENSION_0_SCR                                         (0)
++#define CSC_D_POST_Y_EXTENSION_0_WORD_COUNT                                (0x1)
++#define CSC_D_POST_Y_EXTENSION_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CSC_D_POST_Y_EXTENSION_0_RESET_MASK                (_MK_MASK_CONST(0x3))
++#define CSC_D_POST_Y_EXTENSION_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CSC_D_POST_Y_EXTENSION_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CSC_D_POST_Y_EXTENSION_0_READ_MASK                 (_MK_MASK_CONST(0x3))
++#define CSC_D_POST_Y_EXTENSION_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT          (_MK_SHIFT_CONST(0))
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_FIELD \
++      (_MK_FIELD_CONST(0x3, CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT))
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_RANGE                         (1:0)
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_WOFFSET                       (0x0)
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_ENTRY_PER_SLICE_0
++#define CSC_D_ENTRY_PER_SLICE_0                         (_MK_ADDR_CONST(0x6024))
++#define CSC_D_ENTRY_PER_SLICE_0_SECURE                                     (0x0)
++#define CSC_D_ENTRY_PER_SLICE_0_DUAL                                       (0x0)
++#define CSC_D_ENTRY_PER_SLICE_0_SCR                                          (0)
++#define CSC_D_ENTRY_PER_SLICE_0_WORD_COUNT                                 (0x1)
++#define CSC_D_ENTRY_PER_SLICE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CSC_D_ENTRY_PER_SLICE_0_RESET_MASK               (_MK_MASK_CONST(0xfff))
++#define CSC_D_ENTRY_PER_SLICE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CSC_D_ENTRY_PER_SLICE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CSC_D_ENTRY_PER_SLICE_0_READ_MASK                (_MK_MASK_CONST(0xfff))
++#define CSC_D_ENTRY_PER_SLICE_0_WRITE_MASK               (_MK_MASK_CONST(0xfff))
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT               (_MK_SHIFT_CONST(0))
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD \
++      (_MK_FIELD_CONST(0xfff, CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT))
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_RANGE                             (11:0)
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_WOFFSET                            (0x0)
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT_MASK     (_MK_MASK_CONST(0xfff))
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_WEIGHT_FORMAT_0
++#define CSC_D_WEIGHT_FORMAT_0                           (_MK_ADDR_CONST(0x6028))
++#define CSC_D_WEIGHT_FORMAT_0_SECURE                                       (0x0)
++#define CSC_D_WEIGHT_FORMAT_0_DUAL                                         (0x0)
++#define CSC_D_WEIGHT_FORMAT_0_SCR                                            (0)
++#define CSC_D_WEIGHT_FORMAT_0_WORD_COUNT                                   (0x1)
++#define CSC_D_WEIGHT_FORMAT_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_FORMAT_0_RESET_MASK                   (_MK_MASK_CONST(0x1))
++#define CSC_D_WEIGHT_FORMAT_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_FORMAT_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_FORMAT_0_READ_MASK                    (_MK_MASK_CONST(0x1))
++#define CSC_D_WEIGHT_FORMAT_0_WRITE_MASK                   (_MK_MASK_CONST(0x1))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT           (_MK_SHIFT_CONST(0))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD \
++      (_MK_FIELD_CONST(0x1, CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_RANGE                          (0:0)
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_WOFFSET                        (0x0)
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_INIT_ENUM             (UNCOMPRESSED)
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED     (_MK_ENUM_CONST(0))
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED       (_MK_ENUM_CONST(1))
++
++
++// Register CSC_D_WEIGHT_SIZE_EXT_0_0
++#define CSC_D_WEIGHT_SIZE_EXT_0_0                       (_MK_ADDR_CONST(0x602c))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_SECURE                                   (0x0)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_DUAL                                     (0x0)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_SCR                                        (0)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WORD_COUNT                               (0x1)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_RESET_MASK          (_MK_MASK_CONST(0x1f001f))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_READ_MASK           (_MK_MASK_CONST(0x1f001f))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WRITE_MASK          (_MK_MASK_CONST(0x1f001f))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT    (_MK_SHIFT_CONST(0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_RANGE                   (4:0)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_WOFFSET                 (0x0)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT \
++      (_MK_SHIFT_CONST(16))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_RANGE                (20:16)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_WOFFSET                (0x0)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_WEIGHT_SIZE_EXT_1_0
++#define CSC_D_WEIGHT_SIZE_EXT_1_0                       (_MK_ADDR_CONST(0x6030))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_SECURE                                   (0x0)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_DUAL                                     (0x0)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_SCR                                        (0)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WORD_COUNT                               (0x1)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_RESET_MASK        (_MK_MASK_CONST(0x1fff1fff))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_READ_MASK         (_MK_MASK_CONST(0x1fff1fff))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff1fff))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_RANGE                (12:0)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_WOFFSET               (0x0)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT      (_MK_SHIFT_CONST(16))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_RANGE                    (28:16)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_WOFFSET                    (0x0)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_WEIGHT_BYTES_0
++#define CSC_D_WEIGHT_BYTES_0                            (_MK_ADDR_CONST(0x6034))
++#define CSC_D_WEIGHT_BYTES_0_SECURE                                        (0x0)
++#define CSC_D_WEIGHT_BYTES_0_DUAL                                          (0x0)
++#define CSC_D_WEIGHT_BYTES_0_SCR                                             (0)
++#define CSC_D_WEIGHT_BYTES_0_WORD_COUNT                                    (0x1)
++#define CSC_D_WEIGHT_BYTES_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_BYTES_0_RESET_MASK             (_MK_MASK_CONST(0xffffff80))
++#define CSC_D_WEIGHT_BYTES_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_BYTES_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_BYTES_0_READ_MASK              (_MK_MASK_CONST(0xffffff80))
++#define CSC_D_WEIGHT_BYTES_0_WRITE_MASK             (_MK_MASK_CONST(0xffffff80))
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT             (_MK_SHIFT_CONST(7))
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD \
++      (_MK_FIELD_CONST(0x1ffffff, CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT))
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_RANGE                           (31:7)
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_WOFFSET                          (0x0)
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1ffffff))
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_WMB_BYTES_0
++#define CSC_D_WMB_BYTES_0                               (_MK_ADDR_CONST(0x6038))
++#define CSC_D_WMB_BYTES_0_SECURE                                           (0x0)
++#define CSC_D_WMB_BYTES_0_DUAL                                             (0x0)
++#define CSC_D_WMB_BYTES_0_SCR                                                (0)
++#define CSC_D_WMB_BYTES_0_WORD_COUNT                                       (0x1)
++#define CSC_D_WMB_BYTES_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define CSC_D_WMB_BYTES_0_RESET_MASK                 (_MK_MASK_CONST(0xfffff80))
++#define CSC_D_WMB_BYTES_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define CSC_D_WMB_BYTES_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define CSC_D_WMB_BYTES_0_READ_MASK                  (_MK_MASK_CONST(0xfffff80))
++#define CSC_D_WMB_BYTES_0_WRITE_MASK                 (_MK_MASK_CONST(0xfffff80))
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT                   (_MK_SHIFT_CONST(7))
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_FIELD \
++      (_MK_FIELD_CONST(0x1fffff, CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT))
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_RANGE                                 (27:7)
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_WOFFSET                                (0x0)
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_DEFAULT_MASK      (_MK_MASK_CONST(0x1fffff))
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_DATAOUT_SIZE_0_0
++#define CSC_D_DATAOUT_SIZE_0_0                          (_MK_ADDR_CONST(0x603c))
++#define CSC_D_DATAOUT_SIZE_0_0_SECURE                                      (0x0)
++#define CSC_D_DATAOUT_SIZE_0_0_DUAL                                        (0x0)
++#define CSC_D_DATAOUT_SIZE_0_0_SCR                                           (0)
++#define CSC_D_DATAOUT_SIZE_0_0_WORD_COUNT                                  (0x1)
++#define CSC_D_DATAOUT_SIZE_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_RESET_MASK           (_MK_MASK_CONST(0x1fff1fff))
++#define CSC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_READ_MASK            (_MK_MASK_CONST(0x1fff1fff))
++#define CSC_D_DATAOUT_SIZE_0_0_WRITE_MASK           (_MK_MASK_CONST(0x1fff1fff))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT          (_MK_SHIFT_CONST(0))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_RANGE                        (12:0)
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_WOFFSET                       (0x0)
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT        (_MK_SHIFT_CONST(16))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_RANGE                      (28:16)
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_WOFFSET                      (0x0)
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_DATAOUT_SIZE_1_0
++#define CSC_D_DATAOUT_SIZE_1_0                          (_MK_ADDR_CONST(0x6040))
++#define CSC_D_DATAOUT_SIZE_1_0_SECURE                                      (0x0)
++#define CSC_D_DATAOUT_SIZE_1_0_DUAL                                        (0x0)
++#define CSC_D_DATAOUT_SIZE_1_0_SCR                                           (0)
++#define CSC_D_DATAOUT_SIZE_1_0_WORD_COUNT                                  (0x1)
++#define CSC_D_DATAOUT_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAOUT_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT))
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_RANGE                      (12:0)
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_WOFFSET                     (0x0)
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_ATOMICS_0
++#define CSC_D_ATOMICS_0                                 (_MK_ADDR_CONST(0x6044))
++#define CSC_D_ATOMICS_0_SECURE                                             (0x0)
++#define CSC_D_ATOMICS_0_DUAL                                               (0x0)
++#define CSC_D_ATOMICS_0_SCR                                                  (0)
++#define CSC_D_ATOMICS_0_WORD_COUNT                                         (0x1)
++#define CSC_D_ATOMICS_0_RESET_VAL                          (_MK_MASK_CONST(0x1))
++#define CSC_D_ATOMICS_0_RESET_MASK                    (_MK_MASK_CONST(0x1fffff))
++#define CSC_D_ATOMICS_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define CSC_D_ATOMICS_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CSC_D_ATOMICS_0_READ_MASK                     (_MK_MASK_CONST(0x1fffff))
++#define CSC_D_ATOMICS_0_WRITE_MASK                    (_MK_MASK_CONST(0x1fffff))
++#define CSC_D_ATOMICS_0_ATOMICS_SHIFT                       (_MK_SHIFT_CONST(0))
++#define CSC_D_ATOMICS_0_ATOMICS_FIELD \
++      (_MK_FIELD_CONST(0x1fffff, CSC_D_ATOMICS_0_ATOMICS_SHIFT))
++#define CSC_D_ATOMICS_0_ATOMICS_RANGE                                     (20:0)
++#define CSC_D_ATOMICS_0_ATOMICS_WOFFSET                                    (0x0)
++#define CSC_D_ATOMICS_0_ATOMICS_DEFAULT                    (_MK_MASK_CONST(0x1))
++#define CSC_D_ATOMICS_0_ATOMICS_DEFAULT_MASK          (_MK_MASK_CONST(0x1fffff))
++#define CSC_D_ATOMICS_0_ATOMICS_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CSC_D_ATOMICS_0_ATOMICS_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CSC_D_ATOMICS_0_ATOMICS_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define CSC_D_ATOMICS_0_ATOMICS_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_RELEASE_0
++#define CSC_D_RELEASE_0                                 (_MK_ADDR_CONST(0x6048))
++#define CSC_D_RELEASE_0_SECURE                                             (0x0)
++#define CSC_D_RELEASE_0_DUAL                                               (0x0)
++#define CSC_D_RELEASE_0_SCR                                                  (0)
++#define CSC_D_RELEASE_0_WORD_COUNT                                         (0x1)
++#define CSC_D_RELEASE_0_RESET_VAL                          (_MK_MASK_CONST(0x1))
++#define CSC_D_RELEASE_0_RESET_MASK                       (_MK_MASK_CONST(0xfff))
++#define CSC_D_RELEASE_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define CSC_D_RELEASE_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CSC_D_RELEASE_0_READ_MASK                        (_MK_MASK_CONST(0xfff))
++#define CSC_D_RELEASE_0_WRITE_MASK                       (_MK_MASK_CONST(0xfff))
++#define CSC_D_RELEASE_0_RLS_SLICES_SHIFT                    (_MK_SHIFT_CONST(0))
++#define CSC_D_RELEASE_0_RLS_SLICES_FIELD \
++      (_MK_FIELD_CONST(0xfff, CSC_D_RELEASE_0_RLS_SLICES_SHIFT))
++#define CSC_D_RELEASE_0_RLS_SLICES_RANGE                                  (11:0)
++#define CSC_D_RELEASE_0_RLS_SLICES_WOFFSET                                 (0x0)
++#define CSC_D_RELEASE_0_RLS_SLICES_DEFAULT                 (_MK_MASK_CONST(0x1))
++#define CSC_D_RELEASE_0_RLS_SLICES_DEFAULT_MASK          (_MK_MASK_CONST(0xfff))
++#define CSC_D_RELEASE_0_RLS_SLICES_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CSC_D_RELEASE_0_RLS_SLICES_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CSC_D_RELEASE_0_RLS_SLICES_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CSC_D_RELEASE_0_RLS_SLICES_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_CONV_STRIDE_EXT_0
++#define CSC_D_CONV_STRIDE_EXT_0                         (_MK_ADDR_CONST(0x604c))
++#define CSC_D_CONV_STRIDE_EXT_0_SECURE                                     (0x0)
++#define CSC_D_CONV_STRIDE_EXT_0_DUAL                                       (0x0)
++#define CSC_D_CONV_STRIDE_EXT_0_SCR                                          (0)
++#define CSC_D_CONV_STRIDE_EXT_0_WORD_COUNT                                 (0x1)
++#define CSC_D_CONV_STRIDE_EXT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_RESET_MASK             (_MK_MASK_CONST(0x70007))
++#define CSC_D_CONV_STRIDE_EXT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_READ_MASK              (_MK_MASK_CONST(0x70007))
++#define CSC_D_CONV_STRIDE_EXT_0_WRITE_MASK             (_MK_MASK_CONST(0x70007))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT     (_MK_SHIFT_CONST(0))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_FIELD \
++      (_MK_FIELD_CONST(0x7, \
++      CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_RANGE                    (2:0)
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_WOFFSET                  (0x0)
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT    (_MK_SHIFT_CONST(16))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_FIELD \
++      (_MK_FIELD_CONST(0x7, \
++      CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_RANGE                  (18:16)
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_WOFFSET                  (0x0)
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_DILATION_EXT_0
++#define CSC_D_DILATION_EXT_0                            (_MK_ADDR_CONST(0x6050))
++#define CSC_D_DILATION_EXT_0_SECURE                                        (0x0)
++#define CSC_D_DILATION_EXT_0_DUAL                                          (0x0)
++#define CSC_D_DILATION_EXT_0_SCR                                             (0)
++#define CSC_D_DILATION_EXT_0_WORD_COUNT                                    (0x1)
++#define CSC_D_DILATION_EXT_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_RESET_MASK               (_MK_MASK_CONST(0x1f001f))
++#define CSC_D_DILATION_EXT_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_READ_MASK                (_MK_MASK_CONST(0x1f001f))
++#define CSC_D_DILATION_EXT_0_WRITE_MASK               (_MK_MASK_CONST(0x1f001f))
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT           (_MK_SHIFT_CONST(0))
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT))
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_RANGE                          (4:0)
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_WOFFSET                        (0x0)
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT          (_MK_SHIFT_CONST(16))
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_FIELD \
++      (_MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT))
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_RANGE                        (20:16)
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_WOFFSET                        (0x0)
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_ZERO_PADDING_0
++#define CSC_D_ZERO_PADDING_0                            (_MK_ADDR_CONST(0x6054))
++#define CSC_D_ZERO_PADDING_0_SECURE                                        (0x0)
++#define CSC_D_ZERO_PADDING_0_DUAL                                          (0x0)
++#define CSC_D_ZERO_PADDING_0_SCR                                             (0)
++#define CSC_D_ZERO_PADDING_0_WORD_COUNT                                    (0x1)
++#define CSC_D_ZERO_PADDING_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_RESET_MASK               (_MK_MASK_CONST(0x1f001f))
++#define CSC_D_ZERO_PADDING_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_READ_MASK                (_MK_MASK_CONST(0x1f001f))
++#define CSC_D_ZERO_PADDING_0_WRITE_MASK               (_MK_MASK_CONST(0x1f001f))
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT                 (_MK_SHIFT_CONST(0))
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT))
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_RANGE                                (4:0)
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_WOFFSET                              (0x0)
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT                 (_MK_SHIFT_CONST(16))
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_FIELD \
++      (_MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT))
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_RANGE                               (20:16)
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_WOFFSET                               (0x0)
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_DEFAULT_MASK         (_MK_MASK_CONST(0x1f))
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_ZERO_PADDING_VALUE_0
++#define CSC_D_ZERO_PADDING_VALUE_0                      (_MK_ADDR_CONST(0x6058))
++#define CSC_D_ZERO_PADDING_VALUE_0_SECURE                                  (0x0)
++#define CSC_D_ZERO_PADDING_VALUE_0_DUAL                                    (0x0)
++#define CSC_D_ZERO_PADDING_VALUE_0_SCR                                       (0)
++#define CSC_D_ZERO_PADDING_VALUE_0_WORD_COUNT                              (0x1)
++#define CSC_D_ZERO_PADDING_VALUE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_VALUE_0_RESET_MASK           (_MK_MASK_CONST(0xffff))
++#define CSC_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_VALUE_0_READ_MASK            (_MK_MASK_CONST(0xffff))
++#define CSC_D_ZERO_PADDING_VALUE_0_WRITE_MASK           (_MK_MASK_CONST(0xffff))
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT          (_MK_SHIFT_CONST(0))
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD \
++      (_MK_FIELD_CONST(0xffff, CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT))
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_RANGE                        (15:0)
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_WOFFSET                       (0x0)
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_BANK_0
++#define CSC_D_BANK_0                                    (_MK_ADDR_CONST(0x605c))
++#define CSC_D_BANK_0_SECURE                                                (0x0)
++#define CSC_D_BANK_0_DUAL                                                  (0x0)
++#define CSC_D_BANK_0_SCR                                                     (0)
++#define CSC_D_BANK_0_WORD_COUNT                                            (0x1)
++#define CSC_D_BANK_0_RESET_VAL                             (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_RESET_MASK                        (_MK_MASK_CONST(0xf000f))
++#define CSC_D_BANK_0_SW_DEFAULT_VAL                        (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_SW_DEFAULT_MASK                       (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_READ_MASK                         (_MK_MASK_CONST(0xf000f))
++#define CSC_D_BANK_0_WRITE_MASK                        (_MK_MASK_CONST(0xf000f))
++#define CSC_D_BANK_0_DATA_BANK_SHIFT                        (_MK_SHIFT_CONST(0))
++#define CSC_D_BANK_0_DATA_BANK_FIELD \
++      (_MK_FIELD_CONST(0xf, CSC_D_BANK_0_DATA_BANK_SHIFT))
++#define CSC_D_BANK_0_DATA_BANK_RANGE                                       (3:0)
++#define CSC_D_BANK_0_DATA_BANK_WOFFSET                                     (0x0)
++#define CSC_D_BANK_0_DATA_BANK_DEFAULT                     (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_DATA_BANK_DEFAULT_MASK                (_MK_MASK_CONST(0xf))
++#define CSC_D_BANK_0_DATA_BANK_SW_DEFAULT                  (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_DATA_BANK_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_DATA_BANK_PARITY_PROTECTION           (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_DATA_BANK_PLATFORM_DEPENDENT          (_MK_MASK_CONST(0x1))
++
++#define CSC_D_BANK_0_WEIGHT_BANK_SHIFT                     (_MK_SHIFT_CONST(16))
++#define CSC_D_BANK_0_WEIGHT_BANK_FIELD \
++      (_MK_FIELD_CONST(0xf, CSC_D_BANK_0_WEIGHT_BANK_SHIFT))
++#define CSC_D_BANK_0_WEIGHT_BANK_RANGE                                   (19:16)
++#define CSC_D_BANK_0_WEIGHT_BANK_WOFFSET                                   (0x0)
++#define CSC_D_BANK_0_WEIGHT_BANK_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_WEIGHT_BANK_DEFAULT_MASK              (_MK_MASK_CONST(0xf))
++#define CSC_D_BANK_0_WEIGHT_BANK_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_WEIGHT_BANK_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_WEIGHT_BANK_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CSC_D_BANK_0_WEIGHT_BANK_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_PRA_CFG_0
++#define CSC_D_PRA_CFG_0                                 (_MK_ADDR_CONST(0x6060))
++#define CSC_D_PRA_CFG_0_SECURE                                             (0x0)
++#define CSC_D_PRA_CFG_0_DUAL                                               (0x0)
++#define CSC_D_PRA_CFG_0_SCR                                                  (0)
++#define CSC_D_PRA_CFG_0_WORD_COUNT                                         (0x1)
++#define CSC_D_PRA_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define CSC_D_PRA_CFG_0_RESET_MASK                         (_MK_MASK_CONST(0x3))
++#define CSC_D_PRA_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define CSC_D_PRA_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CSC_D_PRA_CFG_0_READ_MASK                          (_MK_MASK_CONST(0x3))
++#define CSC_D_PRA_CFG_0_WRITE_MASK                         (_MK_MASK_CONST(0x3))
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT                  (_MK_SHIFT_CONST(0))
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_FIELD \
++      (_MK_FIELD_CONST(0x3, CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT))
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_RANGE                                 (1:0)
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_WOFFSET                               (0x0)
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++
++
++// Register CSC_D_CYA_0
++#define CSC_D_CYA_0                                     (_MK_ADDR_CONST(0x6064))
++#define CSC_D_CYA_0_SECURE                                                 (0x0)
++#define CSC_D_CYA_0_DUAL                                                   (0x0)
++#define CSC_D_CYA_0_SCR                                                      (0)
++#define CSC_D_CYA_0_WORD_COUNT                                             (0x1)
++#define CSC_D_CYA_0_RESET_VAL                              (_MK_MASK_CONST(0x0))
++#define CSC_D_CYA_0_RESET_MASK                      (_MK_MASK_CONST(0xffffffff))
++#define CSC_D_CYA_0_SW_DEFAULT_VAL                         (_MK_MASK_CONST(0x0))
++#define CSC_D_CYA_0_SW_DEFAULT_MASK                        (_MK_MASK_CONST(0x0))
++#define CSC_D_CYA_0_READ_MASK                       (_MK_MASK_CONST(0xffffffff))
++#define CSC_D_CYA_0_WRITE_MASK                      (_MK_MASK_CONST(0xffffffff))
++#define CSC_D_CYA_0_CYA_SHIFT                               (_MK_SHIFT_CONST(0))
++#define CSC_D_CYA_0_CYA_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, CSC_D_CYA_0_CYA_SHIFT))
++#define CSC_D_CYA_0_CYA_RANGE                                             (31:0)
++#define CSC_D_CYA_0_CYA_WOFFSET                                            (0x0)
++#define CSC_D_CYA_0_CYA_DEFAULT                            (_MK_MASK_CONST(0x0))
++#define CSC_D_CYA_0_CYA_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff))
++#define CSC_D_CYA_0_CYA_SW_DEFAULT                         (_MK_MASK_CONST(0x0))
++#define CSC_D_CYA_0_CYA_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CSC_D_CYA_0_CYA_PARITY_PROTECTION                  (_MK_MASK_CONST(0x0))
++#define CSC_D_CYA_0_CYA_PLATFORM_DEPENDENT                 (_MK_MASK_CONST(0x1))
++
++
++// Register CMAC_A_S_STATUS_0
++#define CMAC_A_S_STATUS_0                               (_MK_ADDR_CONST(0x7000))
++#define CMAC_A_S_STATUS_0_SECURE                                           (0x0)
++#define CMAC_A_S_STATUS_0_DUAL                                             (0x0)
++#define CMAC_A_S_STATUS_0_SCR                                                (0)
++#define CMAC_A_S_STATUS_0_WORD_COUNT                                       (0x1)
++#define CMAC_A_S_STATUS_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_RESET_MASK                   (_MK_MASK_CONST(0x30003))
++#define CMAC_A_S_STATUS_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_READ_MASK                    (_MK_MASK_CONST(0x30003))
++#define CMAC_A_S_STATUS_0_WRITE_MASK                       (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_STATUS_0_SHIFT                    (_MK_SHIFT_CONST(0))
++#define CMAC_A_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_0_SHIFT))
++#define CMAC_A_S_STATUS_0_STATUS_0_RANGE                                   (1:0)
++#define CMAC_A_S_STATUS_0_STATUS_0_WOFFSET                                 (0x0)
++#define CMAC_A_S_STATUS_0_STATUS_0_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_STATUS_0_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
++#define CMAC_A_S_STATUS_0_STATUS_0_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_STATUS_0_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define CMAC_A_S_STATUS_0_STATUS_0_INIT_ENUM                              (IDLE)
++#define CMAC_A_S_STATUS_0_STATUS_0_IDLE                      (_MK_ENUM_CONST(0))
++#define CMAC_A_S_STATUS_0_STATUS_0_RUNNING                   (_MK_ENUM_CONST(1))
++#define CMAC_A_S_STATUS_0_STATUS_0_PENDING                   (_MK_ENUM_CONST(2))
++
++#define CMAC_A_S_STATUS_0_STATUS_1_SHIFT                   (_MK_SHIFT_CONST(16))
++#define CMAC_A_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_1_SHIFT))
++#define CMAC_A_S_STATUS_0_STATUS_1_RANGE                                 (17:16)
++#define CMAC_A_S_STATUS_0_STATUS_1_WOFFSET                                 (0x0)
++#define CMAC_A_S_STATUS_0_STATUS_1_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_STATUS_1_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
++#define CMAC_A_S_STATUS_0_STATUS_1_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_STATUS_1_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define CMAC_A_S_STATUS_0_STATUS_1_INIT_ENUM                              (IDLE)
++#define CMAC_A_S_STATUS_0_STATUS_1_IDLE                      (_MK_ENUM_CONST(0))
++#define CMAC_A_S_STATUS_0_STATUS_1_RUNNING                   (_MK_ENUM_CONST(1))
++#define CMAC_A_S_STATUS_0_STATUS_1_PENDING                   (_MK_ENUM_CONST(2))
++
++
++// Register CMAC_A_S_POINTER_0
++#define CMAC_A_S_POINTER_0                              (_MK_ADDR_CONST(0x7004))
++#define CMAC_A_S_POINTER_0_SECURE                                          (0x0)
++#define CMAC_A_S_POINTER_0_DUAL                                            (0x0)
++#define CMAC_A_S_POINTER_0_SCR                                               (0)
++#define CMAC_A_S_POINTER_0_WORD_COUNT                                      (0x1)
++#define CMAC_A_S_POINTER_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_RESET_MASK                  (_MK_MASK_CONST(0x10001))
++#define CMAC_A_S_POINTER_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_READ_MASK                   (_MK_MASK_CONST(0x10001))
++#define CMAC_A_S_POINTER_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
++#define CMAC_A_S_POINTER_0_PRODUCER_SHIFT                   (_MK_SHIFT_CONST(0))
++#define CMAC_A_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_PRODUCER_SHIFT))
++#define CMAC_A_S_POINTER_0_PRODUCER_RANGE                                  (0:0)
++#define CMAC_A_S_POINTER_0_PRODUCER_WOFFSET                                (0x0)
++#define CMAC_A_S_POINTER_0_PRODUCER_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_PRODUCER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define CMAC_A_S_POINTER_0_PRODUCER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_PRODUCER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define CMAC_A_S_POINTER_0_PRODUCER_INIT_ENUM                          (GROUP_0)
++#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_0                  (_MK_ENUM_CONST(0))
++#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_1                  (_MK_ENUM_CONST(1))
++
++#define CMAC_A_S_POINTER_0_CONSUMER_SHIFT                  (_MK_SHIFT_CONST(16))
++#define CMAC_A_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_CONSUMER_SHIFT))
++#define CMAC_A_S_POINTER_0_CONSUMER_RANGE                                (16:16)
++#define CMAC_A_S_POINTER_0_CONSUMER_WOFFSET                                (0x0)
++#define CMAC_A_S_POINTER_0_CONSUMER_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_CONSUMER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define CMAC_A_S_POINTER_0_CONSUMER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_CONSUMER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CMAC_A_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define CMAC_A_S_POINTER_0_CONSUMER_INIT_ENUM                          (GROUP_0)
++#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_0                  (_MK_ENUM_CONST(0))
++#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_1                  (_MK_ENUM_CONST(1))
++
++
++// Register CMAC_A_D_OP_ENABLE_0
++#define CMAC_A_D_OP_ENABLE_0                            (_MK_ADDR_CONST(0x7008))
++#define CMAC_A_D_OP_ENABLE_0_SECURE                                        (0x0)
++#define CMAC_A_D_OP_ENABLE_0_DUAL                                          (0x0)
++#define CMAC_A_D_OP_ENABLE_0_SCR                                             (0)
++#define CMAC_A_D_OP_ENABLE_0_WORD_COUNT                                    (0x1)
++#define CMAC_A_D_OP_ENABLE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_OP_ENABLE_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
++#define CMAC_A_D_OP_ENABLE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_OP_ENABLE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_OP_ENABLE_0_READ_MASK                     (_MK_MASK_CONST(0x1))
++#define CMAC_A_D_OP_ENABLE_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT                    (_MK_SHIFT_CONST(0))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_RANGE                                   (0:0)
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_WOFFSET                                 (0x0)
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_INIT_ENUM                           (DISABLE)
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_DISABLE                   (_MK_ENUM_CONST(0))
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_ENABLE                    (_MK_ENUM_CONST(1))
++
++
++// Register CMAC_A_D_MISC_CFG_0
++#define CMAC_A_D_MISC_CFG_0                             (_MK_ADDR_CONST(0x700c))
++#define CMAC_A_D_MISC_CFG_0_SECURE                                         (0x0)
++#define CMAC_A_D_MISC_CFG_0_DUAL                                           (0x0)
++#define CMAC_A_D_MISC_CFG_0_SCR                                              (0)
++#define CMAC_A_D_MISC_CFG_0_WORD_COUNT                                     (0x1)
++#define CMAC_A_D_MISC_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x1000))
++#define CMAC_A_D_MISC_CFG_0_RESET_MASK                  (_MK_MASK_CONST(0x3001))
++#define CMAC_A_D_MISC_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_MISC_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_MISC_CFG_0_READ_MASK                   (_MK_MASK_CONST(0x3001))
++#define CMAC_A_D_MISC_CFG_0_WRITE_MASK                  (_MK_MASK_CONST(0x3001))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT                 (_MK_SHIFT_CONST(0))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_RANGE                                (0:0)
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WOFFSET                              (0x0)
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                         (DIRECT)
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DIRECT                 (_MK_ENUM_CONST(0))
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WINOGRAD               (_MK_ENUM_CONST(1))
++
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT           (_MK_SHIFT_CONST(12))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_RANGE                         (13:12)
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                         (0x0)
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_DEFAULT         (_MK_MASK_CONST(0x1))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK    (_MK_MASK_CONST(0x3))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                     (INT16)
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT8              (_MK_ENUM_CONST(0))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT16             (_MK_ENUM_CONST(1))
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FP16              (_MK_ENUM_CONST(2))
++
++
++// Register CMAC_B_S_STATUS_0
++#define CMAC_B_S_STATUS_0                               (_MK_ADDR_CONST(0x8000))
++#define CMAC_B_S_STATUS_0_SECURE                                           (0x0)
++#define CMAC_B_S_STATUS_0_DUAL                                             (0x0)
++#define CMAC_B_S_STATUS_0_SCR                                                (0)
++#define CMAC_B_S_STATUS_0_WORD_COUNT                                       (0x1)
++#define CMAC_B_S_STATUS_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_RESET_MASK                   (_MK_MASK_CONST(0x30003))
++#define CMAC_B_S_STATUS_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_READ_MASK                    (_MK_MASK_CONST(0x30003))
++#define CMAC_B_S_STATUS_0_WRITE_MASK                       (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_STATUS_0_SHIFT                    (_MK_SHIFT_CONST(0))
++#define CMAC_B_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_0_SHIFT))
++#define CMAC_B_S_STATUS_0_STATUS_0_RANGE                                   (1:0)
++#define CMAC_B_S_STATUS_0_STATUS_0_WOFFSET                                 (0x0)
++#define CMAC_B_S_STATUS_0_STATUS_0_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_STATUS_0_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
++#define CMAC_B_S_STATUS_0_STATUS_0_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_STATUS_0_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define CMAC_B_S_STATUS_0_STATUS_0_INIT_ENUM                              (IDLE)
++#define CMAC_B_S_STATUS_0_STATUS_0_IDLE                      (_MK_ENUM_CONST(0))
++#define CMAC_B_S_STATUS_0_STATUS_0_RUNNING                   (_MK_ENUM_CONST(1))
++#define CMAC_B_S_STATUS_0_STATUS_0_PENDING                   (_MK_ENUM_CONST(2))
++
++#define CMAC_B_S_STATUS_0_STATUS_1_SHIFT                   (_MK_SHIFT_CONST(16))
++#define CMAC_B_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_1_SHIFT))
++#define CMAC_B_S_STATUS_0_STATUS_1_RANGE                                 (17:16)
++#define CMAC_B_S_STATUS_0_STATUS_1_WOFFSET                                 (0x0)
++#define CMAC_B_S_STATUS_0_STATUS_1_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_STATUS_1_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
++#define CMAC_B_S_STATUS_0_STATUS_1_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_STATUS_1_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define CMAC_B_S_STATUS_0_STATUS_1_INIT_ENUM                              (IDLE)
++#define CMAC_B_S_STATUS_0_STATUS_1_IDLE                      (_MK_ENUM_CONST(0))
++#define CMAC_B_S_STATUS_0_STATUS_1_RUNNING                   (_MK_ENUM_CONST(1))
++#define CMAC_B_S_STATUS_0_STATUS_1_PENDING                   (_MK_ENUM_CONST(2))
++
++
++// Register CMAC_B_S_POINTER_0
++#define CMAC_B_S_POINTER_0                              (_MK_ADDR_CONST(0x8004))
++#define CMAC_B_S_POINTER_0_SECURE                                          (0x0)
++#define CMAC_B_S_POINTER_0_DUAL                                            (0x0)
++#define CMAC_B_S_POINTER_0_SCR                                               (0)
++#define CMAC_B_S_POINTER_0_WORD_COUNT                                      (0x1)
++#define CMAC_B_S_POINTER_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_RESET_MASK                  (_MK_MASK_CONST(0x10001))
++#define CMAC_B_S_POINTER_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_READ_MASK                   (_MK_MASK_CONST(0x10001))
++#define CMAC_B_S_POINTER_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
++#define CMAC_B_S_POINTER_0_PRODUCER_SHIFT                   (_MK_SHIFT_CONST(0))
++#define CMAC_B_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_PRODUCER_SHIFT))
++#define CMAC_B_S_POINTER_0_PRODUCER_RANGE                                  (0:0)
++#define CMAC_B_S_POINTER_0_PRODUCER_WOFFSET                                (0x0)
++#define CMAC_B_S_POINTER_0_PRODUCER_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_PRODUCER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define CMAC_B_S_POINTER_0_PRODUCER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_PRODUCER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define CMAC_B_S_POINTER_0_PRODUCER_INIT_ENUM                          (GROUP_0)
++#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_0                  (_MK_ENUM_CONST(0))
++#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_1                  (_MK_ENUM_CONST(1))
++
++#define CMAC_B_S_POINTER_0_CONSUMER_SHIFT                  (_MK_SHIFT_CONST(16))
++#define CMAC_B_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_CONSUMER_SHIFT))
++#define CMAC_B_S_POINTER_0_CONSUMER_RANGE                                (16:16)
++#define CMAC_B_S_POINTER_0_CONSUMER_WOFFSET                                (0x0)
++#define CMAC_B_S_POINTER_0_CONSUMER_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_CONSUMER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define CMAC_B_S_POINTER_0_CONSUMER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_CONSUMER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CMAC_B_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define CMAC_B_S_POINTER_0_CONSUMER_INIT_ENUM                          (GROUP_0)
++#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_0                  (_MK_ENUM_CONST(0))
++#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_1                  (_MK_ENUM_CONST(1))
++
++
++// Register CMAC_B_D_OP_ENABLE_0
++#define CMAC_B_D_OP_ENABLE_0                            (_MK_ADDR_CONST(0x8008))
++#define CMAC_B_D_OP_ENABLE_0_SECURE                                        (0x0)
++#define CMAC_B_D_OP_ENABLE_0_DUAL                                          (0x0)
++#define CMAC_B_D_OP_ENABLE_0_SCR                                             (0)
++#define CMAC_B_D_OP_ENABLE_0_WORD_COUNT                                    (0x1)
++#define CMAC_B_D_OP_ENABLE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_OP_ENABLE_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
++#define CMAC_B_D_OP_ENABLE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_OP_ENABLE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_OP_ENABLE_0_READ_MASK                     (_MK_MASK_CONST(0x1))
++#define CMAC_B_D_OP_ENABLE_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT                    (_MK_SHIFT_CONST(0))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_RANGE                                   (0:0)
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_WOFFSET                                 (0x0)
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_INIT_ENUM                           (DISABLE)
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_DISABLE                   (_MK_ENUM_CONST(0))
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_ENABLE                    (_MK_ENUM_CONST(1))
++
++
++// Register CMAC_B_D_MISC_CFG_0
++#define CMAC_B_D_MISC_CFG_0                             (_MK_ADDR_CONST(0x800c))
++#define CMAC_B_D_MISC_CFG_0_SECURE                                         (0x0)
++#define CMAC_B_D_MISC_CFG_0_DUAL                                           (0x0)
++#define CMAC_B_D_MISC_CFG_0_SCR                                              (0)
++#define CMAC_B_D_MISC_CFG_0_WORD_COUNT                                     (0x1)
++#define CMAC_B_D_MISC_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x1000))
++#define CMAC_B_D_MISC_CFG_0_RESET_MASK                  (_MK_MASK_CONST(0x3001))
++#define CMAC_B_D_MISC_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_MISC_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_MISC_CFG_0_READ_MASK                   (_MK_MASK_CONST(0x3001))
++#define CMAC_B_D_MISC_CFG_0_WRITE_MASK                  (_MK_MASK_CONST(0x3001))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT                 (_MK_SHIFT_CONST(0))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_RANGE                                (0:0)
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WOFFSET                              (0x0)
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                         (DIRECT)
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DIRECT                 (_MK_ENUM_CONST(0))
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WINOGRAD               (_MK_ENUM_CONST(1))
++
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT           (_MK_SHIFT_CONST(12))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_RANGE                         (13:12)
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                         (0x0)
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_DEFAULT         (_MK_MASK_CONST(0x1))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK    (_MK_MASK_CONST(0x3))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                     (INT16)
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT8              (_MK_ENUM_CONST(0))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT16             (_MK_ENUM_CONST(1))
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FP16              (_MK_ENUM_CONST(2))
++
++
++// Register CACC_S_STATUS_0
++#define CACC_S_STATUS_0                                 (_MK_ADDR_CONST(0x9000))
++#define CACC_S_STATUS_0_SECURE                                             (0x0)
++#define CACC_S_STATUS_0_DUAL                                               (0x0)
++#define CACC_S_STATUS_0_SCR                                                  (0)
++#define CACC_S_STATUS_0_WORD_COUNT                                         (0x1)
++#define CACC_S_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_RESET_MASK                     (_MK_MASK_CONST(0x30003))
++#define CACC_S_STATUS_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_READ_MASK                      (_MK_MASK_CONST(0x30003))
++#define CACC_S_STATUS_0_WRITE_MASK                         (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_STATUS_0_SHIFT                      (_MK_SHIFT_CONST(0))
++#define CACC_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_0_SHIFT))
++#define CACC_S_STATUS_0_STATUS_0_RANGE                                     (1:0)
++#define CACC_S_STATUS_0_STATUS_0_WOFFSET                                   (0x0)
++#define CACC_S_STATUS_0_STATUS_0_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_STATUS_0_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
++#define CACC_S_STATUS_0_STATUS_0_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_STATUS_0_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CACC_S_STATUS_0_STATUS_0_INIT_ENUM                                (IDLE)
++#define CACC_S_STATUS_0_STATUS_0_IDLE                        (_MK_ENUM_CONST(0))
++#define CACC_S_STATUS_0_STATUS_0_RUNNING                     (_MK_ENUM_CONST(1))
++#define CACC_S_STATUS_0_STATUS_0_PENDING                     (_MK_ENUM_CONST(2))
++
++#define CACC_S_STATUS_0_STATUS_1_SHIFT                     (_MK_SHIFT_CONST(16))
++#define CACC_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_1_SHIFT))
++#define CACC_S_STATUS_0_STATUS_1_RANGE                                   (17:16)
++#define CACC_S_STATUS_0_STATUS_1_WOFFSET                                   (0x0)
++#define CACC_S_STATUS_0_STATUS_1_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_STATUS_1_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
++#define CACC_S_STATUS_0_STATUS_1_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_STATUS_1_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CACC_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CACC_S_STATUS_0_STATUS_1_INIT_ENUM                                (IDLE)
++#define CACC_S_STATUS_0_STATUS_1_IDLE                        (_MK_ENUM_CONST(0))
++#define CACC_S_STATUS_0_STATUS_1_RUNNING                     (_MK_ENUM_CONST(1))
++#define CACC_S_STATUS_0_STATUS_1_PENDING                     (_MK_ENUM_CONST(2))
++
++
++// Register CACC_S_POINTER_0
++#define CACC_S_POINTER_0                                (_MK_ADDR_CONST(0x9004))
++#define CACC_S_POINTER_0_SECURE                                            (0x0)
++#define CACC_S_POINTER_0_DUAL                                              (0x0)
++#define CACC_S_POINTER_0_SCR                                                 (0)
++#define CACC_S_POINTER_0_WORD_COUNT                                        (0x1)
++#define CACC_S_POINTER_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_RESET_MASK                    (_MK_MASK_CONST(0x10001))
++#define CACC_S_POINTER_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_READ_MASK                     (_MK_MASK_CONST(0x10001))
++#define CACC_S_POINTER_0_WRITE_MASK                        (_MK_MASK_CONST(0x1))
++#define CACC_S_POINTER_0_PRODUCER_SHIFT                     (_MK_SHIFT_CONST(0))
++#define CACC_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, CACC_S_POINTER_0_PRODUCER_SHIFT))
++#define CACC_S_POINTER_0_PRODUCER_RANGE                                    (0:0)
++#define CACC_S_POINTER_0_PRODUCER_WOFFSET                                  (0x0)
++#define CACC_S_POINTER_0_PRODUCER_DEFAULT                  (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_PRODUCER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
++#define CACC_S_POINTER_0_PRODUCER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_PRODUCER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
++#define CACC_S_POINTER_0_PRODUCER_INIT_ENUM                            (GROUP_0)
++#define CACC_S_POINTER_0_PRODUCER_GROUP_0                    (_MK_ENUM_CONST(0))
++#define CACC_S_POINTER_0_PRODUCER_GROUP_1                    (_MK_ENUM_CONST(1))
++
++#define CACC_S_POINTER_0_CONSUMER_SHIFT                    (_MK_SHIFT_CONST(16))
++#define CACC_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, CACC_S_POINTER_0_CONSUMER_SHIFT))
++#define CACC_S_POINTER_0_CONSUMER_RANGE                                  (16:16)
++#define CACC_S_POINTER_0_CONSUMER_WOFFSET                                  (0x0)
++#define CACC_S_POINTER_0_CONSUMER_DEFAULT                  (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_CONSUMER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
++#define CACC_S_POINTER_0_CONSUMER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_CONSUMER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
++#define CACC_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
++#define CACC_S_POINTER_0_CONSUMER_INIT_ENUM                            (GROUP_0)
++#define CACC_S_POINTER_0_CONSUMER_GROUP_0                    (_MK_ENUM_CONST(0))
++#define CACC_S_POINTER_0_CONSUMER_GROUP_1                    (_MK_ENUM_CONST(1))
++
++
++// Register CACC_D_OP_ENABLE_0
++#define CACC_D_OP_ENABLE_0                              (_MK_ADDR_CONST(0x9008))
++#define CACC_D_OP_ENABLE_0_SECURE                                          (0x0)
++#define CACC_D_OP_ENABLE_0_DUAL                                            (0x0)
++#define CACC_D_OP_ENABLE_0_SCR                                               (0)
++#define CACC_D_OP_ENABLE_0_WORD_COUNT                                      (0x1)
++#define CACC_D_OP_ENABLE_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define CACC_D_OP_ENABLE_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
++#define CACC_D_OP_ENABLE_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define CACC_D_OP_ENABLE_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define CACC_D_OP_ENABLE_0_READ_MASK                       (_MK_MASK_CONST(0x1))
++#define CACC_D_OP_ENABLE_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
++#define CACC_D_OP_ENABLE_0_OP_EN_SHIFT                      (_MK_SHIFT_CONST(0))
++#define CACC_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CACC_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define CACC_D_OP_ENABLE_0_OP_EN_RANGE                                     (0:0)
++#define CACC_D_OP_ENABLE_0_OP_EN_WOFFSET                                   (0x0)
++#define CACC_D_OP_ENABLE_0_OP_EN_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CACC_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define CACC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CACC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CACC_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CACC_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CACC_D_OP_ENABLE_0_OP_EN_INIT_ENUM                             (DISABLE)
++#define CACC_D_OP_ENABLE_0_OP_EN_DISABLE                     (_MK_ENUM_CONST(0))
++#define CACC_D_OP_ENABLE_0_OP_EN_ENABLE                      (_MK_ENUM_CONST(1))
++
++
++// Register CACC_D_MISC_CFG_0
++#define CACC_D_MISC_CFG_0                               (_MK_ADDR_CONST(0x900c))
++#define CACC_D_MISC_CFG_0_SECURE                                           (0x0)
++#define CACC_D_MISC_CFG_0_DUAL                                             (0x0)
++#define CACC_D_MISC_CFG_0_SCR                                                (0)
++#define CACC_D_MISC_CFG_0_WORD_COUNT                                       (0x1)
++#define CACC_D_MISC_CFG_0_RESET_VAL                     (_MK_MASK_CONST(0x1000))
++#define CACC_D_MISC_CFG_0_RESET_MASK                    (_MK_MASK_CONST(0x3001))
++#define CACC_D_MISC_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define CACC_D_MISC_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define CACC_D_MISC_CFG_0_READ_MASK                     (_MK_MASK_CONST(0x3001))
++#define CACC_D_MISC_CFG_0_WRITE_MASK                    (_MK_MASK_CONST(0x3001))
++#define CACC_D_MISC_CFG_0_CONV_MODE_SHIFT                   (_MK_SHIFT_CONST(0))
++#define CACC_D_MISC_CFG_0_CONV_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, CACC_D_MISC_CFG_0_CONV_MODE_SHIFT))
++#define CACC_D_MISC_CFG_0_CONV_MODE_RANGE                                  (0:0)
++#define CACC_D_MISC_CFG_0_CONV_MODE_WOFFSET                                (0x0)
++#define CACC_D_MISC_CFG_0_CONV_MODE_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CACC_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define CACC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CACC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CACC_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CACC_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define CACC_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                           (DIRECT)
++#define CACC_D_MISC_CFG_0_CONV_MODE_DIRECT                   (_MK_ENUM_CONST(0))
++#define CACC_D_MISC_CFG_0_CONV_MODE_WINOGRAD                 (_MK_ENUM_CONST(1))
++
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT             (_MK_SHIFT_CONST(12))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_RANGE                           (13:12)
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                           (0x0)
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT           (_MK_MASK_CONST(0x1))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK      (_MK_MASK_CONST(0x3))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                       (INT16)
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT8                (_MK_ENUM_CONST(0))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT16               (_MK_ENUM_CONST(1))
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_FP16                (_MK_ENUM_CONST(2))
++
++
++// Register CACC_D_DATAOUT_SIZE_0_0
++#define CACC_D_DATAOUT_SIZE_0_0                         (_MK_ADDR_CONST(0x9010))
++#define CACC_D_DATAOUT_SIZE_0_0_SECURE                                     (0x0)
++#define CACC_D_DATAOUT_SIZE_0_0_DUAL                                       (0x0)
++#define CACC_D_DATAOUT_SIZE_0_0_SCR                                          (0)
++#define CACC_D_DATAOUT_SIZE_0_0_WORD_COUNT                                 (0x1)
++#define CACC_D_DATAOUT_SIZE_0_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_RESET_MASK          (_MK_MASK_CONST(0x1fff1fff))
++#define CACC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_READ_MASK           (_MK_MASK_CONST(0x1fff1fff))
++#define CACC_D_DATAOUT_SIZE_0_0_WRITE_MASK          (_MK_MASK_CONST(0x1fff1fff))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT         (_MK_SHIFT_CONST(0))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_RANGE                       (12:0)
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_WOFFSET                      (0x0)
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT       (_MK_SHIFT_CONST(16))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_RANGE                     (28:16)
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_WOFFSET                     (0x0)
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CACC_D_DATAOUT_SIZE_1_0
++#define CACC_D_DATAOUT_SIZE_1_0                         (_MK_ADDR_CONST(0x9014))
++#define CACC_D_DATAOUT_SIZE_1_0_SECURE                                     (0x0)
++#define CACC_D_DATAOUT_SIZE_1_0_DUAL                                       (0x0)
++#define CACC_D_DATAOUT_SIZE_1_0_SCR                                          (0)
++#define CACC_D_DATAOUT_SIZE_1_0_WORD_COUNT                                 (0x1)
++#define CACC_D_DATAOUT_SIZE_1_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_1_0_RESET_MASK              (_MK_MASK_CONST(0x1fff))
++#define CACC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_1_0_READ_MASK               (_MK_MASK_CONST(0x1fff))
++#define CACC_D_DATAOUT_SIZE_1_0_WRITE_MASK              (_MK_MASK_CONST(0x1fff))
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT       (_MK_SHIFT_CONST(0))
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT))
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_RANGE                     (12:0)
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_WOFFSET                    (0x0)
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CACC_D_DATAOUT_ADDR_0
++#define CACC_D_DATAOUT_ADDR_0                           (_MK_ADDR_CONST(0x9018))
++#define CACC_D_DATAOUT_ADDR_0_SECURE                                       (0x0)
++#define CACC_D_DATAOUT_ADDR_0_DUAL                                         (0x0)
++#define CACC_D_DATAOUT_ADDR_0_SCR                                            (0)
++#define CACC_D_DATAOUT_ADDR_0_WORD_COUNT                                   (0x1)
++#define CACC_D_DATAOUT_ADDR_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_ADDR_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define CACC_D_DATAOUT_ADDR_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_ADDR_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_ADDR_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
++#define CACC_D_DATAOUT_ADDR_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT            (_MK_SHIFT_CONST(5))
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT))
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_RANGE                          (31:5)
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_WOFFSET                         (0x0)
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CACC_D_BATCH_NUMBER_0
++#define CACC_D_BATCH_NUMBER_0                           (_MK_ADDR_CONST(0x901c))
++#define CACC_D_BATCH_NUMBER_0_SECURE                                       (0x0)
++#define CACC_D_BATCH_NUMBER_0_DUAL                                         (0x0)
++#define CACC_D_BATCH_NUMBER_0_SCR                                            (0)
++#define CACC_D_BATCH_NUMBER_0_WORD_COUNT                                   (0x1)
++#define CACC_D_BATCH_NUMBER_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CACC_D_BATCH_NUMBER_0_RESET_MASK                  (_MK_MASK_CONST(0x1f))
++#define CACC_D_BATCH_NUMBER_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CACC_D_BATCH_NUMBER_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CACC_D_BATCH_NUMBER_0_READ_MASK                   (_MK_MASK_CONST(0x1f))
++#define CACC_D_BATCH_NUMBER_0_WRITE_MASK                  (_MK_MASK_CONST(0x1f))
++#define CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT                 (_MK_SHIFT_CONST(0))
++#define CACC_D_BATCH_NUMBER_0_BATCHES_FIELD \
++      (_MK_FIELD_CONST(0x1f, CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT))
++#define CACC_D_BATCH_NUMBER_0_BATCHES_RANGE                                (4:0)
++#define CACC_D_BATCH_NUMBER_0_BATCHES_WOFFSET                              (0x0)
++#define CACC_D_BATCH_NUMBER_0_BATCHES_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CACC_D_BATCH_NUMBER_0_BATCHES_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
++#define CACC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CACC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CACC_D_BATCH_NUMBER_0_BATCHES_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CACC_D_BATCH_NUMBER_0_BATCHES_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CACC_D_LINE_STRIDE_0
++#define CACC_D_LINE_STRIDE_0                            (_MK_ADDR_CONST(0x9020))
++#define CACC_D_LINE_STRIDE_0_SECURE                                        (0x0)
++#define CACC_D_LINE_STRIDE_0_DUAL                                          (0x0)
++#define CACC_D_LINE_STRIDE_0_SCR                                             (0)
++#define CACC_D_LINE_STRIDE_0_WORD_COUNT                                    (0x1)
++#define CACC_D_LINE_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CACC_D_LINE_STRIDE_0_RESET_MASK               (_MK_MASK_CONST(0xffffe0))
++#define CACC_D_LINE_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CACC_D_LINE_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CACC_D_LINE_STRIDE_0_READ_MASK                (_MK_MASK_CONST(0xffffe0))
++#define CACC_D_LINE_STRIDE_0_WRITE_MASK               (_MK_MASK_CONST(0xffffe0))
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffff, CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT))
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_RANGE                            (23:5)
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_WOFFSET                           (0x0)
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CACC_D_SURF_STRIDE_0
++#define CACC_D_SURF_STRIDE_0                            (_MK_ADDR_CONST(0x9024))
++#define CACC_D_SURF_STRIDE_0_SECURE                                        (0x0)
++#define CACC_D_SURF_STRIDE_0_DUAL                                          (0x0)
++#define CACC_D_SURF_STRIDE_0_SCR                                             (0)
++#define CACC_D_SURF_STRIDE_0_WORD_COUNT                                    (0x1)
++#define CACC_D_SURF_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CACC_D_SURF_STRIDE_0_RESET_MASK               (_MK_MASK_CONST(0xffffe0))
++#define CACC_D_SURF_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CACC_D_SURF_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CACC_D_SURF_STRIDE_0_READ_MASK                (_MK_MASK_CONST(0xffffe0))
++#define CACC_D_SURF_STRIDE_0_WRITE_MASK               (_MK_MASK_CONST(0xffffe0))
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffff, CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT))
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_RANGE                            (23:5)
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_WOFFSET                           (0x0)
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CACC_D_DATAOUT_MAP_0
++#define CACC_D_DATAOUT_MAP_0                            (_MK_ADDR_CONST(0x9028))
++#define CACC_D_DATAOUT_MAP_0_SECURE                                        (0x0)
++#define CACC_D_DATAOUT_MAP_0_DUAL                                          (0x0)
++#define CACC_D_DATAOUT_MAP_0_SCR                                             (0)
++#define CACC_D_DATAOUT_MAP_0_WORD_COUNT                                    (0x1)
++#define CACC_D_DATAOUT_MAP_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
++#define CACC_D_DATAOUT_MAP_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
++#define CACC_D_DATAOUT_MAP_0_WRITE_MASK                (_MK_MASK_CONST(0x10001))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT              (_MK_SHIFT_CONST(0))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FIELD \
++      (_MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_RANGE                             (0:0)
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_WOFFSET                           (0x0)
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_INIT_ENUM                       (FALSE)
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FALSE               (_MK_ENUM_CONST(0))
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE                (_MK_ENUM_CONST(1))
++
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT             (_MK_SHIFT_CONST(16))
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FIELD \
++      (_MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT))
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_RANGE                           (16:16)
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_WOFFSET                           (0x0)
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_INIT_ENUM                       (FALSE)
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FALSE               (_MK_ENUM_CONST(0))
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE                (_MK_ENUM_CONST(1))
++
++
++// Register CACC_D_CLIP_CFG_0
++#define CACC_D_CLIP_CFG_0                               (_MK_ADDR_CONST(0x902c))
++#define CACC_D_CLIP_CFG_0_SECURE                                           (0x0)
++#define CACC_D_CLIP_CFG_0_DUAL                                             (0x0)
++#define CACC_D_CLIP_CFG_0_SCR                                                (0)
++#define CACC_D_CLIP_CFG_0_WORD_COUNT                                       (0x1)
++#define CACC_D_CLIP_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define CACC_D_CLIP_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x1f))
++#define CACC_D_CLIP_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define CACC_D_CLIP_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define CACC_D_CLIP_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x1f))
++#define CACC_D_CLIP_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x1f))
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT               (_MK_SHIFT_CONST(0))
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_FIELD \
++      (_MK_FIELD_CONST(0x1f, CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT))
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_RANGE                              (4:0)
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_WOFFSET                            (0x0)
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_DEFAULT_MASK      (_MK_MASK_CONST(0x1f))
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CACC_D_OUT_SATURATION_0
++#define CACC_D_OUT_SATURATION_0                         (_MK_ADDR_CONST(0x9030))
++#define CACC_D_OUT_SATURATION_0_SECURE                                     (0x0)
++#define CACC_D_OUT_SATURATION_0_DUAL                                       (0x0)
++#define CACC_D_OUT_SATURATION_0_SCR                                          (0)
++#define CACC_D_OUT_SATURATION_0_WORD_COUNT                                 (0x1)
++#define CACC_D_OUT_SATURATION_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CACC_D_OUT_SATURATION_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
++#define CACC_D_OUT_SATURATION_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CACC_D_OUT_SATURATION_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CACC_D_OUT_SATURATION_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CACC_D_OUT_SATURATION_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT             (_MK_SHIFT_CONST(0))
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT))
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_RANGE                           (31:0)
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_WOFFSET                          (0x0)
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CACC_D_CYA_0
++#define CACC_D_CYA_0                                    (_MK_ADDR_CONST(0x9034))
++#define CACC_D_CYA_0_SECURE                                                (0x0)
++#define CACC_D_CYA_0_DUAL                                                  (0x0)
++#define CACC_D_CYA_0_SCR                                                     (0)
++#define CACC_D_CYA_0_WORD_COUNT                                            (0x1)
++#define CACC_D_CYA_0_RESET_VAL                             (_MK_MASK_CONST(0x0))
++#define CACC_D_CYA_0_RESET_MASK                     (_MK_MASK_CONST(0xffffffff))
++#define CACC_D_CYA_0_SW_DEFAULT_VAL                        (_MK_MASK_CONST(0x0))
++#define CACC_D_CYA_0_SW_DEFAULT_MASK                       (_MK_MASK_CONST(0x0))
++#define CACC_D_CYA_0_READ_MASK                      (_MK_MASK_CONST(0xffffffff))
++#define CACC_D_CYA_0_WRITE_MASK                     (_MK_MASK_CONST(0xffffffff))
++#define CACC_D_CYA_0_CYA_SHIFT                              (_MK_SHIFT_CONST(0))
++#define CACC_D_CYA_0_CYA_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, CACC_D_CYA_0_CYA_SHIFT))
++#define CACC_D_CYA_0_CYA_RANGE                                            (31:0)
++#define CACC_D_CYA_0_CYA_WOFFSET                                           (0x0)
++#define CACC_D_CYA_0_CYA_DEFAULT                           (_MK_MASK_CONST(0x0))
++#define CACC_D_CYA_0_CYA_DEFAULT_MASK               (_MK_MASK_CONST(0xffffffff))
++#define CACC_D_CYA_0_CYA_SW_DEFAULT                        (_MK_MASK_CONST(0x0))
++#define CACC_D_CYA_0_CYA_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define CACC_D_CYA_0_CYA_PARITY_PROTECTION                 (_MK_MASK_CONST(0x0))
++#define CACC_D_CYA_0_CYA_PLATFORM_DEPENDENT                (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_S_STATUS_0
++#define SDP_RDMA_S_STATUS_0                             (_MK_ADDR_CONST(0xa000))
++#define SDP_RDMA_S_STATUS_0_SECURE                                         (0x0)
++#define SDP_RDMA_S_STATUS_0_DUAL                                           (0x0)
++#define SDP_RDMA_S_STATUS_0_SCR                                              (0)
++#define SDP_RDMA_S_STATUS_0_WORD_COUNT                                     (0x1)
++#define SDP_RDMA_S_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_RESET_MASK                 (_MK_MASK_CONST(0x30003))
++#define SDP_RDMA_S_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_READ_MASK                  (_MK_MASK_CONST(0x30003))
++#define SDP_RDMA_S_STATUS_0_WRITE_MASK                     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                  (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_RANGE                                 (1:0)
++#define SDP_RDMA_S_STATUS_0_STATUS_0_WOFFSET                               (0x0)
++#define SDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT               (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_INIT_ENUM                            (IDLE)
++#define SDP_RDMA_S_STATUS_0_STATUS_0_IDLE                    (_MK_ENUM_CONST(0))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                 (_MK_ENUM_CONST(1))
++#define SDP_RDMA_S_STATUS_0_STATUS_0_PENDING                 (_MK_ENUM_CONST(2))
++
++#define SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                 (_MK_SHIFT_CONST(16))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_RANGE                               (17:16)
++#define SDP_RDMA_S_STATUS_0_STATUS_1_WOFFSET                               (0x0)
++#define SDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT               (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_INIT_ENUM                            (IDLE)
++#define SDP_RDMA_S_STATUS_0_STATUS_1_IDLE                    (_MK_ENUM_CONST(0))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                 (_MK_ENUM_CONST(1))
++#define SDP_RDMA_S_STATUS_0_STATUS_1_PENDING                 (_MK_ENUM_CONST(2))
++
++
++// Register SDP_RDMA_S_POINTER_0
++#define SDP_RDMA_S_POINTER_0                            (_MK_ADDR_CONST(0xa004))
++#define SDP_RDMA_S_POINTER_0_SECURE                                        (0x0)
++#define SDP_RDMA_S_POINTER_0_DUAL                                          (0x0)
++#define SDP_RDMA_S_POINTER_0_SCR                                             (0)
++#define SDP_RDMA_S_POINTER_0_WORD_COUNT                                    (0x1)
++#define SDP_RDMA_S_POINTER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
++#define SDP_RDMA_S_POINTER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
++#define SDP_RDMA_S_POINTER_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                 (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_RANGE                                (0:0)
++#define SDP_RDMA_S_POINTER_0_PRODUCER_WOFFSET                              (0x0)
++#define SDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_INIT_ENUM                        (GROUP_0)
++#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                (_MK_ENUM_CONST(0))
++#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                (_MK_SHIFT_CONST(16))
++#define SDP_RDMA_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT))
++#define SDP_RDMA_S_POINTER_0_CONSUMER_RANGE                              (16:16)
++#define SDP_RDMA_S_POINTER_0_CONSUMER_WOFFSET                              (0x0)
++#define SDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_S_POINTER_0_CONSUMER_INIT_ENUM                        (GROUP_0)
++#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                (_MK_ENUM_CONST(0))
++#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                (_MK_ENUM_CONST(1))
++
++
++// Register SDP_RDMA_D_OP_ENABLE_0
++#define SDP_RDMA_D_OP_ENABLE_0                          (_MK_ADDR_CONST(0xa008))
++#define SDP_RDMA_D_OP_ENABLE_0_SECURE                                      (0x0)
++#define SDP_RDMA_D_OP_ENABLE_0_DUAL                                        (0x0)
++#define SDP_RDMA_D_OP_ENABLE_0_SCR                                           (0)
++#define SDP_RDMA_D_OP_ENABLE_0_WORD_COUNT                                  (0x1)
++#define SDP_RDMA_D_OP_ENABLE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_OP_ENABLE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_OP_ENABLE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_OP_ENABLE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                  (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_RANGE                                 (0:0)
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                               (0x0)
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT               (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                         (DISABLE)
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                 (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                  (_MK_ENUM_CONST(1))
++
++
++// Register SDP_RDMA_D_DATA_CUBE_WIDTH_0
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0                    (_MK_ADDR_CONST(0xa00c))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SECURE                                (0x0)
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_DUAL                                  (0x0)
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SCR                                     (0)
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WORD_COUNT                            (0x1)
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT            (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_RANGE                          (12:0)
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_WOFFSET                         (0x0)
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_DATA_CUBE_HEIGHT_0
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0                   (_MK_ADDR_CONST(0xa010))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SECURE                               (0x0)
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_DUAL                                 (0x0)
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SCR                                    (0)
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_WORD_COUNT                           (0x1)
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT          (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_RANGE                        (12:0)
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_WOFFSET                       (0x0)
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_DATA_CUBE_CHANNEL_0
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0                  (_MK_ADDR_CONST(0xa014))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SECURE                              (0x0)
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_DUAL                                (0x0)
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SCR                                   (0)
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_WORD_COUNT                          (0x1)
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_MASK       (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_READ_MASK        (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_WRITE_MASK       (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_RANGE                      (12:0)
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_WOFFSET                     (0x0)
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_SRC_BASE_ADDR_LOW_0
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0                  (_MK_ADDR_CONST(0xa018))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SECURE                              (0x0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_DUAL                                (0x0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SCR                                   (0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                          (0x1)
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE            (31:5)
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET           (0x0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                 (_MK_ADDR_CONST(0xa01c))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SECURE                             (0x0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_DUAL                               (0x0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SCR                                  (0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                         (0x1)
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE          (31:0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET         (0x0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_SRC_LINE_STRIDE_0
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0                    (_MK_ADDR_CONST(0xa020))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SECURE                                (0x0)
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_DUAL                                  (0x0)
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SCR                                     (0)
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_WORD_COUNT                            (0x1)
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                (31:5)
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET               (0x0)
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_SRC_SURFACE_STRIDE_0
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0                 (_MK_ADDR_CONST(0xa024))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SECURE                             (0x0)
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_DUAL                               (0x0)
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SCR                                  (0)
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                         (0x1)
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE          (31:5)
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET         (0x0)
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_BRDMA_CFG_0
++#define SDP_RDMA_D_BRDMA_CFG_0                          (_MK_ADDR_CONST(0xa028))
++#define SDP_RDMA_D_BRDMA_CFG_0_SECURE                                      (0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_DUAL                                        (0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_SCR                                           (0)
++#define SDP_RDMA_D_BRDMA_CFG_0_WORD_COUNT                                  (0x1)
++#define SDP_RDMA_D_BRDMA_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
++#define SDP_RDMA_D_BRDMA_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
++#define SDP_RDMA_D_BRDMA_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT          (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_RANGE                         (0:0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_WOFFSET                       (0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_NO              (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_YES             (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT         (_MK_SHIFT_CONST(1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_RANGE                        (2:1)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_WOFFSET                      (0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_MUL            (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_ALU            (_MK_ENUM_CONST(1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_BOTH           (_MK_ENUM_CONST(2))
++
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT        (_MK_SHIFT_CONST(3))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_RANGE                       (3:3)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_WOFFSET                     (0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_ONE_BYTE      (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_TWO_BYTE      (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT        (_MK_SHIFT_CONST(4))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_RANGE                       (4:4)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_WOFFSET                     (0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_KERNEL    (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_ELEMENT \
++      (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_RANGE                        (5:5)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_WOFFSET                      (0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
++
++
++// Register SDP_RDMA_D_BS_BASE_ADDR_LOW_0
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0                   (_MK_ADDR_CONST(0xa02c))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SECURE                               (0x0)
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_DUAL                                 (0x0)
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SCR                                    (0)
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_WORD_COUNT                           (0x1)
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_RESET_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_READ_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_WRITE_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_RANGE              (31:5)
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_WOFFSET             (0x0)
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_BS_BASE_ADDR_HIGH_0
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0                  (_MK_ADDR_CONST(0xa030))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SECURE                              (0x0)
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_DUAL                                (0x0)
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SCR                                   (0)
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_WORD_COUNT                          (0x1)
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_RANGE            (31:0)
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_WOFFSET           (0x0)
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_BS_LINE_STRIDE_0
++#define SDP_RDMA_D_BS_LINE_STRIDE_0                     (_MK_ADDR_CONST(0xa034))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_SECURE                                 (0x0)
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_DUAL                                   (0x0)
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_SCR                                      (0)
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_WORD_COUNT                             (0x1)
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT    (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_RANGE                  (31:5)
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_WOFFSET                 (0x0)
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_BS_SURFACE_STRIDE_0
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0                  (_MK_ADDR_CONST(0xa038))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SECURE                              (0x0)
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_DUAL                                (0x0)
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SCR                                   (0)
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_WORD_COUNT                          (0x1)
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_RANGE            (31:5)
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_WOFFSET           (0x0)
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_BS_BATCH_STRIDE_0
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0                    (_MK_ADDR_CONST(0xa03c))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SECURE                                (0x0)
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_DUAL                                  (0x0)
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SCR                                     (0)
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_WORD_COUNT                            (0x1)
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_RANGE                (31:5)
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_WOFFSET               (0x0)
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_NRDMA_CFG_0
++#define SDP_RDMA_D_NRDMA_CFG_0                          (_MK_ADDR_CONST(0xa040))
++#define SDP_RDMA_D_NRDMA_CFG_0_SECURE                                      (0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_DUAL                                        (0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_SCR                                           (0)
++#define SDP_RDMA_D_NRDMA_CFG_0_WORD_COUNT                                  (0x1)
++#define SDP_RDMA_D_NRDMA_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
++#define SDP_RDMA_D_NRDMA_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
++#define SDP_RDMA_D_NRDMA_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT          (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_RANGE                         (0:0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_WOFFSET                       (0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_NO              (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_YES             (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT         (_MK_SHIFT_CONST(1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_RANGE                        (2:1)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_WOFFSET                      (0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_MUL            (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_ALU            (_MK_ENUM_CONST(1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_BOTH           (_MK_ENUM_CONST(2))
++
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT        (_MK_SHIFT_CONST(3))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_RANGE                       (3:3)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_WOFFSET                     (0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_ONE_BYTE      (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_TWO_BYTE      (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT        (_MK_SHIFT_CONST(4))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_RANGE                       (4:4)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_WOFFSET                     (0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_KERNEL    (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_ELEMENT \
++      (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_RANGE                        (5:5)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_WOFFSET                      (0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
++
++
++// Register SDP_RDMA_D_BN_BASE_ADDR_LOW_0
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0                   (_MK_ADDR_CONST(0xa044))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SECURE                               (0x0)
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_DUAL                                 (0x0)
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SCR                                    (0)
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_WORD_COUNT                           (0x1)
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_RESET_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_READ_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_WRITE_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_RANGE              (31:5)
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_WOFFSET             (0x0)
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_BN_BASE_ADDR_HIGH_0
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0                  (_MK_ADDR_CONST(0xa048))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SECURE                              (0x0)
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_DUAL                                (0x0)
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SCR                                   (0)
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_WORD_COUNT                          (0x1)
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_RANGE            (31:0)
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_WOFFSET           (0x0)
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_BN_LINE_STRIDE_0
++#define SDP_RDMA_D_BN_LINE_STRIDE_0                     (_MK_ADDR_CONST(0xa04c))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_SECURE                                 (0x0)
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_DUAL                                   (0x0)
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_SCR                                      (0)
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_WORD_COUNT                             (0x1)
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT    (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_RANGE                  (31:5)
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_WOFFSET                 (0x0)
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_BN_SURFACE_STRIDE_0
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0                  (_MK_ADDR_CONST(0xa050))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SECURE                              (0x0)
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_DUAL                                (0x0)
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SCR                                   (0)
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_WORD_COUNT                          (0x1)
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_RANGE            (31:5)
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_WOFFSET           (0x0)
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_BN_BATCH_STRIDE_0
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0                    (_MK_ADDR_CONST(0xa054))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SECURE                                (0x0)
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_DUAL                                  (0x0)
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SCR                                     (0)
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_WORD_COUNT                            (0x1)
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_RANGE                (31:5)
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_WOFFSET               (0x0)
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_ERDMA_CFG_0
++#define SDP_RDMA_D_ERDMA_CFG_0                          (_MK_ADDR_CONST(0xa058))
++#define SDP_RDMA_D_ERDMA_CFG_0_SECURE                                      (0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_DUAL                                        (0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_SCR                                           (0)
++#define SDP_RDMA_D_ERDMA_CFG_0_WORD_COUNT                                  (0x1)
++#define SDP_RDMA_D_ERDMA_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
++#define SDP_RDMA_D_ERDMA_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
++#define SDP_RDMA_D_ERDMA_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT          (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_RANGE                         (0:0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_WOFFSET                       (0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_NO              (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_YES             (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT         (_MK_SHIFT_CONST(1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_RANGE                        (2:1)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_WOFFSET                      (0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_MUL            (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_ALU            (_MK_ENUM_CONST(1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_BOTH           (_MK_ENUM_CONST(2))
++
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT        (_MK_SHIFT_CONST(3))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_RANGE                       (3:3)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_WOFFSET                     (0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_ONE_BYTE      (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_TWO_BYTE      (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT        (_MK_SHIFT_CONST(4))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_RANGE                       (4:4)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_WOFFSET                     (0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_KERNEL    (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_ELEMENT \
++      (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_RANGE                        (5:5)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_WOFFSET                      (0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
++
++
++// Register SDP_RDMA_D_EW_BASE_ADDR_LOW_0
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0                   (_MK_ADDR_CONST(0xa05c))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SECURE                               (0x0)
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_DUAL                                 (0x0)
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SCR                                    (0)
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_WORD_COUNT                           (0x1)
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_RESET_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_READ_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_WRITE_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_RANGE              (31:5)
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_WOFFSET             (0x0)
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_EW_BASE_ADDR_HIGH_0
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0                  (_MK_ADDR_CONST(0xa060))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SECURE                              (0x0)
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_DUAL                                (0x0)
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SCR                                   (0)
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_WORD_COUNT                          (0x1)
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_RANGE            (31:0)
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_WOFFSET           (0x0)
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_EW_LINE_STRIDE_0
++#define SDP_RDMA_D_EW_LINE_STRIDE_0                     (_MK_ADDR_CONST(0xa064))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_SECURE                                 (0x0)
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_DUAL                                   (0x0)
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_SCR                                      (0)
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_WORD_COUNT                             (0x1)
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT    (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_RANGE                  (31:5)
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_WOFFSET                 (0x0)
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_EW_SURFACE_STRIDE_0
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0                  (_MK_ADDR_CONST(0xa068))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SECURE                              (0x0)
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_DUAL                                (0x0)
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SCR                                   (0)
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_WORD_COUNT                          (0x1)
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_RANGE            (31:5)
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_WOFFSET           (0x0)
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_EW_BATCH_STRIDE_0
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0                    (_MK_ADDR_CONST(0xa06c))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SECURE                                (0x0)
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_DUAL                                  (0x0)
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SCR                                     (0)
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_WORD_COUNT                            (0x1)
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_RANGE                (31:5)
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_WOFFSET               (0x0)
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_FEATURE_MODE_CFG_0
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0                   (_MK_ADDR_CONST(0xa070))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SECURE                               (0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_DUAL                                 (0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SCR                                    (0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WORD_COUNT                           (0x1)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_RESET_VAL           (_MK_MASK_CONST(0x14))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT     (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_RANGE                    (0:0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_WOFFSET                  (0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF        (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON         (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT        (_MK_SHIFT_CONST(1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_RANGE                       (1:1)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_WOFFSET                     (0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF           (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_ON            (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT    (_MK_SHIFT_CONST(2))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, \
++      SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_RANGE                   (3:2)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_WOFFSET                 (0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_DEFAULT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT8      (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT16     (_MK_ENUM_CONST(1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FP16      (_MK_ENUM_CONST(2))
++
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT \
++      (_MK_SHIFT_CONST(4))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, \
++      SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_RANGE                 (5:4)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_WOFFSET               (0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_DEFAULT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT8    (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT16 \
++      (_MK_ENUM_CONST(1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FP16    (_MK_ENUM_CONST(2))
++
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT \
++      (_MK_SHIFT_CONST(6))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, \
++      SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_RANGE                  (7:6)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_WOFFSET                (0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT8     (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT16    (_MK_ENUM_CONST(1))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FP16     (_MK_ENUM_CONST(2))
++
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT    (_MK_SHIFT_CONST(8))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_RANGE                  (12:8)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_WOFFSET                 (0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_SRC_DMA_CFG_0
++#define SDP_RDMA_D_SRC_DMA_CFG_0                        (_MK_ADDR_CONST(0xa074))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SECURE                                    (0x0)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_DUAL                                      (0x0)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SCR                                         (0)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_WORD_COUNT                                (0x1)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_RANGE                        (0:0)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_WOFFSET                      (0x0)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
++
++
++// Register SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0               (_MK_ADDR_CONST(0xa078))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SECURE                           (0x0)
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_DUAL                             (0x0)
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SCR                                (0)
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_WORD_COUNT                       (0x1)
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_RESET_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_WRITE_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_RANGE      (31:0)
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_WOFFSET     (0x0)
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_STATUS_INF_INPUT_NUM_0
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0               (_MK_ADDR_CONST(0xa07c))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SECURE                           (0x0)
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_DUAL                             (0x0)
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SCR                                (0)
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_WORD_COUNT                       (0x1)
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_RESET_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_WRITE_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_RANGE      (31:0)
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_WOFFSET     (0x0)
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_PERF_ENABLE_0
++#define SDP_RDMA_D_PERF_ENABLE_0                        (_MK_ADDR_CONST(0xa080))
++#define SDP_RDMA_D_PERF_ENABLE_0_SECURE                                    (0x0)
++#define SDP_RDMA_D_PERF_ENABLE_0_DUAL                                      (0x0)
++#define SDP_RDMA_D_PERF_ENABLE_0_SCR                                         (0)
++#define SDP_RDMA_D_PERF_ENABLE_0_WORD_COUNT                                (0x1)
++#define SDP_RDMA_D_PERF_ENABLE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_RESET_MASK                (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_READ_MASK                 (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_D_PERF_ENABLE_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT          (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_RANGE                         (0:0)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_WOFFSET                       (0x0)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_INIT_ENUM                      (NO)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_NO              (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_YES             (_MK_ENUM_CONST(1))
++
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT \
++      (_MK_SHIFT_CONST(1))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_RANGE               (1:1)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_WOFFSET             (0x0)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_INIT_ENUM            (NO)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO    (_MK_ENUM_CONST(0))
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES \
++      (_MK_ENUM_CONST(1))
++
++
++// Register SDP_RDMA_D_PERF_MRDMA_READ_STALL_0
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa084))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SECURE                          (0x0)
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_DUAL                            (0x0)
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SCR                               (0)
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_WORD_COUNT                      (0x1)
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_RANGE              (31:0)
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_WOFFSET             (0x0)
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_PERF_BRDMA_READ_STALL_0
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa088))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SECURE                          (0x0)
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_DUAL                            (0x0)
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SCR                               (0)
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_WORD_COUNT                      (0x1)
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_RANGE              (31:0)
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_WOFFSET             (0x0)
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_PERF_NRDMA_READ_STALL_0
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa08c))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SECURE                          (0x0)
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_DUAL                            (0x0)
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SCR                               (0)
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_WORD_COUNT                      (0x1)
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_RANGE              (31:0)
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_WOFFSET             (0x0)
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_RDMA_D_PERF_ERDMA_READ_STALL_0
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa090))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SECURE                          (0x0)
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_DUAL                            (0x0)
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SCR                               (0)
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_WORD_COUNT                      (0x1)
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_RANGE              (31:0)
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_WOFFSET             (0x0)
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_STATUS_0
++#define SDP_S_STATUS_0                                  (_MK_ADDR_CONST(0xb000))
++#define SDP_S_STATUS_0_SECURE                                              (0x0)
++#define SDP_S_STATUS_0_DUAL                                                (0x0)
++#define SDP_S_STATUS_0_SCR                                                   (0)
++#define SDP_S_STATUS_0_WORD_COUNT                                          (0x1)
++#define SDP_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
++#define SDP_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
++#define SDP_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
++#define SDP_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_0_SHIFT))
++#define SDP_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
++#define SDP_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
++#define SDP_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define SDP_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define SDP_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
++#define SDP_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
++#define SDP_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
++#define SDP_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
++
++#define SDP_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
++#define SDP_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_1_SHIFT))
++#define SDP_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
++#define SDP_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
++#define SDP_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define SDP_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define SDP_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define SDP_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
++#define SDP_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
++#define SDP_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
++#define SDP_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
++
++
++// Register SDP_S_POINTER_0
++#define SDP_S_POINTER_0                                 (_MK_ADDR_CONST(0xb004))
++#define SDP_S_POINTER_0_SECURE                                             (0x0)
++#define SDP_S_POINTER_0_DUAL                                               (0x0)
++#define SDP_S_POINTER_0_SCR                                                  (0)
++#define SDP_S_POINTER_0_WORD_COUNT                                         (0x1)
++#define SDP_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
++#define SDP_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
++#define SDP_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
++#define SDP_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
++#define SDP_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_S_POINTER_0_PRODUCER_SHIFT))
++#define SDP_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
++#define SDP_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
++#define SDP_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define SDP_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define SDP_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
++#define SDP_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define SDP_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++#define SDP_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
++#define SDP_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_S_POINTER_0_CONSUMER_SHIFT))
++#define SDP_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
++#define SDP_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
++#define SDP_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define SDP_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define SDP_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define SDP_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
++#define SDP_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define SDP_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++
++// Register SDP_S_LUT_ACCESS_CFG_0
++#define SDP_S_LUT_ACCESS_CFG_0                          (_MK_ADDR_CONST(0xb008))
++#define SDP_S_LUT_ACCESS_CFG_0_SECURE                                      (0x0)
++#define SDP_S_LUT_ACCESS_CFG_0_DUAL                                        (0x0)
++#define SDP_S_LUT_ACCESS_CFG_0_SCR                                           (0)
++#define SDP_S_LUT_ACCESS_CFG_0_WORD_COUNT                                  (0x1)
++#define SDP_S_LUT_ACCESS_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_RESET_MASK              (_MK_MASK_CONST(0x303ff))
++#define SDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_READ_MASK               (_MK_MASK_CONST(0x303ff))
++#define SDP_S_LUT_ACCESS_CFG_0_WRITE_MASK              (_MK_MASK_CONST(0x303ff))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT               (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD \
++      (_MK_FIELD_CONST(0x3ff, SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_RANGE                              (9:0)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_WOFFSET                            (0x0)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT_MASK     (_MK_MASK_CONST(0x3ff))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT          (_MK_SHIFT_CONST(16))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_RANGE                        (16:16)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_WOFFSET                        (0x0)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_INIT_ENUM                       (LE)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE               (_MK_ENUM_CONST(0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO               (_MK_ENUM_CONST(1))
++
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT       (_MK_SHIFT_CONST(17))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_RANGE                     (17:17)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WOFFSET                     (0x0)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_INIT_ENUM                  (READ)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ          (_MK_ENUM_CONST(0))
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE         (_MK_ENUM_CONST(1))
++
++
++// Register SDP_S_LUT_ACCESS_DATA_0
++#define SDP_S_LUT_ACCESS_DATA_0                         (_MK_ADDR_CONST(0xb00c))
++#define SDP_S_LUT_ACCESS_DATA_0_SECURE                                     (0x0)
++#define SDP_S_LUT_ACCESS_DATA_0_DUAL                                       (0x0)
++#define SDP_S_LUT_ACCESS_DATA_0_SCR                                          (0)
++#define SDP_S_LUT_ACCESS_DATA_0_WORD_COUNT                                 (0x1)
++#define SDP_S_LUT_ACCESS_DATA_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_DATA_0_RESET_MASK              (_MK_MASK_CONST(0xffff))
++#define SDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_DATA_0_READ_MASK               (_MK_MASK_CONST(0xffff))
++#define SDP_S_LUT_ACCESS_DATA_0_WRITE_MASK              (_MK_MASK_CONST(0xffff))
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD \
++      (_MK_FIELD_CONST(0xffff, SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT))
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_RANGE                            (15:0)
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_WOFFSET                           (0x0)
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_LUT_CFG_0
++#define SDP_S_LUT_CFG_0                                 (_MK_ADDR_CONST(0xb010))
++#define SDP_S_LUT_CFG_0_SECURE                                             (0x0)
++#define SDP_S_LUT_CFG_0_DUAL                                               (0x0)
++#define SDP_S_LUT_CFG_0_SCR                                                  (0)
++#define SDP_S_LUT_CFG_0_WORD_COUNT                                         (0x1)
++#define SDP_S_LUT_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_RESET_MASK                        (_MK_MASK_CONST(0x71))
++#define SDP_S_LUT_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_READ_MASK                         (_MK_MASK_CONST(0x71))
++#define SDP_S_LUT_CFG_0_WRITE_MASK                        (_MK_MASK_CONST(0x71))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT               (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_RANGE                              (0:0)
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_WOFFSET                            (0x0)
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_INIT_ENUM                     (EXPONENT)
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT             (_MK_ENUM_CONST(0))
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR               (_MK_ENUM_CONST(1))
++
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(4))
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT))
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_RANGE                           (4:4)
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_WOFFSET                         (0x0)
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
++
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(5))
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT))
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_RANGE                           (5:5)
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_WOFFSET                         (0x0)
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
++
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT           (_MK_SHIFT_CONST(6))
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT))
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_RANGE                          (6:6)
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_WOFFSET                        (0x0)
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE               (_MK_ENUM_CONST(0))
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO               (_MK_ENUM_CONST(1))
++
++
++// Register SDP_S_LUT_INFO_0
++#define SDP_S_LUT_INFO_0                                (_MK_ADDR_CONST(0xb014))
++#define SDP_S_LUT_INFO_0_SECURE                                            (0x0)
++#define SDP_S_LUT_INFO_0_DUAL                                              (0x0)
++#define SDP_S_LUT_INFO_0_SCR                                                 (0)
++#define SDP_S_LUT_INFO_0_WORD_COUNT                                        (0x1)
++#define SDP_S_LUT_INFO_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_RESET_MASK                   (_MK_MASK_CONST(0xffffff))
++#define SDP_S_LUT_INFO_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_READ_MASK                    (_MK_MASK_CONST(0xffffff))
++#define SDP_S_LUT_INFO_0_WRITE_MASK                   (_MK_MASK_CONST(0xffffff))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT          (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_RANGE                         (7:0)
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_WOFFSET                       (0x0)
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT          (_MK_SHIFT_CONST(8))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD \
++      (_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_RANGE                        (15:8)
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_WOFFSET                       (0x0)
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT         (_MK_SHIFT_CONST(16))
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD \
++      (_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT))
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_RANGE                       (23:16)
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_WOFFSET                       (0x0)
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_LUT_LE_START_0
++#define SDP_S_LUT_LE_START_0                            (_MK_ADDR_CONST(0xb018))
++#define SDP_S_LUT_LE_START_0_SECURE                                        (0x0)
++#define SDP_S_LUT_LE_START_0_DUAL                                          (0x0)
++#define SDP_S_LUT_LE_START_0_SCR                                             (0)
++#define SDP_S_LUT_LE_START_0_WORD_COUNT                                    (0x1)
++#define SDP_S_LUT_LE_START_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_START_0_RESET_MASK             (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_START_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_START_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_START_0_READ_MASK              (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_START_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT             (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT))
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_RANGE                           (31:0)
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_WOFFSET                          (0x0)
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_DEFAULT          (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_LUT_LE_END_0
++#define SDP_S_LUT_LE_END_0                              (_MK_ADDR_CONST(0xb01c))
++#define SDP_S_LUT_LE_END_0_SECURE                                          (0x0)
++#define SDP_S_LUT_LE_END_0_DUAL                                            (0x0)
++#define SDP_S_LUT_LE_END_0_SCR                                               (0)
++#define SDP_S_LUT_LE_END_0_WORD_COUNT                                      (0x1)
++#define SDP_S_LUT_LE_END_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_END_0_RESET_MASK               (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_END_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_END_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_END_0_READ_MASK                (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_END_0_WRITE_MASK               (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT                 (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT))
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_RANGE                               (31:0)
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_WOFFSET                              (0x0)
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_LUT_LO_START_0
++#define SDP_S_LUT_LO_START_0                            (_MK_ADDR_CONST(0xb020))
++#define SDP_S_LUT_LO_START_0_SECURE                                        (0x0)
++#define SDP_S_LUT_LO_START_0_DUAL                                          (0x0)
++#define SDP_S_LUT_LO_START_0_SCR                                             (0)
++#define SDP_S_LUT_LO_START_0_WORD_COUNT                                    (0x1)
++#define SDP_S_LUT_LO_START_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_START_0_RESET_MASK             (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_START_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_START_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_START_0_READ_MASK              (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_START_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT             (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT))
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_RANGE                           (31:0)
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_WOFFSET                          (0x0)
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_DEFAULT          (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_LUT_LO_END_0
++#define SDP_S_LUT_LO_END_0                              (_MK_ADDR_CONST(0xb024))
++#define SDP_S_LUT_LO_END_0_SECURE                                          (0x0)
++#define SDP_S_LUT_LO_END_0_DUAL                                            (0x0)
++#define SDP_S_LUT_LO_END_0_SCR                                               (0)
++#define SDP_S_LUT_LO_END_0_WORD_COUNT                                      (0x1)
++#define SDP_S_LUT_LO_END_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_END_0_RESET_MASK               (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_END_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_END_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_END_0_READ_MASK                (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_END_0_WRITE_MASK               (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT                 (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT))
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_RANGE                               (31:0)
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_WOFFSET                              (0x0)
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_LUT_LE_SLOPE_SCALE_0
++#define SDP_S_LUT_LE_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xb028))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_SECURE                                  (0x0)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_DUAL                                    (0x0)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_SCR                                       (0)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_RANGE         (15:0)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(16))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_RANGE        (31:16)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_LUT_LE_SLOPE_SHIFT_0
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xb02c))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SECURE                                  (0x0)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_DUAL                                    (0x0)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SCR                                       (0)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_LUT_LO_SLOPE_SCALE_0
++#define SDP_S_LUT_LO_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xb030))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_SECURE                                  (0x0)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_DUAL                                    (0x0)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_SCR                                       (0)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_RANGE         (15:0)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(16))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_RANGE        (31:16)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_S_LUT_LO_SLOPE_SHIFT_0
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xb034))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SECURE                                  (0x0)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_DUAL                                    (0x0)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SCR                                       (0)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_OP_ENABLE_0
++#define SDP_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0xb038))
++#define SDP_D_OP_ENABLE_0_SECURE                                           (0x0)
++#define SDP_D_OP_ENABLE_0_DUAL                                             (0x0)
++#define SDP_D_OP_ENABLE_0_SCR                                                (0)
++#define SDP_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
++#define SDP_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define SDP_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
++#define SDP_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define SDP_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
++#define SDP_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
++#define SDP_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
++#define SDP_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define SDP_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
++#define SDP_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
++#define SDP_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define SDP_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
++#define SDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define SDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define SDP_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define SDP_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
++#define SDP_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
++#define SDP_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
++
++
++// Register SDP_D_DATA_CUBE_WIDTH_0
++#define SDP_D_DATA_CUBE_WIDTH_0                         (_MK_ADDR_CONST(0xb03c))
++#define SDP_D_DATA_CUBE_WIDTH_0_SECURE                                     (0x0)
++#define SDP_D_DATA_CUBE_WIDTH_0_DUAL                                       (0x0)
++#define SDP_D_DATA_CUBE_WIDTH_0_SCR                                          (0)
++#define SDP_D_DATA_CUBE_WIDTH_0_WORD_COUNT                                 (0x1)
++#define SDP_D_DATA_CUBE_WIDTH_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_WIDTH_0_RESET_MASK              (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_WIDTH_0_READ_MASK               (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_WIDTH_0_WRITE_MASK              (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT                 (_MK_SHIFT_CONST(0))
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT))
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_RANGE                               (12:0)
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_WOFFSET                              (0x0)
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT_MASK      (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DATA_CUBE_HEIGHT_0
++#define SDP_D_DATA_CUBE_HEIGHT_0                        (_MK_ADDR_CONST(0xb040))
++#define SDP_D_DATA_CUBE_HEIGHT_0_SECURE                                    (0x0)
++#define SDP_D_DATA_CUBE_HEIGHT_0_DUAL                                      (0x0)
++#define SDP_D_DATA_CUBE_HEIGHT_0_SCR                                         (0)
++#define SDP_D_DATA_CUBE_HEIGHT_0_WORD_COUNT                                (0x1)
++#define SDP_D_DATA_CUBE_HEIGHT_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_HEIGHT_0_RESET_MASK             (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_HEIGHT_0_READ_MASK              (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_HEIGHT_0_WRITE_MASK             (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT               (_MK_SHIFT_CONST(0))
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT))
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_RANGE                             (12:0)
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_WOFFSET                            (0x0)
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT_MASK    (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DATA_CUBE_CHANNEL_0
++#define SDP_D_DATA_CUBE_CHANNEL_0                       (_MK_ADDR_CONST(0xb044))
++#define SDP_D_DATA_CUBE_CHANNEL_0_SECURE                                   (0x0)
++#define SDP_D_DATA_CUBE_CHANNEL_0_DUAL                                     (0x0)
++#define SDP_D_DATA_CUBE_CHANNEL_0_SCR                                        (0)
++#define SDP_D_DATA_CUBE_CHANNEL_0_WORD_COUNT                               (0x1)
++#define SDP_D_DATA_CUBE_CHANNEL_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_CHANNEL_0_RESET_MASK            (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_CHANNEL_0_READ_MASK             (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_CHANNEL_0_WRITE_MASK            (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT             (_MK_SHIFT_CONST(0))
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT))
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_RANGE                           (12:0)
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_WOFFSET                          (0x0)
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT          (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DST_BASE_ADDR_LOW_0
++#define SDP_D_DST_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xb048))
++#define SDP_D_DST_BASE_ADDR_LOW_0_SECURE                                   (0x0)
++#define SDP_D_DST_BASE_ADDR_LOW_0_DUAL                                     (0x0)
++#define SDP_D_DST_BASE_ADDR_LOW_0_SCR                                        (0)
++#define SDP_D_DST_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
++#define SDP_D_DST_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT))
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_RANGE                 (31:5)
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_WOFFSET                (0x0)
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DST_BASE_ADDR_HIGH_0
++#define SDP_D_DST_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xb04c))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
++#define SDP_D_DST_BASE_ADDR_HIGH_0_SCR                                       (0)
++#define SDP_D_DST_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
++#define SDP_D_DST_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_RANGE               (31:0)
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_WOFFSET              (0x0)
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DST_LINE_STRIDE_0
++#define SDP_D_DST_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xb050))
++#define SDP_D_DST_LINE_STRIDE_0_SECURE                                     (0x0)
++#define SDP_D_DST_LINE_STRIDE_0_DUAL                                       (0x0)
++#define SDP_D_DST_LINE_STRIDE_0_SCR                                          (0)
++#define SDP_D_DST_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
++#define SDP_D_DST_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT))
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_RANGE                     (31:5)
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_WOFFSET                    (0x0)
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DST_SURFACE_STRIDE_0
++#define SDP_D_DST_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xb054))
++#define SDP_D_DST_SURFACE_STRIDE_0_SECURE                                  (0x0)
++#define SDP_D_DST_SURFACE_STRIDE_0_DUAL                                    (0x0)
++#define SDP_D_DST_SURFACE_STRIDE_0_SCR                                       (0)
++#define SDP_D_DST_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
++#define SDP_D_DST_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT))
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_RANGE               (31:5)
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_WOFFSET              (0x0)
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_BS_CFG_0
++#define SDP_D_DP_BS_CFG_0                               (_MK_ADDR_CONST(0xb058))
++#define SDP_D_DP_BS_CFG_0_SECURE                                           (0x0)
++#define SDP_D_DP_BS_CFG_0_DUAL                                             (0x0)
++#define SDP_D_DP_BS_CFG_0_SCR                                                (0)
++#define SDP_D_DP_BS_CFG_0_WORD_COUNT                                       (0x1)
++#define SDP_D_DP_BS_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x7f))
++#define SDP_D_DP_BS_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x7f))
++#define SDP_D_DP_BS_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x7f))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT                   (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_RANGE                                  (0:0)
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_WOFFSET                                (0x0)
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_DEFAULT                (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_NO                       (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_YES                      (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT               (_MK_SHIFT_CONST(1))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_RANGE                              (1:1)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_WOFFSET                            (0x0)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_YES                  (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT                 (_MK_SHIFT_CONST(2))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_RANGE                                (3:2)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_WOFFSET                              (0x0)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MAX                    (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MIN                    (_MK_ENUM_CONST(1))
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SUM                    (_MK_ENUM_CONST(2))
++
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT               (_MK_SHIFT_CONST(4))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_RANGE                              (4:4)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_WOFFSET                            (0x0)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_YES                  (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT                (_MK_SHIFT_CONST(5))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_RANGE                               (5:5)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_WOFFSET                             (0x0)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_DEFAULT             (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_NO                    (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_YES                   (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT              (_MK_SHIFT_CONST(6))
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT))
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_RANGE                             (6:6)
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_WOFFSET                           (0x0)
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_NO                  (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_YES                 (_MK_ENUM_CONST(1))
++
++
++// Register SDP_D_DP_BS_ALU_CFG_0
++#define SDP_D_DP_BS_ALU_CFG_0                           (_MK_ADDR_CONST(0xb05c))
++#define SDP_D_DP_BS_ALU_CFG_0_SECURE                                       (0x0)
++#define SDP_D_DP_BS_ALU_CFG_0_DUAL                                         (0x0)
++#define SDP_D_DP_BS_ALU_CFG_0_SCR                                            (0)
++#define SDP_D_DP_BS_ALU_CFG_0_WORD_COUNT                                   (0x1)
++#define SDP_D_DP_BS_ALU_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x3f01))
++#define SDP_D_DP_BS_ALU_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x3f01))
++#define SDP_D_DP_BS_ALU_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x3f01))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_RANGE                             (0:0)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_WOFFSET                           (0x0)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_REG                 (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_MEM                 (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_FIELD \
++      (_MK_FIELD_CONST(0x3f, \
++      SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_RANGE                    (13:8)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_WOFFSET                   (0x0)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_BS_ALU_SRC_VALUE_0
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb060))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SECURE                                 (0x0)
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_DUAL                                   (0x0)
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SCR                                      (0)
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_WORD_COUNT                             (0x1)
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_RANGE                  (15:0)
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_WOFFSET                 (0x0)
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_BS_MUL_CFG_0
++#define SDP_D_DP_BS_MUL_CFG_0                           (_MK_ADDR_CONST(0xb064))
++#define SDP_D_DP_BS_MUL_CFG_0_SECURE                                       (0x0)
++#define SDP_D_DP_BS_MUL_CFG_0_DUAL                                         (0x0)
++#define SDP_D_DP_BS_MUL_CFG_0_SCR                                            (0)
++#define SDP_D_DP_BS_MUL_CFG_0_WORD_COUNT                                   (0x1)
++#define SDP_D_DP_BS_MUL_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_RESET_MASK                (_MK_MASK_CONST(0xff01))
++#define SDP_D_DP_BS_MUL_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_READ_MASK                 (_MK_MASK_CONST(0xff01))
++#define SDP_D_DP_BS_MUL_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0xff01))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_RANGE                             (0:0)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_WOFFSET                           (0x0)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_REG                 (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_MEM                 (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_FIELD \
++      (_MK_FIELD_CONST(0xff, \
++      SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_RANGE                    (15:8)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_WOFFSET                   (0x0)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_BS_MUL_SRC_VALUE_0
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb068))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SECURE                                 (0x0)
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_DUAL                                   (0x0)
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SCR                                      (0)
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_WORD_COUNT                             (0x1)
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_RANGE                  (15:0)
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_WOFFSET                 (0x0)
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_BN_CFG_0
++#define SDP_D_DP_BN_CFG_0                               (_MK_ADDR_CONST(0xb06c))
++#define SDP_D_DP_BN_CFG_0_SECURE                                           (0x0)
++#define SDP_D_DP_BN_CFG_0_DUAL                                             (0x0)
++#define SDP_D_DP_BN_CFG_0_SCR                                                (0)
++#define SDP_D_DP_BN_CFG_0_WORD_COUNT                                       (0x1)
++#define SDP_D_DP_BN_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x7f))
++#define SDP_D_DP_BN_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x7f))
++#define SDP_D_DP_BN_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x7f))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT                   (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_RANGE                                  (0:0)
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_WOFFSET                                (0x0)
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_DEFAULT                (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_NO                       (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_YES                      (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT               (_MK_SHIFT_CONST(1))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_RANGE                              (1:1)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_WOFFSET                            (0x0)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_YES                  (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT                 (_MK_SHIFT_CONST(2))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_RANGE                                (3:2)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_WOFFSET                              (0x0)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MAX                    (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MIN                    (_MK_ENUM_CONST(1))
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SUM                    (_MK_ENUM_CONST(2))
++
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT               (_MK_SHIFT_CONST(4))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_RANGE                              (4:4)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_WOFFSET                            (0x0)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_YES                  (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT                (_MK_SHIFT_CONST(5))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_RANGE                               (5:5)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_WOFFSET                             (0x0)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_DEFAULT             (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_NO                    (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_YES                   (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT              (_MK_SHIFT_CONST(6))
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT))
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_RANGE                             (6:6)
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_WOFFSET                           (0x0)
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_NO                  (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_YES                 (_MK_ENUM_CONST(1))
++
++
++// Register SDP_D_DP_BN_ALU_CFG_0
++#define SDP_D_DP_BN_ALU_CFG_0                           (_MK_ADDR_CONST(0xb070))
++#define SDP_D_DP_BN_ALU_CFG_0_SECURE                                       (0x0)
++#define SDP_D_DP_BN_ALU_CFG_0_DUAL                                         (0x0)
++#define SDP_D_DP_BN_ALU_CFG_0_SCR                                            (0)
++#define SDP_D_DP_BN_ALU_CFG_0_WORD_COUNT                                   (0x1)
++#define SDP_D_DP_BN_ALU_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x3f01))
++#define SDP_D_DP_BN_ALU_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x3f01))
++#define SDP_D_DP_BN_ALU_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x3f01))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_RANGE                             (0:0)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_WOFFSET                           (0x0)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_REG                 (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_MEM                 (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_FIELD \
++      (_MK_FIELD_CONST(0x3f, \
++      SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_RANGE                    (13:8)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_WOFFSET                   (0x0)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_BN_ALU_SRC_VALUE_0
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb074))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SECURE                                 (0x0)
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_DUAL                                   (0x0)
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SCR                                      (0)
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_WORD_COUNT                             (0x1)
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_RANGE                  (15:0)
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_WOFFSET                 (0x0)
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_BN_MUL_CFG_0
++#define SDP_D_DP_BN_MUL_CFG_0                           (_MK_ADDR_CONST(0xb078))
++#define SDP_D_DP_BN_MUL_CFG_0_SECURE                                       (0x0)
++#define SDP_D_DP_BN_MUL_CFG_0_DUAL                                         (0x0)
++#define SDP_D_DP_BN_MUL_CFG_0_SCR                                            (0)
++#define SDP_D_DP_BN_MUL_CFG_0_WORD_COUNT                                   (0x1)
++#define SDP_D_DP_BN_MUL_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_RESET_MASK                (_MK_MASK_CONST(0xff01))
++#define SDP_D_DP_BN_MUL_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_READ_MASK                 (_MK_MASK_CONST(0xff01))
++#define SDP_D_DP_BN_MUL_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0xff01))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_RANGE                             (0:0)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_WOFFSET                           (0x0)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_REG                 (_MK_ENUM_CONST(0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_MEM                 (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_FIELD \
++      (_MK_FIELD_CONST(0xff, \
++      SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_RANGE                    (15:8)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_WOFFSET                   (0x0)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_BN_MUL_SRC_VALUE_0
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb07c))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SECURE                                 (0x0)
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_DUAL                                   (0x0)
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SCR                                      (0)
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_WORD_COUNT                             (0x1)
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_RANGE                  (15:0)
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_WOFFSET                 (0x0)
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_EW_CFG_0
++#define SDP_D_DP_EW_CFG_0                               (_MK_ADDR_CONST(0xb080))
++#define SDP_D_DP_EW_CFG_0_SECURE                                           (0x0)
++#define SDP_D_DP_EW_CFG_0_DUAL                                             (0x0)
++#define SDP_D_DP_EW_CFG_0_SCR                                                (0)
++#define SDP_D_DP_EW_CFG_0_WORD_COUNT                                       (0x1)
++#define SDP_D_DP_EW_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x7f))
++#define SDP_D_DP_EW_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x7f))
++#define SDP_D_DP_EW_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x7f))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT                   (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_RANGE                                  (0:0)
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_WOFFSET                                (0x0)
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_DEFAULT                (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_NO                       (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_YES                      (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT               (_MK_SHIFT_CONST(1))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_RANGE                              (1:1)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_WOFFSET                            (0x0)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_YES                  (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT                 (_MK_SHIFT_CONST(2))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_RANGE                                (3:2)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_WOFFSET                              (0x0)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MAX                    (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MIN                    (_MK_ENUM_CONST(1))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SUM                    (_MK_ENUM_CONST(2))
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_EQL                    (_MK_ENUM_CONST(3))
++
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT               (_MK_SHIFT_CONST(4))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_RANGE                              (4:4)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_WOFFSET                            (0x0)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_YES                  (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT                (_MK_SHIFT_CONST(5))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_RANGE                               (5:5)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_WOFFSET                             (0x0)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_DEFAULT             (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_NO                    (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_YES                   (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT               (_MK_SHIFT_CONST(6))
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT))
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_RANGE                              (6:6)
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_WOFFSET                            (0x0)
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_YES                  (_MK_ENUM_CONST(1))
++
++
++// Register SDP_D_DP_EW_ALU_CFG_0
++#define SDP_D_DP_EW_ALU_CFG_0                           (_MK_ADDR_CONST(0xb084))
++#define SDP_D_DP_EW_ALU_CFG_0_SECURE                                       (0x0)
++#define SDP_D_DP_EW_ALU_CFG_0_DUAL                                         (0x0)
++#define SDP_D_DP_EW_ALU_CFG_0_SCR                                            (0)
++#define SDP_D_DP_EW_ALU_CFG_0_WORD_COUNT                                   (0x1)
++#define SDP_D_DP_EW_ALU_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_RESET_MASK                   (_MK_MASK_CONST(0x3))
++#define SDP_D_DP_EW_ALU_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_READ_MASK                    (_MK_MASK_CONST(0x3))
++#define SDP_D_DP_EW_ALU_CFG_0_WRITE_MASK                   (_MK_MASK_CONST(0x3))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_RANGE                             (0:0)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_WOFFSET                           (0x0)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_REG                 (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_MEM                 (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT       (_MK_SHIFT_CONST(1))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_RANGE                      (1:1)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_WOFFSET                    (0x0)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_NO           (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_YES          (_MK_ENUM_CONST(1))
++
++
++// Register SDP_D_DP_EW_ALU_SRC_VALUE_0
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb088))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SECURE                                 (0x0)
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_DUAL                                   (0x0)
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SCR                                      (0)
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_WORD_COUNT                             (0x1)
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_RANGE                  (31:0)
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_WOFFSET                 (0x0)
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0              (_MK_ADDR_CONST(0xb08c))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SECURE                          (0x0)
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_DUAL                            (0x0)
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SCR                               (0)
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_WORD_COUNT                      (0x1)
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_RESET_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_RANGE        (31:0)
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_WOFFSET       (0x0)
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0               (_MK_ADDR_CONST(0xb090))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SECURE                           (0x0)
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_DUAL                             (0x0)
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SCR                                (0)
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_WORD_COUNT                       (0x1)
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_RESET_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_RESET_MASK    (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_READ_MASK     (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_WRITE_MASK    (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_RANGE          (15:0)
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_WOFFSET         (0x0)
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0            (_MK_ADDR_CONST(0xb094))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SECURE                        (0x0)
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_DUAL                          (0x0)
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SCR                             (0)
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_WORD_COUNT                    (0x1)
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_RESET_VAL     (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_RESET_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_READ_MASK    (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_FIELD \
++      (_MK_FIELD_CONST(0x3f, \
++      SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_RANGE     (5:0)
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_WOFFSET \
++      (0x0)
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_EW_MUL_CFG_0
++#define SDP_D_DP_EW_MUL_CFG_0                           (_MK_ADDR_CONST(0xb098))
++#define SDP_D_DP_EW_MUL_CFG_0_SECURE                                       (0x0)
++#define SDP_D_DP_EW_MUL_CFG_0_DUAL                                         (0x0)
++#define SDP_D_DP_EW_MUL_CFG_0_SCR                                            (0)
++#define SDP_D_DP_EW_MUL_CFG_0_WORD_COUNT                                   (0x1)
++#define SDP_D_DP_EW_MUL_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_RESET_MASK                   (_MK_MASK_CONST(0x3))
++#define SDP_D_DP_EW_MUL_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_READ_MASK                    (_MK_MASK_CONST(0x3))
++#define SDP_D_DP_EW_MUL_CFG_0_WRITE_MASK                   (_MK_MASK_CONST(0x3))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_RANGE                             (0:0)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_WOFFSET                           (0x0)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_REG                 (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_MEM                 (_MK_ENUM_CONST(1))
++
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT       (_MK_SHIFT_CONST(1))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_RANGE                      (1:1)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_WOFFSET                    (0x0)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_NO           (_MK_ENUM_CONST(0))
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_YES          (_MK_ENUM_CONST(1))
++
++
++// Register SDP_D_DP_EW_MUL_SRC_VALUE_0
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb09c))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SECURE                                 (0x0)
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_DUAL                                   (0x0)
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SCR                                      (0)
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_WORD_COUNT                             (0x1)
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_RANGE                  (31:0)
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_WOFFSET                 (0x0)
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0              (_MK_ADDR_CONST(0xb0a0))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SECURE                          (0x0)
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_DUAL                            (0x0)
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SCR                               (0)
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_WORD_COUNT                      (0x1)
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_RESET_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_RANGE        (31:0)
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_WOFFSET       (0x0)
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0               (_MK_ADDR_CONST(0xb0a4))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SECURE                           (0x0)
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_DUAL                             (0x0)
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SCR                                (0)
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_WORD_COUNT                       (0x1)
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_RESET_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_RESET_MASK    (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_READ_MASK     (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_WRITE_MASK    (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_RANGE          (15:0)
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_WOFFSET         (0x0)
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0            (_MK_ADDR_CONST(0xb0a8))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SECURE                        (0x0)
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_DUAL                          (0x0)
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SCR                             (0)
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_WORD_COUNT                    (0x1)
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_RESET_VAL     (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_RESET_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_READ_MASK    (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_FIELD \
++      (_MK_FIELD_CONST(0x3f, \
++      SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_RANGE     (5:0)
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_WOFFSET \
++      (0x0)
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DP_EW_TRUNCATE_VALUE_0
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0                    (_MK_ADDR_CONST(0xb0ac))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SECURE                                (0x0)
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_DUAL                                  (0x0)
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SCR                                     (0)
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_WORD_COUNT                            (0x1)
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0x3ff))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_READ_MASK           (_MK_MASK_CONST(0x3ff))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0x3ff))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT      (_MK_SHIFT_CONST(0))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_RANGE                     (9:0)
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_WOFFSET                   (0x0)
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_FEATURE_MODE_CFG_0
++#define SDP_D_FEATURE_MODE_CFG_0                        (_MK_ADDR_CONST(0xb0b0))
++#define SDP_D_FEATURE_MODE_CFG_0_SECURE                                    (0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_DUAL                                      (0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_SCR                                         (0)
++#define SDP_D_FEATURE_MODE_CFG_0_WORD_COUNT                                (0x1)
++#define SDP_D_FEATURE_MODE_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_RESET_MASK             (_MK_MASK_CONST(0x1f0f))
++#define SDP_D_FEATURE_MODE_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_READ_MASK              (_MK_MASK_CONST(0x1f0f))
++#define SDP_D_FEATURE_MODE_CFG_0_WRITE_MASK             (_MK_MASK_CONST(0x1f0f))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT          (_MK_SHIFT_CONST(0))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_RANGE                         (0:0)
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_WOFFSET                       (0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF             (_MK_ENUM_CONST(0))
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON              (_MK_ENUM_CONST(1))
++
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT           (_MK_SHIFT_CONST(1))
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT))
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_RANGE                          (1:1)
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_WOFFSET                        (0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_MEM              (_MK_ENUM_CONST(0))
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PDP              (_MK_ENUM_CONST(1))
++
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT             (_MK_SHIFT_CONST(2))
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT))
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_RANGE                            (2:2)
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_WOFFSET                          (0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT          (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF                (_MK_ENUM_CONST(0))
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_ON                 (_MK_ENUM_CONST(1))
++
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT          (_MK_SHIFT_CONST(3))
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT))
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_RANGE                         (3:3)
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_WOFFSET                       (0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_INIT_ENUM                 (DISABLE)
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DISABLE         (_MK_ENUM_CONST(0))
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_ENABLE          (_MK_ENUM_CONST(1))
++
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT         (_MK_SHIFT_CONST(8))
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD \
++      (_MK_FIELD_CONST(0x1f, SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT))
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_RANGE                       (12:8)
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_WOFFSET                      (0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DST_DMA_CFG_0
++#define SDP_D_DST_DMA_CFG_0                             (_MK_ADDR_CONST(0xb0b4))
++#define SDP_D_DST_DMA_CFG_0_SECURE                                         (0x0)
++#define SDP_D_DST_DMA_CFG_0_DUAL                                           (0x0)
++#define SDP_D_DST_DMA_CFG_0_SCR                                              (0)
++#define SDP_D_DST_DMA_CFG_0_WORD_COUNT                                     (0x1)
++#define SDP_D_DST_DMA_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_DMA_CFG_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
++#define SDP_D_DST_DMA_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_DMA_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_DMA_CFG_0_READ_MASK                      (_MK_MASK_CONST(0x1))
++#define SDP_D_DST_DMA_CFG_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_RANGE                             (0:0)
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_WOFFSET                           (0x0)
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV                  (_MK_ENUM_CONST(0))
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC                  (_MK_ENUM_CONST(1))
++
++
++// Register SDP_D_DST_BATCH_STRIDE_0
++#define SDP_D_DST_BATCH_STRIDE_0                        (_MK_ADDR_CONST(0xb0b8))
++#define SDP_D_DST_BATCH_STRIDE_0_SECURE                                    (0x0)
++#define SDP_D_DST_BATCH_STRIDE_0_DUAL                                      (0x0)
++#define SDP_D_DST_BATCH_STRIDE_0_SCR                                         (0)
++#define SDP_D_DST_BATCH_STRIDE_0_WORD_COUNT                                (0x1)
++#define SDP_D_DST_BATCH_STRIDE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BATCH_STRIDE_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_BATCH_STRIDE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BATCH_STRIDE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BATCH_STRIDE_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_BATCH_STRIDE_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT     (_MK_SHIFT_CONST(5))
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT))
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_RANGE                   (31:5)
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_WOFFSET                  (0x0)
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_DATA_FORMAT_0
++#define SDP_D_DATA_FORMAT_0                             (_MK_ADDR_CONST(0xb0bc))
++#define SDP_D_DATA_FORMAT_0_SECURE                                         (0x0)
++#define SDP_D_DATA_FORMAT_0_DUAL                                           (0x0)
++#define SDP_D_DATA_FORMAT_0_SCR                                              (0)
++#define SDP_D_DATA_FORMAT_0_WORD_COUNT                                     (0x1)
++#define SDP_D_DATA_FORMAT_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_RESET_MASK                     (_MK_MASK_CONST(0xf))
++#define SDP_D_DATA_FORMAT_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_READ_MASK                      (_MK_MASK_CONST(0xf))
++#define SDP_D_DATA_FORMAT_0_WRITE_MASK                     (_MK_MASK_CONST(0xf))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT            (_MK_SHIFT_CONST(0))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_RANGE                           (1:0)
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_WOFFSET                         (0x0)
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_DEFAULT_MASK    (_MK_MASK_CONST(0x3))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT8              (_MK_ENUM_CONST(0))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT16             (_MK_ENUM_CONST(1))
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FP16              (_MK_ENUM_CONST(2))
++
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT             (_MK_SHIFT_CONST(2))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_RANGE                            (3:2)
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_WOFFSET                          (0x0)
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_DEFAULT          (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_DEFAULT_MASK     (_MK_MASK_CONST(0x3))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT8               (_MK_ENUM_CONST(0))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT16              (_MK_ENUM_CONST(1))
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FP16               (_MK_ENUM_CONST(2))
++
++
++// Register SDP_D_CVT_OFFSET_0
++#define SDP_D_CVT_OFFSET_0                              (_MK_ADDR_CONST(0xb0c0))
++#define SDP_D_CVT_OFFSET_0_SECURE                                          (0x0)
++#define SDP_D_CVT_OFFSET_0_DUAL                                            (0x0)
++#define SDP_D_CVT_OFFSET_0_SCR                                               (0)
++#define SDP_D_CVT_OFFSET_0_WORD_COUNT                                      (0x1)
++#define SDP_D_CVT_OFFSET_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_OFFSET_0_RESET_MASK               (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_CVT_OFFSET_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_OFFSET_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_OFFSET_0_READ_MASK                (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_CVT_OFFSET_0_WRITE_MASK               (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT                 (_MK_SHIFT_CONST(0))
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT))
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_RANGE                               (31:0)
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_WOFFSET                              (0x0)
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_CVT_SCALE_0
++#define SDP_D_CVT_SCALE_0                               (_MK_ADDR_CONST(0xb0c4))
++#define SDP_D_CVT_SCALE_0_SECURE                                           (0x0)
++#define SDP_D_CVT_SCALE_0_DUAL                                             (0x0)
++#define SDP_D_CVT_SCALE_0_SCR                                                (0)
++#define SDP_D_CVT_SCALE_0_WORD_COUNT                                       (0x1)
++#define SDP_D_CVT_SCALE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SCALE_0_RESET_MASK                    (_MK_MASK_CONST(0xffff))
++#define SDP_D_CVT_SCALE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SCALE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SCALE_0_READ_MASK                     (_MK_MASK_CONST(0xffff))
++#define SDP_D_CVT_SCALE_0_WRITE_MASK                    (_MK_MASK_CONST(0xffff))
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT                   (_MK_SHIFT_CONST(0))
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT))
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_RANGE                                 (15:0)
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_WOFFSET                                (0x0)
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_DEFAULT                (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_DEFAULT_MASK        (_MK_MASK_CONST(0xffff))
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_CVT_SHIFT_0
++#define SDP_D_CVT_SHIFT_0                               (_MK_ADDR_CONST(0xb0c8))
++#define SDP_D_CVT_SHIFT_0_SECURE                                           (0x0)
++#define SDP_D_CVT_SHIFT_0_DUAL                                             (0x0)
++#define SDP_D_CVT_SHIFT_0_SCR                                                (0)
++#define SDP_D_CVT_SHIFT_0_WORD_COUNT                                       (0x1)
++#define SDP_D_CVT_SHIFT_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SHIFT_0_RESET_MASK                      (_MK_MASK_CONST(0x3f))
++#define SDP_D_CVT_SHIFT_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SHIFT_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SHIFT_0_READ_MASK                       (_MK_MASK_CONST(0x3f))
++#define SDP_D_CVT_SHIFT_0_WRITE_MASK                      (_MK_MASK_CONST(0x3f))
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT                   (_MK_SHIFT_CONST(0))
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_FIELD \
++      (_MK_FIELD_CONST(0x3f, SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT))
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_RANGE                                  (5:0)
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_WOFFSET                                (0x0)
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_DEFAULT                (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_DEFAULT_MASK          (_MK_MASK_CONST(0x3f))
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_STATUS_0
++#define SDP_D_STATUS_0                                  (_MK_ADDR_CONST(0xb0cc))
++#define SDP_D_STATUS_0_SECURE                                              (0x0)
++#define SDP_D_STATUS_0_DUAL                                                (0x0)
++#define SDP_D_STATUS_0_SCR                                                   (0)
++#define SDP_D_STATUS_0_WORD_COUNT                                          (0x1)
++#define SDP_D_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_0_RESET_MASK                          (_MK_MASK_CONST(0x1))
++#define SDP_D_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_0_READ_MASK                           (_MK_MASK_CONST(0x1))
++#define SDP_D_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT                 (_MK_SHIFT_CONST(0))
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT))
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_RANGE                                (0:0)
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_WOFFSET                              (0x0)
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_DEFAULT              (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_STATUS_NAN_INPUT_NUM_0
++#define SDP_D_STATUS_NAN_INPUT_NUM_0                    (_MK_ADDR_CONST(0xb0d0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_SECURE                                (0x0)
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_DUAL                                  (0x0)
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_SCR                                     (0)
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_WORD_COUNT                            (0x1)
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_RANGE           (31:0)
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_WOFFSET          (0x0)
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_STATUS_INF_INPUT_NUM_0
++#define SDP_D_STATUS_INF_INPUT_NUM_0                    (_MK_ADDR_CONST(0xb0d4))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_SECURE                                (0x0)
++#define SDP_D_STATUS_INF_INPUT_NUM_0_DUAL                                  (0x0)
++#define SDP_D_STATUS_INF_INPUT_NUM_0_SCR                                     (0)
++#define SDP_D_STATUS_INF_INPUT_NUM_0_WORD_COUNT                            (0x1)
++#define SDP_D_STATUS_INF_INPUT_NUM_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_RANGE           (31:0)
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_WOFFSET          (0x0)
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_STATUS_NAN_OUTPUT_NUM_0
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0                   (_MK_ADDR_CONST(0xb0d8))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SECURE                               (0x0)
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_DUAL                                 (0x0)
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SCR                                    (0)
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_WORD_COUNT                           (0x1)
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_RANGE         (31:0)
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_WOFFSET        (0x0)
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_PERF_ENABLE_0
++#define SDP_D_PERF_ENABLE_0                             (_MK_ADDR_CONST(0xb0dc))
++#define SDP_D_PERF_ENABLE_0_SECURE                                         (0x0)
++#define SDP_D_PERF_ENABLE_0_DUAL                                           (0x0)
++#define SDP_D_PERF_ENABLE_0_SCR                                              (0)
++#define SDP_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
++#define SDP_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0xf))
++#define SDP_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0xf))
++#define SDP_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0xf))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT               (_MK_SHIFT_CONST(0))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_RANGE                              (0:0)
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_WOFFSET                            (0x0)
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_INIT_ENUM                           (NO)
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_YES                  (_MK_ENUM_CONST(1))
++
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT               (_MK_SHIFT_CONST(1))
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT))
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_RANGE                              (1:1)
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_WOFFSET                            (0x0)
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_INIT_ENUM                           (NO)
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_YES                  (_MK_ENUM_CONST(1))
++
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT               (_MK_SHIFT_CONST(2))
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT))
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_RANGE                              (2:2)
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_WOFFSET                            (0x0)
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_DEFAULT            (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_INIT_ENUM                           (NO)
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_NO                   (_MK_ENUM_CONST(0))
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_YES                  (_MK_ENUM_CONST(1))
++
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT     (_MK_SHIFT_CONST(3))
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT))
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_RANGE                    (3:3)
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_WOFFSET                  (0x0)
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_INIT_ENUM                 (NO)
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO         (_MK_ENUM_CONST(0))
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES        (_MK_ENUM_CONST(1))
++
++
++// Register SDP_D_PERF_WDMA_WRITE_STALL_0
++#define SDP_D_PERF_WDMA_WRITE_STALL_0                   (_MK_ADDR_CONST(0xb0e0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_SECURE                               (0x0)
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_DUAL                                 (0x0)
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_SCR                                    (0)
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WORD_COUNT                           (0x1)
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT      (_MK_SHIFT_CONST(0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_RANGE                    (31:0)
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_WOFFSET                   (0x0)
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_PERF_LUT_UFLOW_0
++#define SDP_D_PERF_LUT_UFLOW_0                          (_MK_ADDR_CONST(0xb0e4))
++#define SDP_D_PERF_LUT_UFLOW_0_SECURE                                      (0x0)
++#define SDP_D_PERF_LUT_UFLOW_0_DUAL                                        (0x0)
++#define SDP_D_PERF_LUT_UFLOW_0_SCR                                           (0)
++#define SDP_D_PERF_LUT_UFLOW_0_WORD_COUNT                                  (0x1)
++#define SDP_D_PERF_LUT_UFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_UFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_UFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_UFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT))
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_RANGE                            (31:0)
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_WOFFSET                           (0x0)
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_PERF_LUT_OFLOW_0
++#define SDP_D_PERF_LUT_OFLOW_0                          (_MK_ADDR_CONST(0xb0e8))
++#define SDP_D_PERF_LUT_OFLOW_0_SECURE                                      (0x0)
++#define SDP_D_PERF_LUT_OFLOW_0_DUAL                                        (0x0)
++#define SDP_D_PERF_LUT_OFLOW_0_SCR                                           (0)
++#define SDP_D_PERF_LUT_OFLOW_0_WORD_COUNT                                  (0x1)
++#define SDP_D_PERF_LUT_OFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_OFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_OFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_OFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT              (_MK_SHIFT_CONST(0))
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT))
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_RANGE                            (31:0)
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_WOFFSET                           (0x0)
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_PERF_OUT_SATURATION_0
++#define SDP_D_PERF_OUT_SATURATION_0                     (_MK_ADDR_CONST(0xb0ec))
++#define SDP_D_PERF_OUT_SATURATION_0_SECURE                                 (0x0)
++#define SDP_D_PERF_OUT_SATURATION_0_DUAL                                   (0x0)
++#define SDP_D_PERF_OUT_SATURATION_0_SCR                                      (0)
++#define SDP_D_PERF_OUT_SATURATION_0_WORD_COUNT                             (0x1)
++#define SDP_D_PERF_OUT_SATURATION_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_OUT_SATURATION_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_OUT_SATURATION_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_OUT_SATURATION_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_OUT_SATURATION_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_OUT_SATURATION_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT    (_MK_SHIFT_CONST(0))
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT))
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_RANGE                  (31:0)
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_WOFFSET                 (0x0)
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_PERF_LUT_HYBRID_0
++#define SDP_D_PERF_LUT_HYBRID_0                         (_MK_ADDR_CONST(0xb0f0))
++#define SDP_D_PERF_LUT_HYBRID_0_SECURE                                     (0x0)
++#define SDP_D_PERF_LUT_HYBRID_0_DUAL                                       (0x0)
++#define SDP_D_PERF_LUT_HYBRID_0_SCR                                          (0)
++#define SDP_D_PERF_LUT_HYBRID_0_WORD_COUNT                                 (0x1)
++#define SDP_D_PERF_LUT_HYBRID_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_HYBRID_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_HYBRID_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_HYBRID_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT            (_MK_SHIFT_CONST(0))
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT))
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_RANGE                          (31:0)
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_WOFFSET                         (0x0)
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_PERF_LUT_LE_HIT_0
++#define SDP_D_PERF_LUT_LE_HIT_0                         (_MK_ADDR_CONST(0xb0f4))
++#define SDP_D_PERF_LUT_LE_HIT_0_SECURE                                     (0x0)
++#define SDP_D_PERF_LUT_LE_HIT_0_DUAL                                       (0x0)
++#define SDP_D_PERF_LUT_LE_HIT_0_SCR                                          (0)
++#define SDP_D_PERF_LUT_LE_HIT_0_WORD_COUNT                                 (0x1)
++#define SDP_D_PERF_LUT_LE_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LE_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LE_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_LE_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT            (_MK_SHIFT_CONST(0))
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT))
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_RANGE                          (31:0)
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_WOFFSET                         (0x0)
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register SDP_D_PERF_LUT_LO_HIT_0
++#define SDP_D_PERF_LUT_LO_HIT_0                         (_MK_ADDR_CONST(0xb0f8))
++#define SDP_D_PERF_LUT_LO_HIT_0_SECURE                                     (0x0)
++#define SDP_D_PERF_LUT_LO_HIT_0_DUAL                                       (0x0)
++#define SDP_D_PERF_LUT_LO_HIT_0_SCR                                          (0)
++#define SDP_D_PERF_LUT_LO_HIT_0_WORD_COUNT                                 (0x1)
++#define SDP_D_PERF_LUT_LO_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LO_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LO_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_LO_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT            (_MK_SHIFT_CONST(0))
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT))
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_RANGE                          (31:0)
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_WOFFSET                         (0x0)
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_DEFAULT         (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_S_STATUS_0
++#define PDP_RDMA_S_STATUS_0                             (_MK_ADDR_CONST(0xc000))
++#define PDP_RDMA_S_STATUS_0_SECURE                                         (0x0)
++#define PDP_RDMA_S_STATUS_0_DUAL                                           (0x0)
++#define PDP_RDMA_S_STATUS_0_SCR                                              (0)
++#define PDP_RDMA_S_STATUS_0_WORD_COUNT                                     (0x1)
++#define PDP_RDMA_S_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_RESET_MASK                 (_MK_MASK_CONST(0x30003))
++#define PDP_RDMA_S_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_READ_MASK                  (_MK_MASK_CONST(0x30003))
++#define PDP_RDMA_S_STATUS_0_WRITE_MASK                     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                  (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_RANGE                                 (1:0)
++#define PDP_RDMA_S_STATUS_0_STATUS_0_WOFFSET                               (0x0)
++#define PDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT               (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_INIT_ENUM                            (IDLE)
++#define PDP_RDMA_S_STATUS_0_STATUS_0_IDLE                    (_MK_ENUM_CONST(0))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                 (_MK_ENUM_CONST(1))
++#define PDP_RDMA_S_STATUS_0_STATUS_0_PENDING                 (_MK_ENUM_CONST(2))
++
++#define PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                 (_MK_SHIFT_CONST(16))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_RANGE                               (17:16)
++#define PDP_RDMA_S_STATUS_0_STATUS_1_WOFFSET                               (0x0)
++#define PDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT               (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_INIT_ENUM                            (IDLE)
++#define PDP_RDMA_S_STATUS_0_STATUS_1_IDLE                    (_MK_ENUM_CONST(0))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                 (_MK_ENUM_CONST(1))
++#define PDP_RDMA_S_STATUS_0_STATUS_1_PENDING                 (_MK_ENUM_CONST(2))
++
++
++// Register PDP_RDMA_S_POINTER_0
++#define PDP_RDMA_S_POINTER_0                            (_MK_ADDR_CONST(0xc004))
++#define PDP_RDMA_S_POINTER_0_SECURE                                        (0x0)
++#define PDP_RDMA_S_POINTER_0_DUAL                                          (0x0)
++#define PDP_RDMA_S_POINTER_0_SCR                                             (0)
++#define PDP_RDMA_S_POINTER_0_WORD_COUNT                                    (0x1)
++#define PDP_RDMA_S_POINTER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
++#define PDP_RDMA_S_POINTER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
++#define PDP_RDMA_S_POINTER_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                 (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_RANGE                                (0:0)
++#define PDP_RDMA_S_POINTER_0_PRODUCER_WOFFSET                              (0x0)
++#define PDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT              (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_INIT_ENUM                        (GROUP_0)
++#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                (_MK_ENUM_CONST(0))
++#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                (_MK_ENUM_CONST(1))
++
++#define PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                (_MK_SHIFT_CONST(16))
++#define PDP_RDMA_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT))
++#define PDP_RDMA_S_POINTER_0_CONSUMER_RANGE                              (16:16)
++#define PDP_RDMA_S_POINTER_0_CONSUMER_WOFFSET                              (0x0)
++#define PDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT              (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_S_POINTER_0_CONSUMER_INIT_ENUM                        (GROUP_0)
++#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                (_MK_ENUM_CONST(0))
++#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                (_MK_ENUM_CONST(1))
++
++
++// Register PDP_RDMA_D_OP_ENABLE_0
++#define PDP_RDMA_D_OP_ENABLE_0                          (_MK_ADDR_CONST(0xc008))
++#define PDP_RDMA_D_OP_ENABLE_0_SECURE                                      (0x0)
++#define PDP_RDMA_D_OP_ENABLE_0_DUAL                                        (0x0)
++#define PDP_RDMA_D_OP_ENABLE_0_SCR                                           (0)
++#define PDP_RDMA_D_OP_ENABLE_0_WORD_COUNT                                  (0x1)
++#define PDP_RDMA_D_OP_ENABLE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OP_ENABLE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OP_ENABLE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_OP_ENABLE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                  (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_RANGE                                 (0:0)
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                               (0x0)
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT               (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                         (DISABLE)
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                 (_MK_ENUM_CONST(0))
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                  (_MK_ENUM_CONST(1))
++
++
++// Register PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0                 (_MK_ADDR_CONST(0xc00c))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SECURE                             (0x0)
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_DUAL                               (0x0)
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SCR                                  (0)
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_WORD_COUNT                         (0x1)
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_RESET_MASK      (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_READ_MASK       (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_WRITE_MASK      (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_RANGE               (12:0)
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_WOFFSET              (0x0)
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0                (_MK_ADDR_CONST(0xc010))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SECURE                            (0x0)
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_DUAL                              (0x0)
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SCR                                 (0)
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_WORD_COUNT                        (0x1)
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_RESET_VAL         (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_RESET_MASK     (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_VAL    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_READ_MASK      (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_WRITE_MASK     (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_RANGE             (12:0)
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_WOFFSET            (0x0)
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0               (_MK_ADDR_CONST(0xc014))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SECURE                           (0x0)
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_DUAL                             (0x0)
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SCR                                (0)
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_WORD_COUNT                       (0x1)
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_RESET_VAL        (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_RESET_MASK    (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_READ_MASK     (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_WRITE_MASK    (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_RANGE           (12:0)
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_WOFFSET          (0x0)
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_FLYING_MODE_0
++#define PDP_RDMA_D_FLYING_MODE_0                        (_MK_ADDR_CONST(0xc018))
++#define PDP_RDMA_D_FLYING_MODE_0_SECURE                                    (0x0)
++#define PDP_RDMA_D_FLYING_MODE_0_DUAL                                      (0x0)
++#define PDP_RDMA_D_FLYING_MODE_0_SCR                                         (0)
++#define PDP_RDMA_D_FLYING_MODE_0_WORD_COUNT                                (0x1)
++#define PDP_RDMA_D_FLYING_MODE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_FLYING_MODE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_FLYING_MODE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_FLYING_MODE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_FLYING_MODE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_FLYING_MODE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT          (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_RANGE                         (0:0)
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_WOFFSET                       (0x0)
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_DEFAULT       (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_ON_FLYING       (_MK_ENUM_CONST(0))
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_OFF_FLYING      (_MK_ENUM_CONST(1))
++
++
++// Register PDP_RDMA_D_SRC_BASE_ADDR_LOW_0
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0                  (_MK_ADDR_CONST(0xc01c))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SECURE                              (0x0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_DUAL                                (0x0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SCR                                   (0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                          (0x1)
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE            (31:5)
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET           (0x0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                 (_MK_ADDR_CONST(0xc020))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SECURE                             (0x0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_DUAL                               (0x0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SCR                                  (0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                         (0x1)
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE          (31:0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET         (0x0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_SRC_LINE_STRIDE_0
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0                    (_MK_ADDR_CONST(0xc024))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SECURE                                (0x0)
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_DUAL                                  (0x0)
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SCR                                     (0)
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_WORD_COUNT                            (0x1)
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                (31:5)
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET               (0x0)
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_SRC_SURFACE_STRIDE_0
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0                 (_MK_ADDR_CONST(0xc028))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SECURE                             (0x0)
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_DUAL                               (0x0)
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SCR                                  (0)
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                         (0x1)
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE          (31:5)
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET         (0x0)
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_SRC_RAM_CFG_0
++#define PDP_RDMA_D_SRC_RAM_CFG_0                        (_MK_ADDR_CONST(0xc02c))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SECURE                                    (0x0)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_DUAL                                      (0x0)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SCR                                         (0)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_WORD_COUNT                                (0x1)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_RANGE                        (0:0)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_WOFFSET                      (0x0)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
++
++
++// Register PDP_RDMA_D_DATA_FORMAT_0
++#define PDP_RDMA_D_DATA_FORMAT_0                        (_MK_ADDR_CONST(0xc030))
++#define PDP_RDMA_D_DATA_FORMAT_0_SECURE                                    (0x0)
++#define PDP_RDMA_D_DATA_FORMAT_0_DUAL                                      (0x0)
++#define PDP_RDMA_D_DATA_FORMAT_0_SCR                                         (0)
++#define PDP_RDMA_D_DATA_FORMAT_0_WORD_COUNT                                (0x1)
++#define PDP_RDMA_D_DATA_FORMAT_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_FORMAT_0_RESET_MASK                (_MK_MASK_CONST(0x3))
++#define PDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_FORMAT_0_READ_MASK                 (_MK_MASK_CONST(0x3))
++#define PDP_RDMA_D_DATA_FORMAT_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT           (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD \
++      (_MK_FIELD_CONST(0x3, PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_RANGE                          (1:0)
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_WOFFSET                        (0x0)
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT        (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8             (_MK_ENUM_CONST(0))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16            (_MK_ENUM_CONST(1))
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16             (_MK_ENUM_CONST(2))
++
++
++// Register PDP_RDMA_D_OPERATION_MODE_CFG_0
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0                 (_MK_ADDR_CONST(0xc034))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SECURE                             (0x0)
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_DUAL                               (0x0)
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SCR                                  (0)
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_WORD_COUNT                         (0x1)
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_RESET_MASK        (_MK_MASK_CONST(0xff))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_READ_MASK         (_MK_MASK_CONST(0xff))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0xff))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT     (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xff, \
++      PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_RANGE                    (7:0)
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_WOFFSET                  (0x0)
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_POOLING_KERNEL_CFG_0
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0                 (_MK_ADDR_CONST(0xc038))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SECURE                             (0x0)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_DUAL                               (0x0)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SCR                                  (0)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_WORD_COUNT                         (0x1)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_RESET_MASK        (_MK_MASK_CONST(0xff))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_READ_MASK         (_MK_MASK_CONST(0xff))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0xff))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0xf, \
++      PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_RANGE                 (3:0)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_WOFFSET               (0x0)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xf))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 \
++      (_MK_ENUM_CONST(0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 \
++      (_MK_ENUM_CONST(1))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 \
++      (_MK_ENUM_CONST(2))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 \
++      (_MK_ENUM_CONST(3))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 \
++      (_MK_ENUM_CONST(4))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 \
++      (_MK_ENUM_CONST(5))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 \
++      (_MK_ENUM_CONST(6))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 \
++      (_MK_ENUM_CONST(7))
++
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT \
++      (_MK_SHIFT_CONST(4))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0xf, \
++      PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_RANGE          (7:4)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_WOFFSET        (0x0)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xf))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_POOLING_PADDING_CFG_0
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0                (_MK_ADDR_CONST(0xc03c))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SECURE                            (0x0)
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_DUAL                              (0x0)
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SCR                                 (0)
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_WORD_COUNT                        (0x1)
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_RESET_VAL         (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_RESET_MASK        (_MK_MASK_CONST(0xf))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SW_DEFAULT_VAL    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_READ_MASK         (_MK_MASK_CONST(0xf))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0xf))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT    (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0xf, \
++      PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_RANGE                   (3:0)
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_WOFFSET                 (0x0)
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xf))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_PARTIAL_WIDTH_IN_0
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0                   (_MK_ADDR_CONST(0xc040))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SECURE                               (0x0)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_DUAL                                 (0x0)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SCR                                    (0)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_WORD_COUNT                           (0x1)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_RESET_MASK    (_MK_MASK_CONST(0x3fffffff))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_READ_MASK     (_MK_MASK_CONST(0x3fffffff))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_WRITE_MASK    (_MK_MASK_CONST(0x3fffffff))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_RANGE         (9:0)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_WOFFSET       (0x0)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT \
++      (_MK_SHIFT_CONST(10))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_RANGE        (19:10)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_WOFFSET        (0x0)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT \
++      (_MK_SHIFT_CONST(20))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_RANGE         (29:20)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_WOFFSET         (0x0)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_PERF_ENABLE_0
++#define PDP_RDMA_D_PERF_ENABLE_0                        (_MK_ADDR_CONST(0xc044))
++#define PDP_RDMA_D_PERF_ENABLE_0_SECURE                                    (0x0)
++#define PDP_RDMA_D_PERF_ENABLE_0_DUAL                                      (0x0)
++#define PDP_RDMA_D_PERF_ENABLE_0_SCR                                         (0)
++#define PDP_RDMA_D_PERF_ENABLE_0_WORD_COUNT                                (0x1)
++#define PDP_RDMA_D_PERF_ENABLE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_ENABLE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_ENABLE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_PERF_ENABLE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT               (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_RANGE                              (0:0)
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_WOFFSET                            (0x0)
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                      (DISABLE)
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE              (_MK_ENUM_CONST(0))
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE               (_MK_ENUM_CONST(1))
++
++
++// Register PDP_RDMA_D_PERF_READ_STALL_0
++#define PDP_RDMA_D_PERF_READ_STALL_0                    (_MK_ADDR_CONST(0xc048))
++#define PDP_RDMA_D_PERF_READ_STALL_0_SECURE                                (0x0)
++#define PDP_RDMA_D_PERF_READ_STALL_0_DUAL                                  (0x0)
++#define PDP_RDMA_D_PERF_READ_STALL_0_SCR                                     (0)
++#define PDP_RDMA_D_PERF_READ_STALL_0_WORD_COUNT                            (0x1)
++#define PDP_RDMA_D_PERF_READ_STALL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_READ_STALL_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_READ_STALL_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_PERF_READ_STALL_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT))
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_RANGE                (31:0)
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_WOFFSET               (0x0)
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_RDMA_D_CYA_0
++#define PDP_RDMA_D_CYA_0                                (_MK_ADDR_CONST(0xc04c))
++#define PDP_RDMA_D_CYA_0_SECURE                                            (0x0)
++#define PDP_RDMA_D_CYA_0_DUAL                                              (0x0)
++#define PDP_RDMA_D_CYA_0_SCR                                                 (0)
++#define PDP_RDMA_D_CYA_0_WORD_COUNT                                        (0x1)
++#define PDP_RDMA_D_CYA_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_CYA_0_RESET_MASK                 (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_CYA_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_CYA_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_CYA_0_READ_MASK                  (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_CYA_0_WRITE_MASK                 (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_CYA_0_CYA_SHIFT                          (_MK_SHIFT_CONST(0))
++#define PDP_RDMA_D_CYA_0_CYA_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_CYA_0_CYA_SHIFT))
++#define PDP_RDMA_D_CYA_0_CYA_RANGE                                        (31:0)
++#define PDP_RDMA_D_CYA_0_CYA_WOFFSET                                       (0x0)
++#define PDP_RDMA_D_CYA_0_CYA_DEFAULT                       (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_CYA_0_CYA_DEFAULT_MASK           (_MK_MASK_CONST(0xffffffff))
++#define PDP_RDMA_D_CYA_0_CYA_SW_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_CYA_0_CYA_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_CYA_0_CYA_PARITY_PROTECTION             (_MK_MASK_CONST(0x0))
++#define PDP_RDMA_D_CYA_0_CYA_PLATFORM_DEPENDENT            (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_S_STATUS_0
++#define PDP_S_STATUS_0                                  (_MK_ADDR_CONST(0xd000))
++#define PDP_S_STATUS_0_SECURE                                              (0x0)
++#define PDP_S_STATUS_0_DUAL                                                (0x0)
++#define PDP_S_STATUS_0_SCR                                                   (0)
++#define PDP_S_STATUS_0_WORD_COUNT                                          (0x1)
++#define PDP_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
++#define PDP_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
++#define PDP_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
++#define PDP_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_0_SHIFT))
++#define PDP_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
++#define PDP_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
++#define PDP_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define PDP_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define PDP_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
++#define PDP_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
++#define PDP_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
++#define PDP_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
++
++#define PDP_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
++#define PDP_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_1_SHIFT))
++#define PDP_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
++#define PDP_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
++#define PDP_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define PDP_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define PDP_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define PDP_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
++#define PDP_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
++#define PDP_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
++#define PDP_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
++
++
++// Register PDP_S_POINTER_0
++#define PDP_S_POINTER_0                                 (_MK_ADDR_CONST(0xd004))
++#define PDP_S_POINTER_0_SECURE                                             (0x0)
++#define PDP_S_POINTER_0_DUAL                                               (0x0)
++#define PDP_S_POINTER_0_SCR                                                  (0)
++#define PDP_S_POINTER_0_WORD_COUNT                                         (0x1)
++#define PDP_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
++#define PDP_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
++#define PDP_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
++#define PDP_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
++#define PDP_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_S_POINTER_0_PRODUCER_SHIFT))
++#define PDP_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
++#define PDP_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
++#define PDP_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define PDP_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define PDP_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
++#define PDP_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define PDP_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++#define PDP_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
++#define PDP_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_S_POINTER_0_CONSUMER_SHIFT))
++#define PDP_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
++#define PDP_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
++#define PDP_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define PDP_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define PDP_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define PDP_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
++#define PDP_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define PDP_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++
++// Register PDP_D_OP_ENABLE_0
++#define PDP_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0xd008))
++#define PDP_D_OP_ENABLE_0_SECURE                                           (0x0)
++#define PDP_D_OP_ENABLE_0_DUAL                                             (0x0)
++#define PDP_D_OP_ENABLE_0_SCR                                                (0)
++#define PDP_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
++#define PDP_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define PDP_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
++#define PDP_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define PDP_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define PDP_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
++#define PDP_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
++#define PDP_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
++#define PDP_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define PDP_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
++#define PDP_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
++#define PDP_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define PDP_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
++#define PDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define PDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define PDP_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define PDP_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define PDP_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
++#define PDP_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
++#define PDP_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
++
++
++// Register PDP_D_DATA_CUBE_IN_WIDTH_0
++#define PDP_D_DATA_CUBE_IN_WIDTH_0                      (_MK_ADDR_CONST(0xd00c))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_SECURE                                  (0x0)
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_DUAL                                    (0x0)
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_SCR                                       (0)
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_WORD_COUNT                              (0x1)
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_RESET_MASK           (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_READ_MASK            (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_WRITE_MASK           (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT      (_MK_SHIFT_CONST(0))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_RANGE                    (12:0)
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_WOFFSET                   (0x0)
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DATA_CUBE_IN_HEIGHT_0
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0                     (_MK_ADDR_CONST(0xd010))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SECURE                                 (0x0)
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_DUAL                                   (0x0)
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SCR                                      (0)
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_WORD_COUNT                             (0x1)
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_RESET_MASK          (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_READ_MASK           (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_WRITE_MASK          (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT    (_MK_SHIFT_CONST(0))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_RANGE                  (12:0)
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_WOFFSET                 (0x0)
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DATA_CUBE_IN_CHANNEL_0
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0                    (_MK_ADDR_CONST(0xd014))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SECURE                                (0x0)
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_DUAL                                  (0x0)
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SCR                                     (0)
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_WORD_COUNT                            (0x1)
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_RANGE                (12:0)
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_WOFFSET               (0x0)
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DATA_CUBE_OUT_WIDTH_0
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0                     (_MK_ADDR_CONST(0xd018))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SECURE                                 (0x0)
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_DUAL                                   (0x0)
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SCR                                      (0)
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_WORD_COUNT                             (0x1)
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_RESET_MASK          (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_READ_MASK           (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_WRITE_MASK          (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT    (_MK_SHIFT_CONST(0))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_RANGE                  (12:0)
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_WOFFSET                 (0x0)
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DATA_CUBE_OUT_HEIGHT_0
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0                    (_MK_ADDR_CONST(0xd01c))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SECURE                                (0x0)
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_DUAL                                  (0x0)
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SCR                                     (0)
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_WORD_COUNT                            (0x1)
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_RANGE                (12:0)
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_WOFFSET               (0x0)
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DATA_CUBE_OUT_CHANNEL_0
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0                   (_MK_ADDR_CONST(0xd020))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SECURE                               (0x0)
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_DUAL                                 (0x0)
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SCR                                    (0)
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_WORD_COUNT                           (0x1)
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_RANGE              (12:0)
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_WOFFSET             (0x0)
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_OPERATION_MODE_CFG_0
++#define PDP_D_OPERATION_MODE_CFG_0                      (_MK_ADDR_CONST(0xd024))
++#define PDP_D_OPERATION_MODE_CFG_0_SECURE                                  (0x0)
++#define PDP_D_OPERATION_MODE_CFG_0_DUAL                                    (0x0)
++#define PDP_D_OPERATION_MODE_CFG_0_SCR                                       (0)
++#define PDP_D_OPERATION_MODE_CFG_0_WORD_COUNT                              (0x1)
++#define PDP_D_OPERATION_MODE_CFG_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_RESET_MASK           (_MK_MASK_CONST(0xff13))
++#define PDP_D_OPERATION_MODE_CFG_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_READ_MASK            (_MK_MASK_CONST(0xff13))
++#define PDP_D_OPERATION_MODE_CFG_0_WRITE_MASK           (_MK_MASK_CONST(0xff13))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT     (_MK_SHIFT_CONST(0))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_FIELD \
++      (_MK_FIELD_CONST(0x3, \
++      PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_RANGE                    (1:0)
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_WOFFSET                  (0x0)
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE \
++      (_MK_ENUM_CONST(0))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX \
++      (_MK_ENUM_CONST(1))
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN \
++      (_MK_ENUM_CONST(2))
++
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT        (_MK_SHIFT_CONST(4))
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT))
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_RANGE                       (4:4)
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_WOFFSET                     (0x0)
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING     (_MK_ENUM_CONST(0))
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING    (_MK_ENUM_CONST(1))
++
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT          (_MK_SHIFT_CONST(8))
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xff, PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT))
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_RANGE                        (15:8)
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_WOFFSET                       (0x0)
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT       (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_NAN_FLUSH_TO_ZERO_0
++#define PDP_D_NAN_FLUSH_TO_ZERO_0                       (_MK_ADDR_CONST(0xd028))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_SECURE                                   (0x0)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_DUAL                                     (0x0)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_SCR                                        (0)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_WORD_COUNT                               (0x1)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_RESET_MASK               (_MK_MASK_CONST(0x1))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_READ_MASK                (_MK_MASK_CONST(0x1))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_WRITE_MASK               (_MK_MASK_CONST(0x1))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT         (_MK_SHIFT_CONST(0))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_RANGE                        (0:0)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_WOFFSET                      (0x0)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_INIT_ENUM                (DISABLE)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE        (_MK_ENUM_CONST(0))
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE         (_MK_ENUM_CONST(1))
++
++
++// Register PDP_D_PARTIAL_WIDTH_IN_0
++#define PDP_D_PARTIAL_WIDTH_IN_0                        (_MK_ADDR_CONST(0xd02c))
++#define PDP_D_PARTIAL_WIDTH_IN_0_SECURE                                    (0x0)
++#define PDP_D_PARTIAL_WIDTH_IN_0_DUAL                                      (0x0)
++#define PDP_D_PARTIAL_WIDTH_IN_0_SCR                                         (0)
++#define PDP_D_PARTIAL_WIDTH_IN_0_WORD_COUNT                                (0x1)
++#define PDP_D_PARTIAL_WIDTH_IN_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_RESET_MASK         (_MK_MASK_CONST(0x3fffffff))
++#define PDP_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_READ_MASK          (_MK_MASK_CONST(0x3fffffff))
++#define PDP_D_PARTIAL_WIDTH_IN_0_WRITE_MASK         (_MK_MASK_CONST(0x3fffffff))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_RANGE              (9:0)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_WOFFSET            (0x0)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT \
++      (_MK_SHIFT_CONST(10))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_RANGE             (19:10)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_WOFFSET             (0x0)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT \
++      (_MK_SHIFT_CONST(20))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_RANGE              (29:20)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_WOFFSET              (0x0)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_PARTIAL_WIDTH_OUT_0
++#define PDP_D_PARTIAL_WIDTH_OUT_0                       (_MK_ADDR_CONST(0xd030))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_SECURE                                   (0x0)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_DUAL                                     (0x0)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_SCR                                        (0)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_WORD_COUNT                               (0x1)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_RESET_MASK        (_MK_MASK_CONST(0x3fffffff))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_READ_MASK         (_MK_MASK_CONST(0x3fffffff))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_WRITE_MASK        (_MK_MASK_CONST(0x3fffffff))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_RANGE            (9:0)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_WOFFSET          (0x0)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT \
++      (_MK_SHIFT_CONST(10))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_RANGE           (19:10)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_WOFFSET           (0x0)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT \
++      (_MK_SHIFT_CONST(20))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_FIELD \
++      (_MK_FIELD_CONST(0x3ff, \
++      PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_RANGE            (29:20)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_WOFFSET            (0x0)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3ff))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_POOLING_KERNEL_CFG_0
++#define PDP_D_POOLING_KERNEL_CFG_0                      (_MK_ADDR_CONST(0xd034))
++#define PDP_D_POOLING_KERNEL_CFG_0_SECURE                                  (0x0)
++#define PDP_D_POOLING_KERNEL_CFG_0_DUAL                                    (0x0)
++#define PDP_D_POOLING_KERNEL_CFG_0_SCR                                       (0)
++#define PDP_D_POOLING_KERNEL_CFG_0_WORD_COUNT                              (0x1)
++#define PDP_D_POOLING_KERNEL_CFG_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_RESET_MASK         (_MK_MASK_CONST(0xff0f0f))
++#define PDP_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_READ_MASK          (_MK_MASK_CONST(0xff0f0f))
++#define PDP_D_POOLING_KERNEL_CFG_0_WRITE_MASK         (_MK_MASK_CONST(0xff0f0f))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT       (_MK_SHIFT_CONST(0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_RANGE                      (3:0)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_WOFFSET                    (0x0)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT    (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xf))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 \
++      (_MK_ENUM_CONST(0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 \
++      (_MK_ENUM_CONST(1))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 \
++      (_MK_ENUM_CONST(2))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 \
++      (_MK_ENUM_CONST(3))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 \
++      (_MK_ENUM_CONST(4))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 \
++      (_MK_ENUM_CONST(5))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 \
++      (_MK_ENUM_CONST(6))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 \
++      (_MK_ENUM_CONST(7))
++
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT      (_MK_SHIFT_CONST(8))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0xf, \
++      PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_RANGE                    (11:8)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_WOFFSET                   (0x0)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xf))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_1 \
++      (_MK_ENUM_CONST(0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_2 \
++      (_MK_ENUM_CONST(1))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_3 \
++      (_MK_ENUM_CONST(2))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_4 \
++      (_MK_ENUM_CONST(3))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_5 \
++      (_MK_ENUM_CONST(4))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_6 \
++      (_MK_ENUM_CONST(5))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_7 \
++      (_MK_ENUM_CONST(6))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_8 \
++      (_MK_ENUM_CONST(7))
++
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT \
++      (_MK_SHIFT_CONST(16))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0xf, \
++      PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_RANGE             (19:16)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_WOFFSET             (0x0)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xf))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT \
++      (_MK_SHIFT_CONST(20))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0xf, \
++      PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_RANGE            (23:20)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_WOFFSET            (0x0)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xf))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_RECIP_KERNEL_WIDTH_0
++#define PDP_D_RECIP_KERNEL_WIDTH_0                      (_MK_ADDR_CONST(0xd038))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_SECURE                                  (0x0)
++#define PDP_D_RECIP_KERNEL_WIDTH_0_DUAL                                    (0x0)
++#define PDP_D_RECIP_KERNEL_WIDTH_0_SCR                                       (0)
++#define PDP_D_RECIP_KERNEL_WIDTH_0_WORD_COUNT                              (0x1)
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RESET_MASK          (_MK_MASK_CONST(0x1ffff))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_READ_MASK           (_MK_MASK_CONST(0x1ffff))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_WRITE_MASK          (_MK_MASK_CONST(0x1ffff))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1ffff, \
++      PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_RANGE               (16:0)
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_WOFFSET              (0x0)
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1ffff))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_RECIP_KERNEL_HEIGHT_0
++#define PDP_D_RECIP_KERNEL_HEIGHT_0                     (_MK_ADDR_CONST(0xd03c))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_SECURE                                 (0x0)
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_DUAL                                   (0x0)
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_SCR                                      (0)
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_WORD_COUNT                             (0x1)
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RESET_MASK         (_MK_MASK_CONST(0x1ffff))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_READ_MASK          (_MK_MASK_CONST(0x1ffff))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_WRITE_MASK         (_MK_MASK_CONST(0x1ffff))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1ffff, \
++      PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_RANGE             (16:0)
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_WOFFSET            (0x0)
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1ffff))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_POOLING_PADDING_CFG_0
++#define PDP_D_POOLING_PADDING_CFG_0                     (_MK_ADDR_CONST(0xd040))
++#define PDP_D_POOLING_PADDING_CFG_0_SECURE                                 (0x0)
++#define PDP_D_POOLING_PADDING_CFG_0_DUAL                                   (0x0)
++#define PDP_D_POOLING_PADDING_CFG_0_SCR                                      (0)
++#define PDP_D_POOLING_PADDING_CFG_0_WORD_COUNT                             (0x1)
++#define PDP_D_POOLING_PADDING_CFG_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_RESET_MASK          (_MK_MASK_CONST(0x7777))
++#define PDP_D_POOLING_PADDING_CFG_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_READ_MASK           (_MK_MASK_CONST(0x7777))
++#define PDP_D_POOLING_PADDING_CFG_0_WRITE_MASK          (_MK_MASK_CONST(0x7777))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT          (_MK_SHIFT_CONST(0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_FIELD \
++      (_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_RANGE                         (2:0)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_WOFFSET                       (0x0)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT           (_MK_SHIFT_CONST(4))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_FIELD \
++      (_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_RANGE                          (6:4)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_WOFFSET                        (0x0)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_DEFAULT        (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT         (_MK_SHIFT_CONST(8))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_FIELD \
++      (_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_RANGE                       (10:8)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_WOFFSET                      (0x0)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_DEFAULT      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT       (_MK_SHIFT_CONST(12))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_FIELD \
++      (_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_RANGE                     (14:12)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_WOFFSET                     (0x0)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_DEFAULT     (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_1_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0             (_MK_ADDR_CONST(0xd044))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SECURE                         (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_DUAL                           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SCR                              (0)
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_WORD_COUNT                     (0x1)
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_RESET_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_READ_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_WRITE_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_FIELD \
++      (_MK_FIELD_CONST(0x7ffff, \
++      PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_RANGE            (18:0)
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_WOFFSET           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_2_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0             (_MK_ADDR_CONST(0xd048))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SECURE                         (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_DUAL                           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SCR                              (0)
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_WORD_COUNT                     (0x1)
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_RESET_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_READ_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_WRITE_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_FIELD \
++      (_MK_FIELD_CONST(0x7ffff, \
++      PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_RANGE            (18:0)
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_WOFFSET           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_3_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0             (_MK_ADDR_CONST(0xd04c))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SECURE                         (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_DUAL                           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SCR                              (0)
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_WORD_COUNT                     (0x1)
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_RESET_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_READ_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_WRITE_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_FIELD \
++      (_MK_FIELD_CONST(0x7ffff, \
++      PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_RANGE            (18:0)
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_WOFFSET           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_4_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0             (_MK_ADDR_CONST(0xd050))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SECURE                         (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_DUAL                           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SCR                              (0)
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_WORD_COUNT                     (0x1)
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_RESET_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_READ_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_WRITE_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_FIELD \
++      (_MK_FIELD_CONST(0x7ffff, \
++      PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_RANGE            (18:0)
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_WOFFSET           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_5_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0             (_MK_ADDR_CONST(0xd054))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SECURE                         (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_DUAL                           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SCR                              (0)
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_WORD_COUNT                     (0x1)
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_RESET_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_READ_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_WRITE_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_FIELD \
++      (_MK_FIELD_CONST(0x7ffff, \
++      PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_RANGE            (18:0)
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_WOFFSET           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_6_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0             (_MK_ADDR_CONST(0xd058))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SECURE                         (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_DUAL                           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SCR                              (0)
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_WORD_COUNT                     (0x1)
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_RESET_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_READ_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_WRITE_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_FIELD \
++      (_MK_FIELD_CONST(0x7ffff, \
++      PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_RANGE            (18:0)
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_WOFFSET           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_7_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0             (_MK_ADDR_CONST(0xd05c))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SECURE                         (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_DUAL                           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SCR                              (0)
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_WORD_COUNT                     (0x1)
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_RESET_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SW_DEFAULT_VAL \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_READ_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_WRITE_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_FIELD \
++      (_MK_FIELD_CONST(0x7ffff, \
++      PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_RANGE            (18:0)
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_WOFFSET           (0x0)
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffff))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_SRC_BASE_ADDR_LOW_0
++#define PDP_D_SRC_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xd060))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SECURE                                   (0x0)
++#define PDP_D_SRC_BASE_ADDR_LOW_0_DUAL                                     (0x0)
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SCR                                        (0)
++#define PDP_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
++#define PDP_D_SRC_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE                 (31:5)
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET                (0x0)
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_SRC_BASE_ADDR_HIGH_0
++#define PDP_D_SRC_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xd064))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SCR                                       (0)
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE               (31:0)
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET              (0x0)
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_SRC_LINE_STRIDE_0
++#define PDP_D_SRC_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xd068))
++#define PDP_D_SRC_LINE_STRIDE_0_SECURE                                     (0x0)
++#define PDP_D_SRC_LINE_STRIDE_0_DUAL                                       (0x0)
++#define PDP_D_SRC_LINE_STRIDE_0_SCR                                          (0)
++#define PDP_D_SRC_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
++#define PDP_D_SRC_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_SRC_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                     (31:5)
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET                    (0x0)
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_SRC_SURFACE_STRIDE_0
++#define PDP_D_SRC_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xd06c))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SECURE                                  (0x0)
++#define PDP_D_SRC_SURFACE_STRIDE_0_DUAL                                    (0x0)
++#define PDP_D_SRC_SURFACE_STRIDE_0_SCR                                       (0)
++#define PDP_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
++#define PDP_D_SRC_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE               (31:5)
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET              (0x0)
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DST_BASE_ADDR_LOW_0
++#define PDP_D_DST_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xd070))
++#define PDP_D_DST_BASE_ADDR_LOW_0_SECURE                                   (0x0)
++#define PDP_D_DST_BASE_ADDR_LOW_0_DUAL                                     (0x0)
++#define PDP_D_DST_BASE_ADDR_LOW_0_SCR                                        (0)
++#define PDP_D_DST_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
++#define PDP_D_DST_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT))
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_RANGE                 (31:5)
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_WOFFSET                (0x0)
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DST_BASE_ADDR_HIGH_0
++#define PDP_D_DST_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xd074))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
++#define PDP_D_DST_BASE_ADDR_HIGH_0_SCR                                       (0)
++#define PDP_D_DST_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
++#define PDP_D_DST_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_RANGE               (31:0)
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_WOFFSET              (0x0)
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DST_LINE_STRIDE_0
++#define PDP_D_DST_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xd078))
++#define PDP_D_DST_LINE_STRIDE_0_SECURE                                     (0x0)
++#define PDP_D_DST_LINE_STRIDE_0_DUAL                                       (0x0)
++#define PDP_D_DST_LINE_STRIDE_0_SCR                                          (0)
++#define PDP_D_DST_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
++#define PDP_D_DST_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_DST_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT))
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_RANGE                     (31:5)
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_WOFFSET                    (0x0)
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DST_SURFACE_STRIDE_0
++#define PDP_D_DST_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xd07c))
++#define PDP_D_DST_SURFACE_STRIDE_0_SECURE                                  (0x0)
++#define PDP_D_DST_SURFACE_STRIDE_0_DUAL                                    (0x0)
++#define PDP_D_DST_SURFACE_STRIDE_0_SCR                                       (0)
++#define PDP_D_DST_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
++#define PDP_D_DST_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_DST_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT))
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_RANGE               (31:5)
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_WOFFSET              (0x0)
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_DST_RAM_CFG_0
++#define PDP_D_DST_RAM_CFG_0                             (_MK_ADDR_CONST(0xd080))
++#define PDP_D_DST_RAM_CFG_0_SECURE                                         (0x0)
++#define PDP_D_DST_RAM_CFG_0_DUAL                                           (0x0)
++#define PDP_D_DST_RAM_CFG_0_SCR                                              (0)
++#define PDP_D_DST_RAM_CFG_0_WORD_COUNT                                     (0x1)
++#define PDP_D_DST_RAM_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_RAM_CFG_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
++#define PDP_D_DST_RAM_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_RAM_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_RAM_CFG_0_READ_MASK                      (_MK_MASK_CONST(0x1))
++#define PDP_D_DST_RAM_CFG_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT              (_MK_SHIFT_CONST(0))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_RANGE                             (0:0)
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_WOFFSET                           (0x0)
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_DEFAULT           (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_CV                  (_MK_ENUM_CONST(0))
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_MC                  (_MK_ENUM_CONST(1))
++
++
++// Register PDP_D_DATA_FORMAT_0
++#define PDP_D_DATA_FORMAT_0                             (_MK_ADDR_CONST(0xd084))
++#define PDP_D_DATA_FORMAT_0_SECURE                                         (0x0)
++#define PDP_D_DATA_FORMAT_0_DUAL                                           (0x0)
++#define PDP_D_DATA_FORMAT_0_SCR                                              (0)
++#define PDP_D_DATA_FORMAT_0_WORD_COUNT                                     (0x1)
++#define PDP_D_DATA_FORMAT_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_FORMAT_0_RESET_MASK                     (_MK_MASK_CONST(0x3))
++#define PDP_D_DATA_FORMAT_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_FORMAT_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_FORMAT_0_READ_MASK                      (_MK_MASK_CONST(0x3))
++#define PDP_D_DATA_FORMAT_0_WRITE_MASK                     (_MK_MASK_CONST(0x3))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT                (_MK_SHIFT_CONST(0))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FIELD \
++      (_MK_FIELD_CONST(0x3, PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_RANGE                               (1:0)
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_WOFFSET                             (0x0)
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT             (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT_MASK        (_MK_MASK_CONST(0x3))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT8                  (_MK_ENUM_CONST(0))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT16                 (_MK_ENUM_CONST(1))
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FP16                  (_MK_ENUM_CONST(2))
++
++
++// Register PDP_D_INF_INPUT_NUM_0
++#define PDP_D_INF_INPUT_NUM_0                           (_MK_ADDR_CONST(0xd088))
++#define PDP_D_INF_INPUT_NUM_0_SECURE                                       (0x0)
++#define PDP_D_INF_INPUT_NUM_0_DUAL                                         (0x0)
++#define PDP_D_INF_INPUT_NUM_0_SCR                                            (0)
++#define PDP_D_INF_INPUT_NUM_0_WORD_COUNT                                   (0x1)
++#define PDP_D_INF_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define PDP_D_INF_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_INF_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_INF_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define PDP_D_INF_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_INF_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT))
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_RANGE                         (31:0)
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_WOFFSET                        (0x0)
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_NAN_INPUT_NUM_0
++#define PDP_D_NAN_INPUT_NUM_0                           (_MK_ADDR_CONST(0xd08c))
++#define PDP_D_NAN_INPUT_NUM_0_SECURE                                       (0x0)
++#define PDP_D_NAN_INPUT_NUM_0_DUAL                                         (0x0)
++#define PDP_D_NAN_INPUT_NUM_0_SCR                                            (0)
++#define PDP_D_NAN_INPUT_NUM_0_WORD_COUNT                                   (0x1)
++#define PDP_D_NAN_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_NAN_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT))
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_RANGE                         (31:0)
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_WOFFSET                        (0x0)
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_NAN_OUTPUT_NUM_0
++#define PDP_D_NAN_OUTPUT_NUM_0                          (_MK_ADDR_CONST(0xd090))
++#define PDP_D_NAN_OUTPUT_NUM_0_SECURE                                      (0x0)
++#define PDP_D_NAN_OUTPUT_NUM_0_DUAL                                        (0x0)
++#define PDP_D_NAN_OUTPUT_NUM_0_SCR                                           (0)
++#define PDP_D_NAN_OUTPUT_NUM_0_WORD_COUNT                                  (0x1)
++#define PDP_D_NAN_OUTPUT_NUM_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_OUTPUT_NUM_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_OUTPUT_NUM_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_NAN_OUTPUT_NUM_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT         (_MK_SHIFT_CONST(0))
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT))
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_RANGE                       (31:0)
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_WOFFSET                      (0x0)
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_PERF_ENABLE_0
++#define PDP_D_PERF_ENABLE_0                             (_MK_ADDR_CONST(0xd094))
++#define PDP_D_PERF_ENABLE_0_SECURE                                         (0x0)
++#define PDP_D_PERF_ENABLE_0_DUAL                                           (0x0)
++#define PDP_D_PERF_ENABLE_0_SCR                                              (0)
++#define PDP_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
++#define PDP_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
++#define PDP_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0x1))
++#define PDP_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT                    (_MK_SHIFT_CONST(0))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_RANGE                                   (0:0)
++#define PDP_D_PERF_ENABLE_0_DMA_EN_WOFFSET                                 (0x0)
++#define PDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                           (DISABLE)
++#define PDP_D_PERF_ENABLE_0_DMA_EN_DISABLE                   (_MK_ENUM_CONST(0))
++#define PDP_D_PERF_ENABLE_0_DMA_EN_ENABLE                    (_MK_ENUM_CONST(1))
++
++
++// Register PDP_D_PERF_WRITE_STALL_0
++#define PDP_D_PERF_WRITE_STALL_0                        (_MK_ADDR_CONST(0xd098))
++#define PDP_D_PERF_WRITE_STALL_0_SECURE                                    (0x0)
++#define PDP_D_PERF_WRITE_STALL_0_DUAL                                      (0x0)
++#define PDP_D_PERF_WRITE_STALL_0_SCR                                         (0)
++#define PDP_D_PERF_WRITE_STALL_0_WORD_COUNT                                (0x1)
++#define PDP_D_PERF_WRITE_STALL_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_WRITE_STALL_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_WRITE_STALL_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_PERF_WRITE_STALL_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT     (_MK_SHIFT_CONST(0))
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT))
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_RANGE                   (31:0)
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_WOFFSET                  (0x0)
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register PDP_D_CYA_0
++#define PDP_D_CYA_0                                     (_MK_ADDR_CONST(0xd09c))
++#define PDP_D_CYA_0_SECURE                                                 (0x0)
++#define PDP_D_CYA_0_DUAL                                                   (0x0)
++#define PDP_D_CYA_0_SCR                                                      (0)
++#define PDP_D_CYA_0_WORD_COUNT                                             (0x1)
++#define PDP_D_CYA_0_RESET_VAL                              (_MK_MASK_CONST(0x0))
++#define PDP_D_CYA_0_RESET_MASK                      (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_CYA_0_SW_DEFAULT_VAL                         (_MK_MASK_CONST(0x0))
++#define PDP_D_CYA_0_SW_DEFAULT_MASK                        (_MK_MASK_CONST(0x0))
++#define PDP_D_CYA_0_READ_MASK                       (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_CYA_0_WRITE_MASK                      (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_CYA_0_CYA_SHIFT                               (_MK_SHIFT_CONST(0))
++#define PDP_D_CYA_0_CYA_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, PDP_D_CYA_0_CYA_SHIFT))
++#define PDP_D_CYA_0_CYA_RANGE                                             (31:0)
++#define PDP_D_CYA_0_CYA_WOFFSET                                            (0x0)
++#define PDP_D_CYA_0_CYA_DEFAULT                            (_MK_MASK_CONST(0x0))
++#define PDP_D_CYA_0_CYA_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff))
++#define PDP_D_CYA_0_CYA_SW_DEFAULT                         (_MK_MASK_CONST(0x0))
++#define PDP_D_CYA_0_CYA_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define PDP_D_CYA_0_CYA_PARITY_PROTECTION                  (_MK_MASK_CONST(0x0))
++#define PDP_D_CYA_0_CYA_PLATFORM_DEPENDENT                 (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_RDMA_S_STATUS_0
++#define CDP_RDMA_S_STATUS_0                             (_MK_ADDR_CONST(0xe000))
++#define CDP_RDMA_S_STATUS_0_SECURE                                         (0x0)
++#define CDP_RDMA_S_STATUS_0_DUAL                                           (0x0)
++#define CDP_RDMA_S_STATUS_0_SCR                                              (0)
++#define CDP_RDMA_S_STATUS_0_WORD_COUNT                                     (0x1)
++#define CDP_RDMA_S_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_RESET_MASK                 (_MK_MASK_CONST(0x30003))
++#define CDP_RDMA_S_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_READ_MASK                  (_MK_MASK_CONST(0x30003))
++#define CDP_RDMA_S_STATUS_0_WRITE_MASK                     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                  (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_RANGE                                 (1:0)
++#define CDP_RDMA_S_STATUS_0_STATUS_0_WOFFSET                               (0x0)
++#define CDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_INIT_ENUM                            (IDLE)
++#define CDP_RDMA_S_STATUS_0_STATUS_0_IDLE                    (_MK_ENUM_CONST(0))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                 (_MK_ENUM_CONST(1))
++#define CDP_RDMA_S_STATUS_0_STATUS_0_PENDING                 (_MK_ENUM_CONST(2))
++
++#define CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                 (_MK_SHIFT_CONST(16))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_RANGE                               (17:16)
++#define CDP_RDMA_S_STATUS_0_STATUS_1_WOFFSET                               (0x0)
++#define CDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_INIT_ENUM                            (IDLE)
++#define CDP_RDMA_S_STATUS_0_STATUS_1_IDLE                    (_MK_ENUM_CONST(0))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                 (_MK_ENUM_CONST(1))
++#define CDP_RDMA_S_STATUS_0_STATUS_1_PENDING                 (_MK_ENUM_CONST(2))
++
++
++// Register CDP_RDMA_S_POINTER_0
++#define CDP_RDMA_S_POINTER_0                            (_MK_ADDR_CONST(0xe004))
++#define CDP_RDMA_S_POINTER_0_SECURE                                        (0x0)
++#define CDP_RDMA_S_POINTER_0_DUAL                                          (0x0)
++#define CDP_RDMA_S_POINTER_0_SCR                                             (0)
++#define CDP_RDMA_S_POINTER_0_WORD_COUNT                                    (0x1)
++#define CDP_RDMA_S_POINTER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
++#define CDP_RDMA_S_POINTER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
++#define CDP_RDMA_S_POINTER_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                 (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_RANGE                                (0:0)
++#define CDP_RDMA_S_POINTER_0_PRODUCER_WOFFSET                              (0x0)
++#define CDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_INIT_ENUM                        (GROUP_0)
++#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                (_MK_ENUM_CONST(0))
++#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                (_MK_ENUM_CONST(1))
++
++#define CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                (_MK_SHIFT_CONST(16))
++#define CDP_RDMA_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT))
++#define CDP_RDMA_S_POINTER_0_CONSUMER_RANGE                              (16:16)
++#define CDP_RDMA_S_POINTER_0_CONSUMER_WOFFSET                              (0x0)
++#define CDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_S_POINTER_0_CONSUMER_INIT_ENUM                        (GROUP_0)
++#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                (_MK_ENUM_CONST(0))
++#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                (_MK_ENUM_CONST(1))
++
++
++// Register CDP_RDMA_D_OP_ENABLE_0
++#define CDP_RDMA_D_OP_ENABLE_0                          (_MK_ADDR_CONST(0xe008))
++#define CDP_RDMA_D_OP_ENABLE_0_SECURE                                      (0x0)
++#define CDP_RDMA_D_OP_ENABLE_0_DUAL                                        (0x0)
++#define CDP_RDMA_D_OP_ENABLE_0_SCR                                           (0)
++#define CDP_RDMA_D_OP_ENABLE_0_WORD_COUNT                                  (0x1)
++#define CDP_RDMA_D_OP_ENABLE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OP_ENABLE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OP_ENABLE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_OP_ENABLE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                  (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_RANGE                                 (0:0)
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                               (0x0)
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT               (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                         (DISABLE)
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                 (_MK_ENUM_CONST(0))
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                  (_MK_ENUM_CONST(1))
++
++
++// Register CDP_RDMA_D_DATA_CUBE_WIDTH_0
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0                    (_MK_ADDR_CONST(0xe00c))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SECURE                                (0x0)
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_DUAL                                  (0x0)
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SCR                                     (0)
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WORD_COUNT                            (0x1)
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT            (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_RANGE                          (12:0)
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_WOFFSET                         (0x0)
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_RDMA_D_DATA_CUBE_HEIGHT_0
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0                   (_MK_ADDR_CONST(0xe010))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SECURE                               (0x0)
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_DUAL                                 (0x0)
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SCR                                    (0)
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_WORD_COUNT                           (0x1)
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_VAL            (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT          (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_RANGE                        (12:0)
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_WOFFSET                       (0x0)
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_RDMA_D_DATA_CUBE_CHANNEL_0
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0                  (_MK_ADDR_CONST(0xe014))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SECURE                              (0x0)
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_DUAL                                (0x0)
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SCR                                   (0)
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_WORD_COUNT                          (0x1)
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_MASK       (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_READ_MASK        (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_WRITE_MASK       (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_RANGE                      (12:0)
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_WOFFSET                     (0x0)
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_RDMA_D_SRC_BASE_ADDR_LOW_0
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0                  (_MK_ADDR_CONST(0xe018))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SECURE                              (0x0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_DUAL                                (0x0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SCR                                   (0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                          (0x1)
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_VAL           (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE            (31:5)
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET           (0x0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                 (_MK_ADDR_CONST(0xe01c))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SECURE                             (0x0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_DUAL                               (0x0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SCR                                  (0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                         (0x1)
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE          (31:0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET         (0x0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_RDMA_D_SRC_LINE_STRIDE_0
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0                    (_MK_ADDR_CONST(0xe020))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SECURE                                (0x0)
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_DUAL                                  (0x0)
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SCR                                     (0)
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_WORD_COUNT                            (0x1)
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                (31:5)
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET               (0x0)
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_RDMA_D_SRC_SURFACE_STRIDE_0
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0                 (_MK_ADDR_CONST(0xe024))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SECURE                             (0x0)
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_DUAL                               (0x0)
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SCR                                  (0)
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                         (0x1)
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_READ_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_WRITE_MASK \
++      (_MK_MASK_CONST(0xffffffe0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE          (31:5)
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET         (0x0)
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_RDMA_D_SRC_DMA_CFG_0
++#define CDP_RDMA_D_SRC_DMA_CFG_0                        (_MK_ADDR_CONST(0xe028))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SECURE                                    (0x0)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_DUAL                                      (0x0)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SCR                                         (0)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_WORD_COUNT                                (0x1)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_RANGE                        (0:0)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_WOFFSET                      (0x0)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
++
++
++// Register CDP_RDMA_D_SRC_COMPRESSION_EN_0
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0                 (_MK_ADDR_CONST(0xe02c))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SECURE                             (0x0)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_DUAL                               (0x0)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SCR                                  (0)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_WORD_COUNT                         (0x1)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_RESET_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_RESET_MASK         (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_READ_MASK          (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_WRITE_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_RANGE           (0:0)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_WOFFSET         (0x0)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DISABLE \
++      (_MK_ENUM_CONST(0))
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_ENABLE \
++      (_MK_ENUM_CONST(1))
++
++
++// Register CDP_RDMA_D_OPERATION_MODE_0
++#define CDP_RDMA_D_OPERATION_MODE_0                     (_MK_ADDR_CONST(0xe030))
++#define CDP_RDMA_D_OPERATION_MODE_0_SECURE                                 (0x0)
++#define CDP_RDMA_D_OPERATION_MODE_0_DUAL                                   (0x0)
++#define CDP_RDMA_D_OPERATION_MODE_0_SCR                                      (0)
++#define CDP_RDMA_D_OPERATION_MODE_0_WORD_COUNT                             (0x1)
++#define CDP_RDMA_D_OPERATION_MODE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OPERATION_MODE_0_RESET_MASK             (_MK_MASK_CONST(0x3))
++#define CDP_RDMA_D_OPERATION_MODE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OPERATION_MODE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OPERATION_MODE_0_READ_MASK              (_MK_MASK_CONST(0x3))
++#define CDP_RDMA_D_OPERATION_MODE_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT    (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_FIELD \
++      (_MK_FIELD_CONST(0x3, \
++      CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_RANGE                   (1:0)
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WOFFSET                 (0x0)
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_READPHILE \
++      (_MK_ENUM_CONST(0))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WRITEPHILE \
++      (_MK_ENUM_CONST(1))
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_ORDINARY \
++      (_MK_ENUM_CONST(2))
++
++
++// Register CDP_RDMA_D_DATA_FORMAT_0
++#define CDP_RDMA_D_DATA_FORMAT_0                        (_MK_ADDR_CONST(0xe034))
++#define CDP_RDMA_D_DATA_FORMAT_0_SECURE                                    (0x0)
++#define CDP_RDMA_D_DATA_FORMAT_0_DUAL                                      (0x0)
++#define CDP_RDMA_D_DATA_FORMAT_0_SCR                                         (0)
++#define CDP_RDMA_D_DATA_FORMAT_0_WORD_COUNT                                (0x1)
++#define CDP_RDMA_D_DATA_FORMAT_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_FORMAT_0_RESET_MASK                (_MK_MASK_CONST(0x3))
++#define CDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_FORMAT_0_READ_MASK                 (_MK_MASK_CONST(0x3))
++#define CDP_RDMA_D_DATA_FORMAT_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT           (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD \
++      (_MK_FIELD_CONST(0x3, CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_RANGE                          (1:0)
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_WOFFSET                        (0x0)
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8             (_MK_ENUM_CONST(0))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16            (_MK_ENUM_CONST(1))
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16             (_MK_ENUM_CONST(2))
++
++
++// Register CDP_RDMA_D_PERF_ENABLE_0
++#define CDP_RDMA_D_PERF_ENABLE_0                        (_MK_ADDR_CONST(0xe038))
++#define CDP_RDMA_D_PERF_ENABLE_0_SECURE                                    (0x0)
++#define CDP_RDMA_D_PERF_ENABLE_0_DUAL                                      (0x0)
++#define CDP_RDMA_D_PERF_ENABLE_0_SCR                                         (0)
++#define CDP_RDMA_D_PERF_ENABLE_0_WORD_COUNT                                (0x1)
++#define CDP_RDMA_D_PERF_ENABLE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_ENABLE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_ENABLE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_PERF_ENABLE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT               (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_RANGE                              (0:0)
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_WOFFSET                            (0x0)
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                      (DISABLE)
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE              (_MK_ENUM_CONST(0))
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE               (_MK_ENUM_CONST(1))
++
++
++// Register CDP_RDMA_D_PERF_READ_STALL_0
++#define CDP_RDMA_D_PERF_READ_STALL_0                    (_MK_ADDR_CONST(0xe03c))
++#define CDP_RDMA_D_PERF_READ_STALL_0_SECURE                                (0x0)
++#define CDP_RDMA_D_PERF_READ_STALL_0_DUAL                                  (0x0)
++#define CDP_RDMA_D_PERF_READ_STALL_0_SCR                                     (0)
++#define CDP_RDMA_D_PERF_READ_STALL_0_WORD_COUNT                            (0x1)
++#define CDP_RDMA_D_PERF_READ_STALL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_READ_STALL_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_READ_STALL_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_PERF_READ_STALL_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT))
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_RANGE                (31:0)
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_WOFFSET               (0x0)
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_RDMA_D_CYA_0
++#define CDP_RDMA_D_CYA_0                                (_MK_ADDR_CONST(0xe040))
++#define CDP_RDMA_D_CYA_0_SECURE                                            (0x0)
++#define CDP_RDMA_D_CYA_0_DUAL                                              (0x0)
++#define CDP_RDMA_D_CYA_0_SCR                                                 (0)
++#define CDP_RDMA_D_CYA_0_WORD_COUNT                                        (0x1)
++#define CDP_RDMA_D_CYA_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_CYA_0_RESET_MASK                 (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_CYA_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_CYA_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_CYA_0_READ_MASK                  (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_CYA_0_WRITE_MASK                 (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_CYA_0_CYA_SHIFT                          (_MK_SHIFT_CONST(0))
++#define CDP_RDMA_D_CYA_0_CYA_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_CYA_0_CYA_SHIFT))
++#define CDP_RDMA_D_CYA_0_CYA_RANGE                                        (31:0)
++#define CDP_RDMA_D_CYA_0_CYA_WOFFSET                                       (0x0)
++#define CDP_RDMA_D_CYA_0_CYA_DEFAULT                       (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_CYA_0_CYA_DEFAULT_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_RDMA_D_CYA_0_CYA_SW_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_CYA_0_CYA_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_CYA_0_CYA_PARITY_PROTECTION             (_MK_MASK_CONST(0x0))
++#define CDP_RDMA_D_CYA_0_CYA_PLATFORM_DEPENDENT            (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_STATUS_0
++#define CDP_S_STATUS_0                                  (_MK_ADDR_CONST(0xf000))
++#define CDP_S_STATUS_0_SECURE                                              (0x0)
++#define CDP_S_STATUS_0_DUAL                                                (0x0)
++#define CDP_S_STATUS_0_SCR                                                   (0)
++#define CDP_S_STATUS_0_WORD_COUNT                                          (0x1)
++#define CDP_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
++#define CDP_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
++#define CDP_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
++#define CDP_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_0_SHIFT))
++#define CDP_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
++#define CDP_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
++#define CDP_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define CDP_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define CDP_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
++#define CDP_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
++#define CDP_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
++#define CDP_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
++
++#define CDP_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
++#define CDP_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_1_SHIFT))
++#define CDP_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
++#define CDP_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
++#define CDP_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define CDP_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define CDP_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define CDP_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
++#define CDP_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
++#define CDP_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
++#define CDP_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
++
++
++// Register CDP_S_POINTER_0
++#define CDP_S_POINTER_0                                 (_MK_ADDR_CONST(0xf004))
++#define CDP_S_POINTER_0_SECURE                                             (0x0)
++#define CDP_S_POINTER_0_DUAL                                               (0x0)
++#define CDP_S_POINTER_0_SCR                                                  (0)
++#define CDP_S_POINTER_0_WORD_COUNT                                         (0x1)
++#define CDP_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
++#define CDP_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
++#define CDP_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
++#define CDP_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
++#define CDP_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_S_POINTER_0_PRODUCER_SHIFT))
++#define CDP_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
++#define CDP_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
++#define CDP_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define CDP_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CDP_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
++#define CDP_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define CDP_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++#define CDP_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
++#define CDP_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_S_POINTER_0_CONSUMER_SHIFT))
++#define CDP_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
++#define CDP_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
++#define CDP_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define CDP_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define CDP_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define CDP_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
++#define CDP_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define CDP_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++
++// Register CDP_S_LUT_ACCESS_CFG_0
++#define CDP_S_LUT_ACCESS_CFG_0                          (_MK_ADDR_CONST(0xf008))
++#define CDP_S_LUT_ACCESS_CFG_0_SECURE                                      (0x0)
++#define CDP_S_LUT_ACCESS_CFG_0_DUAL                                        (0x0)
++#define CDP_S_LUT_ACCESS_CFG_0_SCR                                           (0)
++#define CDP_S_LUT_ACCESS_CFG_0_WORD_COUNT                                  (0x1)
++#define CDP_S_LUT_ACCESS_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_RESET_MASK              (_MK_MASK_CONST(0x303ff))
++#define CDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_READ_MASK               (_MK_MASK_CONST(0x303ff))
++#define CDP_S_LUT_ACCESS_CFG_0_WRITE_MASK              (_MK_MASK_CONST(0x303ff))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT               (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD \
++      (_MK_FIELD_CONST(0x3ff, CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_RANGE                              (9:0)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_WOFFSET                            (0x0)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT_MASK     (_MK_MASK_CONST(0x3ff))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT          (_MK_SHIFT_CONST(16))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_RANGE                        (16:16)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_WOFFSET                        (0x0)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE               (_MK_ENUM_CONST(0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO               (_MK_ENUM_CONST(1))
++
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT       (_MK_SHIFT_CONST(17))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_RANGE                     (17:17)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WOFFSET                     (0x0)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ          (_MK_ENUM_CONST(0))
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE         (_MK_ENUM_CONST(1))
++
++
++// Register CDP_S_LUT_ACCESS_DATA_0
++#define CDP_S_LUT_ACCESS_DATA_0                         (_MK_ADDR_CONST(0xf00c))
++#define CDP_S_LUT_ACCESS_DATA_0_SECURE                                     (0x0)
++#define CDP_S_LUT_ACCESS_DATA_0_DUAL                                       (0x0)
++#define CDP_S_LUT_ACCESS_DATA_0_SCR                                          (0)
++#define CDP_S_LUT_ACCESS_DATA_0_WORD_COUNT                                 (0x1)
++#define CDP_S_LUT_ACCESS_DATA_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_DATA_0_RESET_MASK              (_MK_MASK_CONST(0xffff))
++#define CDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_DATA_0_READ_MASK               (_MK_MASK_CONST(0xffff))
++#define CDP_S_LUT_ACCESS_DATA_0_WRITE_MASK              (_MK_MASK_CONST(0xffff))
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT              (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT))
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_RANGE                            (15:0)
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_WOFFSET                           (0x0)
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_CFG_0
++#define CDP_S_LUT_CFG_0                                 (_MK_ADDR_CONST(0xf010))
++#define CDP_S_LUT_CFG_0_SECURE                                             (0x0)
++#define CDP_S_LUT_CFG_0_DUAL                                               (0x0)
++#define CDP_S_LUT_CFG_0_SCR                                                  (0)
++#define CDP_S_LUT_CFG_0_WORD_COUNT                                         (0x1)
++#define CDP_S_LUT_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_RESET_MASK                        (_MK_MASK_CONST(0x71))
++#define CDP_S_LUT_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_READ_MASK                         (_MK_MASK_CONST(0x71))
++#define CDP_S_LUT_CFG_0_WRITE_MASK                        (_MK_MASK_CONST(0x71))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT               (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_RANGE                              (0:0)
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_WOFFSET                            (0x0)
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT            (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT             (_MK_ENUM_CONST(0))
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR               (_MK_ENUM_CONST(1))
++
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(4))
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT))
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_RANGE                           (4:4)
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_WOFFSET                         (0x0)
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
++
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(5))
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT))
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_RANGE                           (5:5)
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_WOFFSET                         (0x0)
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
++
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT           (_MK_SHIFT_CONST(6))
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT))
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_RANGE                          (6:6)
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_WOFFSET                        (0x0)
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE               (_MK_ENUM_CONST(0))
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO               (_MK_ENUM_CONST(1))
++
++
++// Register CDP_S_LUT_INFO_0
++#define CDP_S_LUT_INFO_0                                (_MK_ADDR_CONST(0xf014))
++#define CDP_S_LUT_INFO_0_SECURE                                            (0x0)
++#define CDP_S_LUT_INFO_0_DUAL                                              (0x0)
++#define CDP_S_LUT_INFO_0_SCR                                                 (0)
++#define CDP_S_LUT_INFO_0_WORD_COUNT                                        (0x1)
++#define CDP_S_LUT_INFO_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_RESET_MASK                   (_MK_MASK_CONST(0xffffff))
++#define CDP_S_LUT_INFO_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_READ_MASK                    (_MK_MASK_CONST(0xffffff))
++#define CDP_S_LUT_INFO_0_WRITE_MASK                   (_MK_MASK_CONST(0xffffff))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT          (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_RANGE                         (7:0)
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_WOFFSET                       (0x0)
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT          (_MK_SHIFT_CONST(8))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD \
++      (_MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_RANGE                        (15:8)
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_WOFFSET                       (0x0)
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT         (_MK_SHIFT_CONST(16))
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD \
++      (_MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT))
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_RANGE                       (23:16)
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_WOFFSET                       (0x0)
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xff))
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LE_START_LOW_0
++#define CDP_S_LUT_LE_START_LOW_0                        (_MK_ADDR_CONST(0xf018))
++#define CDP_S_LUT_LE_START_LOW_0_SECURE                                    (0x0)
++#define CDP_S_LUT_LE_START_LOW_0_DUAL                                      (0x0)
++#define CDP_S_LUT_LE_START_LOW_0_SCR                                         (0)
++#define CDP_S_LUT_LE_START_LOW_0_WORD_COUNT                                (0x1)
++#define CDP_S_LUT_LE_START_LOW_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_LOW_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_START_LOW_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_LOW_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_LOW_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_START_LOW_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT     (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT))
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_RANGE                   (31:0)
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_WOFFSET                  (0x0)
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LE_START_HIGH_0
++#define CDP_S_LUT_LE_START_HIGH_0                       (_MK_ADDR_CONST(0xf01c))
++#define CDP_S_LUT_LE_START_HIGH_0_SECURE                                   (0x0)
++#define CDP_S_LUT_LE_START_HIGH_0_DUAL                                     (0x0)
++#define CDP_S_LUT_LE_START_HIGH_0_SCR                                        (0)
++#define CDP_S_LUT_LE_START_HIGH_0_WORD_COUNT                               (0x1)
++#define CDP_S_LUT_LE_START_HIGH_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_HIGH_0_RESET_MASK              (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LE_START_HIGH_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_HIGH_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_HIGH_0_READ_MASK               (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LE_START_HIGH_0_WRITE_MASK              (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_FIELD \
++      (_MK_FIELD_CONST(0x3f, \
++      CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT))
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_RANGE                  (5:0)
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_WOFFSET                (0x0)
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LE_END_LOW_0
++#define CDP_S_LUT_LE_END_LOW_0                          (_MK_ADDR_CONST(0xf020))
++#define CDP_S_LUT_LE_END_LOW_0_SECURE                                      (0x0)
++#define CDP_S_LUT_LE_END_LOW_0_DUAL                                        (0x0)
++#define CDP_S_LUT_LE_END_LOW_0_SCR                                           (0)
++#define CDP_S_LUT_LE_END_LOW_0_WORD_COUNT                                  (0x1)
++#define CDP_S_LUT_LE_END_LOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_LOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_END_LOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_LOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_LOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_END_LOW_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT))
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_RANGE                       (31:0)
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_WOFFSET                      (0x0)
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LE_END_HIGH_0
++#define CDP_S_LUT_LE_END_HIGH_0                         (_MK_ADDR_CONST(0xf024))
++#define CDP_S_LUT_LE_END_HIGH_0_SECURE                                     (0x0)
++#define CDP_S_LUT_LE_END_HIGH_0_DUAL                                       (0x0)
++#define CDP_S_LUT_LE_END_HIGH_0_SCR                                          (0)
++#define CDP_S_LUT_LE_END_HIGH_0_WORD_COUNT                                 (0x1)
++#define CDP_S_LUT_LE_END_HIGH_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_HIGH_0_RESET_MASK                (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LE_END_HIGH_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_HIGH_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_HIGH_0_READ_MASK                 (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LE_END_HIGH_0_WRITE_MASK                (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT       (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_FIELD \
++      (_MK_FIELD_CONST(0x3f, \
++      CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT))
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_RANGE                      (5:0)
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_WOFFSET                    (0x0)
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LO_START_LOW_0
++#define CDP_S_LUT_LO_START_LOW_0                        (_MK_ADDR_CONST(0xf028))
++#define CDP_S_LUT_LO_START_LOW_0_SECURE                                    (0x0)
++#define CDP_S_LUT_LO_START_LOW_0_DUAL                                      (0x0)
++#define CDP_S_LUT_LO_START_LOW_0_SCR                                         (0)
++#define CDP_S_LUT_LO_START_LOW_0_WORD_COUNT                                (0x1)
++#define CDP_S_LUT_LO_START_LOW_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_LOW_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_START_LOW_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_LOW_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_LOW_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_START_LOW_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT     (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT))
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_RANGE                   (31:0)
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_WOFFSET                  (0x0)
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LO_START_HIGH_0
++#define CDP_S_LUT_LO_START_HIGH_0                       (_MK_ADDR_CONST(0xf02c))
++#define CDP_S_LUT_LO_START_HIGH_0_SECURE                                   (0x0)
++#define CDP_S_LUT_LO_START_HIGH_0_DUAL                                     (0x0)
++#define CDP_S_LUT_LO_START_HIGH_0_SCR                                        (0)
++#define CDP_S_LUT_LO_START_HIGH_0_WORD_COUNT                               (0x1)
++#define CDP_S_LUT_LO_START_HIGH_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_HIGH_0_RESET_MASK              (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LO_START_HIGH_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_HIGH_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_HIGH_0_READ_MASK               (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LO_START_HIGH_0_WRITE_MASK              (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_FIELD \
++      (_MK_FIELD_CONST(0x3f, \
++      CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT))
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_RANGE                  (5:0)
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_WOFFSET                (0x0)
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LO_END_LOW_0
++#define CDP_S_LUT_LO_END_LOW_0                          (_MK_ADDR_CONST(0xf030))
++#define CDP_S_LUT_LO_END_LOW_0_SECURE                                      (0x0)
++#define CDP_S_LUT_LO_END_LOW_0_DUAL                                        (0x0)
++#define CDP_S_LUT_LO_END_LOW_0_SCR                                           (0)
++#define CDP_S_LUT_LO_END_LOW_0_WORD_COUNT                                  (0x1)
++#define CDP_S_LUT_LO_END_LOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_LOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_END_LOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_LOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_LOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_END_LOW_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT))
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_RANGE                       (31:0)
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_WOFFSET                      (0x0)
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LO_END_HIGH_0
++#define CDP_S_LUT_LO_END_HIGH_0                         (_MK_ADDR_CONST(0xf034))
++#define CDP_S_LUT_LO_END_HIGH_0_SECURE                                     (0x0)
++#define CDP_S_LUT_LO_END_HIGH_0_DUAL                                       (0x0)
++#define CDP_S_LUT_LO_END_HIGH_0_SCR                                          (0)
++#define CDP_S_LUT_LO_END_HIGH_0_WORD_COUNT                                 (0x1)
++#define CDP_S_LUT_LO_END_HIGH_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_HIGH_0_RESET_MASK                (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LO_END_HIGH_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_HIGH_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_HIGH_0_READ_MASK                 (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LO_END_HIGH_0_WRITE_MASK                (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT       (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_FIELD \
++      (_MK_FIELD_CONST(0x3f, \
++      CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT))
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_RANGE                      (5:0)
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_WOFFSET                    (0x0)
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LE_SLOPE_SCALE_0
++#define CDP_S_LUT_LE_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xf038))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_SECURE                                  (0x0)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_DUAL                                    (0x0)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_SCR                                       (0)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_RANGE         (15:0)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(16))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_RANGE        (31:16)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LE_SLOPE_SHIFT_0
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xf03c))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_SECURE                                  (0x0)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_DUAL                                    (0x0)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_SCR                                       (0)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LO_SLOPE_SCALE_0
++#define CDP_S_LUT_LO_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xf040))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_SECURE                                  (0x0)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_DUAL                                    (0x0)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_SCR                                       (0)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_RANGE         (15:0)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT \
++      (_MK_SHIFT_CONST(16))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, \
++      CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_RANGE        (31:16)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_S_LUT_LO_SLOPE_SHIFT_0
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xf044))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_SECURE                                  (0x0)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_DUAL                                    (0x0)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_SCR                                       (0)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD \
++      (_MK_FIELD_CONST(0x1f, \
++      CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_OP_ENABLE_0
++#define CDP_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0xf048))
++#define CDP_D_OP_ENABLE_0_SECURE                                           (0x0)
++#define CDP_D_OP_ENABLE_0_DUAL                                             (0x0)
++#define CDP_D_OP_ENABLE_0_SCR                                                (0)
++#define CDP_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
++#define CDP_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define CDP_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
++#define CDP_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define CDP_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
++#define CDP_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
++#define CDP_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
++#define CDP_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define CDP_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
++#define CDP_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
++#define CDP_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define CDP_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
++#define CDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define CDP_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define CDP_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
++#define CDP_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
++#define CDP_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
++
++
++// Register CDP_D_FUNC_BYPASS_0
++#define CDP_D_FUNC_BYPASS_0                             (_MK_ADDR_CONST(0xf04c))
++#define CDP_D_FUNC_BYPASS_0_SECURE                                         (0x0)
++#define CDP_D_FUNC_BYPASS_0_DUAL                                           (0x0)
++#define CDP_D_FUNC_BYPASS_0_SCR                                              (0)
++#define CDP_D_FUNC_BYPASS_0_WORD_COUNT                                     (0x1)
++#define CDP_D_FUNC_BYPASS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_RESET_MASK                     (_MK_MASK_CONST(0x3))
++#define CDP_D_FUNC_BYPASS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_READ_MASK                      (_MK_MASK_CONST(0x3))
++#define CDP_D_FUNC_BYPASS_0_WRITE_MASK                     (_MK_MASK_CONST(0x3))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT              (_MK_SHIFT_CONST(0))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_RANGE                             (0:0)
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_WOFFSET                           (0x0)
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_INIT_ENUM                     (DISABLE)
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DISABLE             (_MK_ENUM_CONST(0))
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_ENABLE              (_MK_ENUM_CONST(1))
++
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT                (_MK_SHIFT_CONST(1))
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT))
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_RANGE                               (1:1)
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_WOFFSET                             (0x0)
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SW_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_INIT_ENUM                       (DISABLE)
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DISABLE               (_MK_ENUM_CONST(0))
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_ENABLE                (_MK_ENUM_CONST(1))
++
++
++// Register CDP_D_DST_BASE_ADDR_LOW_0
++#define CDP_D_DST_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xf050))
++#define CDP_D_DST_BASE_ADDR_LOW_0_SECURE                                   (0x0)
++#define CDP_D_DST_BASE_ADDR_LOW_0_DUAL                                     (0x0)
++#define CDP_D_DST_BASE_ADDR_LOW_0_SCR                                        (0)
++#define CDP_D_DST_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
++#define CDP_D_DST_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT))
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_RANGE                 (31:5)
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_WOFFSET                (0x0)
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_DST_BASE_ADDR_HIGH_0
++#define CDP_D_DST_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xf054))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
++#define CDP_D_DST_BASE_ADDR_HIGH_0_SCR                                       (0)
++#define CDP_D_DST_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
++#define CDP_D_DST_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_RANGE               (31:0)
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_WOFFSET              (0x0)
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_DST_LINE_STRIDE_0
++#define CDP_D_DST_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xf058))
++#define CDP_D_DST_LINE_STRIDE_0_SECURE                                     (0x0)
++#define CDP_D_DST_LINE_STRIDE_0_DUAL                                       (0x0)
++#define CDP_D_DST_LINE_STRIDE_0_SCR                                          (0)
++#define CDP_D_DST_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
++#define CDP_D_DST_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define CDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
++#define CDP_D_DST_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT))
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_RANGE                     (31:5)
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_WOFFSET                    (0x0)
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_DST_SURFACE_STRIDE_0
++#define CDP_D_DST_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xf05c))
++#define CDP_D_DST_SURFACE_STRIDE_0_SECURE                                  (0x0)
++#define CDP_D_DST_SURFACE_STRIDE_0_DUAL                                    (0x0)
++#define CDP_D_DST_SURFACE_STRIDE_0_SCR                                       (0)
++#define CDP_D_DST_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
++#define CDP_D_DST_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define CDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define CDP_D_DST_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT))
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_RANGE               (31:5)
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_WOFFSET              (0x0)
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_DST_DMA_CFG_0
++#define CDP_D_DST_DMA_CFG_0                             (_MK_ADDR_CONST(0xf060))
++#define CDP_D_DST_DMA_CFG_0_SECURE                                         (0x0)
++#define CDP_D_DST_DMA_CFG_0_DUAL                                           (0x0)
++#define CDP_D_DST_DMA_CFG_0_SCR                                              (0)
++#define CDP_D_DST_DMA_CFG_0_WORD_COUNT                                     (0x1)
++#define CDP_D_DST_DMA_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_DMA_CFG_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
++#define CDP_D_DST_DMA_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_DMA_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_DMA_CFG_0_READ_MASK                      (_MK_MASK_CONST(0x1))
++#define CDP_D_DST_DMA_CFG_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT              (_MK_SHIFT_CONST(0))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_RANGE                             (0:0)
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_WOFFSET                           (0x0)
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT           (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV                  (_MK_ENUM_CONST(0))
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC                  (_MK_ENUM_CONST(1))
++
++
++// Register CDP_D_DST_COMPRESSION_EN_0
++#define CDP_D_DST_COMPRESSION_EN_0                      (_MK_ADDR_CONST(0xf064))
++#define CDP_D_DST_COMPRESSION_EN_0_SECURE                                  (0x0)
++#define CDP_D_DST_COMPRESSION_EN_0_DUAL                                    (0x0)
++#define CDP_D_DST_COMPRESSION_EN_0_SCR                                       (0)
++#define CDP_D_DST_COMPRESSION_EN_0_WORD_COUNT                              (0x1)
++#define CDP_D_DST_COMPRESSION_EN_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_COMPRESSION_EN_0_RESET_MASK              (_MK_MASK_CONST(0x1))
++#define CDP_D_DST_COMPRESSION_EN_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_COMPRESSION_EN_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_COMPRESSION_EN_0_READ_MASK               (_MK_MASK_CONST(0x1))
++#define CDP_D_DST_COMPRESSION_EN_0_WRITE_MASK              (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT \
++      (_MK_SHIFT_CONST(0))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, \
++      CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_RANGE                (0:0)
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_WOFFSET              (0x0)
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DISABLE \
++      (_MK_ENUM_CONST(0))
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_ENABLE \
++      (_MK_ENUM_CONST(1))
++
++
++// Register CDP_D_DATA_FORMAT_0
++#define CDP_D_DATA_FORMAT_0                             (_MK_ADDR_CONST(0xf068))
++#define CDP_D_DATA_FORMAT_0_SECURE                                         (0x0)
++#define CDP_D_DATA_FORMAT_0_DUAL                                           (0x0)
++#define CDP_D_DATA_FORMAT_0_SCR                                              (0)
++#define CDP_D_DATA_FORMAT_0_WORD_COUNT                                     (0x1)
++#define CDP_D_DATA_FORMAT_0_RESET_VAL                      (_MK_MASK_CONST(0x1))
++#define CDP_D_DATA_FORMAT_0_RESET_MASK                     (_MK_MASK_CONST(0x3))
++#define CDP_D_DATA_FORMAT_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_D_DATA_FORMAT_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define CDP_D_DATA_FORMAT_0_READ_MASK                      (_MK_MASK_CONST(0x3))
++#define CDP_D_DATA_FORMAT_0_WRITE_MASK                     (_MK_MASK_CONST(0x3))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT           (_MK_SHIFT_CONST(0))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x3, CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_RANGE                          (1:0)
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_WOFFSET                        (0x0)
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_DEFAULT        (_MK_MASK_CONST(0x1))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT8             (_MK_ENUM_CONST(0))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT16            (_MK_ENUM_CONST(1))
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FP16             (_MK_ENUM_CONST(2))
++
++
++// Register CDP_D_NAN_FLUSH_TO_ZERO_0
++#define CDP_D_NAN_FLUSH_TO_ZERO_0                       (_MK_ADDR_CONST(0xf06c))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_SECURE                                   (0x0)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_DUAL                                     (0x0)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_SCR                                        (0)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_WORD_COUNT                               (0x1)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_RESET_MASK               (_MK_MASK_CONST(0x1))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_READ_MASK                (_MK_MASK_CONST(0x1))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_WRITE_MASK               (_MK_MASK_CONST(0x1))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_RANGE                        (0:0)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_WOFFSET                      (0x0)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_INIT_ENUM                (DISABLE)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE        (_MK_ENUM_CONST(0))
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE         (_MK_ENUM_CONST(1))
++
++
++// Register CDP_D_LRN_CFG_0
++#define CDP_D_LRN_CFG_0                                 (_MK_ADDR_CONST(0xf070))
++#define CDP_D_LRN_CFG_0_SECURE                                             (0x0)
++#define CDP_D_LRN_CFG_0_DUAL                                               (0x0)
++#define CDP_D_LRN_CFG_0_SCR                                                  (0)
++#define CDP_D_LRN_CFG_0_WORD_COUNT                                         (0x1)
++#define CDP_D_LRN_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define CDP_D_LRN_CFG_0_RESET_MASK                         (_MK_MASK_CONST(0x3))
++#define CDP_D_LRN_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define CDP_D_LRN_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CDP_D_LRN_CFG_0_READ_MASK                          (_MK_MASK_CONST(0x3))
++#define CDP_D_LRN_CFG_0_WRITE_MASK                         (_MK_MASK_CONST(0x3))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT                   (_MK_SHIFT_CONST(0))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_FIELD \
++      (_MK_FIELD_CONST(0x3, CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_RANGE                                  (1:0)
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_WOFFSET                                (0x0)
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_DEFAULT                (_MK_MASK_CONST(0x0))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_DEFAULT_MASK           (_MK_MASK_CONST(0x3))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN3                     (_MK_ENUM_CONST(0))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN5                     (_MK_ENUM_CONST(1))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN7                     (_MK_ENUM_CONST(2))
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9                     (_MK_ENUM_CONST(3))
++
++
++// Register CDP_D_DATIN_OFFSET_0
++#define CDP_D_DATIN_OFFSET_0                            (_MK_ADDR_CONST(0xf074))
++#define CDP_D_DATIN_OFFSET_0_SECURE                                        (0x0)
++#define CDP_D_DATIN_OFFSET_0_DUAL                                          (0x0)
++#define CDP_D_DATIN_OFFSET_0_SCR                                             (0)
++#define CDP_D_DATIN_OFFSET_0_WORD_COUNT                                    (0x1)
++#define CDP_D_DATIN_OFFSET_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_OFFSET_0_RESET_MASK                 (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATIN_OFFSET_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_OFFSET_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_OFFSET_0_READ_MASK                  (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATIN_OFFSET_0_WRITE_MASK                 (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT             (_MK_SHIFT_CONST(0))
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT))
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_RANGE                           (15:0)
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_WOFFSET                          (0x0)
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_DEFAULT          (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_DATIN_SCALE_0
++#define CDP_D_DATIN_SCALE_0                             (_MK_ADDR_CONST(0xf078))
++#define CDP_D_DATIN_SCALE_0_SECURE                                         (0x0)
++#define CDP_D_DATIN_SCALE_0_DUAL                                           (0x0)
++#define CDP_D_DATIN_SCALE_0_SCR                                              (0)
++#define CDP_D_DATIN_SCALE_0_WORD_COUNT                                     (0x1)
++#define CDP_D_DATIN_SCALE_0_RESET_VAL                      (_MK_MASK_CONST(0x1))
++#define CDP_D_DATIN_SCALE_0_RESET_MASK                  (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATIN_SCALE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SCALE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SCALE_0_READ_MASK                   (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATIN_SCALE_0_WRITE_MASK                  (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT               (_MK_SHIFT_CONST(0))
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT))
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_RANGE                             (15:0)
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_WOFFSET                            (0x0)
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_DEFAULT            (_MK_MASK_CONST(0x1))
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_DEFAULT_MASK    (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SW_DEFAULT         (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_DATIN_SHIFTER_0
++#define CDP_D_DATIN_SHIFTER_0                           (_MK_ADDR_CONST(0xf07c))
++#define CDP_D_DATIN_SHIFTER_0_SECURE                                       (0x0)
++#define CDP_D_DATIN_SHIFTER_0_DUAL                                         (0x0)
++#define CDP_D_DATIN_SHIFTER_0_SCR                                            (0)
++#define CDP_D_DATIN_SHIFTER_0_WORD_COUNT                                   (0x1)
++#define CDP_D_DATIN_SHIFTER_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SHIFTER_0_RESET_MASK                  (_MK_MASK_CONST(0x1f))
++#define CDP_D_DATIN_SHIFTER_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SHIFTER_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SHIFTER_0_READ_MASK                   (_MK_MASK_CONST(0x1f))
++#define CDP_D_DATIN_SHIFTER_0_WRITE_MASK                  (_MK_MASK_CONST(0x1f))
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT           (_MK_SHIFT_CONST(0))
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_FIELD \
++      (_MK_FIELD_CONST(0x1f, CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT))
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_RANGE                          (4:0)
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_WOFFSET                        (0x0)
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_DATOUT_OFFSET_0
++#define CDP_D_DATOUT_OFFSET_0                           (_MK_ADDR_CONST(0xf080))
++#define CDP_D_DATOUT_OFFSET_0_SECURE                                       (0x0)
++#define CDP_D_DATOUT_OFFSET_0_DUAL                                         (0x0)
++#define CDP_D_DATOUT_OFFSET_0_SCR                                            (0)
++#define CDP_D_DATOUT_OFFSET_0_WORD_COUNT                                   (0x1)
++#define CDP_D_DATOUT_OFFSET_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_OFFSET_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_DATOUT_OFFSET_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_OFFSET_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_OFFSET_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_DATOUT_OFFSET_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT           (_MK_SHIFT_CONST(0))
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT))
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_RANGE                         (31:0)
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_WOFFSET                        (0x0)
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_DATOUT_SCALE_0
++#define CDP_D_DATOUT_SCALE_0                            (_MK_ADDR_CONST(0xf084))
++#define CDP_D_DATOUT_SCALE_0_SECURE                                        (0x0)
++#define CDP_D_DATOUT_SCALE_0_DUAL                                          (0x0)
++#define CDP_D_DATOUT_SCALE_0_SCR                                             (0)
++#define CDP_D_DATOUT_SCALE_0_WORD_COUNT                                    (0x1)
++#define CDP_D_DATOUT_SCALE_0_RESET_VAL                     (_MK_MASK_CONST(0x1))
++#define CDP_D_DATOUT_SCALE_0_RESET_MASK                 (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATOUT_SCALE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SCALE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SCALE_0_READ_MASK                  (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATOUT_SCALE_0_WRITE_MASK                 (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT             (_MK_SHIFT_CONST(0))
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_FIELD \
++      (_MK_FIELD_CONST(0xffff, CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT))
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_RANGE                           (15:0)
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_WOFFSET                          (0x0)
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_DEFAULT          (_MK_MASK_CONST(0x1))
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffff))
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SW_DEFAULT       (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_DATOUT_SHIFTER_0
++#define CDP_D_DATOUT_SHIFTER_0                          (_MK_ADDR_CONST(0xf088))
++#define CDP_D_DATOUT_SHIFTER_0_SECURE                                      (0x0)
++#define CDP_D_DATOUT_SHIFTER_0_DUAL                                        (0x0)
++#define CDP_D_DATOUT_SHIFTER_0_SCR                                           (0)
++#define CDP_D_DATOUT_SHIFTER_0_WORD_COUNT                                  (0x1)
++#define CDP_D_DATOUT_SHIFTER_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SHIFTER_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
++#define CDP_D_DATOUT_SHIFTER_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SHIFTER_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SHIFTER_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
++#define CDP_D_DATOUT_SHIFTER_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_FIELD \
++      (_MK_FIELD_CONST(0x3f, CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT))
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_RANGE                        (5:0)
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_WOFFSET                      (0x0)
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x3f))
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_NAN_INPUT_NUM_0
++#define CDP_D_NAN_INPUT_NUM_0                           (_MK_ADDR_CONST(0xf08c))
++#define CDP_D_NAN_INPUT_NUM_0_SECURE                                       (0x0)
++#define CDP_D_NAN_INPUT_NUM_0_DUAL                                         (0x0)
++#define CDP_D_NAN_INPUT_NUM_0_SCR                                            (0)
++#define CDP_D_NAN_INPUT_NUM_0_WORD_COUNT                                   (0x1)
++#define CDP_D_NAN_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_NAN_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT))
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_RANGE                         (31:0)
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_WOFFSET                        (0x0)
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_INF_INPUT_NUM_0
++#define CDP_D_INF_INPUT_NUM_0                           (_MK_ADDR_CONST(0xf090))
++#define CDP_D_INF_INPUT_NUM_0_SECURE                                       (0x0)
++#define CDP_D_INF_INPUT_NUM_0_DUAL                                         (0x0)
++#define CDP_D_INF_INPUT_NUM_0_SCR                                            (0)
++#define CDP_D_INF_INPUT_NUM_0_WORD_COUNT                                   (0x1)
++#define CDP_D_INF_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define CDP_D_INF_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_INF_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define CDP_D_INF_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define CDP_D_INF_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_INF_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT))
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_RANGE                         (31:0)
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_WOFFSET                        (0x0)
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_NAN_OUTPUT_NUM_0
++#define CDP_D_NAN_OUTPUT_NUM_0                          (_MK_ADDR_CONST(0xf094))
++#define CDP_D_NAN_OUTPUT_NUM_0_SECURE                                      (0x0)
++#define CDP_D_NAN_OUTPUT_NUM_0_DUAL                                        (0x0)
++#define CDP_D_NAN_OUTPUT_NUM_0_SCR                                           (0)
++#define CDP_D_NAN_OUTPUT_NUM_0_WORD_COUNT                                  (0x1)
++#define CDP_D_NAN_OUTPUT_NUM_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_OUTPUT_NUM_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_OUTPUT_NUM_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_NAN_OUTPUT_NUM_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT))
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_RANGE                       (31:0)
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_WOFFSET                      (0x0)
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_OUT_SATURATION_0
++#define CDP_D_OUT_SATURATION_0                          (_MK_ADDR_CONST(0xf098))
++#define CDP_D_OUT_SATURATION_0_SECURE                                      (0x0)
++#define CDP_D_OUT_SATURATION_0_DUAL                                        (0x0)
++#define CDP_D_OUT_SATURATION_0_SCR                                           (0)
++#define CDP_D_OUT_SATURATION_0_WORD_COUNT                                  (0x1)
++#define CDP_D_OUT_SATURATION_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_D_OUT_SATURATION_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_OUT_SATURATION_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_D_OUT_SATURATION_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_D_OUT_SATURATION_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_OUT_SATURATION_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT))
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_RANGE                       (31:0)
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_WOFFSET                      (0x0)
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_PERF_ENABLE_0
++#define CDP_D_PERF_ENABLE_0                             (_MK_ADDR_CONST(0xf09c))
++#define CDP_D_PERF_ENABLE_0_SECURE                                         (0x0)
++#define CDP_D_PERF_ENABLE_0_DUAL                                           (0x0)
++#define CDP_D_PERF_ENABLE_0_SCR                                              (0)
++#define CDP_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
++#define CDP_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0x3))
++#define CDP_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0x3))
++#define CDP_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0x3))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT                    (_MK_SHIFT_CONST(0))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_RANGE                                   (0:0)
++#define CDP_D_PERF_ENABLE_0_DMA_EN_WOFFSET                                 (0x0)
++#define CDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                           (DISABLE)
++#define CDP_D_PERF_ENABLE_0_DMA_EN_DISABLE                   (_MK_ENUM_CONST(0))
++#define CDP_D_PERF_ENABLE_0_DMA_EN_ENABLE                    (_MK_ENUM_CONST(1))
++
++#define CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT                    (_MK_SHIFT_CONST(1))
++#define CDP_D_PERF_ENABLE_0_LUT_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT))
++#define CDP_D_PERF_ENABLE_0_LUT_EN_RANGE                                   (1:1)
++#define CDP_D_PERF_ENABLE_0_LUT_EN_WOFFSET                                 (0x0)
++#define CDP_D_PERF_ENABLE_0_LUT_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_LUT_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
++#define CDP_D_PERF_ENABLE_0_LUT_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_LUT_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_LUT_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_ENABLE_0_LUT_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
++#define CDP_D_PERF_ENABLE_0_LUT_EN_INIT_ENUM                           (DISABLE)
++#define CDP_D_PERF_ENABLE_0_LUT_EN_DISABLE                   (_MK_ENUM_CONST(0))
++#define CDP_D_PERF_ENABLE_0_LUT_EN_ENABLE                    (_MK_ENUM_CONST(1))
++
++
++// Register CDP_D_PERF_WRITE_STALL_0
++#define CDP_D_PERF_WRITE_STALL_0                        (_MK_ADDR_CONST(0xf0a0))
++#define CDP_D_PERF_WRITE_STALL_0_SECURE                                    (0x0)
++#define CDP_D_PERF_WRITE_STALL_0_DUAL                                      (0x0)
++#define CDP_D_PERF_WRITE_STALL_0_SCR                                         (0)
++#define CDP_D_PERF_WRITE_STALL_0_WORD_COUNT                                (0x1)
++#define CDP_D_PERF_WRITE_STALL_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_WRITE_STALL_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_WRITE_STALL_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_WRITE_STALL_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT     (_MK_SHIFT_CONST(0))
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT))
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_RANGE                   (31:0)
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_WOFFSET                  (0x0)
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_PERF_LUT_UFLOW_0
++#define CDP_D_PERF_LUT_UFLOW_0                          (_MK_ADDR_CONST(0xf0a4))
++#define CDP_D_PERF_LUT_UFLOW_0_SECURE                                      (0x0)
++#define CDP_D_PERF_LUT_UFLOW_0_DUAL                                        (0x0)
++#define CDP_D_PERF_LUT_UFLOW_0_SCR                                           (0)
++#define CDP_D_PERF_LUT_UFLOW_0_WORD_COUNT                                  (0x1)
++#define CDP_D_PERF_LUT_UFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_UFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_UFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_UFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT))
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_RANGE                       (31:0)
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_WOFFSET                      (0x0)
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_PERF_LUT_OFLOW_0
++#define CDP_D_PERF_LUT_OFLOW_0                          (_MK_ADDR_CONST(0xf0a8))
++#define CDP_D_PERF_LUT_OFLOW_0_SECURE                                      (0x0)
++#define CDP_D_PERF_LUT_OFLOW_0_DUAL                                        (0x0)
++#define CDP_D_PERF_LUT_OFLOW_0_SCR                                           (0)
++#define CDP_D_PERF_LUT_OFLOW_0_WORD_COUNT                                  (0x1)
++#define CDP_D_PERF_LUT_OFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_OFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_OFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_OFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT         (_MK_SHIFT_CONST(0))
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT))
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_RANGE                       (31:0)
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_WOFFSET                      (0x0)
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_PERF_LUT_HYBRID_0
++#define CDP_D_PERF_LUT_HYBRID_0                         (_MK_ADDR_CONST(0xf0ac))
++#define CDP_D_PERF_LUT_HYBRID_0_SECURE                                     (0x0)
++#define CDP_D_PERF_LUT_HYBRID_0_DUAL                                       (0x0)
++#define CDP_D_PERF_LUT_HYBRID_0_SCR                                          (0)
++#define CDP_D_PERF_LUT_HYBRID_0_WORD_COUNT                                 (0x1)
++#define CDP_D_PERF_LUT_HYBRID_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_HYBRID_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_HYBRID_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_HYBRID_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT       (_MK_SHIFT_CONST(0))
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT))
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_RANGE                     (31:0)
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_WOFFSET                    (0x0)
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_PERF_LUT_LE_HIT_0
++#define CDP_D_PERF_LUT_LE_HIT_0                         (_MK_ADDR_CONST(0xf0b0))
++#define CDP_D_PERF_LUT_LE_HIT_0_SECURE                                     (0x0)
++#define CDP_D_PERF_LUT_LE_HIT_0_DUAL                                       (0x0)
++#define CDP_D_PERF_LUT_LE_HIT_0_SCR                                          (0)
++#define CDP_D_PERF_LUT_LE_HIT_0_WORD_COUNT                                 (0x1)
++#define CDP_D_PERF_LUT_LE_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LE_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LE_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_LE_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT       (_MK_SHIFT_CONST(0))
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT))
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_RANGE                     (31:0)
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_WOFFSET                    (0x0)
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_PERF_LUT_LO_HIT_0
++#define CDP_D_PERF_LUT_LO_HIT_0                         (_MK_ADDR_CONST(0xf0b4))
++#define CDP_D_PERF_LUT_LO_HIT_0_SECURE                                     (0x0)
++#define CDP_D_PERF_LUT_LO_HIT_0_DUAL                                       (0x0)
++#define CDP_D_PERF_LUT_LO_HIT_0_SCR                                          (0)
++#define CDP_D_PERF_LUT_LO_HIT_0_WORD_COUNT                                 (0x1)
++#define CDP_D_PERF_LUT_LO_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LO_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LO_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_LO_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT       (_MK_SHIFT_CONST(0))
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT))
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_RANGE                     (31:0)
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_WOFFSET                    (0x0)
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_DEFAULT    (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register CDP_D_CYA_0
++#define CDP_D_CYA_0                                     (_MK_ADDR_CONST(0xf0b8))
++#define CDP_D_CYA_0_SECURE                                                 (0x0)
++#define CDP_D_CYA_0_DUAL                                                   (0x0)
++#define CDP_D_CYA_0_SCR                                                      (0)
++#define CDP_D_CYA_0_WORD_COUNT                                             (0x1)
++#define CDP_D_CYA_0_RESET_VAL                              (_MK_MASK_CONST(0x0))
++#define CDP_D_CYA_0_RESET_MASK                      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_CYA_0_SW_DEFAULT_VAL                         (_MK_MASK_CONST(0x0))
++#define CDP_D_CYA_0_SW_DEFAULT_MASK                        (_MK_MASK_CONST(0x0))
++#define CDP_D_CYA_0_READ_MASK                       (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_CYA_0_WRITE_MASK                      (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_CYA_0_CYA_SHIFT                               (_MK_SHIFT_CONST(0))
++#define CDP_D_CYA_0_CYA_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, CDP_D_CYA_0_CYA_SHIFT))
++#define CDP_D_CYA_0_CYA_RANGE                                             (31:0)
++#define CDP_D_CYA_0_CYA_WOFFSET                                            (0x0)
++#define CDP_D_CYA_0_CYA_DEFAULT                            (_MK_MASK_CONST(0x0))
++#define CDP_D_CYA_0_CYA_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff))
++#define CDP_D_CYA_0_CYA_SW_DEFAULT                         (_MK_MASK_CONST(0x0))
++#define CDP_D_CYA_0_CYA_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define CDP_D_CYA_0_CYA_PARITY_PROTECTION                  (_MK_MASK_CONST(0x0))
++#define CDP_D_CYA_0_CYA_PLATFORM_DEPENDENT                 (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_S_STATUS_0
++#define RBK_S_STATUS_0                                 (_MK_ADDR_CONST(0x10000))
++#define RBK_S_STATUS_0_SECURE                                              (0x0)
++#define RBK_S_STATUS_0_DUAL                                                (0x0)
++#define RBK_S_STATUS_0_SCR                                                   (0)
++#define RBK_S_STATUS_0_WORD_COUNT                                          (0x1)
++#define RBK_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
++#define RBK_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
++#define RBK_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
++#define RBK_S_STATUS_0_STATUS_0_FIELD \
++      (_MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_0_SHIFT))
++#define RBK_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
++#define RBK_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
++#define RBK_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define RBK_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define RBK_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
++#define RBK_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
++#define RBK_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
++#define RBK_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
++
++#define RBK_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
++#define RBK_S_STATUS_0_STATUS_1_FIELD \
++      (_MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_1_SHIFT))
++#define RBK_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
++#define RBK_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
++#define RBK_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
++#define RBK_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define RBK_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define RBK_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
++#define RBK_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
++#define RBK_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
++#define RBK_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
++
++
++// Register RBK_S_POINTER_0
++#define RBK_S_POINTER_0                                (_MK_ADDR_CONST(0x10004))
++#define RBK_S_POINTER_0_SECURE                                             (0x0)
++#define RBK_S_POINTER_0_DUAL                                               (0x0)
++#define RBK_S_POINTER_0_SCR                                                  (0)
++#define RBK_S_POINTER_0_WORD_COUNT                                         (0x1)
++#define RBK_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
++#define RBK_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
++#define RBK_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
++#define RBK_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
++#define RBK_S_POINTER_0_PRODUCER_FIELD \
++      (_MK_FIELD_CONST(0x1, RBK_S_POINTER_0_PRODUCER_SHIFT))
++#define RBK_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
++#define RBK_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
++#define RBK_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define RBK_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define RBK_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
++#define RBK_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define RBK_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++#define RBK_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
++#define RBK_S_POINTER_0_CONSUMER_FIELD \
++      (_MK_FIELD_CONST(0x1, RBK_S_POINTER_0_CONSUMER_SHIFT))
++#define RBK_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
++#define RBK_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
++#define RBK_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
++#define RBK_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
++#define RBK_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
++#define RBK_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
++#define RBK_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
++#define RBK_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
++
++
++// Register RBK_D_OP_ENABLE_0
++#define RBK_D_OP_ENABLE_0                              (_MK_ADDR_CONST(0x10008))
++#define RBK_D_OP_ENABLE_0_SECURE                                           (0x0)
++#define RBK_D_OP_ENABLE_0_DUAL                                             (0x0)
++#define RBK_D_OP_ENABLE_0_SCR                                                (0)
++#define RBK_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
++#define RBK_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
++#define RBK_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
++#define RBK_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
++#define RBK_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
++#define RBK_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
++#define RBK_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
++#define RBK_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
++#define RBK_D_OP_ENABLE_0_OP_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, RBK_D_OP_ENABLE_0_OP_EN_SHIFT))
++#define RBK_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
++#define RBK_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
++#define RBK_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
++#define RBK_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
++#define RBK_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
++#define RBK_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define RBK_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
++#define RBK_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
++#define RBK_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
++#define RBK_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
++#define RBK_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
++
++
++// Register RBK_D_MISC_CFG_0
++#define RBK_D_MISC_CFG_0                               (_MK_ADDR_CONST(0x1000c))
++#define RBK_D_MISC_CFG_0_SECURE                                            (0x0)
++#define RBK_D_MISC_CFG_0_DUAL                                              (0x0)
++#define RBK_D_MISC_CFG_0_SCR                                                 (0)
++#define RBK_D_MISC_CFG_0_WORD_COUNT                                        (0x1)
++#define RBK_D_MISC_CFG_0_RESET_VAL                       (_MK_MASK_CONST(0x100))
++#define RBK_D_MISC_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x303))
++#define RBK_D_MISC_CFG_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
++#define RBK_D_MISC_CFG_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
++#define RBK_D_MISC_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x303))
++#define RBK_D_MISC_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x303))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT                   (_MK_SHIFT_CONST(0))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_FIELD \
++      (_MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_RANGE                                  (1:0)
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_WOFFSET                                (0x0)
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_DEFAULT                (_MK_MASK_CONST(0x0))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_DEFAULT_MASK           (_MK_MASK_CONST(0x3))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_INIT_ENUM                         (CONTRACT)
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_CONTRACT                 (_MK_ENUM_CONST(0))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_SPLIT                    (_MK_ENUM_CONST(1))
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE                    (_MK_ENUM_CONST(2))
++
++#define RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT                 (_MK_SHIFT_CONST(8))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_FIELD \
++      (_MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_RANGE                                (9:8)
++#define RBK_D_MISC_CFG_0_IN_PRECISION_WOFFSET                              (0x0)
++#define RBK_D_MISC_CFG_0_IN_PRECISION_DEFAULT              (_MK_MASK_CONST(0x1))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT           (_MK_MASK_CONST(0x0))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_INIT_ENUM                          (INT16)
++#define RBK_D_MISC_CFG_0_IN_PRECISION_INT8                   (_MK_ENUM_CONST(0))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_INT16                  (_MK_ENUM_CONST(1))
++#define RBK_D_MISC_CFG_0_IN_PRECISION_FP16                   (_MK_ENUM_CONST(2))
++
++
++// Register RBK_D_DAIN_RAM_TYPE_0
++#define RBK_D_DAIN_RAM_TYPE_0                          (_MK_ADDR_CONST(0x10010))
++#define RBK_D_DAIN_RAM_TYPE_0_SECURE                                       (0x0)
++#define RBK_D_DAIN_RAM_TYPE_0_DUAL                                         (0x0)
++#define RBK_D_DAIN_RAM_TYPE_0_SCR                                            (0)
++#define RBK_D_DAIN_RAM_TYPE_0_WORD_COUNT                                   (0x1)
++#define RBK_D_DAIN_RAM_TYPE_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_RAM_TYPE_0_RESET_MASK                   (_MK_MASK_CONST(0x1))
++#define RBK_D_DAIN_RAM_TYPE_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_RAM_TYPE_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_RAM_TYPE_0_READ_MASK                    (_MK_MASK_CONST(0x1))
++#define RBK_D_DAIN_RAM_TYPE_0_WRITE_MASK                   (_MK_MASK_CONST(0x1))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_RANGE                        (0:0)
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_WOFFSET                      (0x0)
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_INIT_ENUM                   (CVIF)
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF           (_MK_ENUM_CONST(0))
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF           (_MK_ENUM_CONST(1))
++
++
++// Register RBK_D_DATAIN_SIZE_0_0
++#define RBK_D_DATAIN_SIZE_0_0                          (_MK_ADDR_CONST(0x10014))
++#define RBK_D_DATAIN_SIZE_0_0_SECURE                                       (0x0)
++#define RBK_D_DATAIN_SIZE_0_0_DUAL                                         (0x0)
++#define RBK_D_DATAIN_SIZE_0_0_SCR                                            (0)
++#define RBK_D_DATAIN_SIZE_0_0_WORD_COUNT                                   (0x1)
++#define RBK_D_DATAIN_SIZE_0_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_RESET_MASK            (_MK_MASK_CONST(0x1fff1fff))
++#define RBK_D_DATAIN_SIZE_0_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_READ_MASK             (_MK_MASK_CONST(0x1fff1fff))
++#define RBK_D_DATAIN_SIZE_0_0_WRITE_MASK            (_MK_MASK_CONST(0x1fff1fff))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT            (_MK_SHIFT_CONST(0))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD \
++      (_MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_RANGE                          (12:0)
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_WOFFSET                         (0x0)
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT         (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT          (_MK_SHIFT_CONST(16))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD \
++      (_MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_RANGE                        (28:16)
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_WOFFSET                        (0x0)
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT        (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DATAIN_SIZE_1_0
++#define RBK_D_DATAIN_SIZE_1_0                          (_MK_ADDR_CONST(0x10018))
++#define RBK_D_DATAIN_SIZE_1_0_SECURE                                       (0x0)
++#define RBK_D_DATAIN_SIZE_1_0_DUAL                                         (0x0)
++#define RBK_D_DATAIN_SIZE_1_0_SCR                                            (0)
++#define RBK_D_DATAIN_SIZE_1_0_WORD_COUNT                                   (0x1)
++#define RBK_D_DATAIN_SIZE_1_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_1_0_RESET_MASK                (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAIN_SIZE_1_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_1_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_1_0_READ_MASK                 (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAIN_SIZE_1_0_WRITE_MASK                (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT          (_MK_SHIFT_CONST(0))
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT))
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_RANGE                        (12:0)
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_WOFFSET                       (0x0)
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT       (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAIN_ADDR_HIGH_0
++#define RBK_D_DAIN_ADDR_HIGH_0                         (_MK_ADDR_CONST(0x1001c))
++#define RBK_D_DAIN_ADDR_HIGH_0_SECURE                                      (0x0)
++#define RBK_D_DAIN_ADDR_HIGH_0_DUAL                                        (0x0)
++#define RBK_D_DAIN_ADDR_HIGH_0_SCR                                           (0)
++#define RBK_D_DAIN_ADDR_HIGH_0_WORD_COUNT                                  (0x1)
++#define RBK_D_DAIN_ADDR_HIGH_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_HIGH_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_DAIN_ADDR_HIGH_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_HIGH_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_HIGH_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_DAIN_ADDR_HIGH_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT         (_MK_SHIFT_CONST(0))
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT))
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_RANGE                       (31:0)
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_WOFFSET                      (0x0)
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_DEFAULT      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAIN_ADDR_LOW_0
++#define RBK_D_DAIN_ADDR_LOW_0                          (_MK_ADDR_CONST(0x10020))
++#define RBK_D_DAIN_ADDR_LOW_0_SECURE                                       (0x0)
++#define RBK_D_DAIN_ADDR_LOW_0_DUAL                                         (0x0)
++#define RBK_D_DAIN_ADDR_LOW_0_SCR                                            (0)
++#define RBK_D_DAIN_ADDR_LOW_0_WORD_COUNT                                   (0x1)
++#define RBK_D_DAIN_ADDR_LOW_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_LOW_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_ADDR_LOW_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_LOW_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_LOW_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_ADDR_LOW_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT           (_MK_SHIFT_CONST(5))
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT))
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_RANGE                         (31:5)
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_WOFFSET                        (0x0)
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_DEFAULT        (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SW_DEFAULT     (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAIN_LINE_STRIDE_0
++#define RBK_D_DAIN_LINE_STRIDE_0                       (_MK_ADDR_CONST(0x10024))
++#define RBK_D_DAIN_LINE_STRIDE_0_SECURE                                    (0x0)
++#define RBK_D_DAIN_LINE_STRIDE_0_DUAL                                      (0x0)
++#define RBK_D_DAIN_LINE_STRIDE_0_SCR                                         (0)
++#define RBK_D_DAIN_LINE_STRIDE_0_WORD_COUNT                                (0x1)
++#define RBK_D_DAIN_LINE_STRIDE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_LINE_STRIDE_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_LINE_STRIDE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_LINE_STRIDE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_LINE_STRIDE_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_LINE_STRIDE_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT     (_MK_SHIFT_CONST(5))
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT))
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_RANGE                   (31:5)
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_WOFFSET                  (0x0)
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAIN_SURF_STRIDE_0
++#define RBK_D_DAIN_SURF_STRIDE_0                       (_MK_ADDR_CONST(0x10028))
++#define RBK_D_DAIN_SURF_STRIDE_0_SECURE                                    (0x0)
++#define RBK_D_DAIN_SURF_STRIDE_0_DUAL                                      (0x0)
++#define RBK_D_DAIN_SURF_STRIDE_0_SCR                                         (0)
++#define RBK_D_DAIN_SURF_STRIDE_0_WORD_COUNT                                (0x1)
++#define RBK_D_DAIN_SURF_STRIDE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_SURF_STRIDE_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_SURF_STRIDE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_SURF_STRIDE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_SURF_STRIDE_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_SURF_STRIDE_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT     (_MK_SHIFT_CONST(5))
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT))
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_RANGE                   (31:5)
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_WOFFSET                  (0x0)
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAIN_PLANAR_STRIDE_0
++#define RBK_D_DAIN_PLANAR_STRIDE_0                     (_MK_ADDR_CONST(0x1002c))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_SECURE                                  (0x0)
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DUAL                                    (0x0)
++#define RBK_D_DAIN_PLANAR_STRIDE_0_SCR                                       (0)
++#define RBK_D_DAIN_PLANAR_STRIDE_0_WORD_COUNT                              (0x1)
++#define RBK_D_DAIN_PLANAR_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_RANGE               (31:5)
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_WOFFSET              (0x0)
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAOUT_RAM_TYPE_0
++#define RBK_D_DAOUT_RAM_TYPE_0                         (_MK_ADDR_CONST(0x10030))
++#define RBK_D_DAOUT_RAM_TYPE_0_SECURE                                      (0x0)
++#define RBK_D_DAOUT_RAM_TYPE_0_DUAL                                        (0x0)
++#define RBK_D_DAOUT_RAM_TYPE_0_SCR                                           (0)
++#define RBK_D_DAOUT_RAM_TYPE_0_WORD_COUNT                                  (0x1)
++#define RBK_D_DAOUT_RAM_TYPE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_RAM_TYPE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
++#define RBK_D_DAOUT_RAM_TYPE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_RAM_TYPE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_RAM_TYPE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
++#define RBK_D_DAOUT_RAM_TYPE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT       (_MK_SHIFT_CONST(0))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_FIELD \
++      (_MK_FIELD_CONST(0x1, RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_RANGE                      (0:0)
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_WOFFSET                    (0x0)
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_DEFAULT    (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_INIT_ENUM                 (CVIF)
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_CVIF         (_MK_ENUM_CONST(0))
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_MCIF         (_MK_ENUM_CONST(1))
++
++
++// Register RBK_D_DATAOUT_SIZE_1_0
++#define RBK_D_DATAOUT_SIZE_1_0                         (_MK_ADDR_CONST(0x10034))
++#define RBK_D_DATAOUT_SIZE_1_0_SECURE                                      (0x0)
++#define RBK_D_DATAOUT_SIZE_1_0_DUAL                                        (0x0)
++#define RBK_D_DATAOUT_SIZE_1_0_SCR                                           (0)
++#define RBK_D_DATAOUT_SIZE_1_0_WORD_COUNT                                  (0x1)
++#define RBK_D_DATAOUT_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAOUT_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAOUT_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAOUT_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAOUT_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAOUT_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD \
++      (_MK_FIELD_CONST(0x1fff, \
++      RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT))
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_RANGE                      (12:0)
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_WOFFSET                     (0x0)
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1fff))
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAOUT_ADDR_HIGH_0
++#define RBK_D_DAOUT_ADDR_HIGH_0                        (_MK_ADDR_CONST(0x10038))
++#define RBK_D_DAOUT_ADDR_HIGH_0_SECURE                                     (0x0)
++#define RBK_D_DAOUT_ADDR_HIGH_0_DUAL                                       (0x0)
++#define RBK_D_DAOUT_ADDR_HIGH_0_SCR                                          (0)
++#define RBK_D_DAOUT_ADDR_HIGH_0_WORD_COUNT                                 (0x1)
++#define RBK_D_DAOUT_ADDR_HIGH_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_HIGH_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_DAOUT_ADDR_HIGH_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_HIGH_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_HIGH_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_DAOUT_ADDR_HIGH_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT       (_MK_SHIFT_CONST(0))
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT))
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_RANGE                     (31:0)
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_WOFFSET                    (0x0)
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_DEFAULT    (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAOUT_ADDR_LOW_0
++#define RBK_D_DAOUT_ADDR_LOW_0                         (_MK_ADDR_CONST(0x1003c))
++#define RBK_D_DAOUT_ADDR_LOW_0_SECURE                                      (0x0)
++#define RBK_D_DAOUT_ADDR_LOW_0_DUAL                                        (0x0)
++#define RBK_D_DAOUT_ADDR_LOW_0_SCR                                           (0)
++#define RBK_D_DAOUT_ADDR_LOW_0_WORD_COUNT                                  (0x1)
++#define RBK_D_DAOUT_ADDR_LOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_LOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_ADDR_LOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_LOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_LOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_ADDR_LOW_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT         (_MK_SHIFT_CONST(5))
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT))
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_RANGE                       (31:5)
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_WOFFSET                      (0x0)
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_DEFAULT      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAOUT_LINE_STRIDE_0
++#define RBK_D_DAOUT_LINE_STRIDE_0                      (_MK_ADDR_CONST(0x10040))
++#define RBK_D_DAOUT_LINE_STRIDE_0_SECURE                                   (0x0)
++#define RBK_D_DAOUT_LINE_STRIDE_0_DUAL                                     (0x0)
++#define RBK_D_DAOUT_LINE_STRIDE_0_SCR                                        (0)
++#define RBK_D_DAOUT_LINE_STRIDE_0_WORD_COUNT                               (0x1)
++#define RBK_D_DAOUT_LINE_STRIDE_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT))
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_RANGE                 (31:5)
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_WOFFSET                (0x0)
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_CONTRACT_STRIDE_0_0
++#define RBK_D_CONTRACT_STRIDE_0_0                      (_MK_ADDR_CONST(0x10044))
++#define RBK_D_CONTRACT_STRIDE_0_0_SECURE                                   (0x0)
++#define RBK_D_CONTRACT_STRIDE_0_0_DUAL                                     (0x0)
++#define RBK_D_CONTRACT_STRIDE_0_0_SCR                                        (0)
++#define RBK_D_CONTRACT_STRIDE_0_0_WORD_COUNT                               (0x1)
++#define RBK_D_CONTRACT_STRIDE_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_0_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_CONTRACT_STRIDE_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_0_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_CONTRACT_STRIDE_0_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT))
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_RANGE                 (31:5)
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_WOFFSET                (0x0)
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_CONTRACT_STRIDE_1_0
++#define RBK_D_CONTRACT_STRIDE_1_0                      (_MK_ADDR_CONST(0x10048))
++#define RBK_D_CONTRACT_STRIDE_1_0_SECURE                                   (0x0)
++#define RBK_D_CONTRACT_STRIDE_1_0_DUAL                                     (0x0)
++#define RBK_D_CONTRACT_STRIDE_1_0_SCR                                        (0)
++#define RBK_D_CONTRACT_STRIDE_1_0_WORD_COUNT                               (0x1)
++#define RBK_D_CONTRACT_STRIDE_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_1_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_CONTRACT_STRIDE_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_1_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_CONTRACT_STRIDE_1_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT))
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_RANGE                 (31:5)
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_WOFFSET                (0x0)
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAOUT_SURF_STRIDE_0
++#define RBK_D_DAOUT_SURF_STRIDE_0                      (_MK_ADDR_CONST(0x1004c))
++#define RBK_D_DAOUT_SURF_STRIDE_0_SECURE                                   (0x0)
++#define RBK_D_DAOUT_SURF_STRIDE_0_DUAL                                     (0x0)
++#define RBK_D_DAOUT_SURF_STRIDE_0_SCR                                        (0)
++#define RBK_D_DAOUT_SURF_STRIDE_0_WORD_COUNT                               (0x1)
++#define RBK_D_DAOUT_SURF_STRIDE_0_RESET_VAL                (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT))
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_RANGE                 (31:5)
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_WOFFSET                (0x0)
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DAOUT_PLANAR_STRIDE_0
++#define RBK_D_DAOUT_PLANAR_STRIDE_0                    (_MK_ADDR_CONST(0x10050))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_SECURE                                 (0x0)
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DUAL                                   (0x0)
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_SCR                                      (0)
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_WORD_COUNT                             (0x1)
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT \
++      (_MK_SHIFT_CONST(5))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x7ffffff, \
++      RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_RANGE             (31:5)
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_WOFFSET            (0x0)
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x7ffffff))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_DECONV_STRIDE_0
++#define RBK_D_DECONV_STRIDE_0                          (_MK_ADDR_CONST(0x10054))
++#define RBK_D_DECONV_STRIDE_0_SECURE                                       (0x0)
++#define RBK_D_DECONV_STRIDE_0_DUAL                                         (0x0)
++#define RBK_D_DECONV_STRIDE_0_SCR                                            (0)
++#define RBK_D_DECONV_STRIDE_0_WORD_COUNT                                   (0x1)
++#define RBK_D_DECONV_STRIDE_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_RESET_MASK              (_MK_MASK_CONST(0x1f001f))
++#define RBK_D_DECONV_STRIDE_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_READ_MASK               (_MK_MASK_CONST(0x1f001f))
++#define RBK_D_DECONV_STRIDE_0_WRITE_MASK              (_MK_MASK_CONST(0x1f001f))
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT         (_MK_SHIFT_CONST(0))
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT))
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_RANGE                        (4:0)
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_WOFFSET                      (0x0)
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT        (_MK_SHIFT_CONST(16))
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_FIELD \
++      (_MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT))
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_RANGE                      (20:16)
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_WOFFSET                      (0x0)
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_DEFAULT      (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x1f))
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_PERF_ENABLE_0
++#define RBK_D_PERF_ENABLE_0                            (_MK_ADDR_CONST(0x10058))
++#define RBK_D_PERF_ENABLE_0_SECURE                                         (0x0)
++#define RBK_D_PERF_ENABLE_0_DUAL                                           (0x0)
++#define RBK_D_PERF_ENABLE_0_SCR                                              (0)
++#define RBK_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
++#define RBK_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
++#define RBK_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0x1))
++#define RBK_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
++#define RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT                   (_MK_SHIFT_CONST(0))
++#define RBK_D_PERF_ENABLE_0_PERF_EN_FIELD \
++      (_MK_FIELD_CONST(0x1, RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT))
++#define RBK_D_PERF_ENABLE_0_PERF_EN_RANGE                                  (0:0)
++#define RBK_D_PERF_ENABLE_0_PERF_EN_WOFFSET                                (0x0)
++#define RBK_D_PERF_ENABLE_0_PERF_EN_DEFAULT                (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_ENABLE_0_PERF_EN_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
++#define RBK_D_PERF_ENABLE_0_PERF_EN_SW_DEFAULT             (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_ENABLE_0_PERF_EN_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_ENABLE_0_PERF_EN_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_ENABLE_0_PERF_EN_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_PERF_READ_STALL_0
++#define RBK_D_PERF_READ_STALL_0                        (_MK_ADDR_CONST(0x1005c))
++#define RBK_D_PERF_READ_STALL_0_SECURE                                     (0x0)
++#define RBK_D_PERF_READ_STALL_0_DUAL                                       (0x0)
++#define RBK_D_PERF_READ_STALL_0_SCR                                          (0)
++#define RBK_D_PERF_READ_STALL_0_WORD_COUNT                                 (0x1)
++#define RBK_D_PERF_READ_STALL_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_READ_STALL_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_PERF_READ_STALL_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_READ_STALL_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_READ_STALL_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_PERF_READ_STALL_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT          (_MK_SHIFT_CONST(0))
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT))
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_RANGE                        (31:0)
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_WOFFSET                       (0x0)
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_DEFAULT       (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++// Register RBK_D_PERF_WRITE_STALL_0
++#define RBK_D_PERF_WRITE_STALL_0                       (_MK_ADDR_CONST(0x10060))
++#define RBK_D_PERF_WRITE_STALL_0_SECURE                                    (0x0)
++#define RBK_D_PERF_WRITE_STALL_0_DUAL                                      (0x0)
++#define RBK_D_PERF_WRITE_STALL_0_SCR                                         (0)
++#define RBK_D_PERF_WRITE_STALL_0_WORD_COUNT                                (0x1)
++#define RBK_D_PERF_WRITE_STALL_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_WRITE_STALL_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_PERF_WRITE_STALL_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_WRITE_STALL_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_WRITE_STALL_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_PERF_WRITE_STALL_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT         (_MK_SHIFT_CONST(0))
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_FIELD \
++      (_MK_FIELD_CONST(0xffffffff, \
++      RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT))
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_RANGE                       (31:0)
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_WOFFSET                      (0x0)
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_DEFAULT      (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_DEFAULT_MASK \
++      (_MK_MASK_CONST(0xffffffff))
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SW_DEFAULT \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SW_DEFAULT_MASK \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_PARITY_PROTECTION \
++      (_MK_MASK_CONST(0x0))
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_PLATFORM_DEPENDENT \
++      (_MK_MASK_CONST(0x1))
++
++
++//
++// REGISTER LIST
++//
++#define LIST_ARREGS(_op_) \
++(_op_(GLB_S_NVDLA_HW_VERSION_0) \
++_op_(GLB_S_INTR_MASK_0) \
++_op_(GLB_S_INTR_SET_0) \
++_op_(GLB_S_INTR_STATUS_0) \
++_op_(MCIF_CFG_RD_WEIGHT_0_0) \
++_op_(MCIF_CFG_RD_WEIGHT_1_0) \
++_op_(MCIF_CFG_RD_WEIGHT_2_0) \
++_op_(MCIF_CFG_WR_WEIGHT_0_0) \
++_op_(MCIF_CFG_WR_WEIGHT_1_0) \
++_op_(MCIF_CFG_OUTSTANDING_CNT_0) \
++_op_(MCIF_STATUS_0) \
++_op_(CVIF_CFG_RD_WEIGHT_0_0) \
++_op_(CVIF_CFG_RD_WEIGHT_1_0) \
++_op_(CVIF_CFG_RD_WEIGHT_2_0) \
++_op_(CVIF_CFG_WR_WEIGHT_0_0) \
++_op_(CVIF_CFG_WR_WEIGHT_1_0) \
++_op_(CVIF_CFG_OUTSTANDING_CNT_0) \
++_op_(CVIF_STATUS_0) \
++_op_(BDMA_CFG_SRC_ADDR_LOW_0) \
++_op_(BDMA_CFG_SRC_ADDR_HIGH_0) \
++_op_(BDMA_CFG_DST_ADDR_LOW_0) \
++_op_(BDMA_CFG_DST_ADDR_HIGH_0) \
++_op_(BDMA_CFG_LINE_0) \
++_op_(BDMA_CFG_CMD_0) \
++_op_(BDMA_CFG_LINE_REPEAT_0) \
++_op_(BDMA_CFG_SRC_LINE_0) \
++_op_(BDMA_CFG_DST_LINE_0) \
++_op_(BDMA_CFG_SURF_REPEAT_0) \
++_op_(BDMA_CFG_SRC_SURF_0) \
++_op_(BDMA_CFG_DST_SURF_0) \
++_op_(BDMA_CFG_OP_0) \
++_op_(BDMA_CFG_LAUNCH0_0) \
++_op_(BDMA_CFG_LAUNCH1_0) \
++_op_(BDMA_CFG_STATUS_0) \
++_op_(BDMA_STATUS_0) \
++_op_(BDMA_STATUS_GRP0_READ_STALL_0) \
++_op_(BDMA_STATUS_GRP0_WRITE_STALL_0) \
++_op_(BDMA_STATUS_GRP1_READ_STALL_0) \
++_op_(BDMA_STATUS_GRP1_WRITE_STALL_0) \
++_op_(CDMA_S_STATUS_0) \
++_op_(CDMA_S_POINTER_0) \
++_op_(CDMA_S_ARBITER_0) \
++_op_(CDMA_S_CBUF_FLUSH_STATUS_0) \
++_op_(CDMA_D_OP_ENABLE_0) \
++_op_(CDMA_D_MISC_CFG_0) \
++_op_(CDMA_D_DATAIN_FORMAT_0) \
++_op_(CDMA_D_DATAIN_SIZE_0_0) \
++_op_(CDMA_D_DATAIN_SIZE_1_0) \
++_op_(CDMA_D_DATAIN_SIZE_EXT_0_0) \
++_op_(CDMA_D_PIXEL_OFFSET_0) \
++_op_(CDMA_D_DAIN_RAM_TYPE_0) \
++_op_(CDMA_D_DAIN_ADDR_HIGH_0_0) \
++_op_(CDMA_D_DAIN_ADDR_LOW_0_0) \
++_op_(CDMA_D_DAIN_ADDR_HIGH_1_0) \
++_op_(CDMA_D_DAIN_ADDR_LOW_1_0) \
++_op_(CDMA_D_LINE_STRIDE_0) \
++_op_(CDMA_D_LINE_UV_STRIDE_0) \
++_op_(CDMA_D_SURF_STRIDE_0) \
++_op_(CDMA_D_DAIN_MAP_0) \
++_op_(CDMA_D_RESERVED_X_CFG_0) \
++_op_(CDMA_D_RESERVED_Y_CFG_0) \
++_op_(CDMA_D_BATCH_NUMBER_0) \
++_op_(CDMA_D_BATCH_STRIDE_0) \
++_op_(CDMA_D_ENTRY_PER_SLICE_0) \
++_op_(CDMA_D_FETCH_GRAIN_0) \
++_op_(CDMA_D_WEIGHT_FORMAT_0) \
++_op_(CDMA_D_WEIGHT_SIZE_0_0) \
++_op_(CDMA_D_WEIGHT_SIZE_1_0) \
++_op_(CDMA_D_WEIGHT_RAM_TYPE_0) \
++_op_(CDMA_D_WEIGHT_ADDR_HIGH_0) \
++_op_(CDMA_D_WEIGHT_ADDR_LOW_0) \
++_op_(CDMA_D_WEIGHT_BYTES_0) \
++_op_(CDMA_D_WGS_ADDR_HIGH_0) \
++_op_(CDMA_D_WGS_ADDR_LOW_0) \
++_op_(CDMA_D_WMB_ADDR_HIGH_0) \
++_op_(CDMA_D_WMB_ADDR_LOW_0) \
++_op_(CDMA_D_WMB_BYTES_0) \
++_op_(CDMA_D_MEAN_FORMAT_0) \
++_op_(CDMA_D_MEAN_GLOBAL_0_0) \
++_op_(CDMA_D_MEAN_GLOBAL_1_0) \
++_op_(CDMA_D_CVT_CFG_0) \
++_op_(CDMA_D_CVT_OFFSET_0) \
++_op_(CDMA_D_CVT_SCALE_0) \
++_op_(CDMA_D_CONV_STRIDE_0) \
++_op_(CDMA_D_ZERO_PADDING_0) \
++_op_(CDMA_D_ZERO_PADDING_VALUE_0) \
++_op_(CDMA_D_BANK_0) \
++_op_(CDMA_D_NAN_FLUSH_TO_ZERO_0) \
++_op_(CDMA_D_NAN_INPUT_DATA_NUM_0) \
++_op_(CDMA_D_NAN_INPUT_WEIGHT_NUM_0) \
++_op_(CDMA_D_INF_INPUT_DATA_NUM_0) \
++_op_(CDMA_D_INF_INPUT_WEIGHT_NUM_0) \
++_op_(CDMA_D_PERF_ENABLE_0) \
++_op_(CDMA_D_PERF_DAT_READ_STALL_0) \
++_op_(CDMA_D_PERF_WT_READ_STALL_0) \
++_op_(CDMA_D_PERF_DAT_READ_LATENCY_0) \
++_op_(CDMA_D_PERF_WT_READ_LATENCY_0) \
++_op_(CDMA_D_CYA_0) \
++_op_(CSC_S_STATUS_0) \
++_op_(CSC_S_POINTER_0) \
++_op_(CSC_D_OP_ENABLE_0) \
++_op_(CSC_D_MISC_CFG_0) \
++_op_(CSC_D_DATAIN_FORMAT_0) \
++_op_(CSC_D_DATAIN_SIZE_EXT_0_0) \
++_op_(CSC_D_DATAIN_SIZE_EXT_1_0) \
++_op_(CSC_D_BATCH_NUMBER_0) \
++_op_(CSC_D_POST_Y_EXTENSION_0) \
++_op_(CSC_D_ENTRY_PER_SLICE_0) \
++_op_(CSC_D_WEIGHT_FORMAT_0) \
++_op_(CSC_D_WEIGHT_SIZE_EXT_0_0) \
++_op_(CSC_D_WEIGHT_SIZE_EXT_1_0) \
++_op_(CSC_D_WEIGHT_BYTES_0) \
++_op_(CSC_D_WMB_BYTES_0) \
++_op_(CSC_D_DATAOUT_SIZE_0_0) \
++_op_(CSC_D_DATAOUT_SIZE_1_0) \
++_op_(CSC_D_ATOMICS_0) \
++_op_(CSC_D_RELEASE_0) \
++_op_(CSC_D_CONV_STRIDE_EXT_0) \
++_op_(CSC_D_DILATION_EXT_0) \
++_op_(CSC_D_ZERO_PADDING_0) \
++_op_(CSC_D_ZERO_PADDING_VALUE_0) \
++_op_(CSC_D_BANK_0) \
++_op_(CSC_D_PRA_CFG_0) \
++_op_(CSC_D_CYA_0) \
++_op_(CMAC_A_S_STATUS_0) \
++_op_(CMAC_A_S_POINTER_0) \
++_op_(CMAC_A_D_OP_ENABLE_0) \
++_op_(CMAC_A_D_MISC_CFG_0) \
++_op_(CMAC_B_S_STATUS_0) \
++_op_(CMAC_B_S_POINTER_0) \
++_op_(CMAC_B_D_OP_ENABLE_0) \
++_op_(CMAC_B_D_MISC_CFG_0) \
++_op_(CACC_S_STATUS_0) \
++_op_(CACC_S_POINTER_0) \
++_op_(CACC_D_OP_ENABLE_0) \
++_op_(CACC_D_MISC_CFG_0) \
++_op_(CACC_D_DATAOUT_SIZE_0_0) \
++_op_(CACC_D_DATAOUT_SIZE_1_0) \
++_op_(CACC_D_DATAOUT_ADDR_0) \
++_op_(CACC_D_BATCH_NUMBER_0) \
++_op_(CACC_D_LINE_STRIDE_0) \
++_op_(CACC_D_SURF_STRIDE_0) \
++_op_(CACC_D_DATAOUT_MAP_0) \
++_op_(CACC_D_CLIP_CFG_0) \
++_op_(CACC_D_OUT_SATURATION_0) \
++_op_(CACC_D_CYA_0) \
++_op_(SDP_RDMA_S_STATUS_0) \
++_op_(SDP_RDMA_S_POINTER_0) \
++_op_(SDP_RDMA_D_OP_ENABLE_0) \
++_op_(SDP_RDMA_D_DATA_CUBE_WIDTH_0) \
++_op_(SDP_RDMA_D_DATA_CUBE_HEIGHT_0) \
++_op_(SDP_RDMA_D_DATA_CUBE_CHANNEL_0) \
++_op_(SDP_RDMA_D_SRC_BASE_ADDR_LOW_0) \
++_op_(SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0) \
++_op_(SDP_RDMA_D_SRC_LINE_STRIDE_0) \
++_op_(SDP_RDMA_D_SRC_SURFACE_STRIDE_0) \
++_op_(SDP_RDMA_D_BRDMA_CFG_0) \
++_op_(SDP_RDMA_D_BS_BASE_ADDR_LOW_0) \
++_op_(SDP_RDMA_D_BS_BASE_ADDR_HIGH_0) \
++_op_(SDP_RDMA_D_BS_LINE_STRIDE_0) \
++_op_(SDP_RDMA_D_BS_SURFACE_STRIDE_0) \
++_op_(SDP_RDMA_D_BS_BATCH_STRIDE_0) \
++_op_(SDP_RDMA_D_NRDMA_CFG_0) \
++_op_(SDP_RDMA_D_BN_BASE_ADDR_LOW_0) \
++_op_(SDP_RDMA_D_BN_BASE_ADDR_HIGH_0) \
++_op_(SDP_RDMA_D_BN_LINE_STRIDE_0) \
++_op_(SDP_RDMA_D_BN_SURFACE_STRIDE_0) \
++_op_(SDP_RDMA_D_BN_BATCH_STRIDE_0) \
++_op_(SDP_RDMA_D_ERDMA_CFG_0) \
++_op_(SDP_RDMA_D_EW_BASE_ADDR_LOW_0) \
++_op_(SDP_RDMA_D_EW_BASE_ADDR_HIGH_0) \
++_op_(SDP_RDMA_D_EW_LINE_STRIDE_0) \
++_op_(SDP_RDMA_D_EW_SURFACE_STRIDE_0) \
++_op_(SDP_RDMA_D_EW_BATCH_STRIDE_0) \
++_op_(SDP_RDMA_D_FEATURE_MODE_CFG_0) \
++_op_(SDP_RDMA_D_SRC_DMA_CFG_0) \
++_op_(SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0) \
++_op_(SDP_RDMA_D_STATUS_INF_INPUT_NUM_0) \
++_op_(SDP_RDMA_D_PERF_ENABLE_0) \
++_op_(SDP_RDMA_D_PERF_MRDMA_READ_STALL_0) \
++_op_(SDP_RDMA_D_PERF_BRDMA_READ_STALL_0) \
++_op_(SDP_RDMA_D_PERF_NRDMA_READ_STALL_0) \
++_op_(SDP_RDMA_D_PERF_ERDMA_READ_STALL_0) \
++_op_(SDP_S_STATUS_0) \
++_op_(SDP_S_POINTER_0) \
++_op_(SDP_S_LUT_ACCESS_CFG_0) \
++_op_(SDP_S_LUT_ACCESS_DATA_0) \
++_op_(SDP_S_LUT_CFG_0) \
++_op_(SDP_S_LUT_INFO_0) \
++_op_(SDP_S_LUT_LE_START_0) \
++_op_(SDP_S_LUT_LE_END_0) \
++_op_(SDP_S_LUT_LO_START_0) \
++_op_(SDP_S_LUT_LO_END_0) \
++_op_(SDP_S_LUT_LE_SLOPE_SCALE_0) \
++_op_(SDP_S_LUT_LE_SLOPE_SHIFT_0) \
++_op_(SDP_S_LUT_LO_SLOPE_SCALE_0) \
++_op_(SDP_S_LUT_LO_SLOPE_SHIFT_0) \
++_op_(SDP_D_OP_ENABLE_0) \
++_op_(SDP_D_DATA_CUBE_WIDTH_0) \
++_op_(SDP_D_DATA_CUBE_HEIGHT_0) \
++_op_(SDP_D_DATA_CUBE_CHANNEL_0) \
++_op_(SDP_D_DST_BASE_ADDR_LOW_0) \
++_op_(SDP_D_DST_BASE_ADDR_HIGH_0) \
++_op_(SDP_D_DST_LINE_STRIDE_0) \
++_op_(SDP_D_DST_SURFACE_STRIDE_0) \
++_op_(SDP_D_DP_BS_CFG_0) \
++_op_(SDP_D_DP_BS_ALU_CFG_0) \
++_op_(SDP_D_DP_BS_ALU_SRC_VALUE_0) \
++_op_(SDP_D_DP_BS_MUL_CFG_0) \
++_op_(SDP_D_DP_BS_MUL_SRC_VALUE_0) \
++_op_(SDP_D_DP_BN_CFG_0) \
++_op_(SDP_D_DP_BN_ALU_CFG_0) \
++_op_(SDP_D_DP_BN_ALU_SRC_VALUE_0) \
++_op_(SDP_D_DP_BN_MUL_CFG_0) \
++_op_(SDP_D_DP_BN_MUL_SRC_VALUE_0) \
++_op_(SDP_D_DP_EW_CFG_0) \
++_op_(SDP_D_DP_EW_ALU_CFG_0) \
++_op_(SDP_D_DP_EW_ALU_SRC_VALUE_0) \
++_op_(SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0) \
++_op_(SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0) \
++_op_(SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0) \
++_op_(SDP_D_DP_EW_MUL_CFG_0) \
++_op_(SDP_D_DP_EW_MUL_SRC_VALUE_0) \
++_op_(SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0) \
++_op_(SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0) \
++_op_(SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0) \
++_op_(SDP_D_DP_EW_TRUNCATE_VALUE_0) \
++_op_(SDP_D_FEATURE_MODE_CFG_0) \
++_op_(SDP_D_DST_DMA_CFG_0) \
++_op_(SDP_D_DST_BATCH_STRIDE_0) \
++_op_(SDP_D_DATA_FORMAT_0) \
++_op_(SDP_D_CVT_OFFSET_0) \
++_op_(SDP_D_CVT_SCALE_0) \
++_op_(SDP_D_CVT_SHIFT_0) \
++_op_(SDP_D_STATUS_0) \
++_op_(SDP_D_STATUS_NAN_INPUT_NUM_0) \
++_op_(SDP_D_STATUS_INF_INPUT_NUM_0) \
++_op_(SDP_D_STATUS_NAN_OUTPUT_NUM_0) \
++_op_(SDP_D_PERF_ENABLE_0) \
++_op_(SDP_D_PERF_WDMA_WRITE_STALL_0) \
++_op_(SDP_D_PERF_LUT_UFLOW_0) \
++_op_(SDP_D_PERF_LUT_OFLOW_0) \
++_op_(SDP_D_PERF_OUT_SATURATION_0) \
++_op_(SDP_D_PERF_LUT_HYBRID_0) \
++_op_(SDP_D_PERF_LUT_LE_HIT_0) \
++_op_(SDP_D_PERF_LUT_LO_HIT_0) \
++_op_(PDP_RDMA_S_STATUS_0) \
++_op_(PDP_RDMA_S_POINTER_0) \
++_op_(PDP_RDMA_D_OP_ENABLE_0) \
++_op_(PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0) \
++_op_(PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0) \
++_op_(PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0) \
++_op_(PDP_RDMA_D_FLYING_MODE_0) \
++_op_(PDP_RDMA_D_SRC_BASE_ADDR_LOW_0) \
++_op_(PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0) \
++_op_(PDP_RDMA_D_SRC_LINE_STRIDE_0) \
++_op_(PDP_RDMA_D_SRC_SURFACE_STRIDE_0) \
++_op_(PDP_RDMA_D_SRC_RAM_CFG_0) \
++_op_(PDP_RDMA_D_DATA_FORMAT_0) \
++_op_(PDP_RDMA_D_OPERATION_MODE_CFG_0) \
++_op_(PDP_RDMA_D_POOLING_KERNEL_CFG_0) \
++_op_(PDP_RDMA_D_POOLING_PADDING_CFG_0) \
++_op_(PDP_RDMA_D_PARTIAL_WIDTH_IN_0) \
++_op_(PDP_RDMA_D_PERF_ENABLE_0) \
++_op_(PDP_RDMA_D_PERF_READ_STALL_0) \
++_op_(PDP_RDMA_D_CYA_0) \
++_op_(PDP_S_STATUS_0) \
++_op_(PDP_S_POINTER_0) \
++_op_(PDP_D_OP_ENABLE_0) \
++_op_(PDP_D_DATA_CUBE_IN_WIDTH_0) \
++_op_(PDP_D_DATA_CUBE_IN_HEIGHT_0) \
++_op_(PDP_D_DATA_CUBE_IN_CHANNEL_0) \
++_op_(PDP_D_DATA_CUBE_OUT_WIDTH_0) \
++_op_(PDP_D_DATA_CUBE_OUT_HEIGHT_0) \
++_op_(PDP_D_DATA_CUBE_OUT_CHANNEL_0) \
++_op_(PDP_D_OPERATION_MODE_CFG_0) \
++_op_(PDP_D_NAN_FLUSH_TO_ZERO_0) \
++_op_(PDP_D_PARTIAL_WIDTH_IN_0) \
++_op_(PDP_D_PARTIAL_WIDTH_OUT_0) \
++_op_(PDP_D_POOLING_KERNEL_CFG_0) \
++_op_(PDP_D_RECIP_KERNEL_WIDTH_0) \
++_op_(PDP_D_RECIP_KERNEL_HEIGHT_0) \
++_op_(PDP_D_POOLING_PADDING_CFG_0) \
++_op_(PDP_D_POOLING_PADDING_VALUE_1_CFG_0) \
++_op_(PDP_D_POOLING_PADDING_VALUE_2_CFG_0) \
++_op_(PDP_D_POOLING_PADDING_VALUE_3_CFG_0) \
++_op_(PDP_D_POOLING_PADDING_VALUE_4_CFG_0) \
++_op_(PDP_D_POOLING_PADDING_VALUE_5_CFG_0) \
++_op_(PDP_D_POOLING_PADDING_VALUE_6_CFG_0) \
++_op_(PDP_D_POOLING_PADDING_VALUE_7_CFG_0) \
++_op_(PDP_D_SRC_BASE_ADDR_LOW_0) \
++_op_(PDP_D_SRC_BASE_ADDR_HIGH_0) \
++_op_(PDP_D_SRC_LINE_STRIDE_0) \
++_op_(PDP_D_SRC_SURFACE_STRIDE_0) \
++_op_(PDP_D_DST_BASE_ADDR_LOW_0) \
++_op_(PDP_D_DST_BASE_ADDR_HIGH_0) \
++_op_(PDP_D_DST_LINE_STRIDE_0) \
++_op_(PDP_D_DST_SURFACE_STRIDE_0) \
++_op_(PDP_D_DST_RAM_CFG_0) \
++_op_(PDP_D_DATA_FORMAT_0) \
++_op_(PDP_D_INF_INPUT_NUM_0) \
++_op_(PDP_D_NAN_INPUT_NUM_0) \
++_op_(PDP_D_NAN_OUTPUT_NUM_0) \
++_op_(PDP_D_PERF_ENABLE_0) \
++_op_(PDP_D_PERF_WRITE_STALL_0) \
++_op_(PDP_D_CYA_0) \
++_op_(CDP_RDMA_S_STATUS_0) \
++_op_(CDP_RDMA_S_POINTER_0) \
++_op_(CDP_RDMA_D_OP_ENABLE_0) \
++_op_(CDP_RDMA_D_DATA_CUBE_WIDTH_0) \
++_op_(CDP_RDMA_D_DATA_CUBE_HEIGHT_0) \
++_op_(CDP_RDMA_D_DATA_CUBE_CHANNEL_0) \
++_op_(CDP_RDMA_D_SRC_BASE_ADDR_LOW_0) \
++_op_(CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0) \
++_op_(CDP_RDMA_D_SRC_LINE_STRIDE_0) \
++_op_(CDP_RDMA_D_SRC_SURFACE_STRIDE_0) \
++_op_(CDP_RDMA_D_SRC_DMA_CFG_0) \
++_op_(CDP_RDMA_D_SRC_COMPRESSION_EN_0) \
++_op_(CDP_RDMA_D_OPERATION_MODE_0) \
++_op_(CDP_RDMA_D_DATA_FORMAT_0) \
++_op_(CDP_RDMA_D_PERF_ENABLE_0) \
++_op_(CDP_RDMA_D_PERF_READ_STALL_0) \
++_op_(CDP_RDMA_D_CYA_0) \
++_op_(CDP_S_STATUS_0) \
++_op_(CDP_S_POINTER_0) \
++_op_(CDP_S_LUT_ACCESS_CFG_0) \
++_op_(CDP_S_LUT_ACCESS_DATA_0) \
++_op_(CDP_S_LUT_CFG_0) \
++_op_(CDP_S_LUT_INFO_0) \
++_op_(CDP_S_LUT_LE_START_LOW_0) \
++_op_(CDP_S_LUT_LE_START_HIGH_0) \
++_op_(CDP_S_LUT_LE_END_LOW_0) \
++_op_(CDP_S_LUT_LE_END_HIGH_0) \
++_op_(CDP_S_LUT_LO_START_LOW_0) \
++_op_(CDP_S_LUT_LO_START_HIGH_0) \
++_op_(CDP_S_LUT_LO_END_LOW_0) \
++_op_(CDP_S_LUT_LO_END_HIGH_0) \
++_op_(CDP_S_LUT_LE_SLOPE_SCALE_0) \
++_op_(CDP_S_LUT_LE_SLOPE_SHIFT_0) \
++_op_(CDP_S_LUT_LO_SLOPE_SCALE_0) \
++_op_(CDP_S_LUT_LO_SLOPE_SHIFT_0) \
++_op_(CDP_D_OP_ENABLE_0) \
++_op_(CDP_D_FUNC_BYPASS_0) \
++_op_(CDP_D_DST_BASE_ADDR_LOW_0) \
++_op_(CDP_D_DST_BASE_ADDR_HIGH_0) \
++_op_(CDP_D_DST_LINE_STRIDE_0) \
++_op_(CDP_D_DST_SURFACE_STRIDE_0) \
++_op_(CDP_D_DST_DMA_CFG_0) \
++_op_(CDP_D_DST_COMPRESSION_EN_0) \
++_op_(CDP_D_DATA_FORMAT_0) \
++_op_(CDP_D_NAN_FLUSH_TO_ZERO_0) \
++_op_(CDP_D_LRN_CFG_0) \
++_op_(CDP_D_DATIN_OFFSET_0) \
++_op_(CDP_D_DATIN_SCALE_0) \
++_op_(CDP_D_DATIN_SHIFTER_0) \
++_op_(CDP_D_DATOUT_OFFSET_0) \
++_op_(CDP_D_DATOUT_SCALE_0) \
++_op_(CDP_D_DATOUT_SHIFTER_0) \
++_op_(CDP_D_NAN_INPUT_NUM_0) \
++_op_(CDP_D_INF_INPUT_NUM_0) \
++_op_(CDP_D_NAN_OUTPUT_NUM_0) \
++_op_(CDP_D_OUT_SATURATION_0) \
++_op_(CDP_D_PERF_ENABLE_0) \
++_op_(CDP_D_PERF_WRITE_STALL_0) \
++_op_(CDP_D_PERF_LUT_UFLOW_0) \
++_op_(CDP_D_PERF_LUT_OFLOW_0) \
++_op_(CDP_D_PERF_LUT_HYBRID_0) \
++_op_(CDP_D_PERF_LUT_LE_HIT_0) \
++_op_(CDP_D_PERF_LUT_LO_HIT_0) \
++_op_(CDP_D_CYA_0) \
++_op_(RBK_S_STATUS_0) \
++_op_(RBK_S_POINTER_0) \
++_op_(RBK_D_OP_ENABLE_0) \
++_op_(RBK_D_MISC_CFG_0) \
++_op_(RBK_D_DAIN_RAM_TYPE_0) \
++_op_(RBK_D_DATAIN_SIZE_0_0) \
++_op_(RBK_D_DATAIN_SIZE_1_0) \
++_op_(RBK_D_DAIN_ADDR_HIGH_0) \
++_op_(RBK_D_DAIN_ADDR_LOW_0) \
++_op_(RBK_D_DAIN_LINE_STRIDE_0) \
++_op_(RBK_D_DAIN_SURF_STRIDE_0) \
++_op_(RBK_D_DAIN_PLANAR_STRIDE_0) \
++_op_(RBK_D_DAOUT_RAM_TYPE_0) \
++_op_(RBK_D_DATAOUT_SIZE_1_0) \
++_op_(RBK_D_DAOUT_ADDR_HIGH_0) \
++_op_(RBK_D_DAOUT_ADDR_LOW_0) \
++_op_(RBK_D_DAOUT_LINE_STRIDE_0) \
++_op_(RBK_D_CONTRACT_STRIDE_0_0) \
++_op_(RBK_D_CONTRACT_STRIDE_1_0) \
++_op_(RBK_D_DAOUT_SURF_STRIDE_0) \
++_op_(RBK_D_DAOUT_PLANAR_STRIDE_0) \
++_op_(RBK_D_DECONV_STRIDE_0) \
++_op_(RBK_D_PERF_ENABLE_0) \
++_op_(RBK_D_PERF_READ_STALL_0) \
++_op_(RBK_D_PERF_WRITE_STALL_0))
++
++
++//
++// ADDRESS SPACES
++//
++
++#define BASE_ADDRESS_NVDLA_GLB                                      (0x00000000)
++#define BASE_ADDRESS_NVDLA_MCIF                                     (0x00002000)
++#define BASE_ADDRESS_NVDLA_CVIF                                     (0x00003000)
++#define BASE_ADDRESS_NVDLA_BDMA                                     (0x00004000)
++#define BASE_ADDRESS_NVDLA_CDMA                                     (0x00005000)
++#define BASE_ADDRESS_NVDLA_CSC                                      (0x00006000)
++#define BASE_ADDRESS_NVDLA_CMAC_A                                   (0x00007000)
++#define BASE_ADDRESS_NVDLA_CMAC_B                                   (0x00008000)
++#define BASE_ADDRESS_NVDLA_CACC                                     (0x00009000)
++#define BASE_ADDRESS_NVDLA_SDP_RDMA                                 (0x0000a000)
++#define BASE_ADDRESS_NVDLA_SDP                                      (0x0000b000)
++#define BASE_ADDRESS_NVDLA_PDP_RDMA                                 (0x0000c000)
++#define BASE_ADDRESS_NVDLA_PDP                                      (0x0000d000)
++#define BASE_ADDRESS_NVDLA_CDP_RDMA                                 (0x0000e000)
++#define BASE_ADDRESS_NVDLA_CDP                                      (0x0000f000)
++#define BASE_ADDRESS_NVDLA_RBK                                      (0x00010000)
++
++//
++// ARNVDLA REGISTER BANKS
++//
++
++#define GLB0_FIRST_REG                                                  (0x0000)
++#define GLB0_LAST_REG                                                   (0x000c)
++#define MCIF0_FIRST_REG                                                 (0x2000)
++#define MCIF0_LAST_REG                                                  (0x2018)
++#define CVIF0_FIRST_REG                                                 (0x3000)
++#define CVIF0_LAST_REG                                                  (0x3018)
++#define BDMA0_FIRST_REG                                                 (0x4000)
++#define BDMA0_LAST_REG                                                  (0x4050)
++#define CDMA0_FIRST_REG                                                 (0x5000)
++#define CDMA0_LAST_REG                                                  (0x50e8)
++#define CSC0_FIRST_REG                                                  (0x6000)
++#define CSC0_LAST_REG                                                   (0x6064)
++#define CMAC_A0_FIRST_REG                                               (0x7000)
++#define CMAC_A0_LAST_REG                                                (0x700c)
++#define CMAC_B0_FIRST_REG                                               (0x8000)
++#define CMAC_B0_LAST_REG                                                (0x800c)
++#define CACC0_FIRST_REG                                                 (0x9000)
++#define CACC0_LAST_REG                                                  (0x9034)
++#define SDP_RDMA0_FIRST_REG                                             (0xa000)
++#define SDP_RDMA0_LAST_REG                                              (0xa090)
++#define SDP0_FIRST_REG                                                  (0xb000)
++#define SDP0_LAST_REG                                                   (0xb0f8)
++#define PDP_RDMA0_FIRST_REG                                             (0xc000)
++#define PDP_RDMA0_LAST_REG                                              (0xc04c)
++#define PDP0_FIRST_REG                                                  (0xd000)
++#define PDP0_LAST_REG                                                   (0xd09c)
++#define CDP_RDMA0_FIRST_REG                                             (0xe000)
++#define CDP_RDMA0_LAST_REG                                              (0xe040)
++#define CDP0_FIRST_REG                                                  (0xf000)
++#define CDP0_LAST_REG                                                   (0xf0b8)
++#define RBK0_FIRST_REG                                                 (0x10000)
++#define RBK0_LAST_REG                                                  (0x10060)
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++#define _MK_SHIFT_CONST(_constant_)                                 (_constant_)
++#endif
++#ifndef _MK_MASK_CONST
++#define _MK_MASK_CONST(_constant_)                                  (_constant_)
++#endif
++#ifndef _MK_ENUM_CONST
++#define _MK_ENUM_CONST(_constant_)                          ((_constant_ ## UL))
++#endif
++#ifndef _MK_ADDR_CONST
++#define _MK_ADDR_CONST(_constant_)                                  (_constant_)
++#endif
++#ifndef _MK_FIELD_CONST
++#define _MK_FIELD_CONST(_mask_, _shift_) \
++      ((_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)))
++#endif
++
++#endif // ifndef ___ARH_INC_
+--- /dev/null
++++ b/drivers/nvdla/include/opendla_small.h
+@@ -0,0 +1,6433 @@
++/*
++ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __OPENDLA_SMALL_H_
++#define __OPENDLA_SMALL_H_
++
++// Register NVDLA_CFGROM_CFGROM_HW_VERSION_0
++#define NVDLA_CFGROM_CFGROM_HW_VERSION_0                      _MK_ADDR_CONST(0x0)
++#define NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_GLB_DESC_0
++#define NVDLA_CFGROM_CFGROM_GLB_DESC_0                        _MK_ADDR_CONST(0x4)
++#define NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CIF_DESC_0
++#define NVDLA_CFGROM_CFGROM_CIF_DESC_0                        _MK_ADDR_CONST(0x8)
++#define NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0                        _MK_ADDR_CONST(0xc)
++#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0                  _MK_ADDR_CONST(0x10)
++#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0                  _MK_ADDR_CONST(0x14)
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_FIELD                     _MK_FIELD_CONST(0xff, NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0                        _MK_ADDR_CONST(0x18)
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0                       _MK_ADDR_CONST(0x1c)
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_SHIFT                   _MK_SHIFT_CONST(5)
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_FIELD                   _MK_FIELD_CONST(0x7ffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0                 _MK_ADDR_CONST(0x20)
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_SHIFT                   _MK_SHIFT_CONST(5)
++#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_FIELD                   _MK_FIELD_CONST(0x7ffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_DESC_0
++#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0                       _MK_ADDR_CONST(0x24)
++#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0                       _MK_ADDR_CONST(0x28)
++#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0                 _MK_ADDR_CONST(0x2c)
++#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0                 _MK_ADDR_CONST(0x30)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_FIELD                   _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0                  _MK_ADDR_CONST(0x34)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_FIELD                     _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0                      _MK_ADDR_CONST(0x38)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0                      _MK_ADDR_CONST(0x3c)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0                      _MK_ADDR_CONST(0x40)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0                 _MK_ADDR_CONST(0x44)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0                       _MK_ADDR_CONST(0x48)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0                       _MK_ADDR_CONST(0x4c)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0
++#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0                    _MK_ADDR_CONST(0x50)
++#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0
++#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0                    _MK_ADDR_CONST(0x54)
++#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0
++#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0                      _MK_ADDR_CONST(0x58)
++#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CBUF_DESC_0
++#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0                       _MK_ADDR_CONST(0x5c)
++#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0                       _MK_ADDR_CONST(0x60)
++#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0                 _MK_ADDR_CONST(0x64)
++#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0                 _MK_ADDR_CONST(0x68)
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0                       _MK_ADDR_CONST(0x6c)
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0                       _MK_ADDR_CONST(0x70)
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0                       _MK_ADDR_CONST(0x74)
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_DESC_0
++#define NVDLA_CFGROM_CFGROM_CSC_DESC_0                        _MK_ADDR_CONST(0x78)
++#define NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0                        _MK_ADDR_CONST(0x7c)
++#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0                  _MK_ADDR_CONST(0x80)
++#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0                  _MK_ADDR_CONST(0x84)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_FIELD                     _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0                   _MK_ADDR_CONST(0x88)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_FIELD                       _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0                       _MK_ADDR_CONST(0x8c)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0                       _MK_ADDR_CONST(0x90)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0                       _MK_ADDR_CONST(0x94)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0                  _MK_ADDR_CONST(0x98)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0                        _MK_ADDR_CONST(0x9c)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0                        _MK_ADDR_CONST(0xa0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0                        _MK_ADDR_CONST(0xa4)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0
++#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0                     _MK_ADDR_CONST(0xa8)
++#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0
++#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0                     _MK_ADDR_CONST(0xac)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0                     _MK_ADDR_CONST(0xb0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0                       _MK_ADDR_CONST(0xb4)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0                       _MK_ADDR_CONST(0xb8)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_FIELD                       _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0                        _MK_ADDR_CONST(0xbc)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_FIELD                 _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0                    _MK_ADDR_CONST(0xc0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0                    _MK_ADDR_CONST(0xc4)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0                     _MK_ADDR_CONST(0xc8)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0
++#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0                     _MK_ADDR_CONST(0xcc)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0                     _MK_ADDR_CONST(0xd0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0                       _MK_ADDR_CONST(0xd4)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0                       _MK_ADDR_CONST(0xd8)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_FIELD                       _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0                        _MK_ADDR_CONST(0xdc)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_FIELD                 _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0                    _MK_ADDR_CONST(0xe0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0                    _MK_ADDR_CONST(0xe4)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0                     _MK_ADDR_CONST(0xe8)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CACC_DESC_0
++#define NVDLA_CFGROM_CFGROM_CACC_DESC_0                       _MK_ADDR_CONST(0xec)
++#define NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0                       _MK_ADDR_CONST(0xf0)
++#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0                 _MK_ADDR_CONST(0xf4)
++#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0                 _MK_ADDR_CONST(0xf8)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_FIELD                   _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0                  _MK_ADDR_CONST(0xfc)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_FIELD                     _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0                      _MK_ADDR_CONST(0x100)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0                      _MK_ADDR_CONST(0x104)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0                       _MK_ADDR_CONST(0x108)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0
++#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0                    _MK_ADDR_CONST(0x10c)
++#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0                   _MK_ADDR_CONST(0x110)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0                   _MK_ADDR_CONST(0x114)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0                     _MK_ADDR_CONST(0x118)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0                  _MK_ADDR_CONST(0x11c)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0                    _MK_ADDR_CONST(0x120)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_DESC_0
++#define NVDLA_CFGROM_CFGROM_SDP_DESC_0                        _MK_ADDR_CONST(0x124)
++#define NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0                        _MK_ADDR_CONST(0x128)
++#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0                  _MK_ADDR_CONST(0x12c)
++#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0
++#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0                  _MK_ADDR_CONST(0x130)
++#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_FIELD                     _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0
++#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0                   _MK_ADDR_CONST(0x134)
++#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_FIELD                       _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0
++#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0                        _MK_ADDR_CONST(0x138)
++#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0
++#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0                     _MK_ADDR_CONST(0x13c)
++#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0
++#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0                       _MK_ADDR_CONST(0x140)
++#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0
++#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0                       _MK_ADDR_CONST(0x144)
++#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0
++#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0                       _MK_ADDR_CONST(0x148)
++#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0                   _MK_ADDR_CONST(0x14c)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0                   _MK_ADDR_CONST(0x150)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0                     _MK_ADDR_CONST(0x154)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0                  _MK_ADDR_CONST(0x158)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0                    _MK_ADDR_CONST(0x15c)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_DESC_0
++#define NVDLA_CFGROM_CFGROM_PDP_DESC_0                        _MK_ADDR_CONST(0x160)
++#define NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0                        _MK_ADDR_CONST(0x164)
++#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0                  _MK_ADDR_CONST(0x168)
++#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0
++#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0                  _MK_ADDR_CONST(0x16c)
++#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_FIELD                     _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0
++#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0                     _MK_ADDR_CONST(0x170)
++#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0                   _MK_ADDR_CONST(0x174)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0                   _MK_ADDR_CONST(0x178)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_FIELD                       _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0                     _MK_ADDR_CONST(0x17c)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0                  _MK_ADDR_CONST(0x180)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0                    _MK_ADDR_CONST(0x184)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_DESC_0
++#define NVDLA_CFGROM_CFGROM_CDP_DESC_0                        _MK_ADDR_CONST(0x188)
++#define NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0
++#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0                        _MK_ADDR_CONST(0x18c)
++#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_FIELD                 _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0
++#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0                  _MK_ADDR_CONST(0x190)
++#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_FIELD                     _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0
++#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0                  _MK_ADDR_CONST(0x194)
++#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_FIELD                     _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0
++#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0                     _MK_ADDR_CONST(0x198)
++#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_SHIFT)
++
++
++// Register NVDLA_CFGROM_CFGROM_END_OF_LIST_0
++#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0                     _MK_ADDR_CONST(0x19c)
++#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_FIELD                   _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register GLB_S_NVDLA_HW_VERSION_0
++#define GLB_S_NVDLA_HW_VERSION_0                      _MK_ADDR_CONST(0x1000)
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT                  _MK_SHIFT_CONST(0)
++#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_FIELD                  _MK_FIELD_CONST(0xff, GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT)
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT                  _MK_SHIFT_CONST(8)
++#define GLB_S_NVDLA_HW_VERSION_0_MINOR_FIELD                  _MK_FIELD_CONST(0xffff, GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT)
++
++
++// Register GLB_S_INTR_MASK_0
++#define GLB_S_INTR_MASK_0                     _MK_ADDR_CONST(0x1004)
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT                        _MK_SHIFT_CONST(0)
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT)
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT                        _MK_SHIFT_CONST(1)
++#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT)
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT                        _MK_SHIFT_CONST(2)
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT)
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT                        _MK_SHIFT_CONST(3)
++#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT)
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT                        _MK_SHIFT_CONST(4)
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT)
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT                        _MK_SHIFT_CONST(5)
++#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT)
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT                       _MK_SHIFT_CONST(6)
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_FIELD                       _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT)
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT                       _MK_SHIFT_CONST(7)
++#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_FIELD                       _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT)
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT                      _MK_SHIFT_CONST(8)
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_FIELD                      _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT)
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT                      _MK_SHIFT_CONST(9)
++#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_FIELD                      _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT)
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT                   _MK_SHIFT_CONST(16)
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_FIELD                   _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT)
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT                   _MK_SHIFT_CONST(17)
++#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_FIELD                   _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT)
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT                    _MK_SHIFT_CONST(18)
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_FIELD                    _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT)
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT                    _MK_SHIFT_CONST(19)
++#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_FIELD                    _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT)
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT                       _MK_SHIFT_CONST(20)
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_FIELD                       _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT)
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT                       _MK_SHIFT_CONST(21)
++#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_FIELD                       _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT)
++
++
++// Register GLB_S_INTR_SET_0
++#define GLB_S_INTR_SET_0                      _MK_ADDR_CONST(0x1008)
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT                  _MK_SHIFT_CONST(0)
++#define GLB_S_INTR_SET_0_SDP_DONE_SET0_FIELD                  _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT)
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT                  _MK_SHIFT_CONST(1)
++#define GLB_S_INTR_SET_0_SDP_DONE_SET1_FIELD                  _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT)
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT                  _MK_SHIFT_CONST(2)
++#define GLB_S_INTR_SET_0_CDP_DONE_SET0_FIELD                  _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT)
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT                  _MK_SHIFT_CONST(3)
++#define GLB_S_INTR_SET_0_CDP_DONE_SET1_FIELD                  _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT)
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT                  _MK_SHIFT_CONST(4)
++#define GLB_S_INTR_SET_0_PDP_DONE_SET0_FIELD                  _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT)
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT                  _MK_SHIFT_CONST(5)
++#define GLB_S_INTR_SET_0_PDP_DONE_SET1_FIELD                  _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT)
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT                 _MK_SHIFT_CONST(6)
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_FIELD                 _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT)
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT                 _MK_SHIFT_CONST(7)
++#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_FIELD                 _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT)
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT                        _MK_SHIFT_CONST(8)
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT)
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT                        _MK_SHIFT_CONST(9)
++#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT)
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT                     _MK_SHIFT_CONST(16)
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_FIELD                     _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT)
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT                     _MK_SHIFT_CONST(17)
++#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_FIELD                     _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT)
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT                      _MK_SHIFT_CONST(18)
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_FIELD                      _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT)
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT                      _MK_SHIFT_CONST(19)
++#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_FIELD                      _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT)
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT                 _MK_SHIFT_CONST(20)
++#define GLB_S_INTR_SET_0_CACC_DONE_SET0_FIELD                 _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT)
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT                 _MK_SHIFT_CONST(21)
++#define GLB_S_INTR_SET_0_CACC_DONE_SET1_FIELD                 _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT)
++
++
++// Register GLB_S_INTR_STATUS_0
++#define GLB_S_INTR_STATUS_0                   _MK_ADDR_CONST(0x100c)
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT                    _MK_SHIFT_CONST(0)
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_FIELD                    _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT)
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT                    _MK_SHIFT_CONST(1)
++#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_FIELD                    _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT)
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT                    _MK_SHIFT_CONST(2)
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_FIELD                    _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT)
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT                    _MK_SHIFT_CONST(3)
++#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_FIELD                    _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT)
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT                    _MK_SHIFT_CONST(4)
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_FIELD                    _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT)
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT                    _MK_SHIFT_CONST(5)
++#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_FIELD                    _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT)
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT                   _MK_SHIFT_CONST(6)
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_FIELD                   _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT)
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT                   _MK_SHIFT_CONST(7)
++#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_FIELD                   _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT)
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT                  _MK_SHIFT_CONST(8)
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_FIELD                  _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT)
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT                  _MK_SHIFT_CONST(9)
++#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_FIELD                  _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT)
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT                       _MK_SHIFT_CONST(16)
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_FIELD                       _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT)
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT                       _MK_SHIFT_CONST(17)
++#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_FIELD                       _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT)
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT                        _MK_SHIFT_CONST(18)
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT)
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT                        _MK_SHIFT_CONST(19)
++#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_FIELD                        _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT)
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT                   _MK_SHIFT_CONST(20)
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_FIELD                   _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT)
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT                   _MK_SHIFT_CONST(21)
++#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_FIELD                   _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register NVDLA_MCIF_CFG_RD_WEIGHT_0_0
++#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0                  _MK_ADDR_CONST(0x2000)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD                     _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT                      _MK_SHIFT_CONST(16)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT                      _MK_SHIFT_CONST(24)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT)
++
++
++// Register NVDLA_MCIF_CFG_RD_WEIGHT_1_0
++#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0                  _MK_ADDR_CONST(0x2004)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT                 _MK_SHIFT_CONST(24)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD                 _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT)
++
++
++// Register NVDLA_MCIF_CFG_RD_WEIGHT_2_0
++#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0                  _MK_ADDR_CONST(0x2008)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT                  _MK_SHIFT_CONST(0)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD                  _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT)
++
++
++// Register NVDLA_MCIF_CFG_WR_WEIGHT_0_0
++#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0                  _MK_ADDR_CONST(0x200c)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD                     _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT                      _MK_SHIFT_CONST(16)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT                      _MK_SHIFT_CONST(24)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT)
++
++
++// Register NVDLA_MCIF_CFG_WR_WEIGHT_1_0
++#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0                  _MK_ADDR_CONST(0x2010)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT                      _MK_SHIFT_CONST(0)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT)
++
++
++// Register NVDLA_MCIF_CFG_OUTSTANDING_CNT_0
++#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0                      _MK_ADDR_CONST(0x2014)
++#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT                      _MK_SHIFT_CONST(0)
++#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT)
++#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT)
++
++
++// Register NVDLA_MCIF_STATUS_0
++#define NVDLA_MCIF_STATUS_0                   _MK_ADDR_CONST(0x2018)
++#define NVDLA_MCIF_STATUS_0_IDLE_SHIFT                        _MK_SHIFT_CONST(8)
++#define NVDLA_MCIF_STATUS_0_IDLE_FIELD                        _MK_FIELD_CONST(0x1, NVDLA_MCIF_STATUS_0_IDLE_SHIFT)
++#define NVDLA_MCIF_STATUS_0_IDLE_NO                   _MK_ENUM_CONST(0x0)
++#define NVDLA_MCIF_STATUS_0_IDLE_YES                  _MK_ENUM_CONST(0x1)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register CDMA_S_STATUS_0
++#define CDMA_S_STATUS_0                       _MK_ADDR_CONST(0x3000)
++#define CDMA_S_STATUS_0_STATUS_0_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_S_STATUS_0_STATUS_0_FIELD                        _MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_0_SHIFT)
++#define CDMA_S_STATUS_0_STATUS_0_IDLE                 _MK_ENUM_CONST(0x0)
++#define CDMA_S_STATUS_0_STATUS_0_RUNNING                      _MK_ENUM_CONST(0x1)
++#define CDMA_S_STATUS_0_STATUS_0_PENDING                      _MK_ENUM_CONST(0x2)
++#define CDMA_S_STATUS_0_STATUS_1_SHIFT                        _MK_SHIFT_CONST(16)
++#define CDMA_S_STATUS_0_STATUS_1_FIELD                        _MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_1_SHIFT)
++#define CDMA_S_STATUS_0_STATUS_1_IDLE                 _MK_ENUM_CONST(0x0)
++#define CDMA_S_STATUS_0_STATUS_1_RUNNING                      _MK_ENUM_CONST(0x1)
++#define CDMA_S_STATUS_0_STATUS_1_PENDING                      _MK_ENUM_CONST(0x2)
++
++
++// Register CDMA_S_POINTER_0
++#define CDMA_S_POINTER_0                      _MK_ADDR_CONST(0x3004)
++#define CDMA_S_POINTER_0_PRODUCER_SHIFT                       _MK_SHIFT_CONST(0)
++#define CDMA_S_POINTER_0_PRODUCER_FIELD                       _MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_PRODUCER_SHIFT)
++#define CDMA_S_POINTER_0_PRODUCER_GROUP_0                     _MK_ENUM_CONST(0x0)
++#define CDMA_S_POINTER_0_PRODUCER_GROUP_1                     _MK_ENUM_CONST(0x1)
++#define CDMA_S_POINTER_0_CONSUMER_SHIFT                       _MK_SHIFT_CONST(16)
++#define CDMA_S_POINTER_0_CONSUMER_FIELD                       _MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_CONSUMER_SHIFT)
++#define CDMA_S_POINTER_0_CONSUMER_GROUP_0                     _MK_ENUM_CONST(0x0)
++#define CDMA_S_POINTER_0_CONSUMER_GROUP_1                     _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_S_ARBITER_0
++#define CDMA_S_ARBITER_0                      _MK_ADDR_CONST(0x3008)
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDMA_S_ARBITER_0_ARB_WEIGHT_FIELD                     _MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT)
++#define CDMA_S_ARBITER_0_ARB_WMB_SHIFT                        _MK_SHIFT_CONST(16)
++#define CDMA_S_ARBITER_0_ARB_WMB_FIELD                        _MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WMB_SHIFT)
++
++
++// Register CDMA_S_CBUF_FLUSH_STATUS_0
++#define CDMA_S_CBUF_FLUSH_STATUS_0                    _MK_ADDR_CONST(0x300c)
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_FIELD                   _MK_FIELD_CONST(0x1, CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT)
++
++
++// Register CDMA_D_OP_ENABLE_0
++#define CDMA_D_OP_ENABLE_0                    _MK_ADDR_CONST(0x3010)
++#define CDMA_D_OP_ENABLE_0_OP_EN_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_OP_ENABLE_0_OP_EN_FIELD                        _MK_FIELD_CONST(0x1, CDMA_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define CDMA_D_OP_ENABLE_0_OP_EN_DISABLE                      _MK_ENUM_CONST(0x0)
++#define CDMA_D_OP_ENABLE_0_OP_EN_ENABLE                       _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_D_MISC_CFG_0
++#define CDMA_D_MISC_CFG_0                     _MK_ADDR_CONST(0x3014)
++#define CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDMA_D_MISC_CFG_0_CONV_MODE_FIELD                     _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT)
++#define CDMA_D_MISC_CFG_0_CONV_MODE_DIRECT                    _MK_ENUM_CONST(0x0)
++#define CDMA_D_MISC_CFG_0_CONV_MODE_WINOGRAD                  _MK_ENUM_CONST(0x1)
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT                  _MK_SHIFT_CONST(8)
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_FIELD                  _MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT)
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT8                   _MK_ENUM_CONST(0x0)
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT16                  _MK_ENUM_CONST(0x1)
++#define CDMA_D_MISC_CFG_0_IN_PRECISION_FP16                   _MK_ENUM_CONST(0x2)
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT                        _MK_SHIFT_CONST(12)
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FIELD                        _MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT8                 _MK_ENUM_CONST(0x0)
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT16                        _MK_ENUM_CONST(0x1)
++#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FP16                 _MK_ENUM_CONST(0x2)
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT                    _MK_SHIFT_CONST(16)
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_FIELD                    _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT)
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_DISABLE                  _MK_ENUM_CONST(0x0)
++#define CDMA_D_MISC_CFG_0_DATA_REUSE_ENABLE                   _MK_ENUM_CONST(0x1)
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT                  _MK_SHIFT_CONST(20)
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_FIELD                  _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT)
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE                        _MK_ENUM_CONST(0x0)
++#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE                 _MK_ENUM_CONST(0x1)
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT                 _MK_SHIFT_CONST(24)
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD                 _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT)
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE                       _MK_ENUM_CONST(0x0)
++#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE                        _MK_ENUM_CONST(0x1)
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT                       _MK_SHIFT_CONST(28)
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD                       _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT)
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE                     _MK_ENUM_CONST(0x0)
++#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE                      _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_D_DATAIN_FORMAT_0
++#define CDMA_D_DATAIN_FORMAT_0                        _MK_ADDR_CONST(0x3018)
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD                    _MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT)
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE                  _MK_ENUM_CONST(0x0)
++#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL                    _MK_ENUM_CONST(0x1)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT                     _MK_SHIFT_CONST(8)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_FIELD                     _MK_FIELD_CONST(0x3f, CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8                      _MK_ENUM_CONST(0x0)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10                     _MK_ENUM_CONST(0x1)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R12                     _MK_ENUM_CONST(0x2)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16                     _MK_ENUM_CONST(0x3)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_I                   _MK_ENUM_CONST(0x4)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_F                   _MK_ENUM_CONST(0x5)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16                    _MK_ENUM_CONST(0x6)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X16B16G16R16                    _MK_ENUM_CONST(0x7)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16_F                  _MK_ENUM_CONST(0x8)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16                    _MK_ENUM_CONST(0x9)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V16U16Y16A16                    _MK_ENUM_CONST(0xa)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16_F                  _MK_ENUM_CONST(0xb)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8B8G8R8                        _MK_ENUM_CONST(0xc)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8R8G8B8                        _MK_ENUM_CONST(0xd)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8A8                        _MK_ENUM_CONST(0xe)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8A8                        _MK_ENUM_CONST(0xf)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8B8G8R8                        _MK_ENUM_CONST(0x10)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8R8G8B8                        _MK_ENUM_CONST(0x11)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8X8                        _MK_ENUM_CONST(0x12)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8X8                        _MK_ENUM_CONST(0x13)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2B10G10R10                     _MK_ENUM_CONST(0x14)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2R10G10B10                     _MK_ENUM_CONST(0x15)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B10G10R10A2                     _MK_ENUM_CONST(0x16)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10G10B10A2                     _MK_ENUM_CONST(0x17)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2Y10U10V10                     _MK_ENUM_CONST(0x18)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V10U10Y10A2                     _MK_ENUM_CONST(0x19)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8Y8U8V8                        _MK_ENUM_CONST(0x1a)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V8U8Y8A8                        _MK_ENUM_CONST(0x1b)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___U8V8_N444                  _MK_ENUM_CONST(0x1c)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___V8U8_N444                  _MK_ENUM_CONST(0x1d)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___U10V10_N444                       _MK_ENUM_CONST(0x1e)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___V10U10_N444                       _MK_ENUM_CONST(0x1f)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___U12V12_N444                       _MK_ENUM_CONST(0x20)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___V12U12_N444                       _MK_ENUM_CONST(0x21)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___U16V16_N444                       _MK_ENUM_CONST(0x22)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___V16U16_N444                       _MK_ENUM_CONST(0x23)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT                    _MK_SHIFT_CONST(16)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_FIELD                    _MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PITCH_LINEAR                     _MK_ENUM_CONST(0x0)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RESERVED_LINEAR                  _MK_ENUM_CONST(0x1)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT                      _MK_SHIFT_CONST(20)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_FIELD                      _MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_UNSIGNED_INT                       _MK_ENUM_CONST(0x0)
++#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SIGNED_INT                 _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_D_DATAIN_SIZE_0_0
++#define CDMA_D_DATAIN_SIZE_0_0                        _MK_ADDR_CONST(0x301c)
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD                     _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT)
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT                    _MK_SHIFT_CONST(16)
++#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD                    _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT)
++
++
++// Register CDMA_D_DATAIN_SIZE_1_0
++#define CDMA_D_DATAIN_SIZE_1_0                        _MK_ADDR_CONST(0x3020)
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD                   _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT)
++
++
++// Register CDMA_D_DATAIN_SIZE_EXT_0_0
++#define CDMA_D_DATAIN_SIZE_EXT_0_0                    _MK_ADDR_CONST(0x3024)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD                     _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT                    _MK_SHIFT_CONST(16)
++#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD                    _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT)
++
++
++// Register CDMA_D_PIXEL_OFFSET_0
++#define CDMA_D_PIXEL_OFFSET_0                 _MK_ADDR_CONST(0x3028)
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_FIELD                    _MK_FIELD_CONST(0x1f, CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT)
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT                    _MK_SHIFT_CONST(16)
++#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_FIELD                    _MK_FIELD_CONST(0x7, CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT)
++
++
++// Register CDMA_D_DAIN_RAM_TYPE_0
++#define CDMA_D_DAIN_RAM_TYPE_0                        _MK_ADDR_CONST(0x302c)
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT                  _MK_SHIFT_CONST(0)
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD                  _MK_FIELD_CONST(0x1, CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT)
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF                   _MK_ENUM_CONST(0x0)
++#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF                   _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_D_DAIN_ADDR_HIGH_0_0
++#define CDMA_D_DAIN_ADDR_HIGH_0_0                     _MK_ADDR_CONST(0x3030)
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_FIELD                    _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT)
++
++
++// Register CDMA_D_DAIN_ADDR_LOW_0_0
++#define CDMA_D_DAIN_ADDR_LOW_0_0                      _MK_ADDR_CONST(0x3034)
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_FIELD                      _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT)
++
++
++// Register CDMA_D_DAIN_ADDR_HIGH_1_0
++#define CDMA_D_DAIN_ADDR_HIGH_1_0                     _MK_ADDR_CONST(0x3038)
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_FIELD                    _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT)
++
++
++// Register CDMA_D_DAIN_ADDR_LOW_1_0
++#define CDMA_D_DAIN_ADDR_LOW_1_0                      _MK_ADDR_CONST(0x303c)
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_FIELD                      _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT)
++
++
++// Register CDMA_D_LINE_STRIDE_0
++#define CDMA_D_LINE_STRIDE_0                  _MK_ADDR_CONST(0x3040)
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_FIELD                        _MK_FIELD_CONST(0xffffffff, CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT)
++
++
++// Register CDMA_D_LINE_UV_STRIDE_0
++#define CDMA_D_LINE_UV_STRIDE_0                       _MK_ADDR_CONST(0x3044)
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT                  _MK_SHIFT_CONST(0)
++#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_FIELD                  _MK_FIELD_CONST(0xffffffff, CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT)
++
++
++// Register CDMA_D_SURF_STRIDE_0
++#define CDMA_D_SURF_STRIDE_0                  _MK_ADDR_CONST(0x3048)
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_FIELD                        _MK_FIELD_CONST(0xffffffff, CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT)
++
++
++// Register CDMA_D_DAIN_MAP_0
++#define CDMA_D_DAIN_MAP_0                     _MK_ADDR_CONST(0x304c)
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FIELD                   _MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT)
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FALSE                   _MK_ENUM_CONST(0x0)
++#define CDMA_D_DAIN_MAP_0_LINE_PACKED_TRUE                    _MK_ENUM_CONST(0x1)
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT                   _MK_SHIFT_CONST(16)
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FIELD                   _MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT)
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FALSE                   _MK_ENUM_CONST(0x0)
++#define CDMA_D_DAIN_MAP_0_SURF_PACKED_TRUE                    _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_D_RESERVED_X_CFG_0
++#define CDMA_D_RESERVED_X_CFG_0                       _MK_ADDR_CONST(0x3050)
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_FIELD                    _MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT)
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT                 _MK_SHIFT_CONST(16)
++#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_FIELD                 _MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT)
++
++
++// Register CDMA_D_RESERVED_Y_CFG_0
++#define CDMA_D_RESERVED_Y_CFG_0                       _MK_ADDR_CONST(0x3054)
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_FIELD                      _MK_FIELD_CONST(0x7, CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT)
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT                     _MK_SHIFT_CONST(16)
++#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_FIELD                     _MK_FIELD_CONST(0x1f, CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT)
++
++
++// Register CDMA_D_BATCH_NUMBER_0
++#define CDMA_D_BATCH_NUMBER_0                 _MK_ADDR_CONST(0x3058)
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDMA_D_BATCH_NUMBER_0_BATCHES_FIELD                   _MK_FIELD_CONST(0x1f, CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT)
++
++
++// Register CDMA_D_BATCH_STRIDE_0
++#define CDMA_D_BATCH_STRIDE_0                 _MK_ADDR_CONST(0x305c)
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_FIELD                      _MK_FIELD_CONST(0xffffffff, CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT)
++
++
++// Register CDMA_D_ENTRY_PER_SLICE_0
++#define CDMA_D_ENTRY_PER_SLICE_0                      _MK_ADDR_CONST(0x3060)
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD                        _MK_FIELD_CONST(0x3fff, CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT)
++
++
++// Register CDMA_D_FETCH_GRAIN_0
++#define CDMA_D_FETCH_GRAIN_0                  _MK_ADDR_CONST(0x3064)
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDMA_D_FETCH_GRAIN_0_GRAINS_FIELD                     _MK_FIELD_CONST(0xfff, CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT)
++
++
++// Register CDMA_D_WEIGHT_FORMAT_0
++#define CDMA_D_WEIGHT_FORMAT_0                        _MK_ADDR_CONST(0x3068)
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD                    _MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT)
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED                     _MK_ENUM_CONST(0x0)
++#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED                       _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_D_WEIGHT_SIZE_0_0
++#define CDMA_D_WEIGHT_SIZE_0_0                        _MK_ADDR_CONST(0x306c)
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT                  _MK_SHIFT_CONST(0)
++#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_FIELD                  _MK_FIELD_CONST(0x3ffff, CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT)
++
++
++// Register CDMA_D_WEIGHT_SIZE_1_0
++#define CDMA_D_WEIGHT_SIZE_1_0                        _MK_ADDR_CONST(0x3070)
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_FIELD                    _MK_FIELD_CONST(0x1fff, CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT)
++
++
++// Register CDMA_D_WEIGHT_RAM_TYPE_0
++#define CDMA_D_WEIGHT_RAM_TYPE_0                      _MK_ADDR_CONST(0x3074)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_FIELD                        _MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_CVIF                 _MK_ENUM_CONST(0x0)
++#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_MCIF                 _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_D_WEIGHT_ADDR_HIGH_0
++#define CDMA_D_WEIGHT_ADDR_HIGH_0                     _MK_ADDR_CONST(0x3078)
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_FIELD                      _MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT)
++
++
++// Register CDMA_D_WEIGHT_ADDR_LOW_0
++#define CDMA_D_WEIGHT_ADDR_LOW_0                      _MK_ADDR_CONST(0x307c)
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_FIELD                        _MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT)
++
++
++// Register CDMA_D_WEIGHT_BYTES_0
++#define CDMA_D_WEIGHT_BYTES_0                 _MK_ADDR_CONST(0x3080)
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD                      _MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT)
++
++
++// Register CDMA_D_WGS_ADDR_HIGH_0
++#define CDMA_D_WGS_ADDR_HIGH_0                        _MK_ADDR_CONST(0x3084)
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_FIELD                    _MK_FIELD_CONST(0xffffffff, CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT)
++
++
++// Register CDMA_D_WGS_ADDR_LOW_0
++#define CDMA_D_WGS_ADDR_LOW_0                 _MK_ADDR_CONST(0x3088)
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_FIELD                      _MK_FIELD_CONST(0xffffffff, CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT)
++
++
++// Register CDMA_D_WMB_ADDR_HIGH_0
++#define CDMA_D_WMB_ADDR_HIGH_0                        _MK_ADDR_CONST(0x308c)
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_FIELD                    _MK_FIELD_CONST(0xffffffff, CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT)
++
++
++// Register CDMA_D_WMB_ADDR_LOW_0
++#define CDMA_D_WMB_ADDR_LOW_0                 _MK_ADDR_CONST(0x3090)
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_FIELD                      _MK_FIELD_CONST(0xffffffff, CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT)
++
++
++// Register CDMA_D_WMB_BYTES_0
++#define CDMA_D_WMB_BYTES_0                    _MK_ADDR_CONST(0x3094)
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_WMB_BYTES_0_WMB_BYTES_FIELD                    _MK_FIELD_CONST(0xfffffff, CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT)
++
++
++// Register CDMA_D_MEAN_FORMAT_0
++#define CDMA_D_MEAN_FORMAT_0                  _MK_ADDR_CONST(0x3098)
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_FIELD                        _MK_FIELD_CONST(0x1, CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT)
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DISABLE                      _MK_ENUM_CONST(0x0)
++#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_ENABLE                       _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_D_MEAN_GLOBAL_0_0
++#define CDMA_D_MEAN_GLOBAL_0_0                        _MK_ADDR_CONST(0x309c)
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT                  _MK_SHIFT_CONST(0)
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_FIELD                  _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT)
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT                  _MK_SHIFT_CONST(16)
++#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_FIELD                  _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT)
++
++
++// Register CDMA_D_MEAN_GLOBAL_1_0
++#define CDMA_D_MEAN_GLOBAL_1_0                        _MK_ADDR_CONST(0x30a0)
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT                  _MK_SHIFT_CONST(0)
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_FIELD                  _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT)
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT                  _MK_SHIFT_CONST(16)
++#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_FIELD                  _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT)
++
++
++// Register CDMA_D_CVT_CFG_0
++#define CDMA_D_CVT_CFG_0                      _MK_ADDR_CONST(0x30a4)
++#define CDMA_D_CVT_CFG_0_CVT_EN_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDMA_D_CVT_CFG_0_CVT_EN_FIELD                 _MK_FIELD_CONST(0x1, CDMA_D_CVT_CFG_0_CVT_EN_SHIFT)
++#define CDMA_D_CVT_CFG_0_CVT_EN_DISABLE                       _MK_ENUM_CONST(0x0)
++#define CDMA_D_CVT_CFG_0_CVT_EN_ENABLE                        _MK_ENUM_CONST(0x1)
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT                   _MK_SHIFT_CONST(4)
++#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_FIELD                   _MK_FIELD_CONST(0x3f, CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT)
++
++
++// Register CDMA_D_CVT_OFFSET_0
++#define CDMA_D_CVT_OFFSET_0                   _MK_ADDR_CONST(0x30a8)
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT                  _MK_SHIFT_CONST(0)
++#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_FIELD                  _MK_FIELD_CONST(0xffff, CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT)
++
++
++// Register CDMA_D_CVT_SCALE_0
++#define CDMA_D_CVT_SCALE_0                    _MK_ADDR_CONST(0x30ac)
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_CVT_SCALE_0_CVT_SCALE_FIELD                    _MK_FIELD_CONST(0xffff, CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT)
++
++
++// Register CDMA_D_CONV_STRIDE_0
++#define CDMA_D_CONV_STRIDE_0                  _MK_ADDR_CONST(0x30b0)
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_FIELD                      _MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT)
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT                      _MK_SHIFT_CONST(16)
++#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_FIELD                      _MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT)
++
++
++// Register CDMA_D_ZERO_PADDING_0
++#define CDMA_D_ZERO_PADDING_0                 _MK_ADDR_CONST(0x30b4)
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT                  _MK_SHIFT_CONST(0)
++#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_FIELD                  _MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT)
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT                 _MK_SHIFT_CONST(8)
++#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_FIELD                 _MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT)
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT                   _MK_SHIFT_CONST(16)
++#define CDMA_D_ZERO_PADDING_0_PAD_TOP_FIELD                   _MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT)
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT                        _MK_SHIFT_CONST(24)
++#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_FIELD                        _MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT)
++
++
++// Register CDMA_D_ZERO_PADDING_VALUE_0
++#define CDMA_D_ZERO_PADDING_VALUE_0                   _MK_ADDR_CONST(0x30b8)
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD                   _MK_FIELD_CONST(0xffff, CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT)
++
++
++// Register CDMA_D_BANK_0
++#define CDMA_D_BANK_0                 _MK_ADDR_CONST(0x30bc)
++#define CDMA_D_BANK_0_DATA_BANK_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDMA_D_BANK_0_DATA_BANK_FIELD                 _MK_FIELD_CONST(0x1f, CDMA_D_BANK_0_DATA_BANK_SHIFT)
++#define CDMA_D_BANK_0_WEIGHT_BANK_SHIFT                       _MK_SHIFT_CONST(16)
++#define CDMA_D_BANK_0_WEIGHT_BANK_FIELD                       _MK_FIELD_CONST(0x1f, CDMA_D_BANK_0_WEIGHT_BANK_SHIFT)
++
++
++// Register CDMA_D_NAN_FLUSH_TO_ZERO_0
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0                    _MK_ADDR_CONST(0x30c0)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT                  _MK_SHIFT_CONST(0)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD                  _MK_FIELD_CONST(0x1, CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE                        _MK_ENUM_CONST(0x0)
++#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE                 _MK_ENUM_CONST(0x1)
++
++
++// Register CDMA_D_NAN_INPUT_DATA_NUM_0
++#define CDMA_D_NAN_INPUT_DATA_NUM_0                   _MK_ADDR_CONST(0x30c4)
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_FIELD                        _MK_FIELD_CONST(0xffffffff, CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT)
++
++
++// Register CDMA_D_NAN_INPUT_WEIGHT_NUM_0
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0                 _MK_ADDR_CONST(0x30c8)
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_FIELD                    _MK_FIELD_CONST(0xffffffff, CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT)
++
++
++// Register CDMA_D_INF_INPUT_DATA_NUM_0
++#define CDMA_D_INF_INPUT_DATA_NUM_0                   _MK_ADDR_CONST(0x30cc)
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_FIELD                        _MK_FIELD_CONST(0xffffffff, CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT)
++
++
++// Register CDMA_D_INF_INPUT_WEIGHT_NUM_0
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0                 _MK_ADDR_CONST(0x30d0)
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_FIELD                    _MK_FIELD_CONST(0xffffffff, CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT)
++
++
++// Register CDMA_D_PERF_ENABLE_0
++#define CDMA_D_PERF_ENABLE_0                  _MK_ADDR_CONST(0x30d4)
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDMA_D_PERF_ENABLE_0_DMA_EN_FIELD                     _MK_FIELD_CONST(0x1, CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT)
++
++
++// Register CDMA_D_PERF_DAT_READ_STALL_0
++#define CDMA_D_PERF_DAT_READ_STALL_0                  _MK_ADDR_CONST(0x30d8)
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT                       _MK_SHIFT_CONST(0)
++#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_FIELD                       _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT)
++
++
++// Register CDMA_D_PERF_WT_READ_STALL_0
++#define CDMA_D_PERF_WT_READ_STALL_0                   _MK_ADDR_CONST(0x30dc)
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_FIELD                 _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT)
++
++
++// Register CDMA_D_PERF_DAT_READ_LATENCY_0
++#define CDMA_D_PERF_DAT_READ_LATENCY_0                        _MK_ADDR_CONST(0x30e0)
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_FIELD                   _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT)
++
++
++// Register CDMA_D_PERF_WT_READ_LATENCY_0
++#define CDMA_D_PERF_WT_READ_LATENCY_0                 _MK_ADDR_CONST(0x30e4)
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_FIELD                     _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT)
++
++
++// Register CDMA_D_CYA_0
++#define CDMA_D_CYA_0                  _MK_ADDR_CONST(0x30e8)
++#define CDMA_D_CYA_0_CYA_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDMA_D_CYA_0_CYA_FIELD                        _MK_FIELD_CONST(0xffffffff, CDMA_D_CYA_0_CYA_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register CSC_S_STATUS_0
++#define CSC_S_STATUS_0                        _MK_ADDR_CONST(0x4000)
++#define CSC_S_STATUS_0_STATUS_0_SHIFT                 _MK_SHIFT_CONST(0)
++#define CSC_S_STATUS_0_STATUS_0_FIELD                 _MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_0_SHIFT)
++#define CSC_S_STATUS_0_STATUS_0_IDLE                  _MK_ENUM_CONST(0x0)
++#define CSC_S_STATUS_0_STATUS_0_RUNNING                       _MK_ENUM_CONST(0x1)
++#define CSC_S_STATUS_0_STATUS_0_PENDING                       _MK_ENUM_CONST(0x2)
++#define CSC_S_STATUS_0_STATUS_1_SHIFT                 _MK_SHIFT_CONST(16)
++#define CSC_S_STATUS_0_STATUS_1_FIELD                 _MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_1_SHIFT)
++#define CSC_S_STATUS_0_STATUS_1_IDLE                  _MK_ENUM_CONST(0x0)
++#define CSC_S_STATUS_0_STATUS_1_RUNNING                       _MK_ENUM_CONST(0x1)
++#define CSC_S_STATUS_0_STATUS_1_PENDING                       _MK_ENUM_CONST(0x2)
++
++
++// Register CSC_S_POINTER_0
++#define CSC_S_POINTER_0                       _MK_ADDR_CONST(0x4004)
++#define CSC_S_POINTER_0_PRODUCER_SHIFT                        _MK_SHIFT_CONST(0)
++#define CSC_S_POINTER_0_PRODUCER_FIELD                        _MK_FIELD_CONST(0x1, CSC_S_POINTER_0_PRODUCER_SHIFT)
++#define CSC_S_POINTER_0_PRODUCER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define CSC_S_POINTER_0_PRODUCER_GROUP_1                      _MK_ENUM_CONST(0x1)
++#define CSC_S_POINTER_0_CONSUMER_SHIFT                        _MK_SHIFT_CONST(16)
++#define CSC_S_POINTER_0_CONSUMER_FIELD                        _MK_FIELD_CONST(0x1, CSC_S_POINTER_0_CONSUMER_SHIFT)
++#define CSC_S_POINTER_0_CONSUMER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define CSC_S_POINTER_0_CONSUMER_GROUP_1                      _MK_ENUM_CONST(0x1)
++
++
++// Register CSC_D_OP_ENABLE_0
++#define CSC_D_OP_ENABLE_0                     _MK_ADDR_CONST(0x4008)
++#define CSC_D_OP_ENABLE_0_OP_EN_SHIFT                 _MK_SHIFT_CONST(0)
++#define CSC_D_OP_ENABLE_0_OP_EN_FIELD                 _MK_FIELD_CONST(0x1, CSC_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define CSC_D_OP_ENABLE_0_OP_EN_DISABLE                       _MK_ENUM_CONST(0x0)
++#define CSC_D_OP_ENABLE_0_OP_EN_ENABLE                        _MK_ENUM_CONST(0x1)
++
++
++// Register CSC_D_MISC_CFG_0
++#define CSC_D_MISC_CFG_0                      _MK_ADDR_CONST(0x400c)
++#define CSC_D_MISC_CFG_0_CONV_MODE_SHIFT                      _MK_SHIFT_CONST(0)
++#define CSC_D_MISC_CFG_0_CONV_MODE_FIELD                      _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_CONV_MODE_SHIFT)
++#define CSC_D_MISC_CFG_0_CONV_MODE_DIRECT                     _MK_ENUM_CONST(0x0)
++#define CSC_D_MISC_CFG_0_CONV_MODE_WINOGRAD                   _MK_ENUM_CONST(0x1)
++#define CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT                   _MK_SHIFT_CONST(8)
++#define CSC_D_MISC_CFG_0_IN_PRECISION_FIELD                   _MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT)
++#define CSC_D_MISC_CFG_0_IN_PRECISION_INT8                    _MK_ENUM_CONST(0x0)
++#define CSC_D_MISC_CFG_0_IN_PRECISION_INT16                   _MK_ENUM_CONST(0x1)
++#define CSC_D_MISC_CFG_0_IN_PRECISION_FP16                    _MK_ENUM_CONST(0x2)
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT                 _MK_SHIFT_CONST(12)
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_FIELD                 _MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT8                  _MK_ENUM_CONST(0x0)
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT16                 _MK_ENUM_CONST(0x1)
++#define CSC_D_MISC_CFG_0_PROC_PRECISION_FP16                  _MK_ENUM_CONST(0x2)
++#define CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT                     _MK_SHIFT_CONST(16)
++#define CSC_D_MISC_CFG_0_DATA_REUSE_FIELD                     _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT)
++#define CSC_D_MISC_CFG_0_DATA_REUSE_DISABLE                   _MK_ENUM_CONST(0x0)
++#define CSC_D_MISC_CFG_0_DATA_REUSE_ENABLE                    _MK_ENUM_CONST(0x1)
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT                   _MK_SHIFT_CONST(20)
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_FIELD                   _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT)
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE                 _MK_ENUM_CONST(0x0)
++#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE                  _MK_ENUM_CONST(0x1)
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT                  _MK_SHIFT_CONST(24)
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD                  _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT)
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE                        _MK_ENUM_CONST(0x0)
++#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE                 _MK_ENUM_CONST(0x1)
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT                        _MK_SHIFT_CONST(28)
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD                        _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT)
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE                      _MK_ENUM_CONST(0x0)
++#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE                       _MK_ENUM_CONST(0x1)
++
++
++// Register CSC_D_DATAIN_FORMAT_0
++#define CSC_D_DATAIN_FORMAT_0                 _MK_ADDR_CONST(0x4010)
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT                     _MK_SHIFT_CONST(0)
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD                     _MK_FIELD_CONST(0x1, CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT)
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE                   _MK_ENUM_CONST(0x0)
++#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL                     _MK_ENUM_CONST(0x1)
++
++
++// Register CSC_D_DATAIN_SIZE_EXT_0_0
++#define CSC_D_DATAIN_SIZE_EXT_0_0                     _MK_ADDR_CONST(0x4014)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT                      _MK_SHIFT_CONST(0)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD                      _MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT                     _MK_SHIFT_CONST(16)
++#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD                     _MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT)
++
++
++// Register CSC_D_DATAIN_SIZE_EXT_1_0
++#define CSC_D_DATAIN_SIZE_EXT_1_0                     _MK_ADDR_CONST(0x4018)
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT                    _MK_SHIFT_CONST(0)
++#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_FIELD                    _MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT)
++
++
++// Register CSC_D_BATCH_NUMBER_0
++#define CSC_D_BATCH_NUMBER_0                  _MK_ADDR_CONST(0x401c)
++#define CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT                    _MK_SHIFT_CONST(0)
++#define CSC_D_BATCH_NUMBER_0_BATCHES_FIELD                    _MK_FIELD_CONST(0x1f, CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT)
++
++
++// Register CSC_D_POST_Y_EXTENSION_0
++#define CSC_D_POST_Y_EXTENSION_0                      _MK_ADDR_CONST(0x4020)
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT                    _MK_SHIFT_CONST(0)
++#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_FIELD                    _MK_FIELD_CONST(0x3, CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT)
++
++
++// Register CSC_D_ENTRY_PER_SLICE_0
++#define CSC_D_ENTRY_PER_SLICE_0                       _MK_ADDR_CONST(0x4024)
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT                 _MK_SHIFT_CONST(0)
++#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD                 _MK_FIELD_CONST(0x3fff, CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT)
++
++
++// Register CSC_D_WEIGHT_FORMAT_0
++#define CSC_D_WEIGHT_FORMAT_0                 _MK_ADDR_CONST(0x4028)
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT                     _MK_SHIFT_CONST(0)
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD                     _MK_FIELD_CONST(0x1, CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT)
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED                      _MK_ENUM_CONST(0x0)
++#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED                        _MK_ENUM_CONST(0x1)
++
++
++// Register CSC_D_WEIGHT_SIZE_EXT_0_0
++#define CSC_D_WEIGHT_SIZE_EXT_0_0                     _MK_ADDR_CONST(0x402c)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT                      _MK_SHIFT_CONST(0)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_FIELD                      _MK_FIELD_CONST(0x1f, CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT                     _MK_SHIFT_CONST(16)
++#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_FIELD                     _MK_FIELD_CONST(0x1f, CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT)
++
++
++// Register CSC_D_WEIGHT_SIZE_EXT_1_0
++#define CSC_D_WEIGHT_SIZE_EXT_1_0                     _MK_ADDR_CONST(0x4030)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT                    _MK_SHIFT_CONST(0)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_FIELD                    _MK_FIELD_CONST(0x1fff, CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT                 _MK_SHIFT_CONST(16)
++#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_FIELD                 _MK_FIELD_CONST(0x1fff, CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT)
++
++
++// Register CSC_D_WEIGHT_BYTES_0
++#define CSC_D_WEIGHT_BYTES_0                  _MK_ADDR_CONST(0x4034)
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT                       _MK_SHIFT_CONST(0)
++#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD                       _MK_FIELD_CONST(0xffffffff, CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT)
++
++
++// Register CSC_D_WMB_BYTES_0
++#define CSC_D_WMB_BYTES_0                     _MK_ADDR_CONST(0x4038)
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT                     _MK_SHIFT_CONST(0)
++#define CSC_D_WMB_BYTES_0_WMB_BYTES_FIELD                     _MK_FIELD_CONST(0xfffffff, CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT)
++
++
++// Register CSC_D_DATAOUT_SIZE_0_0
++#define CSC_D_DATAOUT_SIZE_0_0                        _MK_ADDR_CONST(0x403c)
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT                    _MK_SHIFT_CONST(0)
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD                    _MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT)
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT                   _MK_SHIFT_CONST(16)
++#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD                   _MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT)
++
++
++// Register CSC_D_DATAOUT_SIZE_1_0
++#define CSC_D_DATAOUT_SIZE_1_0                        _MK_ADDR_CONST(0x4040)
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT                  _MK_SHIFT_CONST(0)
++#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD                  _MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT)
++
++
++// Register CSC_D_ATOMICS_0
++#define CSC_D_ATOMICS_0                       _MK_ADDR_CONST(0x4044)
++#define CSC_D_ATOMICS_0_ATOMICS_SHIFT                 _MK_SHIFT_CONST(0)
++#define CSC_D_ATOMICS_0_ATOMICS_FIELD                 _MK_FIELD_CONST(0x1fffff, CSC_D_ATOMICS_0_ATOMICS_SHIFT)
++
++
++// Register CSC_D_RELEASE_0
++#define CSC_D_RELEASE_0                       _MK_ADDR_CONST(0x4048)
++#define CSC_D_RELEASE_0_RLS_SLICES_SHIFT                      _MK_SHIFT_CONST(0)
++#define CSC_D_RELEASE_0_RLS_SLICES_FIELD                      _MK_FIELD_CONST(0xfff, CSC_D_RELEASE_0_RLS_SLICES_SHIFT)
++
++
++// Register CSC_D_CONV_STRIDE_EXT_0
++#define CSC_D_CONV_STRIDE_EXT_0                       _MK_ADDR_CONST(0x404c)
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT                       _MK_SHIFT_CONST(0)
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_FIELD                       _MK_FIELD_CONST(0x7, CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT)
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT                       _MK_SHIFT_CONST(16)
++#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_FIELD                       _MK_FIELD_CONST(0x7, CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT)
++
++
++// Register CSC_D_DILATION_EXT_0
++#define CSC_D_DILATION_EXT_0                  _MK_ADDR_CONST(0x4050)
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT                     _MK_SHIFT_CONST(0)
++#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_FIELD                     _MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT)
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT                     _MK_SHIFT_CONST(16)
++#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_FIELD                     _MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT)
++
++
++// Register CSC_D_ZERO_PADDING_0
++#define CSC_D_ZERO_PADDING_0                  _MK_ADDR_CONST(0x4054)
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT                   _MK_SHIFT_CONST(0)
++#define CSC_D_ZERO_PADDING_0_PAD_LEFT_FIELD                   _MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT)
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT                    _MK_SHIFT_CONST(16)
++#define CSC_D_ZERO_PADDING_0_PAD_TOP_FIELD                    _MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT)
++
++
++// Register CSC_D_ZERO_PADDING_VALUE_0
++#define CSC_D_ZERO_PADDING_VALUE_0                    _MK_ADDR_CONST(0x4058)
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
++#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD                    _MK_FIELD_CONST(0xffff, CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT)
++
++
++// Register CSC_D_BANK_0
++#define CSC_D_BANK_0                  _MK_ADDR_CONST(0x405c)
++#define CSC_D_BANK_0_DATA_BANK_SHIFT                  _MK_SHIFT_CONST(0)
++#define CSC_D_BANK_0_DATA_BANK_FIELD                  _MK_FIELD_CONST(0x1f, CSC_D_BANK_0_DATA_BANK_SHIFT)
++#define CSC_D_BANK_0_WEIGHT_BANK_SHIFT                        _MK_SHIFT_CONST(16)
++#define CSC_D_BANK_0_WEIGHT_BANK_FIELD                        _MK_FIELD_CONST(0x1f, CSC_D_BANK_0_WEIGHT_BANK_SHIFT)
++
++
++// Register CSC_D_PRA_CFG_0
++#define CSC_D_PRA_CFG_0                       _MK_ADDR_CONST(0x4060)
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT                    _MK_SHIFT_CONST(0)
++#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_FIELD                    _MK_FIELD_CONST(0x3, CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT)
++
++
++// Register CSC_D_CYA_0
++#define CSC_D_CYA_0                   _MK_ADDR_CONST(0x4064)
++#define CSC_D_CYA_0_CYA_SHIFT                 _MK_SHIFT_CONST(0)
++#define CSC_D_CYA_0_CYA_FIELD                 _MK_FIELD_CONST(0xffffffff, CSC_D_CYA_0_CYA_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register CMAC_A_S_STATUS_0
++#define CMAC_A_S_STATUS_0                     _MK_ADDR_CONST(0x5000)
++#define CMAC_A_S_STATUS_0_STATUS_0_SHIFT                      _MK_SHIFT_CONST(0)
++#define CMAC_A_S_STATUS_0_STATUS_0_FIELD                      _MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_0_SHIFT)
++#define CMAC_A_S_STATUS_0_STATUS_0_IDLE                       _MK_ENUM_CONST(0x0)
++#define CMAC_A_S_STATUS_0_STATUS_0_RUNNING                    _MK_ENUM_CONST(0x1)
++#define CMAC_A_S_STATUS_0_STATUS_0_PENDING                    _MK_ENUM_CONST(0x2)
++#define CMAC_A_S_STATUS_0_STATUS_1_SHIFT                      _MK_SHIFT_CONST(16)
++#define CMAC_A_S_STATUS_0_STATUS_1_FIELD                      _MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_1_SHIFT)
++#define CMAC_A_S_STATUS_0_STATUS_1_IDLE                       _MK_ENUM_CONST(0x0)
++#define CMAC_A_S_STATUS_0_STATUS_1_RUNNING                    _MK_ENUM_CONST(0x1)
++#define CMAC_A_S_STATUS_0_STATUS_1_PENDING                    _MK_ENUM_CONST(0x2)
++
++
++// Register CMAC_A_S_POINTER_0
++#define CMAC_A_S_POINTER_0                    _MK_ADDR_CONST(0x5004)
++#define CMAC_A_S_POINTER_0_PRODUCER_SHIFT                     _MK_SHIFT_CONST(0)
++#define CMAC_A_S_POINTER_0_PRODUCER_FIELD                     _MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_PRODUCER_SHIFT)
++#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_0                   _MK_ENUM_CONST(0x0)
++#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_1                   _MK_ENUM_CONST(0x1)
++#define CMAC_A_S_POINTER_0_CONSUMER_SHIFT                     _MK_SHIFT_CONST(16)
++#define CMAC_A_S_POINTER_0_CONSUMER_FIELD                     _MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_CONSUMER_SHIFT)
++#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_0                   _MK_ENUM_CONST(0x0)
++#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_1                   _MK_ENUM_CONST(0x1)
++
++
++// Register CMAC_A_D_OP_ENABLE_0
++#define CMAC_A_D_OP_ENABLE_0                  _MK_ADDR_CONST(0x5008)
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT                      _MK_SHIFT_CONST(0)
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_FIELD                      _MK_FIELD_CONST(0x1, CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_DISABLE                    _MK_ENUM_CONST(0x0)
++#define CMAC_A_D_OP_ENABLE_0_OP_EN_ENABLE                     _MK_ENUM_CONST(0x1)
++
++
++// Register CMAC_A_D_MISC_CFG_0
++#define CMAC_A_D_MISC_CFG_0                   _MK_ADDR_CONST(0x500c)
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT                   _MK_SHIFT_CONST(0)
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_FIELD                   _MK_FIELD_CONST(0x1, CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT)
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DIRECT                  _MK_ENUM_CONST(0x0)
++#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WINOGRAD                        _MK_ENUM_CONST(0x1)
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT                      _MK_SHIFT_CONST(12)
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FIELD                      _MK_FIELD_CONST(0x3, CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT8                       _MK_ENUM_CONST(0x0)
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT16                      _MK_ENUM_CONST(0x1)
++#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FP16                       _MK_ENUM_CONST(0x2)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register CMAC_B_S_STATUS_0
++#define CMAC_B_S_STATUS_0                     _MK_ADDR_CONST(0x6000)
++#define CMAC_B_S_STATUS_0_STATUS_0_SHIFT                      _MK_SHIFT_CONST(0)
++#define CMAC_B_S_STATUS_0_STATUS_0_FIELD                      _MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_0_SHIFT)
++#define CMAC_B_S_STATUS_0_STATUS_0_IDLE                       _MK_ENUM_CONST(0x0)
++#define CMAC_B_S_STATUS_0_STATUS_0_RUNNING                    _MK_ENUM_CONST(0x1)
++#define CMAC_B_S_STATUS_0_STATUS_0_PENDING                    _MK_ENUM_CONST(0x2)
++#define CMAC_B_S_STATUS_0_STATUS_1_SHIFT                      _MK_SHIFT_CONST(16)
++#define CMAC_B_S_STATUS_0_STATUS_1_FIELD                      _MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_1_SHIFT)
++#define CMAC_B_S_STATUS_0_STATUS_1_IDLE                       _MK_ENUM_CONST(0x0)
++#define CMAC_B_S_STATUS_0_STATUS_1_RUNNING                    _MK_ENUM_CONST(0x1)
++#define CMAC_B_S_STATUS_0_STATUS_1_PENDING                    _MK_ENUM_CONST(0x2)
++
++
++// Register CMAC_B_S_POINTER_0
++#define CMAC_B_S_POINTER_0                    _MK_ADDR_CONST(0x6004)
++#define CMAC_B_S_POINTER_0_PRODUCER_SHIFT                     _MK_SHIFT_CONST(0)
++#define CMAC_B_S_POINTER_0_PRODUCER_FIELD                     _MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_PRODUCER_SHIFT)
++#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_0                   _MK_ENUM_CONST(0x0)
++#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_1                   _MK_ENUM_CONST(0x1)
++#define CMAC_B_S_POINTER_0_CONSUMER_SHIFT                     _MK_SHIFT_CONST(16)
++#define CMAC_B_S_POINTER_0_CONSUMER_FIELD                     _MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_CONSUMER_SHIFT)
++#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_0                   _MK_ENUM_CONST(0x0)
++#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_1                   _MK_ENUM_CONST(0x1)
++
++
++// Register CMAC_B_D_OP_ENABLE_0
++#define CMAC_B_D_OP_ENABLE_0                  _MK_ADDR_CONST(0x6008)
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT                      _MK_SHIFT_CONST(0)
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_FIELD                      _MK_FIELD_CONST(0x1, CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_DISABLE                    _MK_ENUM_CONST(0x0)
++#define CMAC_B_D_OP_ENABLE_0_OP_EN_ENABLE                     _MK_ENUM_CONST(0x1)
++
++
++// Register CMAC_B_D_MISC_CFG_0
++#define CMAC_B_D_MISC_CFG_0                   _MK_ADDR_CONST(0x600c)
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT                   _MK_SHIFT_CONST(0)
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_FIELD                   _MK_FIELD_CONST(0x1, CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT)
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DIRECT                  _MK_ENUM_CONST(0x0)
++#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WINOGRAD                        _MK_ENUM_CONST(0x1)
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT                      _MK_SHIFT_CONST(12)
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FIELD                      _MK_FIELD_CONST(0x3, CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT8                       _MK_ENUM_CONST(0x0)
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT16                      _MK_ENUM_CONST(0x1)
++#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FP16                       _MK_ENUM_CONST(0x2)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register CACC_S_STATUS_0
++#define CACC_S_STATUS_0                       _MK_ADDR_CONST(0x7000)
++#define CACC_S_STATUS_0_STATUS_0_SHIFT                        _MK_SHIFT_CONST(0)
++#define CACC_S_STATUS_0_STATUS_0_FIELD                        _MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_0_SHIFT)
++#define CACC_S_STATUS_0_STATUS_0_IDLE                 _MK_ENUM_CONST(0x0)
++#define CACC_S_STATUS_0_STATUS_0_RUNNING                      _MK_ENUM_CONST(0x1)
++#define CACC_S_STATUS_0_STATUS_0_PENDING                      _MK_ENUM_CONST(0x2)
++#define CACC_S_STATUS_0_STATUS_1_SHIFT                        _MK_SHIFT_CONST(16)
++#define CACC_S_STATUS_0_STATUS_1_FIELD                        _MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_1_SHIFT)
++#define CACC_S_STATUS_0_STATUS_1_IDLE                 _MK_ENUM_CONST(0x0)
++#define CACC_S_STATUS_0_STATUS_1_RUNNING                      _MK_ENUM_CONST(0x1)
++#define CACC_S_STATUS_0_STATUS_1_PENDING                      _MK_ENUM_CONST(0x2)
++
++
++// Register CACC_S_POINTER_0
++#define CACC_S_POINTER_0                      _MK_ADDR_CONST(0x7004)
++#define CACC_S_POINTER_0_PRODUCER_SHIFT                       _MK_SHIFT_CONST(0)
++#define CACC_S_POINTER_0_PRODUCER_FIELD                       _MK_FIELD_CONST(0x1, CACC_S_POINTER_0_PRODUCER_SHIFT)
++#define CACC_S_POINTER_0_PRODUCER_GROUP_0                     _MK_ENUM_CONST(0x0)
++#define CACC_S_POINTER_0_PRODUCER_GROUP_1                     _MK_ENUM_CONST(0x1)
++#define CACC_S_POINTER_0_CONSUMER_SHIFT                       _MK_SHIFT_CONST(16)
++#define CACC_S_POINTER_0_CONSUMER_FIELD                       _MK_FIELD_CONST(0x1, CACC_S_POINTER_0_CONSUMER_SHIFT)
++#define CACC_S_POINTER_0_CONSUMER_GROUP_0                     _MK_ENUM_CONST(0x0)
++#define CACC_S_POINTER_0_CONSUMER_GROUP_1                     _MK_ENUM_CONST(0x1)
++
++
++// Register CACC_D_OP_ENABLE_0
++#define CACC_D_OP_ENABLE_0                    _MK_ADDR_CONST(0x7008)
++#define CACC_D_OP_ENABLE_0_OP_EN_SHIFT                        _MK_SHIFT_CONST(0)
++#define CACC_D_OP_ENABLE_0_OP_EN_FIELD                        _MK_FIELD_CONST(0x1, CACC_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define CACC_D_OP_ENABLE_0_OP_EN_DISABLE                      _MK_ENUM_CONST(0x0)
++#define CACC_D_OP_ENABLE_0_OP_EN_ENABLE                       _MK_ENUM_CONST(0x1)
++
++
++// Register CACC_D_MISC_CFG_0
++#define CACC_D_MISC_CFG_0                     _MK_ADDR_CONST(0x700c)
++#define CACC_D_MISC_CFG_0_CONV_MODE_SHIFT                     _MK_SHIFT_CONST(0)
++#define CACC_D_MISC_CFG_0_CONV_MODE_FIELD                     _MK_FIELD_CONST(0x1, CACC_D_MISC_CFG_0_CONV_MODE_SHIFT)
++#define CACC_D_MISC_CFG_0_CONV_MODE_DIRECT                    _MK_ENUM_CONST(0x0)
++#define CACC_D_MISC_CFG_0_CONV_MODE_WINOGRAD                  _MK_ENUM_CONST(0x1)
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT                        _MK_SHIFT_CONST(12)
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_FIELD                        _MK_FIELD_CONST(0x3, CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT8                 _MK_ENUM_CONST(0x0)
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT16                        _MK_ENUM_CONST(0x1)
++#define CACC_D_MISC_CFG_0_PROC_PRECISION_FP16                 _MK_ENUM_CONST(0x2)
++
++
++// Register CACC_D_DATAOUT_SIZE_0_0
++#define CACC_D_DATAOUT_SIZE_0_0                       _MK_ADDR_CONST(0x7010)
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD                   _MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT)
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT                  _MK_SHIFT_CONST(16)
++#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD                  _MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT)
++
++
++// Register CACC_D_DATAOUT_SIZE_1_0
++#define CACC_D_DATAOUT_SIZE_1_0                       _MK_ADDR_CONST(0x7014)
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT                 _MK_SHIFT_CONST(0)
++#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD                 _MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT)
++
++
++// Register CACC_D_DATAOUT_ADDR_0
++#define CACC_D_DATAOUT_ADDR_0                 _MK_ADDR_CONST(0x7018)
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT                      _MK_SHIFT_CONST(0)
++#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_FIELD                      _MK_FIELD_CONST(0xffffffff, CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT)
++
++
++// Register CACC_D_BATCH_NUMBER_0
++#define CACC_D_BATCH_NUMBER_0                 _MK_ADDR_CONST(0x701c)
++#define CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT                   _MK_SHIFT_CONST(0)
++#define CACC_D_BATCH_NUMBER_0_BATCHES_FIELD                   _MK_FIELD_CONST(0x1f, CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT)
++
++
++// Register CACC_D_LINE_STRIDE_0
++#define CACC_D_LINE_STRIDE_0                  _MK_ADDR_CONST(0x7020)
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT                        _MK_SHIFT_CONST(0)
++#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_FIELD                        _MK_FIELD_CONST(0xffffff, CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT)
++
++
++// Register CACC_D_SURF_STRIDE_0
++#define CACC_D_SURF_STRIDE_0                  _MK_ADDR_CONST(0x7024)
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT                        _MK_SHIFT_CONST(0)
++#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_FIELD                        _MK_FIELD_CONST(0xffffff, CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT)
++
++
++// Register CACC_D_DATAOUT_MAP_0
++#define CACC_D_DATAOUT_MAP_0                  _MK_ADDR_CONST(0x7028)
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT                        _MK_SHIFT_CONST(0)
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FIELD                        _MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT)
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FALSE                        _MK_ENUM_CONST(0x0)
++#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE                 _MK_ENUM_CONST(0x1)
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT                        _MK_SHIFT_CONST(16)
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FIELD                        _MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT)
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FALSE                        _MK_ENUM_CONST(0x0)
++#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE                 _MK_ENUM_CONST(0x1)
++
++
++// Register CACC_D_CLIP_CFG_0
++#define CACC_D_CLIP_CFG_0                     _MK_ADDR_CONST(0x702c)
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT                 _MK_SHIFT_CONST(0)
++#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_FIELD                 _MK_FIELD_CONST(0x1f, CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT)
++
++
++// Register CACC_D_OUT_SATURATION_0
++#define CACC_D_OUT_SATURATION_0                       _MK_ADDR_CONST(0x7030)
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT                       _MK_SHIFT_CONST(0)
++#define CACC_D_OUT_SATURATION_0_SAT_COUNT_FIELD                       _MK_FIELD_CONST(0xffffffff, CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT)
++
++
++// Register CACC_D_CYA_0
++#define CACC_D_CYA_0                  _MK_ADDR_CONST(0x7034)
++#define CACC_D_CYA_0_CYA_SHIFT                        _MK_SHIFT_CONST(0)
++#define CACC_D_CYA_0_CYA_FIELD                        _MK_FIELD_CONST(0xffffffff, CACC_D_CYA_0_CYA_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register SDP_RDMA_S_STATUS_0
++#define SDP_RDMA_S_STATUS_0                   _MK_ADDR_CONST(0x8000)
++#define SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_S_STATUS_0_STATUS_0_FIELD                    _MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT)
++#define SDP_RDMA_S_STATUS_0_STATUS_0_IDLE                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                  _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_S_STATUS_0_STATUS_0_PENDING                  _MK_ENUM_CONST(0x2)
++#define SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                    _MK_SHIFT_CONST(16)
++#define SDP_RDMA_S_STATUS_0_STATUS_1_FIELD                    _MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT)
++#define SDP_RDMA_S_STATUS_0_STATUS_1_IDLE                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                  _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_S_STATUS_0_STATUS_1_PENDING                  _MK_ENUM_CONST(0x2)
++
++
++// Register SDP_RDMA_S_POINTER_0
++#define SDP_RDMA_S_POINTER_0                  _MK_ADDR_CONST(0x8004)
++#define SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                   _MK_SHIFT_CONST(0)
++#define SDP_RDMA_S_POINTER_0_PRODUCER_FIELD                   _MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT)
++#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                 _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                 _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                   _MK_SHIFT_CONST(16)
++#define SDP_RDMA_S_POINTER_0_CONSUMER_FIELD                   _MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT)
++#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                 _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                 _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_RDMA_D_OP_ENABLE_0
++#define SDP_RDMA_D_OP_ENABLE_0                        _MK_ADDR_CONST(0x8008)
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD                    _MK_FIELD_CONST(0x1, SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                  _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                   _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_RDMA_D_DATA_CUBE_WIDTH_0
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0                  _MK_ADDR_CONST(0x800c)
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD                      _MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT)
++
++
++// Register SDP_RDMA_D_DATA_CUBE_HEIGHT_0
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0                 _MK_ADDR_CONST(0x8010)
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD                    _MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT)
++
++
++// Register SDP_RDMA_D_DATA_CUBE_CHANNEL_0
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0                        _MK_ADDR_CONST(0x8014)
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD                  _MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT)
++
++
++// Register SDP_RDMA_D_SRC_BASE_ADDR_LOW_0
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0                        _MK_ADDR_CONST(0x8018)
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT)
++
++
++// Register SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                       _MK_ADDR_CONST(0x801c)
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register SDP_RDMA_D_SRC_LINE_STRIDE_0
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0                  _MK_ADDR_CONST(0x8020)
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD                    _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_SRC_SURFACE_STRIDE_0
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0                       _MK_ADDR_CONST(0x8024)
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_BRDMA_CFG_0
++#define SDP_RDMA_D_BRDMA_CFG_0                        _MK_ADDR_CONST(0x8028)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_NO                       _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_YES                      _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT                   _MK_SHIFT_CONST(1)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_FIELD                   _MK_FIELD_CONST(0x3, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_MUL                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_ALU                     _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_BOTH                    _MK_ENUM_CONST(0x2)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT                  _MK_SHIFT_CONST(3)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_FIELD                  _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_ONE_BYTE                       _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_TWO_BYTE                       _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT                  _MK_SHIFT_CONST(4)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_FIELD                  _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_KERNEL                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_ELEMENT                    _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT                   _MK_SHIFT_CONST(5)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_FIELD                   _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_CV                      _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_MC                      _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_RDMA_D_BS_BASE_ADDR_LOW_0
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0                 _MK_ADDR_CONST(0x802c)
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_FIELD                  _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT)
++
++
++// Register SDP_RDMA_D_BS_BASE_ADDR_HIGH_0
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0                        _MK_ADDR_CONST(0x8030)
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register SDP_RDMA_D_BS_LINE_STRIDE_0
++#define SDP_RDMA_D_BS_LINE_STRIDE_0                   _MK_ADDR_CONST(0x8034)
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_BS_SURFACE_STRIDE_0
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0                        _MK_ADDR_CONST(0x8038)
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_BS_BATCH_STRIDE_0
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0                  _MK_ADDR_CONST(0x803c)
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_FIELD                    _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_NRDMA_CFG_0
++#define SDP_RDMA_D_NRDMA_CFG_0                        _MK_ADDR_CONST(0x8040)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_NO                       _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_YES                      _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT                   _MK_SHIFT_CONST(1)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_FIELD                   _MK_FIELD_CONST(0x3, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_MUL                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_ALU                     _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_BOTH                    _MK_ENUM_CONST(0x2)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT                  _MK_SHIFT_CONST(3)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_FIELD                  _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_ONE_BYTE                       _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_TWO_BYTE                       _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT                  _MK_SHIFT_CONST(4)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_FIELD                  _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_KERNEL                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_ELEMENT                    _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT                   _MK_SHIFT_CONST(5)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_FIELD                   _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_CV                      _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_MC                      _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_RDMA_D_BN_BASE_ADDR_LOW_0
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0                 _MK_ADDR_CONST(0x8044)
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_FIELD                  _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT)
++
++
++// Register SDP_RDMA_D_BN_BASE_ADDR_HIGH_0
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0                        _MK_ADDR_CONST(0x8048)
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register SDP_RDMA_D_BN_LINE_STRIDE_0
++#define SDP_RDMA_D_BN_LINE_STRIDE_0                   _MK_ADDR_CONST(0x804c)
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_BN_SURFACE_STRIDE_0
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0                        _MK_ADDR_CONST(0x8050)
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_BN_BATCH_STRIDE_0
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0                  _MK_ADDR_CONST(0x8054)
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_FIELD                    _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_ERDMA_CFG_0
++#define SDP_RDMA_D_ERDMA_CFG_0                        _MK_ADDR_CONST(0x8058)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_NO                       _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_YES                      _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT                   _MK_SHIFT_CONST(1)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_FIELD                   _MK_FIELD_CONST(0x3, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_MUL                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_ALU                     _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_BOTH                    _MK_ENUM_CONST(0x2)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT                  _MK_SHIFT_CONST(3)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_FIELD                  _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_ONE_BYTE                       _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_TWO_BYTE                       _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT                  _MK_SHIFT_CONST(4)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_FIELD                  _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_KERNEL                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_ELEMENT                    _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT                   _MK_SHIFT_CONST(5)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_FIELD                   _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_CV                      _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_MC                      _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_RDMA_D_EW_BASE_ADDR_LOW_0
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0                 _MK_ADDR_CONST(0x805c)
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_FIELD                  _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT)
++
++
++// Register SDP_RDMA_D_EW_BASE_ADDR_HIGH_0
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0                        _MK_ADDR_CONST(0x8060)
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register SDP_RDMA_D_EW_LINE_STRIDE_0
++#define SDP_RDMA_D_EW_LINE_STRIDE_0                   _MK_ADDR_CONST(0x8064)
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_EW_SURFACE_STRIDE_0
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0                        _MK_ADDR_CONST(0x8068)
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_EW_BATCH_STRIDE_0
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0                  _MK_ADDR_CONST(0x806c)
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_FIELD                    _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT)
++
++
++// Register SDP_RDMA_D_FEATURE_MODE_CFG_0
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0                 _MK_ADDR_CONST(0x8070)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT                       _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD                       _MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF                 _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON                  _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT                  _MK_SHIFT_CONST(1)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD                  _MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF                    _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_ON                     _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT                      _MK_SHIFT_CONST(2)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FIELD                      _MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT8                       _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT16                      _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FP16                       _MK_ENUM_CONST(0x2)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT                    _MK_SHIFT_CONST(4)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FIELD                    _MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT8                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT16                    _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FP16                     _MK_ENUM_CONST(0x2)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT                     _MK_SHIFT_CONST(6)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FIELD                     _MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT8                      _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT16                     _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FP16                      _MK_ENUM_CONST(0x2)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT                      _MK_SHIFT_CONST(8)
++#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD                      _MK_FIELD_CONST(0x1f, SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT)
++
++
++// Register SDP_RDMA_D_SRC_DMA_CFG_0
++#define SDP_RDMA_D_SRC_DMA_CFG_0                      _MK_ADDR_CONST(0x8074)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT                   _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD                   _MK_FIELD_CONST(0x1, SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV                      _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC                      _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0                     _MK_ADDR_CONST(0x8078)
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD                  _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT)
++
++
++// Register SDP_RDMA_D_STATUS_INF_INPUT_NUM_0
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0                     _MK_ADDR_CONST(0x807c)
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD                  _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT)
++
++
++// Register SDP_RDMA_D_PERF_ENABLE_0
++#define SDP_RDMA_D_PERF_ENABLE_0                      _MK_ADDR_CONST(0x8080)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD                    _MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_NO                       _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_YES                      _MK_ENUM_CONST(0x1)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT                  _MK_SHIFT_CONST(1)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD                  _MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO                     _MK_ENUM_CONST(0x0)
++#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES                    _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_RDMA_D_PERF_MRDMA_READ_STALL_0
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0                    _MK_ADDR_CONST(0x8084)
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_FIELD                  _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT)
++
++
++// Register SDP_RDMA_D_PERF_BRDMA_READ_STALL_0
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0                    _MK_ADDR_CONST(0x8088)
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_FIELD                  _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT)
++
++
++// Register SDP_RDMA_D_PERF_NRDMA_READ_STALL_0
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0                    _MK_ADDR_CONST(0x808c)
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_FIELD                  _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT)
++
++
++// Register SDP_RDMA_D_PERF_ERDMA_READ_STALL_0
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0                    _MK_ADDR_CONST(0x8090)
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT                  _MK_SHIFT_CONST(0)
++#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_FIELD                  _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register SDP_S_STATUS_0
++#define SDP_S_STATUS_0                        _MK_ADDR_CONST(0x9000)
++#define SDP_S_STATUS_0_STATUS_0_SHIFT                 _MK_SHIFT_CONST(0)
++#define SDP_S_STATUS_0_STATUS_0_FIELD                 _MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_0_SHIFT)
++#define SDP_S_STATUS_0_STATUS_0_IDLE                  _MK_ENUM_CONST(0x0)
++#define SDP_S_STATUS_0_STATUS_0_RUNNING                       _MK_ENUM_CONST(0x1)
++#define SDP_S_STATUS_0_STATUS_0_PENDING                       _MK_ENUM_CONST(0x2)
++#define SDP_S_STATUS_0_STATUS_1_SHIFT                 _MK_SHIFT_CONST(16)
++#define SDP_S_STATUS_0_STATUS_1_FIELD                 _MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_1_SHIFT)
++#define SDP_S_STATUS_0_STATUS_1_IDLE                  _MK_ENUM_CONST(0x0)
++#define SDP_S_STATUS_0_STATUS_1_RUNNING                       _MK_ENUM_CONST(0x1)
++#define SDP_S_STATUS_0_STATUS_1_PENDING                       _MK_ENUM_CONST(0x2)
++
++
++// Register SDP_S_POINTER_0
++#define SDP_S_POINTER_0                       _MK_ADDR_CONST(0x9004)
++#define SDP_S_POINTER_0_PRODUCER_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_S_POINTER_0_PRODUCER_FIELD                        _MK_FIELD_CONST(0x1, SDP_S_POINTER_0_PRODUCER_SHIFT)
++#define SDP_S_POINTER_0_PRODUCER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define SDP_S_POINTER_0_PRODUCER_GROUP_1                      _MK_ENUM_CONST(0x1)
++#define SDP_S_POINTER_0_CONSUMER_SHIFT                        _MK_SHIFT_CONST(16)
++#define SDP_S_POINTER_0_CONSUMER_FIELD                        _MK_FIELD_CONST(0x1, SDP_S_POINTER_0_CONSUMER_SHIFT)
++#define SDP_S_POINTER_0_CONSUMER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define SDP_S_POINTER_0_CONSUMER_GROUP_1                      _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_S_LUT_ACCESS_CFG_0
++#define SDP_S_LUT_ACCESS_CFG_0                        _MK_ADDR_CONST(0x9008)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT                 _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD                 _MK_FIELD_CONST(0x3ff, SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT                     _MK_SHIFT_CONST(16)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD                     _MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE                        _MK_ENUM_CONST(0x0)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO                        _MK_ENUM_CONST(0x1)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT                  _MK_SHIFT_CONST(17)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD                  _MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ                   _MK_ENUM_CONST(0x0)
++#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE                  _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_S_LUT_ACCESS_DATA_0
++#define SDP_S_LUT_ACCESS_DATA_0                       _MK_ADDR_CONST(0x900c)
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD                        _MK_FIELD_CONST(0xffff, SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT)
++
++
++// Register SDP_S_LUT_CFG_0
++#define SDP_S_LUT_CFG_0                       _MK_ADDR_CONST(0x9010)
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT                 _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD                 _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT)
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT                      _MK_ENUM_CONST(0x0)
++#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR                        _MK_ENUM_CONST(0x1)
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT                      _MK_SHIFT_CONST(4)
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD                      _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT)
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE                 _MK_ENUM_CONST(0x0)
++#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO                 _MK_ENUM_CONST(0x1)
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT                      _MK_SHIFT_CONST(5)
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD                      _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT)
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE                 _MK_ENUM_CONST(0x0)
++#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO                 _MK_ENUM_CONST(0x1)
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT                     _MK_SHIFT_CONST(6)
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD                     _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT)
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE                        _MK_ENUM_CONST(0x0)
++#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO                        _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_S_LUT_INFO_0
++#define SDP_S_LUT_INFO_0                      _MK_ADDR_CONST(0x9014)
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD                    _MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT)
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT                    _MK_SHIFT_CONST(8)
++#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD                    _MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT)
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT                    _MK_SHIFT_CONST(16)
++#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD                    _MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT)
++
++
++// Register SDP_S_LUT_LE_START_0
++#define SDP_S_LUT_LE_START_0                  _MK_ADDR_CONST(0x9018)
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT                       _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_LE_START_0_LUT_LE_START_FIELD                       _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT)
++
++
++// Register SDP_S_LUT_LE_END_0
++#define SDP_S_LUT_LE_END_0                    _MK_ADDR_CONST(0x901c)
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT                   _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_LE_END_0_LUT_LE_END_FIELD                   _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT)
++
++
++// Register SDP_S_LUT_LO_START_0
++#define SDP_S_LUT_LO_START_0                  _MK_ADDR_CONST(0x9020)
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT                       _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_LO_START_0_LUT_LO_START_FIELD                       _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT)
++
++
++// Register SDP_S_LUT_LO_END_0
++#define SDP_S_LUT_LO_END_0                    _MK_ADDR_CONST(0x9024)
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT                   _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_LO_END_0_LUT_LO_END_FIELD                   _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT)
++
++
++// Register SDP_S_LUT_LE_SLOPE_SCALE_0
++#define SDP_S_LUT_LE_SLOPE_SCALE_0                    _MK_ADDR_CONST(0x9028)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD                     _MK_FIELD_CONST(0xffff, SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT                     _MK_SHIFT_CONST(16)
++#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD                     _MK_FIELD_CONST(0xffff, SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT)
++
++
++// Register SDP_S_LUT_LE_SLOPE_SHIFT_0
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0                    _MK_ADDR_CONST(0x902c)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD                     _MK_FIELD_CONST(0x1f, SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT                     _MK_SHIFT_CONST(5)
++#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD                     _MK_FIELD_CONST(0x1f, SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT)
++
++
++// Register SDP_S_LUT_LO_SLOPE_SCALE_0
++#define SDP_S_LUT_LO_SLOPE_SCALE_0                    _MK_ADDR_CONST(0x9030)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD                     _MK_FIELD_CONST(0xffff, SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT                     _MK_SHIFT_CONST(16)
++#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD                     _MK_FIELD_CONST(0xffff, SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT)
++
++
++// Register SDP_S_LUT_LO_SLOPE_SHIFT_0
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0                    _MK_ADDR_CONST(0x9034)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD                     _MK_FIELD_CONST(0x1f, SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT                     _MK_SHIFT_CONST(5)
++#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD                     _MK_FIELD_CONST(0x1f, SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT)
++
++
++// Register SDP_D_OP_ENABLE_0
++#define SDP_D_OP_ENABLE_0                     _MK_ADDR_CONST(0x9038)
++#define SDP_D_OP_ENABLE_0_OP_EN_SHIFT                 _MK_SHIFT_CONST(0)
++#define SDP_D_OP_ENABLE_0_OP_EN_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define SDP_D_OP_ENABLE_0_OP_EN_DISABLE                       _MK_ENUM_CONST(0x0)
++#define SDP_D_OP_ENABLE_0_OP_EN_ENABLE                        _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_D_DATA_CUBE_WIDTH_0
++#define SDP_D_DATA_CUBE_WIDTH_0                       _MK_ADDR_CONST(0x903c)
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
++#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD                   _MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT)
++
++
++// Register SDP_D_DATA_CUBE_HEIGHT_0
++#define SDP_D_DATA_CUBE_HEIGHT_0                      _MK_ADDR_CONST(0x9040)
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT                 _MK_SHIFT_CONST(0)
++#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD                 _MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT)
++
++
++// Register SDP_D_DATA_CUBE_CHANNEL_0
++#define SDP_D_DATA_CUBE_CHANNEL_0                     _MK_ADDR_CONST(0x9044)
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT                       _MK_SHIFT_CONST(0)
++#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD                       _MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT)
++
++
++// Register SDP_D_DST_BASE_ADDR_LOW_0
++#define SDP_D_DST_BASE_ADDR_LOW_0                     _MK_ADDR_CONST(0x9048)
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT)
++
++
++// Register SDP_D_DST_BASE_ADDR_HIGH_0
++#define SDP_D_DST_BASE_ADDR_HIGH_0                    _MK_ADDR_CONST(0x904c)
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT                   _MK_SHIFT_CONST(0)
++#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD                   _MK_FIELD_CONST(0xffffffff, SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register SDP_D_DST_LINE_STRIDE_0
++#define SDP_D_DST_LINE_STRIDE_0                       _MK_ADDR_CONST(0x9050)
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT                 _MK_SHIFT_CONST(0)
++#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD                 _MK_FIELD_CONST(0xffffffff, SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT)
++
++
++// Register SDP_D_DST_SURFACE_STRIDE_0
++#define SDP_D_DST_SURFACE_STRIDE_0                    _MK_ADDR_CONST(0x9054)
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT                   _MK_SHIFT_CONST(0)
++#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD                   _MK_FIELD_CONST(0xffffffff, SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT)
++
++
++// Register SDP_D_DP_BS_CFG_0
++#define SDP_D_DP_BS_CFG_0                     _MK_ADDR_CONST(0x9058)
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_FIELD                     _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT)
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_NO                        _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BS_CFG_0_BS_BYPASS_YES                       _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT                 _MK_SHIFT_CONST(1)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_YES                   _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT                   _MK_SHIFT_CONST(2)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_FIELD                   _MK_FIELD_CONST(0x3, SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MAX                     _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MIN                     _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SUM                     _MK_ENUM_CONST(0x2)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT                 _MK_SHIFT_CONST(4)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_YES                   _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT                  _MK_SHIFT_CONST(5)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_FIELD                  _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_NO                     _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_YES                    _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT                        _MK_SHIFT_CONST(6)
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT)
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_NO                   _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_YES                  _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_D_DP_BS_ALU_CFG_0
++#define SDP_D_DP_BS_ALU_CFG_0                 _MK_ADDR_CONST(0x905c)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_FIELD                        _MK_FIELD_CONST(0x1, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_REG                  _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_MEM                  _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT                        _MK_SHIFT_CONST(8)
++#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_FIELD                        _MK_FIELD_CONST(0x3f, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT)
++
++
++// Register SDP_D_DP_BS_ALU_SRC_VALUE_0
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0                   _MK_ADDR_CONST(0x9060)
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_FIELD                      _MK_FIELD_CONST(0xffff, SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT)
++
++
++// Register SDP_D_DP_BS_MUL_CFG_0
++#define SDP_D_DP_BS_MUL_CFG_0                 _MK_ADDR_CONST(0x9064)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_FIELD                        _MK_FIELD_CONST(0x1, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_REG                  _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_MEM                  _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT                        _MK_SHIFT_CONST(8)
++#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_FIELD                        _MK_FIELD_CONST(0xff, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT)
++
++
++// Register SDP_D_DP_BS_MUL_SRC_VALUE_0
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0                   _MK_ADDR_CONST(0x9068)
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_FIELD                      _MK_FIELD_CONST(0xffff, SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT)
++
++
++// Register SDP_D_DP_BN_CFG_0
++#define SDP_D_DP_BN_CFG_0                     _MK_ADDR_CONST(0x906c)
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_FIELD                     _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT)
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_NO                        _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BN_CFG_0_BN_BYPASS_YES                       _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT                 _MK_SHIFT_CONST(1)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_YES                   _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT                   _MK_SHIFT_CONST(2)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_FIELD                   _MK_FIELD_CONST(0x3, SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MAX                     _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MIN                     _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SUM                     _MK_ENUM_CONST(0x2)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT                 _MK_SHIFT_CONST(4)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_YES                   _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT                  _MK_SHIFT_CONST(5)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_FIELD                  _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_NO                     _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_YES                    _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT                        _MK_SHIFT_CONST(6)
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT)
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_NO                   _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_YES                  _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_D_DP_BN_ALU_CFG_0
++#define SDP_D_DP_BN_ALU_CFG_0                 _MK_ADDR_CONST(0x9070)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_FIELD                        _MK_FIELD_CONST(0x1, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_REG                  _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_MEM                  _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT                        _MK_SHIFT_CONST(8)
++#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_FIELD                        _MK_FIELD_CONST(0x3f, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT)
++
++
++// Register SDP_D_DP_BN_ALU_SRC_VALUE_0
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0                   _MK_ADDR_CONST(0x9074)
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_FIELD                      _MK_FIELD_CONST(0xffff, SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT)
++
++
++// Register SDP_D_DP_BN_MUL_CFG_0
++#define SDP_D_DP_BN_MUL_CFG_0                 _MK_ADDR_CONST(0x9078)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_FIELD                        _MK_FIELD_CONST(0x1, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_REG                  _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_MEM                  _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT                        _MK_SHIFT_CONST(8)
++#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_FIELD                        _MK_FIELD_CONST(0xff, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT)
++
++
++// Register SDP_D_DP_BN_MUL_SRC_VALUE_0
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0                   _MK_ADDR_CONST(0x907c)
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_FIELD                      _MK_FIELD_CONST(0xffff, SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT)
++
++
++// Register SDP_D_DP_EW_CFG_0
++#define SDP_D_DP_EW_CFG_0                     _MK_ADDR_CONST(0x9080)
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_FIELD                     _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT)
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_NO                        _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_CFG_0_EW_BYPASS_YES                       _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT                 _MK_SHIFT_CONST(1)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_YES                   _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT                   _MK_SHIFT_CONST(2)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_FIELD                   _MK_FIELD_CONST(0x3, SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MAX                     _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MIN                     _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SUM                     _MK_ENUM_CONST(0x2)
++#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_EQL                     _MK_ENUM_CONST(0x3)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT                 _MK_SHIFT_CONST(4)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_YES                   _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT                  _MK_SHIFT_CONST(5)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_FIELD                  _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_NO                     _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_YES                    _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT                 _MK_SHIFT_CONST(6)
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT)
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_YES                   _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_D_DP_EW_ALU_CFG_0
++#define SDP_D_DP_EW_ALU_CFG_0                 _MK_ADDR_CONST(0x9084)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_FIELD                        _MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_REG                  _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_MEM                  _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT                 _MK_SHIFT_CONST(1)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_YES                   _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_D_DP_EW_ALU_SRC_VALUE_0
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0                   _MK_ADDR_CONST(0x9088)
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT)
++
++
++// Register SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0                    _MK_ADDR_CONST(0x908c)
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_FIELD                    _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT)
++
++
++// Register SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0                     _MK_ADDR_CONST(0x9090)
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_FIELD                      _MK_FIELD_CONST(0xffff, SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT)
++
++
++// Register SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0                  _MK_ADDR_CONST(0x9094)
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_FIELD                        _MK_FIELD_CONST(0x3f, SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT)
++
++
++// Register SDP_D_DP_EW_MUL_CFG_0
++#define SDP_D_DP_EW_MUL_CFG_0                 _MK_ADDR_CONST(0x9098)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_FIELD                        _MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_REG                  _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_MEM                  _MK_ENUM_CONST(0x1)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT                 _MK_SHIFT_CONST(1)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_YES                   _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_D_DP_EW_MUL_SRC_VALUE_0
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0                   _MK_ADDR_CONST(0x909c)
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT)
++
++
++// Register SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0                    _MK_ADDR_CONST(0x90a0)
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_FIELD                    _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT)
++
++
++// Register SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0                     _MK_ADDR_CONST(0x90a4)
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_FIELD                      _MK_FIELD_CONST(0xffff, SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT)
++
++
++// Register SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0                  _MK_ADDR_CONST(0x90a8)
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_FIELD                        _MK_FIELD_CONST(0x3f, SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT)
++
++
++// Register SDP_D_DP_EW_TRUNCATE_VALUE_0
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0                  _MK_ADDR_CONST(0x90ac)
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_FIELD                        _MK_FIELD_CONST(0x3ff, SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT)
++
++
++// Register SDP_D_FEATURE_MODE_CFG_0
++#define SDP_D_FEATURE_MODE_CFG_0                      _MK_ADDR_CONST(0x90b0)
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT                    _MK_SHIFT_CONST(0)
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD                    _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT)
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF                      _MK_ENUM_CONST(0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON                       _MK_ENUM_CONST(0x1)
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT                     _MK_SHIFT_CONST(1)
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_FIELD                     _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT)
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_MEM                       _MK_ENUM_CONST(0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PDP                       _MK_ENUM_CONST(0x1)
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT                       _MK_SHIFT_CONST(2)
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD                       _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT)
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF                 _MK_ENUM_CONST(0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_ON                  _MK_ENUM_CONST(0x1)
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT                    _MK_SHIFT_CONST(3)
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_FIELD                    _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT)
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DISABLE                  _MK_ENUM_CONST(0x0)
++#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_ENABLE                   _MK_ENUM_CONST(0x1)
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT                   _MK_SHIFT_CONST(8)
++#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD                   _MK_FIELD_CONST(0x1f, SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT)
++
++
++// Register SDP_D_DST_DMA_CFG_0
++#define SDP_D_DST_DMA_CFG_0                   _MK_ADDR_CONST(0x90b4)
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD                        _MK_FIELD_CONST(0x1, SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT)
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV                   _MK_ENUM_CONST(0x0)
++#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC                   _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_D_DST_BATCH_STRIDE_0
++#define SDP_D_DST_BATCH_STRIDE_0                      _MK_ADDR_CONST(0x90b8)
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT                       _MK_SHIFT_CONST(0)
++#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_FIELD                       _MK_FIELD_CONST(0xffffffff, SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT)
++
++
++// Register SDP_D_DATA_FORMAT_0
++#define SDP_D_DATA_FORMAT_0                   _MK_ADDR_CONST(0x90bc)
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FIELD                      _MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT)
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT8                       _MK_ENUM_CONST(0x0)
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT16                      _MK_ENUM_CONST(0x1)
++#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FP16                       _MK_ENUM_CONST(0x2)
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT                       _MK_SHIFT_CONST(2)
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FIELD                       _MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT)
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT8                        _MK_ENUM_CONST(0x0)
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT16                       _MK_ENUM_CONST(0x1)
++#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FP16                        _MK_ENUM_CONST(0x2)
++
++
++// Register SDP_D_CVT_OFFSET_0
++#define SDP_D_CVT_OFFSET_0                    _MK_ADDR_CONST(0x90c0)
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
++#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_FIELD                   _MK_FIELD_CONST(0xffffffff, SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT)
++
++
++// Register SDP_D_CVT_SCALE_0
++#define SDP_D_CVT_SCALE_0                     _MK_ADDR_CONST(0x90c4)
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_D_CVT_SCALE_0_CVT_SCALE_FIELD                     _MK_FIELD_CONST(0xffff, SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT)
++
++
++// Register SDP_D_CVT_SHIFT_0
++#define SDP_D_CVT_SHIFT_0                     _MK_ADDR_CONST(0x90c8)
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_FIELD                     _MK_FIELD_CONST(0x3f, SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT)
++
++
++// Register SDP_D_STATUS_0
++#define SDP_D_STATUS_0                        _MK_ADDR_CONST(0x90cc)
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT                   _MK_SHIFT_CONST(0)
++#define SDP_D_STATUS_0_STATUS_UNEQUAL_FIELD                   _MK_FIELD_CONST(0x1, SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT)
++
++
++// Register SDP_D_STATUS_NAN_INPUT_NUM_0
++#define SDP_D_STATUS_NAN_INPUT_NUM_0                  _MK_ADDR_CONST(0x90d0)
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT                       _MK_SHIFT_CONST(0)
++#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD                       _MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT)
++
++
++// Register SDP_D_STATUS_INF_INPUT_NUM_0
++#define SDP_D_STATUS_INF_INPUT_NUM_0                  _MK_ADDR_CONST(0x90d4)
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT                       _MK_SHIFT_CONST(0)
++#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD                       _MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT)
++
++
++// Register SDP_D_STATUS_NAN_OUTPUT_NUM_0
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0                 _MK_ADDR_CONST(0x90d8)
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT                     _MK_SHIFT_CONST(0)
++#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_FIELD                     _MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT)
++
++
++// Register SDP_D_PERF_ENABLE_0
++#define SDP_D_PERF_ENABLE_0                   _MK_ADDR_CONST(0x90dc)
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT                 _MK_SHIFT_CONST(0)
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT)
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_YES                   _MK_ENUM_CONST(0x1)
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT                 _MK_SHIFT_CONST(1)
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT)
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_YES                   _MK_ENUM_CONST(0x1)
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT                 _MK_SHIFT_CONST(2)
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_FIELD                 _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT)
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_NO                    _MK_ENUM_CONST(0x0)
++#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_YES                   _MK_ENUM_CONST(0x1)
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT                       _MK_SHIFT_CONST(3)
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD                       _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT)
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO                  _MK_ENUM_CONST(0x0)
++#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES                 _MK_ENUM_CONST(0x1)
++
++
++// Register SDP_D_PERF_WDMA_WRITE_STALL_0
++#define SDP_D_PERF_WDMA_WRITE_STALL_0                 _MK_ADDR_CONST(0x90e0)
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT)
++
++
++// Register SDP_D_PERF_LUT_UFLOW_0
++#define SDP_D_PERF_LUT_UFLOW_0                        _MK_ADDR_CONST(0x90e4)
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT)
++
++
++// Register SDP_D_PERF_LUT_OFLOW_0
++#define SDP_D_PERF_LUT_OFLOW_0                        _MK_ADDR_CONST(0x90e8)
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT                        _MK_SHIFT_CONST(0)
++#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_FIELD                        _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT)
++
++
++// Register SDP_D_PERF_OUT_SATURATION_0
++#define SDP_D_PERF_OUT_SATURATION_0                   _MK_ADDR_CONST(0x90ec)
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT)
++
++
++// Register SDP_D_PERF_LUT_HYBRID_0
++#define SDP_D_PERF_LUT_HYBRID_0                       _MK_ADDR_CONST(0x90f0)
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT)
++
++
++// Register SDP_D_PERF_LUT_LE_HIT_0
++#define SDP_D_PERF_LUT_LE_HIT_0                       _MK_ADDR_CONST(0x90f4)
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT)
++
++
++// Register SDP_D_PERF_LUT_LO_HIT_0
++#define SDP_D_PERF_LUT_LO_HIT_0                       _MK_ADDR_CONST(0x90f8)
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT                      _MK_SHIFT_CONST(0)
++#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_FIELD                      _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register PDP_RDMA_S_STATUS_0
++#define PDP_RDMA_S_STATUS_0                   _MK_ADDR_CONST(0xa000)
++#define PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_RDMA_S_STATUS_0_STATUS_0_FIELD                    _MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT)
++#define PDP_RDMA_S_STATUS_0_STATUS_0_IDLE                     _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                  _MK_ENUM_CONST(0x1)
++#define PDP_RDMA_S_STATUS_0_STATUS_0_PENDING                  _MK_ENUM_CONST(0x2)
++#define PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                    _MK_SHIFT_CONST(16)
++#define PDP_RDMA_S_STATUS_0_STATUS_1_FIELD                    _MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT)
++#define PDP_RDMA_S_STATUS_0_STATUS_1_IDLE                     _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                  _MK_ENUM_CONST(0x1)
++#define PDP_RDMA_S_STATUS_0_STATUS_1_PENDING                  _MK_ENUM_CONST(0x2)
++
++
++// Register PDP_RDMA_S_POINTER_0
++#define PDP_RDMA_S_POINTER_0                  _MK_ADDR_CONST(0xa004)
++#define PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_RDMA_S_POINTER_0_PRODUCER_FIELD                   _MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT)
++#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                 _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                 _MK_ENUM_CONST(0x1)
++#define PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                   _MK_SHIFT_CONST(16)
++#define PDP_RDMA_S_POINTER_0_CONSUMER_FIELD                   _MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT)
++#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                 _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                 _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_RDMA_D_OP_ENABLE_0
++#define PDP_RDMA_D_OP_ENABLE_0                        _MK_ADDR_CONST(0xa008)
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD                    _MK_FIELD_CONST(0x1, PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                  _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                   _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0                       _MK_ADDR_CONST(0xa00c)
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD                   _MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT)
++
++
++// Register PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0                      _MK_ADDR_CONST(0xa010)
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD                 _MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT)
++
++
++// Register PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0                     _MK_ADDR_CONST(0xa014)
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT                       _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD                       _MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT)
++
++
++// Register PDP_RDMA_D_FLYING_MODE_0
++#define PDP_RDMA_D_FLYING_MODE_0                      _MK_ADDR_CONST(0xa018)
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_FIELD                    _MK_FIELD_CONST(0x1, PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT)
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_ON_FLYING                        _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_OFF_FLYING                       _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_RDMA_D_SRC_BASE_ADDR_LOW_0
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0                        _MK_ADDR_CONST(0xa01c)
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD                        _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT)
++
++
++// Register PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                       _MK_ADDR_CONST(0xa020)
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT                      _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD                      _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register PDP_RDMA_D_SRC_LINE_STRIDE_0
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0                  _MK_ADDR_CONST(0xa024)
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD                    _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT)
++
++
++// Register PDP_RDMA_D_SRC_SURFACE_STRIDE_0
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0                       _MK_ADDR_CONST(0xa028)
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD                      _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT)
++
++
++// Register PDP_RDMA_D_SRC_RAM_CFG_0
++#define PDP_RDMA_D_SRC_RAM_CFG_0                      _MK_ADDR_CONST(0xa02c)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_FIELD                   _MK_FIELD_CONST(0x1, PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_CV                      _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_MC                      _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_RDMA_D_DATA_FORMAT_0
++#define PDP_RDMA_D_DATA_FORMAT_0                      _MK_ADDR_CONST(0xa030)
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT                     _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD                     _MK_FIELD_CONST(0x3, PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT)
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8                      _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16                     _MK_ENUM_CONST(0x1)
++#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16                      _MK_ENUM_CONST(0x2)
++
++
++// Register PDP_RDMA_D_OPERATION_MODE_CFG_0
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0                       _MK_ADDR_CONST(0xa034)
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT                       _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD                       _MK_FIELD_CONST(0xff, PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT)
++
++
++// Register PDP_RDMA_D_POOLING_KERNEL_CFG_0
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0                       _MK_ADDR_CONST(0xa038)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD                    _MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1                   _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2                   _MK_ENUM_CONST(0x1)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3                   _MK_ENUM_CONST(0x2)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4                   _MK_ENUM_CONST(0x3)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5                   _MK_ENUM_CONST(0x4)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6                   _MK_ENUM_CONST(0x5)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7                   _MK_ENUM_CONST(0x6)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8                   _MK_ENUM_CONST(0x7)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT                     _MK_SHIFT_CONST(4)
++#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD                     _MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT)
++
++
++// Register PDP_RDMA_D_POOLING_PADDING_CFG_0
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0                      _MK_ADDR_CONST(0xa03c)
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT                      _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_FIELD                      _MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT)
++
++
++// Register PDP_RDMA_D_PARTIAL_WIDTH_IN_0
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0                 _MK_ADDR_CONST(0xa040)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD                    _MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT                     _MK_SHIFT_CONST(10)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD                     _MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT                      _MK_SHIFT_CONST(20)
++#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD                      _MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT)
++
++
++// Register PDP_RDMA_D_PERF_ENABLE_0
++#define PDP_RDMA_D_PERF_ENABLE_0                      _MK_ADDR_CONST(0xa044)
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD                 _MK_FIELD_CONST(0x1, PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT)
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE                       _MK_ENUM_CONST(0x0)
++#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE                        _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_RDMA_D_PERF_READ_STALL_0
++#define PDP_RDMA_D_PERF_READ_STALL_0                  _MK_ADDR_CONST(0xa048)
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD                    _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT)
++
++
++// Register PDP_RDMA_D_CYA_0
++#define PDP_RDMA_D_CYA_0                      _MK_ADDR_CONST(0xa04c)
++#define PDP_RDMA_D_CYA_0_CYA_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_RDMA_D_CYA_0_CYA_FIELD                    _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_CYA_0_CYA_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register PDP_S_STATUS_0
++#define PDP_S_STATUS_0                        _MK_ADDR_CONST(0xb000)
++#define PDP_S_STATUS_0_STATUS_0_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_S_STATUS_0_STATUS_0_FIELD                 _MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_0_SHIFT)
++#define PDP_S_STATUS_0_STATUS_0_IDLE                  _MK_ENUM_CONST(0x0)
++#define PDP_S_STATUS_0_STATUS_0_RUNNING                       _MK_ENUM_CONST(0x1)
++#define PDP_S_STATUS_0_STATUS_0_PENDING                       _MK_ENUM_CONST(0x2)
++#define PDP_S_STATUS_0_STATUS_1_SHIFT                 _MK_SHIFT_CONST(16)
++#define PDP_S_STATUS_0_STATUS_1_FIELD                 _MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_1_SHIFT)
++#define PDP_S_STATUS_0_STATUS_1_IDLE                  _MK_ENUM_CONST(0x0)
++#define PDP_S_STATUS_0_STATUS_1_RUNNING                       _MK_ENUM_CONST(0x1)
++#define PDP_S_STATUS_0_STATUS_1_PENDING                       _MK_ENUM_CONST(0x2)
++
++
++// Register PDP_S_POINTER_0
++#define PDP_S_POINTER_0                       _MK_ADDR_CONST(0xb004)
++#define PDP_S_POINTER_0_PRODUCER_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_S_POINTER_0_PRODUCER_FIELD                        _MK_FIELD_CONST(0x1, PDP_S_POINTER_0_PRODUCER_SHIFT)
++#define PDP_S_POINTER_0_PRODUCER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define PDP_S_POINTER_0_PRODUCER_GROUP_1                      _MK_ENUM_CONST(0x1)
++#define PDP_S_POINTER_0_CONSUMER_SHIFT                        _MK_SHIFT_CONST(16)
++#define PDP_S_POINTER_0_CONSUMER_FIELD                        _MK_FIELD_CONST(0x1, PDP_S_POINTER_0_CONSUMER_SHIFT)
++#define PDP_S_POINTER_0_CONSUMER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define PDP_S_POINTER_0_CONSUMER_GROUP_1                      _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_D_OP_ENABLE_0
++#define PDP_D_OP_ENABLE_0                     _MK_ADDR_CONST(0xb008)
++#define PDP_D_OP_ENABLE_0_OP_EN_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_D_OP_ENABLE_0_OP_EN_FIELD                 _MK_FIELD_CONST(0x1, PDP_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define PDP_D_OP_ENABLE_0_OP_EN_DISABLE                       _MK_ENUM_CONST(0x0)
++#define PDP_D_OP_ENABLE_0_OP_EN_ENABLE                        _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_D_DATA_CUBE_IN_WIDTH_0
++#define PDP_D_DATA_CUBE_IN_WIDTH_0                    _MK_ADDR_CONST(0xb00c)
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD                        _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT)
++
++
++// Register PDP_D_DATA_CUBE_IN_HEIGHT_0
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0                   _MK_ADDR_CONST(0xb010)
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT                      _MK_SHIFT_CONST(0)
++#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD                      _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT)
++
++
++// Register PDP_D_DATA_CUBE_IN_CHANNEL_0
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0                  _MK_ADDR_CONST(0xb014)
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD                    _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT)
++
++
++// Register PDP_D_DATA_CUBE_OUT_WIDTH_0
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0                   _MK_ADDR_CONST(0xb018)
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT                      _MK_SHIFT_CONST(0)
++#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_FIELD                      _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT)
++
++
++// Register PDP_D_DATA_CUBE_OUT_HEIGHT_0
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0                  _MK_ADDR_CONST(0xb01c)
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_FIELD                    _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT)
++
++
++// Register PDP_D_DATA_CUBE_OUT_CHANNEL_0
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0                 _MK_ADDR_CONST(0xb020)
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT                  _MK_SHIFT_CONST(0)
++#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_FIELD                  _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT)
++
++
++// Register PDP_D_OPERATION_MODE_CFG_0
++#define PDP_D_OPERATION_MODE_CFG_0                    _MK_ADDR_CONST(0xb024)
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT                       _MK_SHIFT_CONST(0)
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_FIELD                       _MK_FIELD_CONST(0x3, PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT)
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE                      _MK_ENUM_CONST(0x0)
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX                  _MK_ENUM_CONST(0x1)
++#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN                  _MK_ENUM_CONST(0x2)
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT                  _MK_SHIFT_CONST(4)
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_FIELD                  _MK_FIELD_CONST(0x1, PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT)
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING                      _MK_ENUM_CONST(0x0)
++#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING                     _MK_ENUM_CONST(0x1)
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT                    _MK_SHIFT_CONST(8)
++#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD                    _MK_FIELD_CONST(0xff, PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT)
++
++
++// Register PDP_D_NAN_FLUSH_TO_ZERO_0
++#define PDP_D_NAN_FLUSH_TO_ZERO_0                     _MK_ADDR_CONST(0xb028)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD                   _MK_FIELD_CONST(0x1, PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE                 _MK_ENUM_CONST(0x0)
++#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE                  _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_D_PARTIAL_WIDTH_IN_0
++#define PDP_D_PARTIAL_WIDTH_IN_0                      _MK_ADDR_CONST(0xb02c)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD                 _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT                  _MK_SHIFT_CONST(10)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD                  _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT                   _MK_SHIFT_CONST(20)
++#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD                   _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT)
++
++
++// Register PDP_D_PARTIAL_WIDTH_OUT_0
++#define PDP_D_PARTIAL_WIDTH_OUT_0                     _MK_ADDR_CONST(0xb030)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT                       _MK_SHIFT_CONST(0)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_FIELD                       _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT                        _MK_SHIFT_CONST(10)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_FIELD                        _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT                 _MK_SHIFT_CONST(20)
++#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_FIELD                 _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT)
++
++
++// Register PDP_D_POOLING_KERNEL_CFG_0
++#define PDP_D_POOLING_KERNEL_CFG_0                    _MK_ADDR_CONST(0xb034)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD                 _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1                        _MK_ENUM_CONST(0x0)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2                        _MK_ENUM_CONST(0x1)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3                        _MK_ENUM_CONST(0x2)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4                        _MK_ENUM_CONST(0x3)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5                        _MK_ENUM_CONST(0x4)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6                        _MK_ENUM_CONST(0x5)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7                        _MK_ENUM_CONST(0x6)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8                        _MK_ENUM_CONST(0x7)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT                        _MK_SHIFT_CONST(8)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_FIELD                        _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_1                      _MK_ENUM_CONST(0x0)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_2                      _MK_ENUM_CONST(0x1)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_3                      _MK_ENUM_CONST(0x2)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_4                      _MK_ENUM_CONST(0x3)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_5                      _MK_ENUM_CONST(0x4)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_6                      _MK_ENUM_CONST(0x5)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_7                      _MK_ENUM_CONST(0x6)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_8                      _MK_ENUM_CONST(0x7)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT                  _MK_SHIFT_CONST(16)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD                  _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(20)
++#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_FIELD                 _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT)
++
++
++// Register PDP_D_RECIP_KERNEL_WIDTH_0
++#define PDP_D_RECIP_KERNEL_WIDTH_0                    _MK_ADDR_CONST(0xb038)
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_FIELD                   _MK_FIELD_CONST(0x1ffff, PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT)
++
++
++// Register PDP_D_RECIP_KERNEL_HEIGHT_0
++#define PDP_D_RECIP_KERNEL_HEIGHT_0                   _MK_ADDR_CONST(0xb03c)
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_FIELD                 _MK_FIELD_CONST(0x1ffff, PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT)
++
++
++// Register PDP_D_POOLING_PADDING_CFG_0
++#define PDP_D_POOLING_PADDING_CFG_0                   _MK_ADDR_CONST(0xb040)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT                    _MK_SHIFT_CONST(0)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_FIELD                    _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT                     _MK_SHIFT_CONST(4)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_FIELD                     _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT                   _MK_SHIFT_CONST(8)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_FIELD                   _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT                  _MK_SHIFT_CONST(12)
++#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_FIELD                  _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT)
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_1_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0                   _MK_ADDR_CONST(0xb044)
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_FIELD                        _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT)
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_2_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0                   _MK_ADDR_CONST(0xb048)
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_FIELD                        _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT)
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_3_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0                   _MK_ADDR_CONST(0xb04c)
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_FIELD                        _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT)
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_4_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0                   _MK_ADDR_CONST(0xb050)
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_FIELD                        _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT)
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_5_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0                   _MK_ADDR_CONST(0xb054)
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_FIELD                        _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT)
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_6_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0                   _MK_ADDR_CONST(0xb058)
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_FIELD                        _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT)
++
++
++// Register PDP_D_POOLING_PADDING_VALUE_7_CFG_0
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0                   _MK_ADDR_CONST(0xb05c)
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_FIELD                        _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT)
++
++
++// Register PDP_D_SRC_BASE_ADDR_LOW_0
++#define PDP_D_SRC_BASE_ADDR_LOW_0                     _MK_ADDR_CONST(0xb060)
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT                     _MK_SHIFT_CONST(0)
++#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT)
++
++
++// Register PDP_D_SRC_BASE_ADDR_HIGH_0
++#define PDP_D_SRC_BASE_ADDR_HIGH_0                    _MK_ADDR_CONST(0xb064)
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD                   _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register PDP_D_SRC_LINE_STRIDE_0
++#define PDP_D_SRC_LINE_STRIDE_0                       _MK_ADDR_CONST(0xb068)
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD                 _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT)
++
++
++// Register PDP_D_SRC_SURFACE_STRIDE_0
++#define PDP_D_SRC_SURFACE_STRIDE_0                    _MK_ADDR_CONST(0xb06c)
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD                   _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT)
++
++
++// Register PDP_D_DST_BASE_ADDR_LOW_0
++#define PDP_D_DST_BASE_ADDR_LOW_0                     _MK_ADDR_CONST(0xb070)
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT                     _MK_SHIFT_CONST(0)
++#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT)
++
++
++// Register PDP_D_DST_BASE_ADDR_HIGH_0
++#define PDP_D_DST_BASE_ADDR_HIGH_0                    _MK_ADDR_CONST(0xb074)
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD                   _MK_FIELD_CONST(0xffffffff, PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register PDP_D_DST_LINE_STRIDE_0
++#define PDP_D_DST_LINE_STRIDE_0                       _MK_ADDR_CONST(0xb078)
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD                 _MK_FIELD_CONST(0xffffffff, PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT)
++
++
++// Register PDP_D_DST_SURFACE_STRIDE_0
++#define PDP_D_DST_SURFACE_STRIDE_0                    _MK_ADDR_CONST(0xb07c)
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD                   _MK_FIELD_CONST(0xffffffff, PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT)
++
++
++// Register PDP_D_DST_RAM_CFG_0
++#define PDP_D_DST_RAM_CFG_0                   _MK_ADDR_CONST(0xb080)
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT                        _MK_SHIFT_CONST(0)
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_FIELD                        _MK_FIELD_CONST(0x1, PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT)
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_CV                   _MK_ENUM_CONST(0x0)
++#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_MC                   _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_D_DATA_FORMAT_0
++#define PDP_D_DATA_FORMAT_0                   _MK_ADDR_CONST(0xb084)
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT                  _MK_SHIFT_CONST(0)
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FIELD                  _MK_FIELD_CONST(0x3, PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT)
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT8                   _MK_ENUM_CONST(0x0)
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT16                  _MK_ENUM_CONST(0x1)
++#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FP16                   _MK_ENUM_CONST(0x2)
++
++
++// Register PDP_D_INF_INPUT_NUM_0
++#define PDP_D_INF_INPUT_NUM_0                 _MK_ADDR_CONST(0xb088)
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT                     _MK_SHIFT_CONST(0)
++#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD                     _MK_FIELD_CONST(0xffffffff, PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT)
++
++
++// Register PDP_D_NAN_INPUT_NUM_0
++#define PDP_D_NAN_INPUT_NUM_0                 _MK_ADDR_CONST(0xb08c)
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT                     _MK_SHIFT_CONST(0)
++#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD                     _MK_FIELD_CONST(0xffffffff, PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT)
++
++
++// Register PDP_D_NAN_OUTPUT_NUM_0
++#define PDP_D_NAN_OUTPUT_NUM_0                        _MK_ADDR_CONST(0xb090)
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT                   _MK_SHIFT_CONST(0)
++#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD                   _MK_FIELD_CONST(0xffffffff, PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT)
++
++
++// Register PDP_D_PERF_ENABLE_0
++#define PDP_D_PERF_ENABLE_0                   _MK_ADDR_CONST(0xb094)
++#define PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT                      _MK_SHIFT_CONST(0)
++#define PDP_D_PERF_ENABLE_0_DMA_EN_FIELD                      _MK_FIELD_CONST(0x1, PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT)
++#define PDP_D_PERF_ENABLE_0_DMA_EN_DISABLE                    _MK_ENUM_CONST(0x0)
++#define PDP_D_PERF_ENABLE_0_DMA_EN_ENABLE                     _MK_ENUM_CONST(0x1)
++
++
++// Register PDP_D_PERF_WRITE_STALL_0
++#define PDP_D_PERF_WRITE_STALL_0                      _MK_ADDR_CONST(0xb098)
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT                       _MK_SHIFT_CONST(0)
++#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD                       _MK_FIELD_CONST(0xffffffff, PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT)
++
++
++// Register PDP_D_CYA_0
++#define PDP_D_CYA_0                   _MK_ADDR_CONST(0xb09c)
++#define PDP_D_CYA_0_CYA_SHIFT                 _MK_SHIFT_CONST(0)
++#define PDP_D_CYA_0_CYA_FIELD                 _MK_FIELD_CONST(0xffffffff, PDP_D_CYA_0_CYA_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register CDP_RDMA_S_STATUS_0
++#define CDP_RDMA_S_STATUS_0                   _MK_ADDR_CONST(0xc000)
++#define CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDP_RDMA_S_STATUS_0_STATUS_0_FIELD                    _MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT)
++#define CDP_RDMA_S_STATUS_0_STATUS_0_IDLE                     _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                  _MK_ENUM_CONST(0x1)
++#define CDP_RDMA_S_STATUS_0_STATUS_0_PENDING                  _MK_ENUM_CONST(0x2)
++#define CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                    _MK_SHIFT_CONST(16)
++#define CDP_RDMA_S_STATUS_0_STATUS_1_FIELD                    _MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT)
++#define CDP_RDMA_S_STATUS_0_STATUS_1_IDLE                     _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                  _MK_ENUM_CONST(0x1)
++#define CDP_RDMA_S_STATUS_0_STATUS_1_PENDING                  _MK_ENUM_CONST(0x2)
++
++
++// Register CDP_RDMA_S_POINTER_0
++#define CDP_RDMA_S_POINTER_0                  _MK_ADDR_CONST(0xc004)
++#define CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_RDMA_S_POINTER_0_PRODUCER_FIELD                   _MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT)
++#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                 _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                 _MK_ENUM_CONST(0x1)
++#define CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                   _MK_SHIFT_CONST(16)
++#define CDP_RDMA_S_POINTER_0_CONSUMER_FIELD                   _MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT)
++#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                 _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                 _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_RDMA_D_OP_ENABLE_0
++#define CDP_RDMA_D_OP_ENABLE_0                        _MK_ADDR_CONST(0xc008)
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD                    _MK_FIELD_CONST(0x1, CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                  _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                   _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_RDMA_D_DATA_CUBE_WIDTH_0
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0                  _MK_ADDR_CONST(0xc00c)
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD                      _MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT)
++
++
++// Register CDP_RDMA_D_DATA_CUBE_HEIGHT_0
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0                 _MK_ADDR_CONST(0xc010)
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD                    _MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT)
++
++
++// Register CDP_RDMA_D_DATA_CUBE_CHANNEL_0
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0                        _MK_ADDR_CONST(0xc014)
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT                  _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD                  _MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT)
++
++
++// Register CDP_RDMA_D_SRC_BASE_ADDR_LOW_0
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0                        _MK_ADDR_CONST(0xc018)
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD                        _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT)
++
++
++// Register CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                       _MK_ADDR_CONST(0xc01c)
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD                      _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register CDP_RDMA_D_SRC_LINE_STRIDE_0
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0                  _MK_ADDR_CONST(0xc020)
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD                    _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT)
++
++
++// Register CDP_RDMA_D_SRC_SURFACE_STRIDE_0
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0                       _MK_ADDR_CONST(0xc024)
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD                      _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT)
++
++
++// Register CDP_RDMA_D_SRC_DMA_CFG_0
++#define CDP_RDMA_D_SRC_DMA_CFG_0                      _MK_ADDR_CONST(0xc028)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD                   _MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV                      _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC                      _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_RDMA_D_SRC_COMPRESSION_EN_0
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0                       _MK_ADDR_CONST(0xc02c)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_FIELD                      _MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DISABLE                    _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_ENABLE                     _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_RDMA_D_OPERATION_MODE_0
++#define CDP_RDMA_D_OPERATION_MODE_0                   _MK_ADDR_CONST(0xc030)
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_FIELD                      _MK_FIELD_CONST(0x3, CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT)
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_READPHILE                  _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WRITEPHILE                 _MK_ENUM_CONST(0x1)
++#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_ORDINARY                   _MK_ENUM_CONST(0x2)
++
++
++// Register CDP_RDMA_D_DATA_FORMAT_0
++#define CDP_RDMA_D_DATA_FORMAT_0                      _MK_ADDR_CONST(0xc034)
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD                     _MK_FIELD_CONST(0x3, CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT)
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8                      _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16                     _MK_ENUM_CONST(0x1)
++#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16                      _MK_ENUM_CONST(0x2)
++
++
++// Register CDP_RDMA_D_PERF_ENABLE_0
++#define CDP_RDMA_D_PERF_ENABLE_0                      _MK_ADDR_CONST(0xc038)
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD                 _MK_FIELD_CONST(0x1, CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT)
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE                       _MK_ENUM_CONST(0x0)
++#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE                        _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_RDMA_D_PERF_READ_STALL_0
++#define CDP_RDMA_D_PERF_READ_STALL_0                  _MK_ADDR_CONST(0xc03c)
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD                    _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT)
++
++
++// Register CDP_RDMA_D_CYA_0
++#define CDP_RDMA_D_CYA_0                      _MK_ADDR_CONST(0xc040)
++#define CDP_RDMA_D_CYA_0_CYA_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDP_RDMA_D_CYA_0_CYA_FIELD                    _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_CYA_0_CYA_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register CDP_S_STATUS_0
++#define CDP_S_STATUS_0                        _MK_ADDR_CONST(0xd000)
++#define CDP_S_STATUS_0_STATUS_0_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_S_STATUS_0_STATUS_0_FIELD                 _MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_0_SHIFT)
++#define CDP_S_STATUS_0_STATUS_0_IDLE                  _MK_ENUM_CONST(0x0)
++#define CDP_S_STATUS_0_STATUS_0_RUNNING                       _MK_ENUM_CONST(0x1)
++#define CDP_S_STATUS_0_STATUS_0_PENDING                       _MK_ENUM_CONST(0x2)
++#define CDP_S_STATUS_0_STATUS_1_SHIFT                 _MK_SHIFT_CONST(16)
++#define CDP_S_STATUS_0_STATUS_1_FIELD                 _MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_1_SHIFT)
++#define CDP_S_STATUS_0_STATUS_1_IDLE                  _MK_ENUM_CONST(0x0)
++#define CDP_S_STATUS_0_STATUS_1_RUNNING                       _MK_ENUM_CONST(0x1)
++#define CDP_S_STATUS_0_STATUS_1_PENDING                       _MK_ENUM_CONST(0x2)
++
++
++// Register CDP_S_POINTER_0
++#define CDP_S_POINTER_0                       _MK_ADDR_CONST(0xd004)
++#define CDP_S_POINTER_0_PRODUCER_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDP_S_POINTER_0_PRODUCER_FIELD                        _MK_FIELD_CONST(0x1, CDP_S_POINTER_0_PRODUCER_SHIFT)
++#define CDP_S_POINTER_0_PRODUCER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define CDP_S_POINTER_0_PRODUCER_GROUP_1                      _MK_ENUM_CONST(0x1)
++#define CDP_S_POINTER_0_CONSUMER_SHIFT                        _MK_SHIFT_CONST(16)
++#define CDP_S_POINTER_0_CONSUMER_FIELD                        _MK_FIELD_CONST(0x1, CDP_S_POINTER_0_CONSUMER_SHIFT)
++#define CDP_S_POINTER_0_CONSUMER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define CDP_S_POINTER_0_CONSUMER_GROUP_1                      _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_S_LUT_ACCESS_CFG_0
++#define CDP_S_LUT_ACCESS_CFG_0                        _MK_ADDR_CONST(0xd008)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD                 _MK_FIELD_CONST(0x3ff, CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT                     _MK_SHIFT_CONST(16)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD                     _MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE                        _MK_ENUM_CONST(0x0)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO                        _MK_ENUM_CONST(0x1)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT                  _MK_SHIFT_CONST(17)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD                  _MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ                   _MK_ENUM_CONST(0x0)
++#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE                  _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_S_LUT_ACCESS_DATA_0
++#define CDP_S_LUT_ACCESS_DATA_0                       _MK_ADDR_CONST(0xd00c)
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD                        _MK_FIELD_CONST(0xffff, CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT)
++
++
++// Register CDP_S_LUT_CFG_0
++#define CDP_S_LUT_CFG_0                       _MK_ADDR_CONST(0xd010)
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD                 _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT)
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT                      _MK_ENUM_CONST(0x0)
++#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR                        _MK_ENUM_CONST(0x1)
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT                      _MK_SHIFT_CONST(4)
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD                      _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT)
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE                 _MK_ENUM_CONST(0x0)
++#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO                 _MK_ENUM_CONST(0x1)
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT                      _MK_SHIFT_CONST(5)
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD                      _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT)
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE                 _MK_ENUM_CONST(0x0)
++#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO                 _MK_ENUM_CONST(0x1)
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT                     _MK_SHIFT_CONST(6)
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD                     _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT)
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE                        _MK_ENUM_CONST(0x0)
++#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO                        _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_S_LUT_INFO_0
++#define CDP_S_LUT_INFO_0                      _MK_ADDR_CONST(0xd014)
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT                    _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD                    _MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT)
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT                    _MK_SHIFT_CONST(8)
++#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD                    _MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT)
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT                    _MK_SHIFT_CONST(16)
++#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD                    _MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT)
++
++
++// Register CDP_S_LUT_LE_START_LOW_0
++#define CDP_S_LUT_LE_START_LOW_0                      _MK_ADDR_CONST(0xd018)
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT                       _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_FIELD                       _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT)
++
++
++// Register CDP_S_LUT_LE_START_HIGH_0
++#define CDP_S_LUT_LE_START_HIGH_0                     _MK_ADDR_CONST(0xd01c)
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_FIELD                     _MK_FIELD_CONST(0x3f, CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT)
++
++
++// Register CDP_S_LUT_LE_END_LOW_0
++#define CDP_S_LUT_LE_END_LOW_0                        _MK_ADDR_CONST(0xd020)
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_FIELD                   _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT)
++
++
++// Register CDP_S_LUT_LE_END_HIGH_0
++#define CDP_S_LUT_LE_END_HIGH_0                       _MK_ADDR_CONST(0xd024)
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_FIELD                 _MK_FIELD_CONST(0x3f, CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT)
++
++
++// Register CDP_S_LUT_LO_START_LOW_0
++#define CDP_S_LUT_LO_START_LOW_0                      _MK_ADDR_CONST(0xd028)
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT                       _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_FIELD                       _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT)
++
++
++// Register CDP_S_LUT_LO_START_HIGH_0
++#define CDP_S_LUT_LO_START_HIGH_0                     _MK_ADDR_CONST(0xd02c)
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_FIELD                     _MK_FIELD_CONST(0x3f, CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT)
++
++
++// Register CDP_S_LUT_LO_END_LOW_0
++#define CDP_S_LUT_LO_END_LOW_0                        _MK_ADDR_CONST(0xd030)
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_FIELD                   _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT)
++
++
++// Register CDP_S_LUT_LO_END_HIGH_0
++#define CDP_S_LUT_LO_END_HIGH_0                       _MK_ADDR_CONST(0xd034)
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_FIELD                 _MK_FIELD_CONST(0x3f, CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT)
++
++
++// Register CDP_S_LUT_LE_SLOPE_SCALE_0
++#define CDP_S_LUT_LE_SLOPE_SCALE_0                    _MK_ADDR_CONST(0xd038)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD                     _MK_FIELD_CONST(0xffff, CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT                     _MK_SHIFT_CONST(16)
++#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD                     _MK_FIELD_CONST(0xffff, CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT)
++
++
++// Register CDP_S_LUT_LE_SLOPE_SHIFT_0
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0                    _MK_ADDR_CONST(0xd03c)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD                     _MK_FIELD_CONST(0x1f, CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT                     _MK_SHIFT_CONST(5)
++#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD                     _MK_FIELD_CONST(0x1f, CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT)
++
++
++// Register CDP_S_LUT_LO_SLOPE_SCALE_0
++#define CDP_S_LUT_LO_SLOPE_SCALE_0                    _MK_ADDR_CONST(0xd040)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD                     _MK_FIELD_CONST(0xffff, CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT                     _MK_SHIFT_CONST(16)
++#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD                     _MK_FIELD_CONST(0xffff, CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT)
++
++
++// Register CDP_S_LUT_LO_SLOPE_SHIFT_0
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0                    _MK_ADDR_CONST(0xd044)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD                     _MK_FIELD_CONST(0x1f, CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT                     _MK_SHIFT_CONST(5)
++#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD                     _MK_FIELD_CONST(0x1f, CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT)
++
++
++// Register CDP_D_OP_ENABLE_0
++#define CDP_D_OP_ENABLE_0                     _MK_ADDR_CONST(0xd048)
++#define CDP_D_OP_ENABLE_0_OP_EN_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_D_OP_ENABLE_0_OP_EN_FIELD                 _MK_FIELD_CONST(0x1, CDP_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define CDP_D_OP_ENABLE_0_OP_EN_DISABLE                       _MK_ENUM_CONST(0x0)
++#define CDP_D_OP_ENABLE_0_OP_EN_ENABLE                        _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_D_FUNC_BYPASS_0
++#define CDP_D_FUNC_BYPASS_0                   _MK_ADDR_CONST(0xd04c)
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT)
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DISABLE                      _MK_ENUM_CONST(0x0)
++#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_ENABLE                       _MK_ENUM_CONST(0x1)
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT                  _MK_SHIFT_CONST(1)
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_FIELD                  _MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT)
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DISABLE                        _MK_ENUM_CONST(0x0)
++#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_ENABLE                 _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_D_DST_BASE_ADDR_LOW_0
++#define CDP_D_DST_BASE_ADDR_LOW_0                     _MK_ADDR_CONST(0xd050)
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT)
++
++
++// Register CDP_D_DST_BASE_ADDR_HIGH_0
++#define CDP_D_DST_BASE_ADDR_HIGH_0                    _MK_ADDR_CONST(0xd054)
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD                   _MK_FIELD_CONST(0xffffffff, CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT)
++
++
++// Register CDP_D_DST_LINE_STRIDE_0
++#define CDP_D_DST_LINE_STRIDE_0                       _MK_ADDR_CONST(0xd058)
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD                 _MK_FIELD_CONST(0xffffffff, CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT)
++
++
++// Register CDP_D_DST_SURFACE_STRIDE_0
++#define CDP_D_DST_SURFACE_STRIDE_0                    _MK_ADDR_CONST(0xd05c)
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD                   _MK_FIELD_CONST(0xffffffff, CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT)
++
++
++// Register CDP_D_DST_DMA_CFG_0
++#define CDP_D_DST_DMA_CFG_0                   _MK_ADDR_CONST(0xd060)
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT                        _MK_SHIFT_CONST(0)
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD                        _MK_FIELD_CONST(0x1, CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT)
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV                   _MK_ENUM_CONST(0x0)
++#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC                   _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_D_DST_COMPRESSION_EN_0
++#define CDP_D_DST_COMPRESSION_EN_0                    _MK_ADDR_CONST(0xd064)
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_FIELD                   _MK_FIELD_CONST(0x1, CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT)
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DISABLE                 _MK_ENUM_CONST(0x0)
++#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_ENABLE                  _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_D_DATA_FORMAT_0
++#define CDP_D_DATA_FORMAT_0                   _MK_ADDR_CONST(0xd068)
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FIELD                     _MK_FIELD_CONST(0x3, CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT)
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT8                      _MK_ENUM_CONST(0x0)
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT16                     _MK_ENUM_CONST(0x1)
++#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FP16                      _MK_ENUM_CONST(0x2)
++
++
++// Register CDP_D_NAN_FLUSH_TO_ZERO_0
++#define CDP_D_NAN_FLUSH_TO_ZERO_0                     _MK_ADDR_CONST(0xd06c)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD                   _MK_FIELD_CONST(0x1, CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE                 _MK_ENUM_CONST(0x0)
++#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE                  _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_D_LRN_CFG_0
++#define CDP_D_LRN_CFG_0                       _MK_ADDR_CONST(0xd070)
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_FIELD                     _MK_FIELD_CONST(0x3, CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT)
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN3                      _MK_ENUM_CONST(0x0)
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN5                      _MK_ENUM_CONST(0x1)
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN7                      _MK_ENUM_CONST(0x2)
++#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9                      _MK_ENUM_CONST(0x3)
++
++
++// Register CDP_D_DATIN_OFFSET_0
++#define CDP_D_DATIN_OFFSET_0                  _MK_ADDR_CONST(0xd074)
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT                       _MK_SHIFT_CONST(0)
++#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_FIELD                       _MK_FIELD_CONST(0xffff, CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT)
++
++
++// Register CDP_D_DATIN_SCALE_0
++#define CDP_D_DATIN_SCALE_0                   _MK_ADDR_CONST(0xd078)
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_FIELD                 _MK_FIELD_CONST(0xffff, CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT)
++
++
++// Register CDP_D_DATIN_SHIFTER_0
++#define CDP_D_DATIN_SHIFTER_0                 _MK_ADDR_CONST(0xd07c)
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_FIELD                     _MK_FIELD_CONST(0x1f, CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT)
++
++
++// Register CDP_D_DATOUT_OFFSET_0
++#define CDP_D_DATOUT_OFFSET_0                 _MK_ADDR_CONST(0xd080)
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_FIELD                     _MK_FIELD_CONST(0xffffffff, CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT)
++
++
++// Register CDP_D_DATOUT_SCALE_0
++#define CDP_D_DATOUT_SCALE_0                  _MK_ADDR_CONST(0xd084)
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT                       _MK_SHIFT_CONST(0)
++#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_FIELD                       _MK_FIELD_CONST(0xffff, CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT)
++
++
++// Register CDP_D_DATOUT_SHIFTER_0
++#define CDP_D_DATOUT_SHIFTER_0                        _MK_ADDR_CONST(0xd088)
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_FIELD                   _MK_FIELD_CONST(0x3f, CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT)
++
++
++// Register CDP_D_NAN_INPUT_NUM_0
++#define CDP_D_NAN_INPUT_NUM_0                 _MK_ADDR_CONST(0xd08c)
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD                     _MK_FIELD_CONST(0xffffffff, CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT)
++
++
++// Register CDP_D_INF_INPUT_NUM_0
++#define CDP_D_INF_INPUT_NUM_0                 _MK_ADDR_CONST(0xd090)
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT                     _MK_SHIFT_CONST(0)
++#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD                     _MK_FIELD_CONST(0xffffffff, CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT)
++
++
++// Register CDP_D_NAN_OUTPUT_NUM_0
++#define CDP_D_NAN_OUTPUT_NUM_0                        _MK_ADDR_CONST(0xd094)
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD                   _MK_FIELD_CONST(0xffffffff, CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT)
++
++
++// Register CDP_D_OUT_SATURATION_0
++#define CDP_D_OUT_SATURATION_0                        _MK_ADDR_CONST(0xd098)
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_FIELD                   _MK_FIELD_CONST(0xffffffff, CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT)
++
++
++// Register CDP_D_PERF_ENABLE_0
++#define CDP_D_PERF_ENABLE_0                   _MK_ADDR_CONST(0xd09c)
++#define CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT                      _MK_SHIFT_CONST(0)
++#define CDP_D_PERF_ENABLE_0_DMA_EN_FIELD                      _MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT)
++#define CDP_D_PERF_ENABLE_0_DMA_EN_DISABLE                    _MK_ENUM_CONST(0x0)
++#define CDP_D_PERF_ENABLE_0_DMA_EN_ENABLE                     _MK_ENUM_CONST(0x1)
++#define CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT                      _MK_SHIFT_CONST(1)
++#define CDP_D_PERF_ENABLE_0_LUT_EN_FIELD                      _MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT)
++#define CDP_D_PERF_ENABLE_0_LUT_EN_DISABLE                    _MK_ENUM_CONST(0x0)
++#define CDP_D_PERF_ENABLE_0_LUT_EN_ENABLE                     _MK_ENUM_CONST(0x1)
++
++
++// Register CDP_D_PERF_WRITE_STALL_0
++#define CDP_D_PERF_WRITE_STALL_0                      _MK_ADDR_CONST(0xd0a0)
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT                       _MK_SHIFT_CONST(0)
++#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD                       _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT)
++
++
++// Register CDP_D_PERF_LUT_UFLOW_0
++#define CDP_D_PERF_LUT_UFLOW_0                        _MK_ADDR_CONST(0xd0a4)
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_FIELD                   _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT)
++
++
++// Register CDP_D_PERF_LUT_OFLOW_0
++#define CDP_D_PERF_LUT_OFLOW_0                        _MK_ADDR_CONST(0xd0a8)
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT                   _MK_SHIFT_CONST(0)
++#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_FIELD                   _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT)
++
++
++// Register CDP_D_PERF_LUT_HYBRID_0
++#define CDP_D_PERF_LUT_HYBRID_0                       _MK_ADDR_CONST(0xd0ac)
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_FIELD                 _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT)
++
++
++// Register CDP_D_PERF_LUT_LE_HIT_0
++#define CDP_D_PERF_LUT_LE_HIT_0                       _MK_ADDR_CONST(0xd0b0)
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_FIELD                 _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT)
++
++
++// Register CDP_D_PERF_LUT_LO_HIT_0
++#define CDP_D_PERF_LUT_LO_HIT_0                       _MK_ADDR_CONST(0xd0b4)
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_FIELD                 _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT)
++
++
++// Register CDP_D_CYA_0
++#define CDP_D_CYA_0                   _MK_ADDR_CONST(0xd0b8)
++#define CDP_D_CYA_0_CYA_SHIFT                 _MK_SHIFT_CONST(0)
++#define CDP_D_CYA_0_CYA_FIELD                 _MK_FIELD_CONST(0xffffffff, CDP_D_CYA_0_CYA_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register NVDLA_GEC_FEATURE_0
++#define NVDLA_GEC_FEATURE_0                   _MK_ADDR_CONST(0xe000)
++#define NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_SHIFT                      _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_FIELD                      _MK_FIELD_CONST(0x3f, NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_SHIFT)
++#define NVDLA_GEC_FEATURE_0_NUM_ERR_SHIFT                     _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_FEATURE_0_NUM_ERR_FIELD                     _MK_FIELD_CONST(0xffff, NVDLA_GEC_FEATURE_0_NUM_ERR_SHIFT)
++
++
++// Register NVDLA_GEC_SWRESET_0
++#define NVDLA_GEC_SWRESET_0                   _MK_ADDR_CONST(0xe004)
++#define NVDLA_GEC_SWRESET_0_SWRST_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_SWRESET_0_SWRST_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_SWRESET_0_SWRST_SHIFT)
++
++
++// Register NVDLA_GEC_MISSIONERR_TYPE_0
++#define NVDLA_GEC_MISSIONERR_TYPE_0                   _MK_ADDR_CONST(0xe008)
++#define NVDLA_GEC_MISSIONERR_TYPE_0_CODE_SHIFT                        _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_MISSIONERR_TYPE_0_CODE_FIELD                        _MK_FIELD_CONST(0x3f, NVDLA_GEC_MISSIONERR_TYPE_0_CODE_SHIFT)
++
++
++// Register NVDLA_GEC_CURRENT_COUNTER_VALUE_0
++#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0                     _MK_ADDR_CONST(0xe00c)
++#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                 _MK_FIELD_CONST(0x1ff, NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
++
++
++// Register NVDLA_GEC_MISSIONERR_INDEX_0
++#define NVDLA_GEC_MISSIONERR_INDEX_0                  _MK_ADDR_CONST(0xe014)
++#define NVDLA_GEC_MISSIONERR_INDEX_0_IDX_SHIFT                        _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_MISSIONERR_INDEX_0_IDX_FIELD                        _MK_FIELD_CONST(0x7f, NVDLA_GEC_MISSIONERR_INDEX_0_IDX_SHIFT)
++
++
++// Register NVDLA_GEC_CORRECTABLE_THRESHOLD_0
++#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0                     _MK_ADDR_CONST(0xe018)
++#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                 _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                 _MK_FIELD_CONST(0xff, NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
++
++
++// Register NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0
++#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0                  _MK_ADDR_CONST(0xe01c)
++#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
++#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                       _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                     _MK_ENUM_CONST(0xe1)
++
++
++// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0                       _MK_ADDR_CONST(0xe030)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                    _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                    _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                    _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                    _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                    _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                    _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT                    _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT                    _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT                   _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT                   _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT                   _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT                   _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT                   _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT                   _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT                   _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT                   _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT                   _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT                   _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_SHIFT                   _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_SHIFT                   _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_SHIFT                   _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_SHIFT                   _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_SHIFT                   _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_SHIFT                   _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_SHIFT                   _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_SHIFT                   _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_SHIFT                   _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_SHIFT                   _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_SHIFT                   _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_SHIFT                   _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_ENABLE                  _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0                        _MK_ADDR_CONST(0xe034)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                     _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                     _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                     _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                     _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                     _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                     _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT                     _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT                     _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT                     _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT                    _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT                    _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT                    _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT                    _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT                    _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT                    _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT                    _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT                    _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT                    _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_SHIFT                    _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_SHIFT                    _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_SHIFT                    _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_SHIFT                    _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_SHIFT                    _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_SHIFT                    _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_SHIFT                    _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_SHIFT                    _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_SHIFT                    _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_SHIFT                    _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_SHIFT                    _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_FORCE                    _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0                       _MK_ADDR_CONST(0xe038)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                    _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                    _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                    _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                    _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                    _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                    _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT                    _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT                    _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT                   _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT                   _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT                   _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT                   _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT                   _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT                   _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT                   _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT                   _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT                   _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT                   _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_SHIFT                   _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_SHIFT                   _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_SHIFT                   _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_SHIFT                   _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_SHIFT                   _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_SHIFT                   _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_SHIFT                   _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_SHIFT                   _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_SHIFT                   _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_SHIFT                   _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_SHIFT                   _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_SHIFT                   _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_SHIFT)
++
++
++// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0                       _MK_ADDR_CONST(0xe03c)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT                    _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                    _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                    _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                    _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                    _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT                    _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT                    _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT                   _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT                   _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT                   _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT                   _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT                   _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_SHIFT                   _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_SHIFT                   _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_SHIFT                   _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_SHIFT                   _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_SHIFT                   _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_SHIFT                   _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_SHIFT                   _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_SHIFT                   _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_SHIFT                   _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_SHIFT                   _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_SHIFT                   _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_SHIFT                   _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_ENABLE                  _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0                        _MK_ADDR_CONST(0xe040)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                     _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                     _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                     _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                     _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                     _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                     _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT                     _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT                     _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT                     _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DISABLE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_ENABLE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT                    _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT                    _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT                    _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT                    _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT                    _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT                    _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT                    _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT                    _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT                    _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_SHIFT                    _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_SHIFT                    _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_SHIFT                    _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_SHIFT                    _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_SHIFT                    _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_SHIFT                    _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_SHIFT                    _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_SHIFT                    _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_SHIFT                    _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_SHIFT                    _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_SHIFT                    _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_ENABLE                   _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0                 _MK_ADDR_CONST(0xe044)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                      _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                      _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                      _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                      _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                      _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                      _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                      _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT                      _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT                      _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_NOFORCE                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FORCE                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT                     _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT                     _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT                     _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT                     _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT                     _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT                     _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT                     _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT                     _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT                     _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT                     _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_SHIFT                     _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_SHIFT                     _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_SHIFT                     _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_SHIFT                     _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_SHIFT                     _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_SHIFT                     _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_SHIFT                     _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_SHIFT                     _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_SHIFT                     _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_SHIFT                     _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_SHIFT                     _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_SHIFT                     _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_FORCE                     _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0                        _MK_ADDR_CONST(0xe048)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                     _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                     _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                     _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                     _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                     _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                     _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT                     _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT                     _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT                     _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT                    _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT                    _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT                    _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT                    _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT                    _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT                    _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT                    _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT                    _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT                    _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_SHIFT                    _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_SHIFT                    _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_SHIFT                    _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_SHIFT                    _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_SHIFT                    _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_SHIFT                    _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_SHIFT                    _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_SHIFT                    _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_SHIFT                    _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_SHIFT                    _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_SHIFT                    _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_SHIFT)
++
++
++// Register NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0                  _MK_ADDR_CONST(0xe050)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                       _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                       _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                       _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                       _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                       _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                       _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                       _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT                       _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT                       _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT                       _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_NORELOAD                    _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RELOAD                      _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT                      _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT                      _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT                      _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT                      _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT                      _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT                      _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT                      _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT                      _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT                      _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT                      _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_SHIFT                      _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_SHIFT                      _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_SHIFT                      _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_SHIFT                      _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_SHIFT                      _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_SHIFT                      _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_SHIFT                      _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_SHIFT                      _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_SHIFT                      _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_SHIFT                      _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_SHIFT                      _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_SHIFT                      _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_SHIFT)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_RELOAD                     _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0                       _MK_ADDR_CONST(0xe060)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_SHIFT                   _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_SHIFT                   _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_SHIFT                   _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_SHIFT                   _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_SHIFT                   _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_SHIFT                   _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_SHIFT                   _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_SHIFT                   _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_SHIFT                   _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_SHIFT                   _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_SHIFT                   _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_SHIFT                   _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_SHIFT                   _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_SHIFT                   _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_SHIFT                   _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_SHIFT                   _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_SHIFT                   _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_SHIFT                   _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_SHIFT                   _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_SHIFT                   _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_SHIFT                   _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_SHIFT                   _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_SHIFT                   _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_SHIFT                   _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_SHIFT                   _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_SHIFT                   _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_SHIFT                   _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_SHIFT                   _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_SHIFT                   _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_SHIFT                   _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_SHIFT                   _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_ENABLE                  _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0                        _MK_ADDR_CONST(0xe064)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_SHIFT                    _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_SHIFT                    _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_SHIFT                    _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_SHIFT                    _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_SHIFT                    _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_SHIFT                    _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_SHIFT                    _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_SHIFT                    _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_SHIFT                    _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_SHIFT                    _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_SHIFT                    _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_SHIFT                    _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_SHIFT                    _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_SHIFT                    _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_SHIFT                    _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_SHIFT                    _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_SHIFT                    _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_SHIFT                    _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_SHIFT                    _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_SHIFT                    _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_SHIFT                    _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_SHIFT                    _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_SHIFT                    _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_SHIFT                    _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_SHIFT                    _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_SHIFT                    _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_SHIFT                    _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_SHIFT                    _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_FORCE                    _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0                       _MK_ADDR_CONST(0xe068)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_SHIFT                   _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_SHIFT                   _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_SHIFT                   _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_SHIFT                   _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_SHIFT                   _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_SHIFT                   _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_SHIFT                   _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_SHIFT                   _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_SHIFT                   _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_SHIFT                   _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_SHIFT                   _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_SHIFT                   _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_SHIFT                   _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_SHIFT                   _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_SHIFT                   _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_SHIFT                   _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_SHIFT                   _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_SHIFT                   _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_SHIFT                   _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_SHIFT                   _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_SHIFT                   _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_SHIFT                   _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_SHIFT                   _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_SHIFT                   _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_SHIFT                   _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_SHIFT                   _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_SHIFT                   _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_SHIFT                   _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_SHIFT                   _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_SHIFT                   _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_SHIFT                   _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_SHIFT)
++
++
++// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0                       _MK_ADDR_CONST(0xe06c)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_SHIFT                   _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_SHIFT                   _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_SHIFT                   _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_SHIFT                   _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_SHIFT                   _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_SHIFT                   _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_SHIFT                   _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_SHIFT                   _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_SHIFT                   _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_SHIFT                   _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_SHIFT                   _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_SHIFT                   _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_SHIFT                   _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_SHIFT                   _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_SHIFT                   _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_SHIFT                   _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_SHIFT                   _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_SHIFT                   _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_SHIFT                   _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_SHIFT                   _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_SHIFT                   _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_SHIFT                   _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_SHIFT                   _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_SHIFT                   _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_SHIFT                   _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_SHIFT                   _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_SHIFT                   _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_SHIFT                   _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_SHIFT                   _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_SHIFT                   _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_SHIFT                   _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_ENABLE                  _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0                        _MK_ADDR_CONST(0xe070)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_SHIFT                    _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_SHIFT                    _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_SHIFT                    _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_SHIFT                    _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_SHIFT                    _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_SHIFT                    _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_SHIFT                    _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_SHIFT                    _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_SHIFT                    _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_SHIFT                    _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_SHIFT                    _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_SHIFT                    _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_SHIFT                    _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_SHIFT                    _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_SHIFT                    _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_SHIFT                    _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_SHIFT                    _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_SHIFT                    _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_SHIFT                    _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_SHIFT                    _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_SHIFT                    _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_SHIFT                    _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_SHIFT                    _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_SHIFT                    _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_SHIFT                    _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_SHIFT                    _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_SHIFT                    _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_SHIFT                    _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_ENABLE                   _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0                 _MK_ADDR_CONST(0xe074)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_SHIFT                     _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_SHIFT                     _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_SHIFT                     _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_SHIFT                     _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_SHIFT                     _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_SHIFT                     _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_SHIFT                     _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_SHIFT                     _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_SHIFT                     _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_SHIFT                     _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_SHIFT                     _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_SHIFT                     _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_SHIFT                     _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_SHIFT                     _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_SHIFT                     _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_SHIFT                     _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_SHIFT                     _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_SHIFT                     _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_SHIFT                     _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_SHIFT                     _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_SHIFT                     _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_SHIFT                     _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_SHIFT                     _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_SHIFT                     _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_SHIFT                     _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_SHIFT                     _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_SHIFT                     _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_SHIFT                     _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_SHIFT                     _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_SHIFT                     _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_SHIFT                     _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_FORCE                     _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0                        _MK_ADDR_CONST(0xe078)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_SHIFT                    _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_SHIFT                    _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_SHIFT                    _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_SHIFT                    _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_SHIFT                    _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_SHIFT                    _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_SHIFT                    _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_SHIFT                    _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_SHIFT                    _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_SHIFT                    _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_SHIFT                    _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_SHIFT                    _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_SHIFT                    _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_SHIFT                    _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_SHIFT                    _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_SHIFT                    _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_SHIFT                    _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_SHIFT                    _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_SHIFT                    _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_SHIFT                    _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_SHIFT                    _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_SHIFT                    _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_SHIFT                    _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_SHIFT                    _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_SHIFT                    _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_SHIFT                    _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_SHIFT                    _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_SHIFT                    _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_SHIFT)
++
++
++// Register NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0                  _MK_ADDR_CONST(0xe080)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_SHIFT                      _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_SHIFT                      _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_SHIFT                      _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_SHIFT                      _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_SHIFT                      _MK_SHIFT_CONST(4)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_SHIFT                      _MK_SHIFT_CONST(5)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_SHIFT                      _MK_SHIFT_CONST(6)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_SHIFT                      _MK_SHIFT_CONST(7)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_SHIFT                      _MK_SHIFT_CONST(9)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_SHIFT                      _MK_SHIFT_CONST(10)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_SHIFT                      _MK_SHIFT_CONST(11)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_SHIFT                      _MK_SHIFT_CONST(12)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_SHIFT                      _MK_SHIFT_CONST(13)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_SHIFT                      _MK_SHIFT_CONST(14)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_SHIFT                      _MK_SHIFT_CONST(15)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_SHIFT                      _MK_SHIFT_CONST(16)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_SHIFT                      _MK_SHIFT_CONST(17)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_SHIFT                      _MK_SHIFT_CONST(18)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_SHIFT                      _MK_SHIFT_CONST(19)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_SHIFT                      _MK_SHIFT_CONST(20)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_SHIFT                      _MK_SHIFT_CONST(21)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_SHIFT                      _MK_SHIFT_CONST(22)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_SHIFT                      _MK_SHIFT_CONST(23)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_SHIFT                      _MK_SHIFT_CONST(24)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_SHIFT                      _MK_SHIFT_CONST(25)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_SHIFT                      _MK_SHIFT_CONST(26)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_SHIFT                      _MK_SHIFT_CONST(27)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_SHIFT                      _MK_SHIFT_CONST(28)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_SHIFT                      _MK_SHIFT_CONST(29)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_SHIFT                      _MK_SHIFT_CONST(30)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_SHIFT                      _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_RELOAD                     _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0                   _MK_ADDR_CONST(0xe084)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_SHIFT                       _MK_SHIFT_CONST(31)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_FIELD                       _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_SHIFT)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_DISABLE                     _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_ENABLE                      _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0                       _MK_ADDR_CONST(0xe090)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_SHIFT                   _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_SHIFT                   _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_SHIFT                   _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_ENABLE                  _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0                        _MK_ADDR_CONST(0xe094)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_SHIFT                    _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_SHIFT                    _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_FORCE                    _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_SHIFT                    _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_NOFORCE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_FORCE                    _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0                       _MK_ADDR_CONST(0xe098)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_SHIFT                   _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_SHIFT                   _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_SHIFT                   _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_SHIFT)
++
++
++// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0                       _MK_ADDR_CONST(0xe09c)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_SHIFT                   _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_ENABLE                  _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_SHIFT                   _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_FIELD                   _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_DISABLE                 _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_ENABLE                  _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0                        _MK_ADDR_CONST(0xe0a0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_SHIFT                    _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_SHIFT                    _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_ENABLE                   _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_SHIFT                    _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_DISABLE                  _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_ENABLE                   _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0                 _MK_ADDR_CONST(0xe0a4)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_SHIFT                     _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_SHIFT                     _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_FORCE                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_SHIFT                     _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_FIELD                     _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_NOFORCE                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_FORCE                     _MK_ENUM_CONST(0x1)
++
++
++// Register NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0                        _MK_ADDR_CONST(0xe0a8)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_SHIFT                    _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_SHIFT                    _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_SHIFT                    _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_FIELD                    _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_SHIFT)
++
++
++// Register NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0                  _MK_ADDR_CONST(0xe0b0)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_SHIFT                      _MK_SHIFT_CONST(0)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_SHIFT                      _MK_SHIFT_CONST(1)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_SHIFT                      _MK_SHIFT_CONST(2)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_RELOAD                     _MK_ENUM_CONST(0x1)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_SHIFT                      _MK_SHIFT_CONST(3)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_FIELD                      _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_SHIFT)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_NORELOAD                   _MK_ENUM_CONST(0x0)
++#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_RELOAD                     _MK_ENUM_CONST(0x1)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register NVDLA_CVIF_CFG_RD_WEIGHT_0_0
++#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0                  _MK_ADDR_CONST(0xf000)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD                     _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT                      _MK_SHIFT_CONST(16)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT                      _MK_SHIFT_CONST(24)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT)
++
++
++// Register NVDLA_CVIF_CFG_RD_WEIGHT_1_0
++#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0                  _MK_ADDR_CONST(0xf004)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT                    _MK_SHIFT_CONST(0)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT                 _MK_SHIFT_CONST(24)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD                 _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT)
++
++
++// Register NVDLA_CVIF_CFG_RD_WEIGHT_2_0
++#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0                  _MK_ADDR_CONST(0xf008)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT                  _MK_SHIFT_CONST(0)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD                  _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT)
++
++
++// Register NVDLA_CVIF_CFG_WR_WEIGHT_0_0
++#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0                  _MK_ADDR_CONST(0xf00c)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT                     _MK_SHIFT_CONST(0)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD                     _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT                      _MK_SHIFT_CONST(16)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT                      _MK_SHIFT_CONST(24)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT)
++
++
++// Register NVDLA_CVIF_CFG_WR_WEIGHT_1_0
++#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0                  _MK_ADDR_CONST(0xf010)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT                      _MK_SHIFT_CONST(0)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT                    _MK_SHIFT_CONST(8)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT                    _MK_SHIFT_CONST(16)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT                    _MK_SHIFT_CONST(24)
++#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD                    _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT)
++
++
++// Register NVDLA_CVIF_CFG_OUTSTANDING_CNT_0
++#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0                      _MK_ADDR_CONST(0xf014)
++#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT                      _MK_SHIFT_CONST(0)
++#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT)
++#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT                      _MK_SHIFT_CONST(8)
++#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD                      _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT)
++
++
++// Register NVDLA_CVIF_STATUS_0
++#define NVDLA_CVIF_STATUS_0                   _MK_ADDR_CONST(0xf018)
++#define NVDLA_CVIF_STATUS_0_IDLE_SHIFT                        _MK_SHIFT_CONST(8)
++#define NVDLA_CVIF_STATUS_0_IDLE_FIELD                        _MK_FIELD_CONST(0x1, NVDLA_CVIF_STATUS_0_IDLE_SHIFT)
++#define NVDLA_CVIF_STATUS_0_IDLE_NO                   _MK_ENUM_CONST(0x0)
++#define NVDLA_CVIF_STATUS_0_IDLE_YES                  _MK_ENUM_CONST(0x1)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register BDMA_CFG_SRC_ADDR_LOW_0
++#define BDMA_CFG_SRC_ADDR_LOW_0                       _MK_ADDR_CONST(0x10000)
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT                     _MK_SHIFT_CONST(5)
++#define BDMA_CFG_SRC_ADDR_LOW_0_V32_FIELD                     _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT)
++
++
++// Register BDMA_CFG_SRC_ADDR_HIGH_0
++#define BDMA_CFG_SRC_ADDR_HIGH_0                      _MK_ADDR_CONST(0x10004)
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT                     _MK_SHIFT_CONST(0)
++#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_FIELD                     _MK_FIELD_CONST(0xffffffff, BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT)
++
++
++// Register BDMA_CFG_DST_ADDR_LOW_0
++#define BDMA_CFG_DST_ADDR_LOW_0                       _MK_ADDR_CONST(0x10008)
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT                     _MK_SHIFT_CONST(5)
++#define BDMA_CFG_DST_ADDR_LOW_0_V32_FIELD                     _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT)
++
++
++// Register BDMA_CFG_DST_ADDR_HIGH_0
++#define BDMA_CFG_DST_ADDR_HIGH_0                      _MK_ADDR_CONST(0x1000c)
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT                     _MK_SHIFT_CONST(0)
++#define BDMA_CFG_DST_ADDR_HIGH_0_V8_FIELD                     _MK_FIELD_CONST(0xffffffff, BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT)
++
++
++// Register BDMA_CFG_LINE_0
++#define BDMA_CFG_LINE_0                       _MK_ADDR_CONST(0x10010)
++#define BDMA_CFG_LINE_0_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
++#define BDMA_CFG_LINE_0_SIZE_FIELD                    _MK_FIELD_CONST(0x1fff, BDMA_CFG_LINE_0_SIZE_SHIFT)
++
++
++// Register BDMA_CFG_CMD_0
++#define BDMA_CFG_CMD_0                        _MK_ADDR_CONST(0x10014)
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT                     _MK_SHIFT_CONST(0)
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_FIELD                     _MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT)
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_CVSRAM                    _MK_ENUM_CONST(0x0)
++#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_MC                        _MK_ENUM_CONST(0x1)
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT                     _MK_SHIFT_CONST(1)
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_FIELD                     _MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT)
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_CVSRAM                    _MK_ENUM_CONST(0x0)
++#define BDMA_CFG_CMD_0_DST_RAM_TYPE_MC                        _MK_ENUM_CONST(0x1)
++
++
++// Register BDMA_CFG_LINE_REPEAT_0
++#define BDMA_CFG_LINE_REPEAT_0                        _MK_ADDR_CONST(0x10018)
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT                   _MK_SHIFT_CONST(0)
++#define BDMA_CFG_LINE_REPEAT_0_NUMBER_FIELD                   _MK_FIELD_CONST(0xffffff, BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT)
++
++
++// Register BDMA_CFG_SRC_LINE_0
++#define BDMA_CFG_SRC_LINE_0                   _MK_ADDR_CONST(0x1001c)
++#define BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT                      _MK_SHIFT_CONST(5)
++#define BDMA_CFG_SRC_LINE_0_STRIDE_FIELD                      _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT)
++
++
++// Register BDMA_CFG_DST_LINE_0
++#define BDMA_CFG_DST_LINE_0                   _MK_ADDR_CONST(0x10020)
++#define BDMA_CFG_DST_LINE_0_STRIDE_SHIFT                      _MK_SHIFT_CONST(5)
++#define BDMA_CFG_DST_LINE_0_STRIDE_FIELD                      _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_LINE_0_STRIDE_SHIFT)
++
++
++// Register BDMA_CFG_SURF_REPEAT_0
++#define BDMA_CFG_SURF_REPEAT_0                        _MK_ADDR_CONST(0x10024)
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT                   _MK_SHIFT_CONST(0)
++#define BDMA_CFG_SURF_REPEAT_0_NUMBER_FIELD                   _MK_FIELD_CONST(0xffffff, BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT)
++
++
++// Register BDMA_CFG_SRC_SURF_0
++#define BDMA_CFG_SRC_SURF_0                   _MK_ADDR_CONST(0x10028)
++#define BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT                      _MK_SHIFT_CONST(5)
++#define BDMA_CFG_SRC_SURF_0_STRIDE_FIELD                      _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT)
++
++
++// Register BDMA_CFG_DST_SURF_0
++#define BDMA_CFG_DST_SURF_0                   _MK_ADDR_CONST(0x1002c)
++#define BDMA_CFG_DST_SURF_0_STRIDE_SHIFT                      _MK_SHIFT_CONST(5)
++#define BDMA_CFG_DST_SURF_0_STRIDE_FIELD                      _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_SURF_0_STRIDE_SHIFT)
++
++
++// Register BDMA_CFG_OP_0
++#define BDMA_CFG_OP_0                 _MK_ADDR_CONST(0x10030)
++#define BDMA_CFG_OP_0_EN_SHIFT                        _MK_SHIFT_CONST(0)
++#define BDMA_CFG_OP_0_EN_FIELD                        _MK_FIELD_CONST(0x1, BDMA_CFG_OP_0_EN_SHIFT)
++#define BDMA_CFG_OP_0_EN_DISABLE                      _MK_ENUM_CONST(0x0)
++#define BDMA_CFG_OP_0_EN_ENABLE                       _MK_ENUM_CONST(0x1)
++
++
++// Register BDMA_CFG_LAUNCH0_0
++#define BDMA_CFG_LAUNCH0_0                    _MK_ADDR_CONST(0x10034)
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT                  _MK_SHIFT_CONST(0)
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_FIELD                  _MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT)
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_NO                     _MK_ENUM_CONST(0x0)
++#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_YES                    _MK_ENUM_CONST(0x1)
++
++
++// Register BDMA_CFG_LAUNCH1_0
++#define BDMA_CFG_LAUNCH1_0                    _MK_ADDR_CONST(0x10038)
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT                  _MK_SHIFT_CONST(0)
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_FIELD                  _MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT)
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_NO                     _MK_ENUM_CONST(0x0)
++#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_YES                    _MK_ENUM_CONST(0x1)
++
++
++// Register BDMA_CFG_STATUS_0
++#define BDMA_CFG_STATUS_0                     _MK_ADDR_CONST(0x1003c)
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT                        _MK_SHIFT_CONST(0)
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_FIELD                        _MK_FIELD_CONST(0x1, BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT)
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_NO                   _MK_ENUM_CONST(0x0)
++#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_YES                  _MK_ENUM_CONST(0x1)
++
++
++// Register BDMA_STATUS_0
++#define BDMA_STATUS_0                 _MK_ADDR_CONST(0x10040)
++#define BDMA_STATUS_0_FREE_SLOT_SHIFT                 _MK_SHIFT_CONST(0)
++#define BDMA_STATUS_0_FREE_SLOT_FIELD                 _MK_FIELD_CONST(0xff, BDMA_STATUS_0_FREE_SLOT_SHIFT)
++#define BDMA_STATUS_0_IDLE_SHIFT                      _MK_SHIFT_CONST(8)
++#define BDMA_STATUS_0_IDLE_FIELD                      _MK_FIELD_CONST(0x1, BDMA_STATUS_0_IDLE_SHIFT)
++#define BDMA_STATUS_0_IDLE_NO                 _MK_ENUM_CONST(0x0)
++#define BDMA_STATUS_0_IDLE_YES                        _MK_ENUM_CONST(0x1)
++#define BDMA_STATUS_0_GRP0_BUSY_SHIFT                 _MK_SHIFT_CONST(9)
++#define BDMA_STATUS_0_GRP0_BUSY_FIELD                 _MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP0_BUSY_SHIFT)
++#define BDMA_STATUS_0_GRP0_BUSY_NO                    _MK_ENUM_CONST(0x0)
++#define BDMA_STATUS_0_GRP0_BUSY_YES                   _MK_ENUM_CONST(0x1)
++#define BDMA_STATUS_0_GRP1_BUSY_SHIFT                 _MK_SHIFT_CONST(10)
++#define BDMA_STATUS_0_GRP1_BUSY_FIELD                 _MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP1_BUSY_SHIFT)
++#define BDMA_STATUS_0_GRP1_BUSY_NO                    _MK_ENUM_CONST(0x0)
++#define BDMA_STATUS_0_GRP1_BUSY_YES                   _MK_ENUM_CONST(0x1)
++
++
++// Register BDMA_STATUS_GRP0_READ_STALL_0
++#define BDMA_STATUS_GRP0_READ_STALL_0                 _MK_ADDR_CONST(0x10044)
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT                     _MK_SHIFT_CONST(0)
++#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_FIELD                     _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT)
++
++
++// Register BDMA_STATUS_GRP0_WRITE_STALL_0
++#define BDMA_STATUS_GRP0_WRITE_STALL_0                        _MK_ADDR_CONST(0x10048)
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT                    _MK_SHIFT_CONST(0)
++#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_FIELD                    _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT)
++
++
++// Register BDMA_STATUS_GRP1_READ_STALL_0
++#define BDMA_STATUS_GRP1_READ_STALL_0                 _MK_ADDR_CONST(0x1004c)
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT                     _MK_SHIFT_CONST(0)
++#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_FIELD                     _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT)
++
++
++// Register BDMA_STATUS_GRP1_WRITE_STALL_0
++#define BDMA_STATUS_GRP1_WRITE_STALL_0                        _MK_ADDR_CONST(0x10050)
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT                    _MK_SHIFT_CONST(0)
++#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_FIELD                    _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++// Register RBK_S_STATUS_0
++#define RBK_S_STATUS_0                        _MK_ADDR_CONST(0x11000)
++#define RBK_S_STATUS_0_STATUS_0_SHIFT                 _MK_SHIFT_CONST(0)
++#define RBK_S_STATUS_0_STATUS_0_FIELD                 _MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_0_SHIFT)
++#define RBK_S_STATUS_0_STATUS_0_IDLE                  _MK_ENUM_CONST(0x0)
++#define RBK_S_STATUS_0_STATUS_0_RUNNING                       _MK_ENUM_CONST(0x1)
++#define RBK_S_STATUS_0_STATUS_0_PENDING                       _MK_ENUM_CONST(0x2)
++#define RBK_S_STATUS_0_STATUS_1_SHIFT                 _MK_SHIFT_CONST(16)
++#define RBK_S_STATUS_0_STATUS_1_FIELD                 _MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_1_SHIFT)
++#define RBK_S_STATUS_0_STATUS_1_IDLE                  _MK_ENUM_CONST(0x0)
++#define RBK_S_STATUS_0_STATUS_1_RUNNING                       _MK_ENUM_CONST(0x1)
++#define RBK_S_STATUS_0_STATUS_1_PENDING                       _MK_ENUM_CONST(0x2)
++
++
++// Register RBK_S_POINTER_0
++#define RBK_S_POINTER_0                       _MK_ADDR_CONST(0x11004)
++#define RBK_S_POINTER_0_PRODUCER_SHIFT                        _MK_SHIFT_CONST(0)
++#define RBK_S_POINTER_0_PRODUCER_FIELD                        _MK_FIELD_CONST(0x1, RBK_S_POINTER_0_PRODUCER_SHIFT)
++#define RBK_S_POINTER_0_PRODUCER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define RBK_S_POINTER_0_PRODUCER_GROUP_1                      _MK_ENUM_CONST(0x1)
++#define RBK_S_POINTER_0_CONSUMER_SHIFT                        _MK_SHIFT_CONST(16)
++#define RBK_S_POINTER_0_CONSUMER_FIELD                        _MK_FIELD_CONST(0x1, RBK_S_POINTER_0_CONSUMER_SHIFT)
++#define RBK_S_POINTER_0_CONSUMER_GROUP_0                      _MK_ENUM_CONST(0x0)
++#define RBK_S_POINTER_0_CONSUMER_GROUP_1                      _MK_ENUM_CONST(0x1)
++
++
++// Register RBK_D_OP_ENABLE_0
++#define RBK_D_OP_ENABLE_0                     _MK_ADDR_CONST(0x11008)
++#define RBK_D_OP_ENABLE_0_OP_EN_SHIFT                 _MK_SHIFT_CONST(0)
++#define RBK_D_OP_ENABLE_0_OP_EN_FIELD                 _MK_FIELD_CONST(0x1, RBK_D_OP_ENABLE_0_OP_EN_SHIFT)
++#define RBK_D_OP_ENABLE_0_OP_EN_DISABLE                       _MK_ENUM_CONST(0x0)
++#define RBK_D_OP_ENABLE_0_OP_EN_ENABLE                        _MK_ENUM_CONST(0x1)
++
++
++// Register RBK_D_MISC_CFG_0
++#define RBK_D_MISC_CFG_0                      _MK_ADDR_CONST(0x1100c)
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT                     _MK_SHIFT_CONST(0)
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_FIELD                     _MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT)
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_CONTRACT                  _MK_ENUM_CONST(0x0)
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_SPLIT                     _MK_ENUM_CONST(0x1)
++#define RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE                     _MK_ENUM_CONST(0x2)
++#define RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT                   _MK_SHIFT_CONST(8)
++#define RBK_D_MISC_CFG_0_IN_PRECISION_FIELD                   _MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT)
++#define RBK_D_MISC_CFG_0_IN_PRECISION_INT8                    _MK_ENUM_CONST(0x0)
++#define RBK_D_MISC_CFG_0_IN_PRECISION_INT16                   _MK_ENUM_CONST(0x1)
++#define RBK_D_MISC_CFG_0_IN_PRECISION_FP16                    _MK_ENUM_CONST(0x2)
++
++
++// Register RBK_D_DAIN_RAM_TYPE_0
++#define RBK_D_DAIN_RAM_TYPE_0                 _MK_ADDR_CONST(0x11010)
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT                   _MK_SHIFT_CONST(0)
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD                   _MK_FIELD_CONST(0x1, RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT)
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF                    _MK_ENUM_CONST(0x0)
++#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF                    _MK_ENUM_CONST(0x1)
++
++
++// Register RBK_D_DATAIN_SIZE_0_0
++#define RBK_D_DATAIN_SIZE_0_0                 _MK_ADDR_CONST(0x11014)
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT                      _MK_SHIFT_CONST(0)
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD                      _MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT)
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT                     _MK_SHIFT_CONST(16)
++#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD                     _MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT)
++
++
++// Register RBK_D_DATAIN_SIZE_1_0
++#define RBK_D_DATAIN_SIZE_1_0                 _MK_ADDR_CONST(0x11018)
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT                    _MK_SHIFT_CONST(0)
++#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD                    _MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT)
++
++
++// Register RBK_D_DAIN_ADDR_HIGH_0
++#define RBK_D_DAIN_ADDR_HIGH_0                        _MK_ADDR_CONST(0x1101c)
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT                   _MK_SHIFT_CONST(0)
++#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_FIELD                   _MK_FIELD_CONST(0xffffffff, RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT)
++
++
++// Register RBK_D_DAIN_ADDR_LOW_0
++#define RBK_D_DAIN_ADDR_LOW_0                 _MK_ADDR_CONST(0x11020)
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT                     _MK_SHIFT_CONST(5)
++#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_FIELD                     _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT)
++
++
++// Register RBK_D_DAIN_LINE_STRIDE_0
++#define RBK_D_DAIN_LINE_STRIDE_0                      _MK_ADDR_CONST(0x11024)
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT                       _MK_SHIFT_CONST(5)
++#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_FIELD                       _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT)
++
++
++// Register RBK_D_DAIN_SURF_STRIDE_0
++#define RBK_D_DAIN_SURF_STRIDE_0                      _MK_ADDR_CONST(0x11028)
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT                       _MK_SHIFT_CONST(5)
++#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_FIELD                       _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT)
++
++
++// Register RBK_D_DAIN_PLANAR_STRIDE_0
++#define RBK_D_DAIN_PLANAR_STRIDE_0                    _MK_ADDR_CONST(0x1102c)
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT                   _MK_SHIFT_CONST(5)
++#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_FIELD                   _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT)
++
++
++// Register RBK_D_DAOUT_RAM_TYPE_0
++#define RBK_D_DAOUT_RAM_TYPE_0                        _MK_ADDR_CONST(0x11030)
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT                 _MK_SHIFT_CONST(0)
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_FIELD                 _MK_FIELD_CONST(0x1, RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT)
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_CVIF                  _MK_ENUM_CONST(0x0)
++#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_MCIF                  _MK_ENUM_CONST(0x1)
++
++
++// Register RBK_D_DATAOUT_SIZE_1_0
++#define RBK_D_DATAOUT_SIZE_1_0                        _MK_ADDR_CONST(0x11034)
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT                  _MK_SHIFT_CONST(0)
++#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD                  _MK_FIELD_CONST(0x1fff, RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT)
++
++
++// Register RBK_D_DAOUT_ADDR_HIGH_0
++#define RBK_D_DAOUT_ADDR_HIGH_0                       _MK_ADDR_CONST(0x11038)
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT                 _MK_SHIFT_CONST(0)
++#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_FIELD                 _MK_FIELD_CONST(0xffffffff, RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT)
++
++
++// Register RBK_D_DAOUT_ADDR_LOW_0
++#define RBK_D_DAOUT_ADDR_LOW_0                        _MK_ADDR_CONST(0x1103c)
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT                   _MK_SHIFT_CONST(5)
++#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_FIELD                   _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT)
++
++
++// Register RBK_D_DAOUT_LINE_STRIDE_0
++#define RBK_D_DAOUT_LINE_STRIDE_0                     _MK_ADDR_CONST(0x11040)
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT                     _MK_SHIFT_CONST(5)
++#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_FIELD                     _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT)
++
++
++// Register RBK_D_CONTRACT_STRIDE_0_0
++#define RBK_D_CONTRACT_STRIDE_0_0                     _MK_ADDR_CONST(0x11044)
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT                     _MK_SHIFT_CONST(5)
++#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_FIELD                     _MK_FIELD_CONST(0x7ffffff, RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT)
++
++
++// Register RBK_D_CONTRACT_STRIDE_1_0
++#define RBK_D_CONTRACT_STRIDE_1_0                     _MK_ADDR_CONST(0x11048)
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT                     _MK_SHIFT_CONST(5)
++#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_FIELD                     _MK_FIELD_CONST(0x7ffffff, RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT)
++
++
++// Register RBK_D_DAOUT_SURF_STRIDE_0
++#define RBK_D_DAOUT_SURF_STRIDE_0                     _MK_ADDR_CONST(0x1104c)
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT                     _MK_SHIFT_CONST(5)
++#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_FIELD                     _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT)
++
++
++// Register RBK_D_DAOUT_PLANAR_STRIDE_0
++#define RBK_D_DAOUT_PLANAR_STRIDE_0                   _MK_ADDR_CONST(0x11050)
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT                 _MK_SHIFT_CONST(5)
++#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_FIELD                 _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT)
++
++
++// Register RBK_D_DECONV_STRIDE_0
++#define RBK_D_DECONV_STRIDE_0                 _MK_ADDR_CONST(0x11054)
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT                   _MK_SHIFT_CONST(0)
++#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_FIELD                   _MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT)
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT                   _MK_SHIFT_CONST(16)
++#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_FIELD                   _MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT)
++
++
++// Register RBK_D_PERF_ENABLE_0
++#define RBK_D_PERF_ENABLE_0                   _MK_ADDR_CONST(0x11058)
++#define RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT                     _MK_SHIFT_CONST(0)
++#define RBK_D_PERF_ENABLE_0_PERF_EN_FIELD                     _MK_FIELD_CONST(0x1, RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT)
++
++
++// Register RBK_D_PERF_READ_STALL_0
++#define RBK_D_PERF_READ_STALL_0                       _MK_ADDR_CONST(0x1105c)
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT                    _MK_SHIFT_CONST(0)
++#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_FIELD                    _MK_FIELD_CONST(0xffffffff, RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT)
++
++
++// Register RBK_D_PERF_WRITE_STALL_0
++#define RBK_D_PERF_WRITE_STALL_0                      _MK_ADDR_CONST(0x11060)
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT                   _MK_SHIFT_CONST(0)
++#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_FIELD                   _MK_FIELD_CONST(0xffffffff, RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT)
++
++
++
++// To satisfy various compilers and platforms,
++// we let users control the types and syntax of certain constants, using macros.
++#ifndef _MK_SHIFT_CONST
++  #define _MK_SHIFT_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_MASK_CONST
++  #define _MK_MASK_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_ENUM_CONST
++  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
++#endif
++#ifndef _MK_ADDR_CONST
++  #define _MK_ADDR_CONST(_constant_) _constant_
++#endif
++#ifndef _MK_FIELD_CONST
++  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
++#endif
++
++
++
++//
++// ADDRESS SPACES
++//
++
++#define BASE_ADDRESS_NVDLA_CFGROM     0x0
++#define BASE_ADDRESS_NVDLA_GLB        0x1000
++#define BASE_ADDRESS_NVDLA_MCIF       0x2000
++#define BASE_ADDRESS_NVDLA_CDMA       0x3000
++#define BASE_ADDRESS_NVDLA_CSC        0x4000
++#define BASE_ADDRESS_NVDLA_CMAC_A     0x5000
++#define BASE_ADDRESS_NVDLA_CMAC_B     0x6000
++#define BASE_ADDRESS_NVDLA_CACC       0x7000
++#define BASE_ADDRESS_NVDLA_SDP_RDMA   0x8000
++#define BASE_ADDRESS_NVDLA_SDP        0x9000
++#define BASE_ADDRESS_NVDLA_PDP_RDMA   0xa000
++#define BASE_ADDRESS_NVDLA_PDP        0xb000
++#define BASE_ADDRESS_NVDLA_CDP_RDMA   0xc000
++#define BASE_ADDRESS_NVDLA_CDP        0xd000
++#define BASE_ADDRESS_NVDLA_GEC        0xe000
++#define BASE_ADDRESS_NVDLA_CVIF       0xf000
++#define BASE_ADDRESS_NVDLA_BDMA       0x10000
++#define BASE_ADDRESS_NVDLA_RBK        0x11000
++
++#endif
+--- /dev/null
++++ b/drivers/nvdla/nvdla_core_callbacks.c
+@@ -0,0 +1,446 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License version 2
++ * as published by the Free Software Foundation; or, when distributed
++ * separately from the Linux kernel or incorporated into other
++ * software packages, subject to the following license:
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/dma-buf.h>
++#include <linux/dma-mapping.h>
++#include <linux/fs.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/irqdomain.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/printk.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/time.h>
++#include <linux/uaccess.h>
++
++#include <nvdla_interface.h>
++#include <nvdla_linux.h>
++#include <nvdla_ioctl.h>
++#include <opendla.h>
++
++static struct nvdla_config nvdla_config_os_initial = {
++      .atom_size = 32,
++      .bdma_enable = true,
++      .rubik_enable = true,
++      .weight_compress_support = true,
++};
++
++static struct nvdla_config nvdla_config_small = {
++      .atom_size = 8,
++      .bdma_enable = false,
++      .rubik_enable = false,
++      .weight_compress_support = false,
++};
++
++static struct nvdla_config nvdla_config_large = {
++      .atom_size = 32,
++      .bdma_enable = false,
++      .rubik_enable = false,
++      .weight_compress_support = false,
++};
++
++void dla_debug(const char *str, ...)
++{
++      va_list args;
++      va_start(args, str);
++      vprintk(pr_fmt(str), args);
++      va_end(args);
++}
++
++void dla_info(const char *str, ...)
++{
++      va_list args;
++      va_start(args, str);
++      vprintk(str, args);
++      va_end(args);
++}
++
++void dla_warn(const char *str, ...)
++{
++      va_list args;
++      va_start(args, str);
++      vprintk(str, args);
++      va_end(args);
++}
++
++void dla_error(const char *str, ...)
++{
++      va_list args;
++      va_start(args, str);
++      vprintk(str, args);
++      va_end(args);
++}
++
++void *dla_memset(void *src, int ch, uint64_t len)
++{
++      memset(src, ch, len);
++      return src;
++}
++
++void *dla_memcpy(void *dest, const void *src, uint64_t len)
++{
++      return memcpy(dest, src, len);
++}
++
++int64_t dla_get_time_us(void)
++{
++      return ktime_get_ns() / NSEC_PER_USEC;
++}
++
++void dla_reg_write(void *driver_context, uint32_t addr, uint32_t reg)
++{
++      struct nvdla_device *nvdla_dev =
++                      (struct nvdla_device *)driver_context;
++
++      if (!nvdla_dev)
++              return;
++
++      writel(reg, nvdla_dev->base + addr);
++}
++
++uint32_t dla_reg_read(void *driver_context, uint32_t addr)
++{
++      struct nvdla_device *nvdla_dev =
++                      (struct nvdla_device *)driver_context;
++
++      if (!nvdla_dev)
++              return 0;
++
++      return readl(nvdla_dev->base + addr);
++}
++
++static irqreturn_t nvdla_engine_isr(int32_t irq, void *data)
++{
++      unsigned long flags;
++      struct nvdla_device *nvdla_dev = (struct nvdla_device *)data;
++
++      if (!nvdla_dev)
++              return IRQ_NONE;
++
++      spin_lock_irqsave(&nvdla_dev->nvdla_lock, flags);
++      dla_isr_handler(nvdla_dev->engine_context);
++      complete(&nvdla_dev->event_notifier);
++      spin_unlock_irqrestore(&nvdla_dev->nvdla_lock, flags);
++
++      return IRQ_HANDLED;
++}
++
++static int32_t dla_read_dma_address(void *driver_context, void *task_data,
++                                              int16_t index, void *dst)
++{
++      int32_t ret = 0;
++      struct nvdla_mem_handle *handles;
++      dma_addr_t *phys_addr = (dma_addr_t *)(dst);
++      struct nvdla_device *nvdla_dev =
++                      (struct nvdla_device *)driver_context;
++      struct nvdla_task *task = (struct nvdla_task *)task_data;
++
++      if (index == -1 || index > task->num_addresses)
++              return -EINVAL;
++
++      handles = (struct nvdla_mem_handle *)task->address_list;
++      ret = nvdla_gem_dma_addr(nvdla_dev->drm, task->file,
++                                      handles[index].handle,
++                                      phys_addr);
++
++      /* Add offset to IOVA address */
++      *phys_addr = *phys_addr + handles[index].offset;
++
++      return ret;
++}
++
++static int32_t dla_read_cpu_address(void *driver_context, void *task_data,
++                                              int16_t index, void *dst)
++{
++      uint64_t *temp = (uint64_t *)dst;
++      struct nvdla_task *task = (struct nvdla_task *)task_data;
++
++      if (index == -1 || index > task->num_addresses)
++              return -EINVAL;
++
++      *temp = (uint64_t)index;
++      return 0;
++}
++
++int32_t dla_get_dma_address(void *driver_context, void *task_data,
++                                      int16_t index, void *dst_ptr,
++                                      uint32_t destination)
++{
++      int32_t ret = 0;
++
++      if (destination == DESTINATION_PROCESSOR) {
++              ret = dla_read_cpu_address(driver_context, task_data,
++                                              index, dst_ptr);
++      } else if (destination == DESTINATION_DMA) {
++              ret = dla_read_dma_address(driver_context, task_data,
++                                              index, dst_ptr);
++      } else {
++              ret = -EINVAL;
++      }
++
++      return ret;
++}
++
++int32_t dla_data_write(void *driver_context, void *task_data,
++                              void *src, uint64_t dst,
++                              uint32_t size, uint64_t offset)
++{
++      int32_t ret;
++      void *ptr = NULL;
++      struct dma_buf *buf;
++      struct dma_buf_map map;
++      struct nvdla_mem_handle *handles;
++      struct nvdla_task *task = (struct nvdla_task *)task_data;
++      uint64_t dma_addr = 0;
++
++      dla_get_dma_address(driver_context, task_data,dst, (void *)&dma_addr, DESTINATION_DMA);
++      handles = task->address_list;
++      buf = dma_buf_get(handles[dst].handle);
++      if (IS_ERR(buf)) {
++              pr_err("%s: Failed get dma_buf for handle=%d\n", __func__,
++                                              handles[dst].handle);
++              return -EFAULT;
++      }
++
++      ret = dma_buf_begin_cpu_access(buf, DMA_BIDIRECTIONAL);
++      if (ret)
++              goto put_dma_buf;
++
++      ret = dma_buf_vmap(buf, &map);
++      ptr = ret ? NULL : map.vaddr;
++      if (!ptr) {
++              pr_err("%s: Failed to vmap dma_buf for handle=%d\n", __func__,
++                                              handles[dst].handle);
++              ret = -ENOMEM;
++              goto end_cpu_access;
++      }
++
++      memcpy((void *)((uint8_t *)ptr + offset), src, size);
++      dma_buf_vunmap(buf, &map);
++
++end_cpu_access:
++      dma_buf_end_cpu_access(buf, DMA_BIDIRECTIONAL);
++
++put_dma_buf:
++      dma_buf_put(buf);
++
++      return ret;
++}
++
++int32_t dla_data_read(void *driver_context, void *task_data,
++                              uint64_t src, void *dst,
++                              uint32_t size, uint64_t offset)
++{
++      int32_t ret;
++      void *ptr = NULL;
++      struct dma_buf *buf;
++      struct dma_buf_map map;
++      struct nvdla_mem_handle *handles;
++      struct nvdla_task *task = (struct nvdla_task *)task_data;
++      uint64_t dma_addr = 0;
++
++      dla_get_dma_address(driver_context, task_data, src, (void *)&dma_addr, DESTINATION_DMA);
++      handles = task->address_list;
++
++      buf = dma_buf_get(handles[src].handle);
++      if (IS_ERR(buf)) {
++              pr_err("%s: Failed get dma_buf for handle=%d\n", __func__,
++                                              handles[src].handle);
++              return -EFAULT;
++      }
++
++      ret = dma_buf_begin_cpu_access(buf, DMA_BIDIRECTIONAL);
++      if (ret)
++              goto put_dma_buf;
++
++      ret = dma_buf_vmap(buf, &map);
++      ptr = ret ? NULL : map.vaddr;
++      if (!ptr) {
++              pr_err("%s: Failed to vmap dma_buf for handle=%d\n", __func__,
++                                              handles[src].handle);
++              ret = -ENOMEM;
++              goto end_cpu_access;
++      }
++
++      memcpy(dst, (void *)(((uint8_t *)ptr) + offset), size);
++      dma_buf_vunmap(buf, &map);
++
++end_cpu_access:
++      dma_buf_end_cpu_access(buf, DMA_BIDIRECTIONAL);
++
++put_dma_buf:
++      dma_buf_put(buf);
++
++      return ret;
++}
++
++int32_t nvdla_task_submit(struct nvdla_device *nvdla_dev, struct nvdla_task *task)
++{
++      int32_t err = 0;
++      uint32_t task_complete = 0;
++
++      nvdla_dev->task = task;
++
++      err = dla_execute_task(nvdla_dev->engine_context, (void *)task, nvdla_dev->config_data);
++      if (err) {
++              pr_err("Task execution failed\n");
++              return err;
++      }
++
++      pr_debug("Wait for task complete\n");
++
++      while (1) {
++              unsigned long flags;
++
++              wait_for_completion(&nvdla_dev->event_notifier);
++
++              spin_lock_irqsave(&nvdla_dev->nvdla_lock, flags);
++
++              err = dla_process_events(nvdla_dev->engine_context, &task_complete);
++
++              spin_unlock_irqrestore(&nvdla_dev->nvdla_lock, flags);
++
++              if (err || task_complete)
++                      break;
++      }
++
++      pr_debug("Task complete\n");
++      dla_clear_task(nvdla_dev->engine_context);
++
++      return err;
++}
++
++/* driver probe and init */
++static const struct of_device_id nvdla_of_match[] = {
++      {
++              .compatible = "nvidia,nvdla_os_initial",
++              .data = &nvdla_config_os_initial,
++      },
++      {
++              .compatible = "nvidia,nv_small",
++              .data = &nvdla_config_small,
++      },
++      {
++              .compatible = "nvidia,nv_large",
++              .data = &nvdla_config_large,
++      },
++      { },
++};
++
++static int32_t nvdla_probe(struct platform_device *pdev)
++{
++      int32_t err = 0;
++      struct resource *res;
++      struct nvdla_device *nvdla_dev;
++      struct device *dev = &pdev->dev;
++      const struct of_device_id *match;
++
++      if (!pdev->dev.of_node)
++              return -EINVAL;
++
++      match = of_match_device(nvdla_of_match, &pdev->dev);
++      if (!match) {
++              pr_err("Missing DT entry!\n");
++              return -EINVAL;
++      }
++
++      pr_err("Probe NVDLA config %s\n", match->compatible);
++
++      nvdla_dev = devm_kzalloc(dev, sizeof(*nvdla_dev), GFP_KERNEL);
++      if (!nvdla_dev)
++              return -ENOMEM;
++
++      platform_set_drvdata(pdev, nvdla_dev);
++      nvdla_dev->pdev = pdev;
++      nvdla_dev->config_data = (struct nvdla_config *)match->data;
++
++      init_completion(&nvdla_dev->event_notifier);
++
++      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      nvdla_dev->base = devm_ioremap_resource(&pdev->dev, res);
++      if (IS_ERR(nvdla_dev->base))
++              return PTR_ERR(nvdla_dev->base);
++
++      res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++      if (!res) {
++              dev_err(&pdev->dev, "no irq resource\n");
++              return -EINVAL;
++      }
++      nvdla_dev->irq = res->start;
++
++      err = devm_request_irq(&pdev->dev, nvdla_dev->irq,
++                              nvdla_engine_isr, 0,
++                              dev_name(&pdev->dev), nvdla_dev);
++      if (err)
++              return err;
++
++      dla_register_driver(&nvdla_dev->engine_context, (void *)nvdla_dev);
++      dla_clear_task(nvdla_dev->engine_context);
++
++      err = nvdla_drm_probe(nvdla_dev);
++      if (err)
++              dev_err(&pdev->dev, "failed to register drm device\n");
++
++      return err;
++}
++
++static int32_t __exit nvdla_remove(struct platform_device *pdev)
++{
++      struct nvdla_device *nvdla_dev = dev_get_drvdata(&pdev->dev);
++
++      nvdla_drm_remove(nvdla_dev);
++
++      return 0;
++}
++
++static struct platform_driver nvdla_driver = {
++      .probe = nvdla_probe,
++      .remove = __exit_p(nvdla_remove),
++      .driver = {
++              .owner = THIS_MODULE,
++              .name = "NVDLA",
++              .of_match_table = of_match_ptr(nvdla_of_match),
++      },
++};
++module_platform_driver(nvdla_driver);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_AUTHOR("NVIDIA");
++MODULE_DESCRIPTION("Nvidia Deep Learning Accelerator driver");
+--- /dev/null
++++ b/drivers/nvdla/nvdla_gem.c
+@@ -0,0 +1,475 @@
++/*
++ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License version 2
++ * as published by the Free Software Foundation; or, when distributed
++ * separately from the Linux kernel or incorporated into other
++ * software packages, subject to the following license:
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <drm/drm_device.h>
++#include <drm/drm_drv.h>
++#include <drm/drm_gem.h>
++#include <drm/drm_gem_cma_helper.h>
++
++#include <linux/dma-buf.h>
++#include <linux/dma-mapping.h>
++#include <linux/dma-map-ops.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++
++#include <nvdla_linux.h>
++#include <nvdla_ioctl.h>
++#include <opendla.h>
++#define to_nvdla_obj(x) container_of(x, struct nvdla_gem_object, object)
++
++struct nvdla_gem_object {
++      struct drm_gem_object object;
++
++      void *kvaddr;
++      dma_addr_t dma_addr;
++      unsigned long dma_attrs;
++};
++
++static int32_t nvdla_fill_task_desc(struct nvdla_ioctl_submit_task *local_task,
++                              struct nvdla_task *task)
++{
++      struct nvdla_mem_handle *handles;
++
++      /* update task desc fields */
++      task->num_addresses = local_task->num_addresses;
++
++      handles = kzalloc(local_task->num_addresses *
++                              sizeof(struct nvdla_mem_handle), GFP_KERNEL);
++      if (handles == NULL)
++              return -EFAULT;
++
++      /* get user addresses list */
++      if (copy_from_user(handles,
++              (void __user *)local_task->address_list,
++              (task->num_addresses *
++                      sizeof(struct nvdla_mem_handle)))) {
++              pr_err("failed to copy address list from user ptr\n");
++              kfree(handles);
++              return -EFAULT;
++      }
++
++      task->address_list = handles;
++      return 0;
++}
++
++static int32_t nvdla_submit(struct drm_device *drm, void *arg,
++                                      struct drm_file *file)
++{
++      int32_t err = 0;
++      struct nvdla_task *task;
++      struct nvdla_ioctl_submit_task local_task;
++      struct nvdla_ioctl_submit_task __user *user_task;
++      struct nvdla_device *nvdla_dev = dev_get_drvdata(drm->dev);
++      struct nvdla_submit_args *args =
++                      (struct nvdla_submit_args *)arg;
++
++      user_task = (struct nvdla_ioctl_submit_task __user *)
++                      (uintptr_t)args->tasks;
++      if (!user_task)
++              return -EINVAL;
++
++      /* IOCTL copy descriptors */
++      if (copy_from_user(&local_task, (void __user *)user_task,
++                      (sizeof(*user_task))))
++              return -EFAULT;
++
++      task = kzalloc(sizeof(*task), GFP_KERNEL);
++      if (task == NULL)
++              return -EFAULT;
++
++      nvdla_dev->task = task;
++      kref_init(&task->ref);
++      task->nvdla_dev = nvdla_dev;
++      task->file = file;
++
++      /* update task desc fields */
++      err = nvdla_fill_task_desc(&local_task, task);
++      if (err)
++              goto free_task_desc;
++
++      err = nvdla_task_submit(nvdla_dev, task);
++
++      kfree(task->address_list);
++
++free_task_desc:
++      kfree(task);
++      return err;
++}
++
++static int32_t nvdla_gem_alloc(struct nvdla_gem_object *nobj)
++{
++      struct drm_gem_object *dobj = &nobj->object;
++      struct drm_device *drm = dobj->dev;
++
++      nobj->dma_attrs = DMA_ATTR_WRITE_COMBINE;
++
++      nobj->kvaddr = dma_alloc_attrs(drm->dev, dobj->size, &nobj->dma_addr,
++                                              GFP_KERNEL, nobj->dma_attrs);
++
++      if (!nobj->kvaddr)
++              return -ENOMEM;
++
++      return 0;
++}
++
++static void nvdla_gem_free(struct nvdla_gem_object *nobj)
++{
++      struct drm_gem_object *dobj = &nobj->object;
++      struct drm_device *drm = dobj->dev;
++
++      dma_free_attrs(drm->dev, dobj->size, nobj->kvaddr, nobj->dma_addr,
++                              nobj->dma_attrs);
++}
++
++static void nvdla_gem_free_object(struct drm_gem_object *dobj)
++{
++      struct nvdla_gem_object *nobj;
++
++      drm_gem_free_mmap_offset(dobj);
++
++      nobj = to_nvdla_obj(dobj);
++
++      nvdla_gem_free(nobj);
++
++      kfree(nobj);
++}
++
++static struct sg_table
++*nvdla_drm_gem_prime_get_sg_table(struct drm_gem_object *dobj)
++{
++      int32_t ret;
++      struct sg_table *sgt;
++      struct drm_device *drm = dobj->dev;
++      struct nvdla_gem_object *nobj = to_nvdla_obj(dobj);
++
++      sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
++      if (!sgt)
++              return ERR_PTR(-ENOMEM);
++
++      ret = dma_get_sgtable_attrs(drm->dev, sgt, nobj->kvaddr,
++                      nobj->dma_addr, dobj->size,
++                      nobj->dma_attrs);
++      if (ret) {
++              DRM_ERROR("failed to allocate sgt, %d\n", ret);
++              kfree(sgt);
++              return ERR_PTR(ret);
++      }
++
++      return sgt;
++}
++
++static int nvdla_drm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
++{
++      struct nvdla_gem_object *nobj = to_nvdla_obj(obj);
++      if (nobj->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING)
++              return -ENOMEM;
++      dma_buf_map_set_vaddr(map, nobj->kvaddr);
++      return 0;
++}
++
++static void nvdla_drm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map)
++{
++    /* Nothing to do */
++}
++
++static const struct drm_gem_object_funcs nvdla_gem_funcs = {
++      .free                   = nvdla_gem_free_object,
++      .export                 = drm_gem_prime_export,
++      .vmap                   = nvdla_drm_gem_prime_vmap,
++      .vunmap                 = nvdla_drm_gem_prime_vunmap,
++      .get_sg_table   = nvdla_drm_gem_prime_get_sg_table,
++      .vm_ops                 = &drm_gem_cma_vm_ops,
++};
++
++static struct nvdla_gem_object *
++nvdla_gem_create_object(struct drm_device *drm, uint32_t size)
++{
++      int32_t ret;
++      struct drm_gem_object *dobj;
++      struct nvdla_gem_object *nobj;
++
++      size = round_up(size, PAGE_SIZE);
++
++      nobj = kzalloc(sizeof(*nobj), GFP_KERNEL);
++      if (!nobj)
++              return ERR_PTR(-ENOMEM);
++
++      dobj = &nobj->object;
++      dobj->funcs = &nvdla_gem_funcs;
++
++      drm_gem_private_object_init(drm, dobj, size);
++
++      ret = nvdla_gem_alloc(nobj);
++      if (ret)
++              goto free_nvdla_obj;
++
++      return nobj;
++
++free_nvdla_obj:
++      kfree(nobj);
++      return ERR_PTR(ret);
++}
++
++static struct nvdla_gem_object *
++nvdla_gem_create_with_handle(struct drm_file *file_priv,
++                              struct drm_device *drm, uint32_t size,
++                              uint32_t *handle)
++{
++      int32_t ret;
++      struct drm_gem_object *dobj;
++      struct nvdla_gem_object *nobj;
++
++      nobj = nvdla_gem_create_object(drm, size);
++      if (IS_ERR(nobj))
++              return ERR_CAST(nobj);
++
++      dobj = &nobj->object;
++
++      ret = drm_gem_handle_create(file_priv, dobj, handle);
++      if (ret)
++              goto free_drm_object;
++
++      drm_gem_object_put(dobj);
++
++      return nobj;
++
++free_drm_object:
++      nvdla_gem_free_object(dobj);
++
++      return ERR_PTR(ret);
++}
++
++static int32_t nvdla_gem_create(struct drm_device *drm, void *data,
++                              struct drm_file *file)
++{
++      struct nvdla_gem_object *nobj;
++      struct nvdla_gem_create_args *args = data;
++
++      nobj = nvdla_gem_create_with_handle(file, drm, args->size,
++                                       &args->handle);
++      if (IS_ERR(nobj))
++              return PTR_ERR(nobj);
++
++      return 0;
++}
++
++static int32_t nvdla_drm_gem_object_mmap(struct drm_gem_object *dobj,
++                                      struct vm_area_struct *vma)
++{
++      int32_t ret;
++      struct nvdla_gem_object *nobj = to_nvdla_obj(dobj);
++      struct drm_device *drm = dobj->dev;
++
++      vma->vm_flags &= ~VM_PFNMAP;
++      vma->vm_pgoff = 0;
++
++      ret = dma_mmap_attrs(drm->dev, vma, nobj->kvaddr, nobj->dma_addr,
++                           dobj->size, nobj->dma_attrs);
++      if (ret)
++              drm_gem_vm_close(vma);
++
++      return ret;
++}
++
++static int32_t nvdla_drm_gem_mmap_buf(struct drm_gem_object *obj,
++                              struct vm_area_struct *vma)
++{
++      int32_t ret;
++
++      ret = drm_gem_mmap_obj(obj, obj->size, vma);
++      if (ret)
++              return ret;
++
++      return nvdla_drm_gem_object_mmap(obj, vma);
++}
++
++static int32_t nvdla_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
++{
++      int32_t ret;
++      struct drm_gem_object *obj;
++
++      ret = drm_gem_mmap(filp, vma);
++      if (ret)
++              return ret;
++
++      obj = vma->vm_private_data;
++
++      return nvdla_drm_gem_object_mmap(obj, vma);
++}
++
++int32_t nvdla_gem_dma_addr(struct drm_device *dev, struct drm_file *file,
++                      uint32_t fd, dma_addr_t *addr)
++{
++      int32_t ret;
++      uint32_t handle;
++      struct nvdla_gem_object *nobj;
++      struct drm_gem_object *dobj;
++
++      ret = drm_gem_prime_fd_to_handle(dev, file, fd, &handle);
++      if (ret)
++              return ret;
++
++      dobj = drm_gem_object_lookup(file, handle);
++      if (!dobj)
++              return -EINVAL;
++
++      nobj = to_nvdla_obj(dobj);
++
++      *addr = nobj->dma_addr;
++
++      drm_gem_object_put(dobj);
++
++      return 0;
++}
++
++static int32_t nvdla_gem_map_offset(struct drm_device *drm, void *data,
++                              struct drm_file *file)
++{
++      int32_t ret;
++      struct drm_gem_object *dobj;
++      struct nvdla_gem_map_offset_args *args = data;
++
++      dobj = drm_gem_object_lookup(file, args->handle);
++      if (!dobj)
++              return -EINVAL;
++
++      ret = drm_gem_create_mmap_offset(dobj);
++      if (ret)
++              goto out;
++
++      args->offset = drm_vma_node_offset_addr(&dobj->vma_node);
++
++out:
++      drm_gem_object_put(dobj);
++
++      return 0;
++}
++
++static int32_t nvdla_gem_destroy(struct drm_device *drm, void *data,
++                              struct drm_file *file)
++{
++      struct nvdla_gem_destroy_args *args = data;
++
++      return drm_gem_handle_delete(file, args->handle);
++}
++
++static const struct file_operations nvdla_drm_fops = {
++      .owner = THIS_MODULE,
++      .open = drm_open,
++      .release = drm_release,
++      .unlocked_ioctl = drm_ioctl,
++      .mmap = nvdla_drm_gem_mmap,
++      .poll = drm_poll,
++      .read = drm_read,
++#ifdef CONFIG_COMPAT
++      .compat_ioctl = drm_compat_ioctl,
++#endif
++      .llseek = noop_llseek,
++};
++
++static const struct drm_ioctl_desc nvdla_drm_ioctls[] = {
++      DRM_IOCTL_DEF_DRV(NVDLA_SUBMIT, nvdla_submit, DRM_RENDER_ALLOW),
++      DRM_IOCTL_DEF_DRV(NVDLA_GEM_CREATE, nvdla_gem_create, DRM_RENDER_ALLOW),
++      DRM_IOCTL_DEF_DRV(NVDLA_GEM_MMAP, nvdla_gem_map_offset, DRM_RENDER_ALLOW),
++      DRM_IOCTL_DEF_DRV(NVDLA_GEM_DESTROY, nvdla_gem_destroy, DRM_RENDER_ALLOW),
++};
++
++static struct drm_driver nvdla_drm_driver = {
++      .driver_features = DRIVER_GEM | DRIVER_RENDER,
++
++      .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
++      .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
++      .gem_prime_import = drm_gem_prime_import,
++      .gem_prime_mmap         = nvdla_drm_gem_mmap_buf,
++
++      .ioctls = nvdla_drm_ioctls,
++      .num_ioctls = ARRAY_SIZE(nvdla_drm_ioctls),
++      .fops = &nvdla_drm_fops,
++
++      .name = "nvdla",
++      .desc = "NVDLA driver",
++      .date = "20171017",
++      .major = 0,
++      .minor = 0,
++      .patchlevel = 0,
++};
++
++int32_t nvdla_drm_probe(struct nvdla_device *nvdla_dev)
++{
++      int32_t err;
++      struct drm_device *drm;
++      struct drm_driver *driver = &nvdla_drm_driver;
++      struct resource res_cma;
++      struct device_node *node;
++
++      drm = drm_dev_alloc(driver, &nvdla_dev->pdev->dev);
++      if (IS_ERR(drm))
++              return PTR_ERR(drm);
++
++      nvdla_dev->drm = drm;
++
++      err = drm_dev_register(drm, 0);
++      if (err < 0)
++              goto unref;
++
++      /**
++       * TODO Register separate driver for memory and use DT node to
++       * read memory range
++       */
++      node = of_parse_phandle(drm->dev->of_node, "memory-region", 0);
++      if(node ){
++              dev_info(drm->dev, "Get mem from memory-region\n");
++              of_address_to_resource(node, 0, &res_cma);
++              err = dma_declare_coherent_memory(drm->dev, res_cma.start, res_cma.start,resource_size(&res_cma));
++      } else {
++              dev_info(drm->dev, "NVDLA using the default mem.\n");
++              err = dma_declare_coherent_memory(drm->dev, 0xC0000000, 0xC0000000, 0x40000000);
++      }
++
++      if (err < 0) {
++              goto unref;
++      }
++
++      return 0;
++
++unref:
++      drm_dev_put(drm);
++      return err;
++}
++
++void nvdla_drm_remove(struct nvdla_device *nvdla_dev)
++{
++      drm_dev_unregister(nvdla_dev->drm);
++      drm_dev_put(nvdla_dev->drm);
++}
+--- /dev/null
++++ b/drivers/nvdla/pdp.c
+@@ -0,0 +1,528 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_err.h>
++#include <dla_interface.h>
++
++#include "common.h"
++#include "dla_engine_internal.h"
++#include "engine_debug.h"
++
++#define MAX_SPLIT_NUM 64
++#ifndef ARRAY_SIZE
++#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a[0])))
++#endif
++
++static const uint8_t map_ram[] = {
++      FIELD_ENUM(PDP_RDMA_D_SRC_RAM_CFG_0, SRC_RAM_TYPE, MC),
++      FIELD_ENUM(PDP_RDMA_D_SRC_RAM_CFG_0, SRC_RAM_TYPE, CV),
++};
++
++static const uint8_t map_pool[] = {
++      FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
++                      POOLING_METHOD, POOLING_METHOD_AVERAGE),
++      FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
++                      POOLING_METHOD, POOLING_METHOD_MAX),
++      FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
++                      POOLING_METHOD, POOLING_METHOD_MIN),
++};
++
++static const uint8_t map_precision[] = {
++      FIELD_ENUM(PDP_D_DATA_FORMAT_0, INPUT_DATA, INT8),
++      FIELD_ENUM(PDP_D_DATA_FORMAT_0, INPUT_DATA, INT16),
++      FIELD_ENUM(PDP_D_DATA_FORMAT_0, INPUT_DATA, FP16),
++};
++
++static const uint8_t map_pool_kernel[] = {
++      FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_1),
++      FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_2),
++      FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_3),
++      FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_4),
++      FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_5),
++      FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_6),
++      FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_7),
++      FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_8),
++};
++
++/* The reciprocal of kernel width: 1/1, 1/2, 1/3, ... */
++static const uint32_t recip_kernel_size[2][8] = {
++      /*
++       * INT8/16
++       * 1      1/2     1/3     1/4     1/5     1/6     1/7     1/8
++       */
++      {0x10000, 0x8000, 0x5555, 0x4000, 0x3333, 0x2aaa, 0x2492, 0x2000},
++      {0x7c00, 0x7800, 0x7555,  0x7400, 0x7266, 0x7155, 0x7092, 0x7000},
++};
++
++#if STAT_ENABLE
++void
++dla_pdp_stat_data(struct dla_processor *processor,
++                                      struct dla_processor_group *group)
++{
++      uint64_t end_time = 0;
++      struct dla_pdp_stat_desc *pdp_stat;
++
++      pdp_stat = &processor->stat_data_desc->pdp_stat;
++
++      end_time = dla_get_time_us();
++
++      pdp_stat->write_stall = pdp_reg_read(D_PERF_WRITE_STALL);
++      pdp_stat->runtime = (uint32_t)(end_time - group->start_time);
++}
++
++void
++dla_pdp_dump_stat(struct dla_processor *processor)
++{
++      struct dla_pdp_stat_desc *pdp_stat;
++
++      pdp_stat = &processor->stat_data_desc->pdp_stat;
++
++      dla_debug_pdp_stats(pdp_stat);
++}
++#endif /* STAT_ENABLE */
++
++static uint32_t
++get_fly_mode(uint8_t type)
++{
++      uint32_t val;
++
++      val = type == DLA_MEM_HW ?
++                      FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
++                                              FLYING_MODE, ON_FLYING) :
++                      FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
++                                              FLYING_MODE, OFF_FLYING);
++
++      return val;
++}
++
++void
++dla_pdp_set_producer(int32_t group_id, int32_t rdma_group_id)
++{
++      uint32_t reg;
++
++      dla_trace("Enter: %s", __func__);
++
++      dla_debug("group id %d rdma id %d\n", group_id, rdma_group_id);
++
++      reg = group_id << SHIFT(PDP_S_POINTER_0, PRODUCER);
++      pdp_reg_write(S_POINTER, reg);
++
++      reg = rdma_group_id << SHIFT(PDP_RDMA_S_POINTER_0, PRODUCER);
++      pdp_rdma_reg_write(S_POINTER, reg);
++
++      dla_trace("Exit: %s", __func__);
++}
++
++int
++dla_pdp_enable(struct dla_processor_group *group)
++{
++      int32_t ret = 0;
++      uint32_t reg;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_trace("Enter: %s", __func__);
++
++      if (!group) {
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      if (engine->stat_enable == (uint32_t)1) {
++              reg = FIELD_ENUM(PDP_D_PERF_ENABLE_0, DMA_EN, ENABLE);
++              pdp_reg_write(D_PERF_ENABLE, reg);
++              group->start_time = dla_get_time_us();
++      }
++
++      dla_debug("rdma needed %u\n", group->is_rdma_needed);
++
++      /**
++       * enable all sub-modules
++       */
++      if (group->is_rdma_needed) {
++              reg = FIELD_ENUM(PDP_RDMA_D_OP_ENABLE_0, OP_EN, ENABLE);
++              pdp_rdma_reg_write(D_OP_ENABLE, reg);
++      }
++      reg = FIELD_ENUM(PDP_D_OP_ENABLE_0, OP_EN, ENABLE);
++      pdp_reg_write(D_OP_ENABLE, reg);
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
++
++void
++dla_pdp_rdma_check(struct dla_processor_group *group)
++{
++      struct dla_pdp_surface_desc *pdp_surface;
++
++      pdp_surface = &group->surface_desc->pdp_surface;
++
++      group->is_rdma_needed = 0;
++
++      if (pdp_surface->src_data.type != DLA_MEM_HW)
++              group->is_rdma_needed = 1;
++}
++
++static int
++validate_strides(uint8_t stride_x, uint8_t stride_y)
++{
++      int32_t ret = 0;
++
++      if (stride_x < 1 || stride_y < 1 || stride_x > 8 || stride_y > 8) {
++              dla_error("Invalid Stride (x[%d], y[%d])\n", stride_x, stride_y);
++              ret = ERR(INVALID_INPUT);
++      }
++
++      RETURN(ret);
++}
++
++static int
++vaildate_pdp_configs(struct dla_processor_group *group)
++{
++      int32_t ret = 0;
++      struct dla_pdp_op_desc *pdp_op;
++      struct dla_pdp_surface_desc *pdp_surface;
++
++      dla_trace("Enter: %s", __func__);
++
++      pdp_op = &group->operation_desc->pdp_op;
++      pdp_surface = &group->surface_desc->pdp_surface;
++
++      if (pdp_surface->dst_data.type == DLA_MEM_HW) {
++              dla_error("Destination buffer for PDP has to be either MC or CV");
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      ret = validate_data_cube(pdp_surface->src_data, pdp_surface->dst_data,
++                                                              DLA_MEM_HW);
++      if (ret)
++              goto exit;
++
++      ret = validate_precision(pdp_op->precision, ARRAY_SIZE(map_precision));
++      if (ret)
++              goto exit;
++
++      ret = validate_strides(pdp_op->stride_x, pdp_op->stride_y);
++      if (ret)
++              goto exit;
++
++      if (pdp_op->split_num > MAX_SPLIT_NUM) {
++              dla_error("Invalid split_num: %u\n", pdp_op->split_num);
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      if (pdp_op->pool_width >= ARRAY_SIZE(map_pool_kernel)) {
++              dla_error("Invalid pool_width: %u\n", pdp_op->pool_width);
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      if (pdp_op->pool_height >= ARRAY_SIZE(map_pool_kernel)) {
++              dla_error("Invalid pool_height: %u\n", pdp_op->pool_height);
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      if (pdp_op->pool_mode >= ARRAY_SIZE(map_pool)) {
++              dla_error("Invalid pool_mode: %u\n", pdp_op->pool_mode);
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
++
++static int
++processor_pdp_program(struct dla_processor_group *group)
++{
++      int32_t ret = 0;
++      uint32_t reg, high, low;
++      uint64_t input_address = 0;
++      uint64_t output_address = 0;
++      struct dla_engine *engine = dla_get_engine();
++      struct dla_pdp_op_desc *pdp_op;
++      struct dla_pdp_surface_desc *pdp_surface;
++
++      dla_trace("Enter: %s", __func__);
++
++      pdp_op = &group->operation_desc->pdp_op;
++      pdp_surface = &group->surface_desc->pdp_surface;
++
++      ret = vaildate_pdp_configs(group);
++      if (ret)
++              goto exit;
++
++      ret = dla_read_input_address(&pdp_surface->src_data,
++                                      &input_address,
++                                      group->op_desc->index,
++                                      group->roi_index,
++                                      1);
++      if (ret)
++              goto exit;
++
++      if (pdp_surface->dst_data.address != -1)
++              dla_get_dma_cube_address(engine->driver_context,
++                                      engine->task->task_data,
++                                      pdp_surface->dst_data.address,
++                                      pdp_surface->dst_data.offset,
++                                      (void *)&output_address,
++                                      DESTINATION_DMA);
++
++      if (pdp_surface->src_data.type != DLA_MEM_HW) {
++              /* PDP RDMA */
++              pdp_rdma_reg_write(D_DATA_CUBE_IN_WIDTH,
++                              pdp_surface->src_data.width - 1);
++              pdp_rdma_reg_write(D_DATA_CUBE_IN_HEIGHT,
++                              pdp_surface->src_data.height - 1);
++              pdp_rdma_reg_write(D_DATA_CUBE_IN_CHANNEL,
++                              pdp_surface->src_data.channel - 1);
++
++              high = HIGH32BITS(input_address);
++              low  = LOW32BITS(input_address);
++              pdp_rdma_reg_write(D_SRC_BASE_ADDR_HIGH, high);
++              pdp_rdma_reg_write(D_SRC_BASE_ADDR_LOW, low);
++              pdp_rdma_reg_write(D_SRC_LINE_STRIDE,
++                              pdp_surface->src_data.line_stride);
++              pdp_rdma_reg_write(D_SRC_SURFACE_STRIDE,
++                              pdp_surface->src_data.surf_stride);
++
++              reg = (map_precision[pdp_op->precision]
++                      << SHIFT(PDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA));
++              pdp_rdma_reg_write(D_DATA_FORMAT, reg);
++
++              reg = map_ram[pdp_surface->src_data.type]
++                      << SHIFT(PDP_RDMA_D_SRC_RAM_CFG_0, SRC_RAM_TYPE);
++              pdp_rdma_reg_write(D_SRC_RAM_CFG, reg);
++
++              reg = ((pdp_op->split_num - 1)
++                       << SHIFT(PDP_RDMA_D_OPERATION_MODE_CFG_0, SPLIT_NUM));
++              pdp_rdma_reg_write(D_OPERATION_MODE_CFG, reg);
++
++              reg = (map_pool_kernel[pdp_op->pool_width]
++                      << SHIFT(PDP_RDMA_D_POOLING_KERNEL_CFG_0,
++                                                      KERNEL_WIDTH)) |
++                      ((pdp_op->stride_x - 1)
++                      << SHIFT(PDP_RDMA_D_POOLING_KERNEL_CFG_0,
++                                                      KERNEL_STRIDE_WIDTH));
++              pdp_rdma_reg_write(D_POOLING_KERNEL_CFG, reg);
++
++              reg = (pdp_op->pad_left
++                      << SHIFT(PDP_RDMA_D_POOLING_PADDING_CFG_0, PAD_WIDTH));
++              pdp_rdma_reg_write(D_POOLING_PADDING_CFG, reg);
++
++              reg = ((pdp_op->partial_in_width_first == 0 ? 0 :
++                              pdp_op->partial_in_width_first - 1)
++                      << SHIFT(PDP_RDMA_D_PARTIAL_WIDTH_IN_0,
++                              PARTIAL_WIDTH_IN_FIRST)) |
++                      ((pdp_op->partial_in_width_mid == 0 ? 0 :
++                              pdp_op->partial_in_width_mid - 1)
++                      << SHIFT(PDP_RDMA_D_PARTIAL_WIDTH_IN_0,
++                              PARTIAL_WIDTH_IN_MID)) |
++                      ((pdp_op->partial_in_width_last == 0 ? 0 :
++                              pdp_op->partial_in_width_last - 1)
++                      << SHIFT(PDP_RDMA_D_PARTIAL_WIDTH_IN_0,
++                              PARTIAL_WIDTH_IN_LAST));
++              pdp_rdma_reg_write(D_PARTIAL_WIDTH_IN, reg);
++      } else {
++              ASSERT_GOTO(pdp_op->split_num == 1, ret,
++                                      ERR(INVALID_INPUT), exit);
++      }
++
++      reg = ((pdp_surface->src_data.width - 1)
++              << SHIFT(PDP_D_DATA_CUBE_IN_WIDTH_0, CUBE_IN_WIDTH));
++      pdp_reg_write(D_DATA_CUBE_IN_WIDTH, reg);
++
++      reg = ((pdp_surface->src_data.height - 1)
++              << SHIFT(PDP_D_DATA_CUBE_IN_HEIGHT_0, CUBE_IN_HEIGHT));
++      pdp_reg_write(D_DATA_CUBE_IN_HEIGHT, reg);
++
++      reg = ((pdp_surface->src_data.channel - 1)
++              << SHIFT(PDP_D_DATA_CUBE_IN_CHANNEL_0, CUBE_IN_CHANNEL));
++      pdp_reg_write(D_DATA_CUBE_IN_CHANNEL, reg);
++
++      reg = ((pdp_surface->dst_data.width - 1)
++              << SHIFT(PDP_D_DATA_CUBE_OUT_WIDTH_0, CUBE_OUT_WIDTH));
++      pdp_reg_write(D_DATA_CUBE_OUT_WIDTH, reg);
++
++      reg = ((pdp_surface->dst_data.height - 1)
++              << SHIFT(PDP_D_DATA_CUBE_OUT_HEIGHT_0, CUBE_OUT_HEIGHT));
++      pdp_reg_write(D_DATA_CUBE_OUT_HEIGHT, reg);
++
++      reg = ((pdp_surface->dst_data.channel - 1)
++              << SHIFT(PDP_D_DATA_CUBE_OUT_CHANNEL_0, CUBE_OUT_CHANNEL));
++      pdp_reg_write(D_DATA_CUBE_OUT_CHANNEL, reg);
++
++      reg = (map_pool[pdp_op->pool_mode]
++              << SHIFT(PDP_D_OPERATION_MODE_CFG_0, POOLING_METHOD)) |
++              (get_fly_mode(pdp_surface->src_data.type)
++              << SHIFT(PDP_D_OPERATION_MODE_CFG_0, FLYING_MODE)) |
++              ((pdp_op->split_num - 1)
++              << SHIFT(PDP_D_OPERATION_MODE_CFG_0, SPLIT_NUM));
++      pdp_reg_write(D_OPERATION_MODE_CFG, reg);
++
++      reg = ((pdp_op->partial_in_width_first == 0 ? 0 :
++                      pdp_op->partial_in_width_first-1)
++              << SHIFT(PDP_D_PARTIAL_WIDTH_IN_0, PARTIAL_WIDTH_IN_FIRST)) |
++              ((pdp_op->partial_in_width_mid == 0 ? 0 :
++                      pdp_op->partial_in_width_mid-1)
++              << SHIFT(PDP_D_PARTIAL_WIDTH_IN_0, PARTIAL_WIDTH_IN_MID)) |
++              ((pdp_op->partial_in_width_last == 0 ? 0 :
++                      pdp_op->partial_in_width_last-1)
++              << SHIFT(PDP_D_PARTIAL_WIDTH_IN_0, PARTIAL_WIDTH_IN_LAST));
++      pdp_reg_write(D_PARTIAL_WIDTH_IN, reg);
++
++      reg = ((pdp_op->partial_width_first == 0 ? 0 :
++                      pdp_op->partial_width_first-1)
++              << SHIFT(PDP_D_PARTIAL_WIDTH_OUT_0, PARTIAL_WIDTH_OUT_FIRST)) |
++              ((pdp_op->partial_width_mid == 0 ? 0 :
++                      pdp_op->partial_width_mid-1)
++              << SHIFT(PDP_D_PARTIAL_WIDTH_OUT_0, PARTIAL_WIDTH_OUT_MID))   |
++              ((pdp_op->partial_width_last == 0 ? 0 :
++                      pdp_op->partial_width_last-1)
++              << SHIFT(PDP_D_PARTIAL_WIDTH_OUT_0, PARTIAL_WIDTH_OUT_LAST));
++      pdp_reg_write(D_PARTIAL_WIDTH_OUT, reg);
++
++      reg = (map_pool_kernel[pdp_op->pool_width]
++              << SHIFT(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH)) |
++              (map_pool_kernel[pdp_op->pool_height]
++              << SHIFT(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_HEIGHT))|
++              ((pdp_op->stride_x - 1)
++              << SHIFT(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_STRIDE_WIDTH)) |
++              ((pdp_op->stride_y - 1)
++              << SHIFT(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_STRIDE_HEIGHT));
++      pdp_reg_write(D_POOLING_KERNEL_CFG, reg);
++
++      pdp_reg_write(D_RECIP_KERNEL_WIDTH,
++                      recip_kernel_size[pdp_op->precision ==
++                                      PRECISION_FP16][pdp_op->pool_width]);
++      pdp_reg_write(D_RECIP_KERNEL_HEIGHT,
++                      recip_kernel_size[pdp_op->precision ==
++                                      PRECISION_FP16][pdp_op->pool_height]);
++
++      reg = (pdp_op->pad_left
++              << SHIFT(PDP_D_POOLING_PADDING_CFG_0, PAD_LEFT)) |
++              (pdp_op->pad_right
++              << SHIFT(PDP_D_POOLING_PADDING_CFG_0, PAD_RIGHT)) |
++              (pdp_op->pad_top
++              << SHIFT(PDP_D_POOLING_PADDING_CFG_0, PAD_TOP)) |
++              (pdp_op->pad_bottom
++              << SHIFT(PDP_D_POOLING_PADDING_CFG_0, PAD_BOTTOM));
++      if (pdp_op->precision == PRECISION_FP16) {
++              int32_t i;
++
++              for (i = 0; i < 7; i++)
++                      ASSERT_GOTO(pdp_op->padding_value[i] == 0, ret,
++                                              ERR(INVALID_INPUT), exit);
++      }
++
++      pdp_reg_write(D_POOLING_PADDING_CFG, reg);
++      pdp_reg_write(D_POOLING_PADDING_VALUE_1_CFG, pdp_op->padding_value[0]);
++      pdp_reg_write(D_POOLING_PADDING_VALUE_2_CFG, pdp_op->padding_value[1]);
++      pdp_reg_write(D_POOLING_PADDING_VALUE_3_CFG, pdp_op->padding_value[2]);
++      pdp_reg_write(D_POOLING_PADDING_VALUE_4_CFG, pdp_op->padding_value[3]);
++      pdp_reg_write(D_POOLING_PADDING_VALUE_5_CFG, pdp_op->padding_value[4]);
++      pdp_reg_write(D_POOLING_PADDING_VALUE_6_CFG, pdp_op->padding_value[5]);
++      pdp_reg_write(D_POOLING_PADDING_VALUE_7_CFG, pdp_op->padding_value[6]);
++
++      if (pdp_surface->src_data.type != DLA_MEM_HW) {
++              pdp_reg_write(D_SRC_LINE_STRIDE,
++                              pdp_surface->src_data.line_stride);
++              pdp_reg_write(D_SRC_SURFACE_STRIDE,
++                              pdp_surface->src_data.surf_stride);
++      }
++
++      high = HIGH32BITS(output_address);
++      low = LOW32BITS(output_address);
++      pdp_reg_write(D_DST_BASE_ADDR_LOW, low);
++      pdp_reg_write(D_DST_BASE_ADDR_HIGH, high);
++
++      pdp_reg_write(D_DST_LINE_STRIDE, pdp_surface->dst_data.line_stride);
++      pdp_reg_write(D_DST_SURFACE_STRIDE, pdp_surface->dst_data.surf_stride);
++
++      reg = (map_ram[pdp_surface->dst_data.type]
++              << SHIFT(PDP_D_DST_RAM_CFG_0, DST_RAM_TYPE));
++      pdp_reg_write(D_DST_RAM_CFG, reg);
++
++      reg = (map_precision[pdp_op->precision]
++              << SHIFT(PDP_D_DATA_FORMAT_0, INPUT_DATA));
++      pdp_reg_write(D_DATA_FORMAT, reg);
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
++
++int
++dla_pdp_is_ready(struct dla_processor *processor,
++                         struct dla_processor_group *group)
++{
++      return 1;
++}
++
++void
++dla_pdp_dump_config(struct dla_processor_group *group)
++{
++      struct dla_pdp_op_desc *pdp_op;
++      struct dla_pdp_surface_desc *pdp_surface;
++
++      pdp_surface = &group->surface_desc->pdp_surface;
++      pdp_op = &group->operation_desc->pdp_op;
++
++      dla_debug_pdp_surface_desc(pdp_surface, group->roi_index);
++      dla_debug_pdp_op_desc(pdp_op, group->roi_index);
++}
++
++int
++dla_pdp_program(struct dla_processor_group *group)
++{
++      int32_t ret;
++
++      dla_trace("Enter: %s", __func__);
++
++      if (!group) {
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      dla_enable_intr(MASK(GLB_S_INTR_MASK_0, PDP_DONE_MASK1) |
++                      MASK(GLB_S_INTR_MASK_0, PDP_DONE_MASK0));
++
++      ret = processor_pdp_program(group);
++      if (ret)
++              goto exit;
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
+--- /dev/null
++++ b/drivers/nvdla/rubik.c
+@@ -0,0 +1,292 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_err.h>
++#include <dla_interface.h>
++
++#include "common.h"
++#include "dla_engine_internal.h"
++#include "engine_debug.h"
++
++static uint8_t map_rubik_mode[] = {
++      FIELD_ENUM(RBK_D_MISC_CFG_0, RUBIK_MODE, CONTRACT),
++      FIELD_ENUM(RBK_D_MISC_CFG_0, RUBIK_MODE, SPLIT),
++      FIELD_ENUM(RBK_D_MISC_CFG_0, RUBIK_MODE, MERGE),
++};
++
++static uint8_t  map_ram_type[] = {
++      FIELD_ENUM(RBK_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, MCIF),
++      FIELD_ENUM(RBK_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, CVIF),
++};
++
++static uint8_t  map_precision[] = {
++      FIELD_ENUM(RBK_D_MISC_CFG_0, IN_PRECISION, INT8),
++      FIELD_ENUM(RBK_D_MISC_CFG_0, IN_PRECISION, INT16),
++      FIELD_ENUM(RBK_D_MISC_CFG_0, IN_PRECISION, FP16),
++};
++
++static uint8_t map_bpe[] = {
++      BPE_PRECISION_INT8,
++      BPE_PRECISION_INT16,
++      BPE_PRECISION_FP16,
++};
++
++#if STAT_ENABLE
++void
++dla_rubik_stat_data(struct dla_processor *processor,
++                                      struct dla_processor_group *group)
++{
++      uint64_t end_time = 0;
++      struct dla_rubik_stat_desc *rubik_stat;
++
++      rubik_stat = &processor->stat_data_desc->rubik_stat;
++
++      end_time = dla_get_time_us();
++
++      rubik_stat->read_stall = rubik_reg_read(D_PERF_READ_STALL);
++      rubik_stat->write_stall = rubik_reg_read(D_PERF_WRITE_STALL);
++      rubik_stat->runtime = (uint32_t)(end_time - group->start_time);
++}
++
++void
++dla_rubik_dump_stat(struct dla_processor *processor)
++{
++      struct dla_rubik_stat_desc *rubik_stat;
++
++      rubik_stat = &processor->stat_data_desc->rubik_stat;
++
++      dla_debug_rubik_stats(rubik_stat);
++}
++#endif /* STAT_ENABLE */
++
++void
++dla_rubik_set_producer(int32_t group_id, int32_t __unused)
++{
++      uint32_t reg;
++
++      /**
++       * set producer pointer for all sub-modules
++       */
++      reg = group_id << SHIFT(RBK_S_POINTER_0, PRODUCER);
++      rubik_reg_write(S_POINTER, reg);
++}
++
++int
++dla_rubik_enable(struct dla_processor_group *group)
++{
++      uint32_t reg;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_trace("Enter: %s", __func__);
++
++      if (engine->stat_enable == (uint32_t)1) {
++              rubik_reg_write(D_PERF_ENABLE, 1);
++              group->start_time = dla_get_time_us();
++      }
++
++      /**
++       * enable all sub-modules
++       */
++      reg = FIELD_ENUM(RBK_D_OP_ENABLE_0, OP_EN, ENABLE);
++      rubik_reg_write(D_OP_ENABLE, reg);
++
++      dla_trace("Exit: %s", __func__);
++
++      RETURN(0);
++}
++
++void
++dla_rubik_rdma_check(struct dla_processor_group *group)
++{
++      group->is_rdma_needed = 0;
++}
++
++static int32_t
++processor_rubik_program(struct dla_processor_group *group)
++{
++      int32_t ret = 0;
++      uint32_t reg, high, low;
++      uint64_t input_address = 0;
++      uint64_t output_address = 0;
++      struct dla_engine *engine = dla_get_engine();
++      struct dla_rubik_op_desc *rubik_op;
++      struct dla_rubik_surface_desc *rubik_surface;
++
++      dla_trace("Enter: %s", __func__);
++
++      rubik_op = &group->operation_desc->rubik_op;
++      rubik_surface = &group->surface_desc->rubik_surface;
++
++      /* Argument check */
++      ASSERT_GOTO((rubik_surface->src_data.type != DLA_MEM_HW),
++              ret, ERR(INVALID_INPUT), exit);
++      ASSERT_GOTO((rubik_surface->dst_data.type != DLA_MEM_HW),
++              ret, ERR(INVALID_INPUT), exit);
++
++      /* get the addresses from task descriptor */
++      ret = dla_read_input_address(&rubik_surface->src_data,
++                                              &input_address,
++                                              group->op_desc->index,
++                                              group->roi_index,
++                                              1);
++      if (ret)
++              goto exit;
++
++      dla_get_dma_cube_address(engine->driver_context,
++                              engine->task->task_data,
++                              rubik_surface->dst_data.address,
++                              rubik_surface->dst_data.offset,
++                              (void *)&output_address,
++                              DESTINATION_DMA);
++
++      /* config rubik */
++      reg = (((uint32_t)map_rubik_mode[rubik_op->mode]) <<
++                      SHIFT(RBK_D_MISC_CFG_0, RUBIK_MODE)) |
++                      (((uint32_t)map_precision[rubik_op->precision]) <<
++                      SHIFT(RBK_D_MISC_CFG_0, IN_PRECISION));
++      rubik_reg_write(D_MISC_CFG, reg);
++      reg = (((uint32_t)map_ram_type[rubik_surface->src_data.type]) <<
++                      SHIFT(RBK_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE));
++      rubik_reg_write(D_DAIN_RAM_TYPE, reg);
++      reg =  ((rubik_surface->src_data.width-1) <<
++                      SHIFT(RBK_D_DATAIN_SIZE_0_0, DATAIN_WIDTH)) |
++                      ((rubik_surface->src_data.height-1) <<
++                      SHIFT(RBK_D_DATAIN_SIZE_0_0, DATAIN_HEIGHT));
++      rubik_reg_write(D_DATAIN_SIZE_0, reg);
++      reg =  ((rubik_surface->src_data.channel-1) <<
++                      SHIFT(RBK_D_DATAIN_SIZE_1_0, DATAIN_CHANNEL));
++      rubik_reg_write(D_DATAIN_SIZE_1, reg);
++
++      high = HIGH32BITS(input_address);
++      low = LOW32BITS(input_address);
++      rubik_reg_write(D_DAIN_ADDR_LOW, low);
++      rubik_reg_write(D_DAIN_ADDR_HIGH, high);
++      if (rubik_op->mode == RUBIK_MODE_MERGE) {
++              ASSERT_GOTO((rubik_surface->src_data.plane_stride != 0),
++                      ret, ERR(INVALID_INPUT), exit);
++              ASSERT_GOTO(((rubik_surface->src_data.plane_stride&0x1F) == 0),
++                      ret, ERR(INVALID_INPUT), exit);
++              rubik_reg_write(D_DAIN_PLANAR_STRIDE,
++                      rubik_surface->src_data.plane_stride);
++      } else {
++              rubik_reg_write(D_DAIN_SURF_STRIDE,
++                      rubik_surface->src_data.surf_stride);
++      }
++      rubik_reg_write(D_DAIN_LINE_STRIDE,
++                              rubik_surface->src_data.line_stride);
++
++      reg = (((uint32_t)map_ram_type[rubik_surface->dst_data.type]) <<
++                      SHIFT(RBK_D_DAOUT_RAM_TYPE_0, DATAOUT_RAM_TYPE));
++      rubik_reg_write(D_DAOUT_RAM_TYPE, reg);
++      reg =  ((rubik_surface->dst_data.channel-1) <<
++                      SHIFT(RBK_D_DATAOUT_SIZE_1_0, DATAOUT_CHANNEL));
++      rubik_reg_write(D_DATAOUT_SIZE_1, reg);
++
++      high = HIGH32BITS(output_address);
++      low = LOW32BITS(output_address);
++      rubik_reg_write(D_DAOUT_ADDR_LOW, low);
++      rubik_reg_write(D_DAOUT_ADDR_HIGH, high);
++
++      rubik_reg_write(D_DAOUT_LINE_STRIDE,
++                      rubik_surface->dst_data.line_stride);
++      if (rubik_op->mode != RUBIK_MODE_SPLIT) {
++              rubik_reg_write(D_DAOUT_SURF_STRIDE,
++                              rubik_surface->dst_data.surf_stride);
++              if (rubik_op->mode == RUBIK_MODE_CONTRACT) {
++                      reg = ((rubik_surface->dst_data.channel *
++                              map_bpe[rubik_op->precision] + 31) >> 5) *
++                              rubik_surface->src_data.surf_stride;
++                      rubik_reg_write(D_CONTRACT_STRIDE_0, reg);
++
++                      reg = rubik_op->stride_y *
++                              rubik_surface->dst_data.line_stride;
++                      rubik_reg_write(D_CONTRACT_STRIDE_1, reg);
++
++                      reg = (((uint32_t)(rubik_op->stride_x-1)) <<
++                      SHIFT(RBK_D_DECONV_STRIDE_0, DECONV_X_STRIDE)) |
++                              (((uint32_t)(rubik_op->stride_y-1)) <<
++                      SHIFT(RBK_D_DECONV_STRIDE_0, DECONV_Y_STRIDE));
++                      rubik_reg_write(D_DECONV_STRIDE, reg);
++              }
++      } else {
++              rubik_reg_write(D_DAOUT_PLANAR_STRIDE,
++                              rubik_surface->dst_data.plane_stride);
++      }
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
++
++int
++dla_rubik_is_ready(struct dla_processor *processor,
++                           struct dla_processor_group *group)
++{
++      return 1;
++}
++
++void
++dla_rubik_dump_config(struct dla_processor_group *group)
++{
++      struct dla_rubik_op_desc *rubik_op;
++      struct dla_rubik_surface_desc *rubik_surface;
++
++      rubik_surface = &group->surface_desc->rubik_surface;
++      rubik_op = &group->operation_desc->rubik_op;
++
++      dla_debug_rubik_surface_desc(rubik_surface, group->roi_index);
++      dla_debug_rubik_op_desc(rubik_op, group->roi_index);
++}
++
++int
++dla_rubik_program(struct dla_processor_group *group)
++{
++      int32_t ret = 0;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_trace("Enter: %s", __func__);
++
++      if (!engine->config_data->rubik_enable) {
++              dla_error("RUBIK is not supported for this configuration\n");
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      dla_enable_intr(MASK(GLB_S_INTR_MASK_0, RUBIK_DONE_MASK1) |
++                      MASK(GLB_S_INTR_MASK_0, RUBIK_DONE_MASK0));
++
++      ret = processor_rubik_program(group);
++      if (ret)
++              goto exit;
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
+--- /dev/null
++++ b/drivers/nvdla/scheduler.c
+@@ -0,0 +1,1160 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_engine.h>
++#include <dla_err.h>
++#include <dla_interface.h>
++
++#include "dla_engine_internal.h"
++#include "engine_debug.h"
++
++#define MAX_NUM_ADDRESSES     256
++
++static uint64_t roi_array_length __aligned(8);
++static struct dla_network_desc network;
++
++static int
++dla_update_consumers(struct dla_processor_group *group,
++                      struct dla_common_op_desc *op, uint8_t event);
++
++static int32_t
++dla_read_address_list(struct dla_engine *engine)
++{
++      RETURN(0);
++}
++
++int32_t
++dla_read_lut(struct dla_engine *engine, int16_t index, void *dst)
++{
++      int32_t ret = 0;
++      uint64_t src_addr;
++
++      if (index == -1) {
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      src_addr = engine->task->lut_data_addr;
++
++      ret = dla_data_read(engine->driver_context,
++                      engine->task->task_data,
++                      src_addr, (void *)dst,
++                      sizeof(struct dla_lut_param),
++                      (sizeof(struct dla_lut_param) * (uint64_t)index));
++
++exit:
++      RETURN(ret);
++}
++
++static int
++dla_op_enabled(struct dla_processor_group *group)
++{
++      int32_t ret;
++      struct dla_common_op_desc *op_desc;
++
++      dla_debug("Enter: %s\n", __func__);
++      op_desc = group->op_desc;
++
++      group->active = 1;
++
++      /* update dependency graph for this task */
++      ret = dla_update_consumers(group, op_desc, DLA_EVENT_OP_ENABLED);
++      dla_debug("Exit: %s\n", __func__);
++
++      RETURN(ret);
++}
++
++static int
++dla_op_programmed(struct dla_processor *processor,
++                struct dla_processor_group *group,
++                uint8_t rdma_id)
++{
++      int32_t ret;
++      struct dla_common_op_desc *op_desc;
++
++      dla_debug("Enter: %s\n", __func__);
++      op_desc = group->op_desc;
++
++      group->pending = 0;
++
++      /* update dependency graph for this task */
++      ret = dla_update_consumers(group, op_desc, DLA_EVENT_OP_PROGRAMMED);
++      dla_debug("Exit: %s\n", __func__);
++
++      RETURN(ret);
++}
++
++static int32_t
++dla_read_config(struct dla_task *task, struct dla_processor *processor,
++                                      struct dla_processor_group *group)
++{
++      int32_t ret;
++      uint64_t base;
++      int16_t index;
++      uint8_t roi_index;
++      struct dla_engine *engine;
++
++      dla_debug("Enter: %s\n", __func__);
++
++      engine = dla_get_engine();
++
++      roi_index = group->roi_index;
++      index = group->op_desc->index;
++
++      base = (sizeof(union dla_operation_container) *
++                      (uint64_t)engine->network->num_operations *
++                      (uint64_t)roi_index);
++      base = base + (sizeof(union dla_operation_container) *
++                      (uint64_t)index);
++
++      LOG_EVENT(roi_index, group->id, processor->op_type,
++                                      LOG_READ_OP_CONFIG_START);
++
++      ret = dla_data_read(engine->driver_context, task->task_data,
++                              task->operation_desc_addr,
++                              (void *)group->operation_desc,
++                              sizeof(union dla_operation_container),
++                              base);
++      if (ret)
++              goto exit;
++
++      LOG_EVENT(roi_index, group->id, processor->op_type,
++                                      LOG_READ_OP_CONFIG_END);
++
++      base = (sizeof(union dla_surface_container) *
++                      (uint64_t)engine->network->num_operations *
++                      (uint64_t)roi_index);
++
++      base = base + (sizeof(union dla_surface_container) *
++                      (uint64_t)index);
++
++      LOG_EVENT(roi_index, group->id, processor->op_type,
++                                      LOG_READ_SURF_CONFIG_START);
++
++      ret = dla_data_read(engine->driver_context, task->task_data,
++                              task->surface_desc_addr,
++                              (void *)group->surface_desc,
++                              sizeof(union dla_surface_container), base);
++      if (ret)
++              goto exit;
++
++      LOG_EVENT(roi_index, group->id, processor->op_type,
++                                      LOG_READ_SURF_CONFIG_END);
++
++      processor->dump_config(group);
++
++exit:
++      dla_debug("Exit: %s\n", __func__);
++      RETURN(ret);
++}
++
++static void
++dla_reset_group(struct dla_processor_group *group)
++{
++      int32_t i;
++
++      for (i = 0; i < DLA_OP_NUM; i++) {
++              dla_put_op_desc(group->consumers[i]);
++              group->consumers[i] = NULL;
++      }
++
++      dla_put_op_desc(group->fused_parent);
++      group->fused_parent = NULL;
++
++      dla_put_op_desc(group->op_desc);
++      group->op_desc = NULL;
++}
++
++static int
++dla_prepare_operation(struct dla_processor *processor,
++                      struct dla_common_op_desc *op_desc,
++                      uint8_t roi_index, uint32_t *group_number)
++{
++      int32_t ret = 0;
++      uint8_t group_id;
++      uint8_t rdma_id;
++      struct dla_processor_group *group;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_debug("Enter: %s\n", __func__);
++
++      /*
++       * If not already programmed then find out if
++       * processor is free and which group is free
++       */
++      ret = utils_get_free_group(processor, &group_id, &rdma_id);
++      if (ret) {
++              dla_debug("processor:%s register groups are busy\n",
++                      processor->name);
++              goto exit;
++      } else {
++              dla_info("processor:%s group:%d, rdma_group:%d available\n",
++                              processor->name, group_id, rdma_id);
++      }
++      *group_number = group_id;
++      group = &processor->groups[group_id];
++
++      /*
++       * update operation descriptor
++       */
++      group->op_desc = op_desc;
++      dla_get_refcount(op_desc);
++      group->id = group_id;
++      group->roi_index = roi_index;
++      group->rdma_id = rdma_id;
++
++      ret = dla_read_config(engine->task, processor, group);
++      if (ret)
++              goto exit;
++
++      group->pending = 1;
++
++      processor->group_status |= (1 << group->id);
++
++      processor->rdma_check(group);
++      if (group->is_rdma_needed) {
++              group->rdma_id = rdma_id;
++              processor->rdma_status |= (1 << rdma_id);
++      }
++
++      processor->tail_op = op_desc;
++exit:
++      dla_debug("Exit: %s status=%d\n", __func__, ret);
++      RETURN(ret);
++}
++
++static int
++dla_program_operation(struct dla_processor *processor,
++                      struct dla_processor_group *group)
++{
++      int32_t i;
++      int32_t ret = 0;
++      struct dla_common_op_desc *op_desc;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_debug("Enter: %s\n", __func__);
++
++      dla_info("Program %s operation index %d ROI %d Group[%d]\n",
++                                      processor->name,
++                                      group->op_desc->index,
++                                      group->roi_index,
++                                      group->id);
++
++      group->programming = 1;
++
++      op_desc = group->op_desc;
++
++      processor->set_producer(group->id, group->rdma_id);
++
++      LOG_EVENT(group->roi_index, group->id, processor->op_type,
++                                              LOG_PROGRAM_START);
++
++      ret = processor->program(group);
++      if (ret)
++              goto exit;
++
++      LOG_EVENT(group->roi_index, group->id, processor->op_type,
++                                              LOG_PROGRAM_END);
++
++      /**
++       * Pre-fetch consumers
++       */
++      for (i = 0; i < DLA_OP_NUM; i++) {
++              group->consumers[i] = dla_get_op_desc(engine->task,
++                                      op_desc->consumers[i].index, i,
++                                      group->roi_index);
++      }
++
++      group->fused_parent = dla_get_op_desc(engine->task,
++                                      op_desc->fused_parent.index,
++                                      op_desc->op_type - 1,
++                                      group->roi_index);
++
++      if (group->fused_parent != NULL) {
++              if (group->fused_parent->op_type != (op_desc->op_type - 1)) {
++                      dla_warn("Invalid fused op type");
++                      ret = ERR(INVALID_INPUT);
++                      goto exit;
++              }
++      }
++
++      ret = dla_op_programmed(processor, group, group->rdma_id);
++      if (!ret)
++              goto exit;
++
++exit:
++      group->programming = 0;
++      dla_debug("Exit: %s status=%d\n", __func__, ret);
++      RETURN(ret);
++}
++
++static int
++dla_enable_operation(struct dla_processor *processor,
++                      struct dla_common_op_desc *op_desc)
++{
++      int32_t ret = 0;
++      int32_t group_id;
++      struct dla_engine *engine;
++      struct dla_processor_group *group;
++
++      dla_debug("Enter: %s\n", __func__);
++      assert(op_desc->dependency_count == 0);
++
++      /**
++       * If some operation has reported error then skip
++       * enabling next operations
++       */
++      engine = dla_get_engine();
++      if (engine->status)
++              goto exit;
++
++      /**
++       * Find out if operation is already programmed
++       */
++      group_id = 0;
++      group = &processor->groups[group_id];
++      if ((processor->group_status & (1 << group_id)) &&
++                      group->op_desc->index == op_desc->index &&
++                      group->roi_index == op_desc->roi_index &&
++                      !group->pending)
++              goto enable_op;
++
++      group_id = 1;
++      group = &processor->groups[group_id];
++      if ((processor->group_status & (1 << group_id)) &&
++                      group->op_desc->index == op_desc->index &&
++                      group->roi_index == op_desc->roi_index &&
++                      !group->pending)
++              goto enable_op;
++
++      /**
++       * Operation is not programmed yet, ignore
++       */
++      dla_debug("exit %s without actual enable due to processor "
++                              "hasn't been programmed\n", __func__);
++      goto exit;
++
++enable_op:
++      /**
++       * If this event is triggered as part of programming same
++       * group then skip enable, it will get enabled after programming
++       * is complete
++       */
++      if (group->programming)
++              goto exit;
++
++      if (group->active) {
++              dla_debug("Processor:%s already enabled on group:%d\n",
++                      processor->name, group_id);
++              goto exit;
++      }
++
++      dla_info("Enable %s operation index %d ROI %d\n",
++                                      processor->name,
++                                      group->op_desc->index,
++                                      group->roi_index);
++
++      processor->set_producer(group->id, group->rdma_id);
++
++      LOG_EVENT(group->roi_index, group->id, processor->op_type,
++                                              LOG_OPERATION_START);
++
++      ret = processor->enable(group);
++      if (ret)
++              goto exit;
++
++      ret = dla_op_enabled(group);
++exit:
++      dla_debug("Exit: %s status=%d\n", __func__, ret);
++      RETURN(ret);
++}
++
++static int
++dla_submit_operation(struct dla_processor *processor,
++                      struct dla_common_op_desc *op_desc,
++                      uint8_t roi_index)
++{
++      int32_t err;
++      uint32_t group_id = 0;
++
++      dla_debug("Enter: %s\n", __func__);
++
++      dla_info("Prepare %s operation index %d ROI %d dep_count %d\n",
++                      processor->name, op_desc->index, roi_index,
++                      op_desc->dependency_count);
++      err = dla_prepare_operation(processor, op_desc, roi_index, &group_id);
++      if (err)
++              goto exit;
++
++      if (!processor->is_ready(processor, &processor->groups[group_id]))
++              goto exit;
++
++      err = dla_program_operation(processor, &processor->groups[group_id]);
++      if (err)
++              goto exit;
++
++      if (op_desc->dependency_count == 0)
++              err = dla_enable_operation(processor, op_desc);
++
++exit:
++      dla_debug("Exit: %s\n", __func__);
++      RETURN(err);
++}
++
++/**
++ * Dequeue next operation of same type from list of operations
++ */
++static int32_t
++dla_dequeue_operation(struct dla_engine *engine,
++                      struct dla_processor *processor)
++{
++      int32_t ret = 0;
++      int16_t index;
++      struct dla_common_op_desc *consumer;
++
++      dla_debug("Enter: %s\n", __func__);
++
++      if (engine->status) {
++              dla_debug("Skip dequeue op as engine has reported error\n");
++              goto exit;
++      }
++
++      /**
++       * If we are done processing all ROIs for current op then
++       * load next op of same type otherwise reload same op for
++       * next ROI.
++       */
++      if (processor->roi_index == (engine->network->num_rois - 1)) {
++              index = processor->tail_op->consumers[processor->op_type].index;
++              if (-1 == index) {
++                      /**
++                       * It means we are done processing
++                       * all ops of this type
++                       */
++                      dla_debug("exit %s as there's no further operation\n",
++                              processor->name);
++                      goto exit;
++              }
++              processor->roi_index = 0;
++      } else {
++              processor->roi_index++;
++              index = processor->tail_op->index;
++      }
++
++      dla_debug("Dequeue op from %s processor, index=%d ROI=%d\n",
++                      processor->name, index, processor->roi_index);
++
++      /**
++       * Get operation descriptor
++       */
++      consumer = dla_get_op_desc(engine->task, index,
++                              processor->op_type, processor->roi_index);
++      if (consumer == NULL) {
++              ret = ERR(NO_MEM);
++              dla_error("Failed to allocate op_desc");
++              goto exit;
++      }
++
++      ret = dla_submit_operation(processor, consumer, processor->roi_index);
++      dla_put_op_desc(consumer);
++
++exit:
++      dla_debug("Exit: %s\n", __func__);
++      RETURN(ret);
++}
++
++static int
++dla_update_dependency(struct dla_consumer *consumer,
++                      struct dla_common_op_desc *op_desc,
++                      uint8_t event, uint8_t roi_index)
++{
++      int32_t ret = 0;
++      struct dla_processor *processor;
++      struct dla_engine *engine = dla_get_engine();
++
++      if (consumer->index == -1)
++              goto exit;
++
++      /* Update dependency only if event matches */
++      if (event != consumer->event)
++              goto exit;
++
++      /**
++       * If consumer index is valid but op desc is NULL means
++       * op desc for consumer was not pre-fetched
++       */
++      if (op_desc == NULL) {
++              ret = ERR(INVALID_INPUT);
++              dla_error("Operation descriptor is NULL, consumer index %d",
++                              consumer->index);
++              goto exit;
++      }
++
++      assert(op_desc->dependency_count > 0);
++
++      dla_debug("Update dependency operation index %d ROI %d DEP_COUNT=%d\n",
++                                      op_desc->index, op_desc->roi_index,
++                                      op_desc->dependency_count);
++      op_desc->dependency_count--;
++
++      if (op_desc->dependency_count == 0) {
++              processor = &engine->processors[op_desc->op_type];
++              dla_debug("enable %s in %s as depdency are resolved\n",
++                      processor->name, __func__);
++
++              ret = dla_enable_operation(processor, op_desc);
++              if (ret)
++                      goto exit;
++      }
++exit:
++      RETURN(ret);
++}
++
++static int
++dla_update_consumers(struct dla_processor_group *group,
++                   struct dla_common_op_desc *op,
++                   uint8_t event)
++{
++      int32_t i;
++      int32_t ret = 0;
++      struct dla_engine *engine = dla_get_engine();
++
++      if (engine->status) {
++              dla_debug("Skip update as engine has reported error\n");
++              goto exit;
++      }
++
++      for (i = 0; i < DLA_OP_NUM; i++) {
++              ret = dla_update_dependency(&op->consumers[i],
++                                              group->consumers[i],
++                                              event, group->roi_index);
++              if (ret) {
++                      dla_error("Failed to update dependency for "
++                              "consumer %d, ROI %d", i, group->roi_index);
++                      goto exit;
++              }
++      }
++
++      ret = dla_update_dependency(&op->fused_parent,
++                                      group->fused_parent,
++                                      event, group->roi_index);
++      if (ret) {
++              dla_error("Failed to update dependency for "
++                      "fused parent, ROI %d", group->roi_index);
++              goto exit;
++      }
++
++exit:
++      RETURN(ret);
++}
++
++/**
++ * Handle operation completion notification
++ */
++int
++dla_op_completion(struct dla_processor *processor,
++                struct dla_processor_group *group)
++{
++      int32_t ret;
++#if STAT_ENABLE
++      uint64_t stat_data_address;
++      uint64_t stat_base;
++#endif /* STAT_ENABLE */
++      struct dla_task *task;
++      struct dla_common_op_desc *op_desc;
++      struct dla_processor_group *next_group;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_debug("Enter:%s processor %s group%u\n", __func__,
++                                      processor->name, group->id);
++
++      dla_info("Completed %s operation index %d ROI %d\n",
++                                      processor->name,
++                                      group->op_desc->index,
++                                      group->roi_index);
++
++      task = engine->task;
++
++      /**
++       * Mark OP as done only when all ROIs are done for that
++       * operation
++       */
++      if (group->roi_index == (engine->network->num_rois - 1))
++              engine->num_proc_hwl++;
++
++      op_desc = group->op_desc;
++
++#if STAT_ENABLE
++      if (engine->stat_enable == (uint32_t)1) {
++              processor->get_stat_data(processor, group);
++
++              processor->dump_stat(processor);
++
++              stat_data_address = (uint64_t)(engine->task->stat_data_addr +
++                              (sizeof(union dla_stat_container) *
++                              (uint64_t)(engine->network->num_operations) *
++                              (uint64_t)(op_desc->roi_index)));
++
++              stat_base = (stat_data_address +
++                              (sizeof(union dla_stat_container) *
++                              (uint64_t)op_desc->index));
++
++              /**
++               * Flush stat descriptor to DRAM
++               */
++              ret = dla_data_write(engine->driver_context, task->task_data,
++                                      (void *)(processor->stat_data_desc),
++                                      stat_base,
++                                      sizeof(union dla_stat_container),
++                                      0);
++              if (ret < 0)
++                      dla_error("Failed to write stats to DMA memory\n");
++      }
++#endif /* STAT_ENABLE */
++
++      /**
++       * Get an extra reference count to keep op descriptor
++       * in cache until this operation completes
++       */
++      dla_get_refcount(op_desc);
++
++      LOG_EVENT(group->roi_index, group->id, processor->op_type,
++                                              LOG_OPERATION_END);
++
++      processor->group_status &= ~(1 << group->id);
++      if (group->is_rdma_needed) {
++              group->is_rdma_needed = 0;
++              processor->rdma_status &= ~(1 << group->rdma_id);
++              group->rdma_id = 0;
++      }
++      group->active = 0;
++      group->lut_index = -1;
++      processor->last_group = group->id;
++
++      /**
++       * Switch consumer pointer to next group
++       */
++      processor->consumer_ptr = !group->id;
++
++      /**
++       * update dependency graph for this task
++       * TODO: Add proper error handling
++       */
++      ret = dla_update_consumers(group, op_desc, DLA_EVENT_OP_COMPLETED);
++      if (ret)
++              goto exit;
++
++      dla_info("%d HWLs done, totally %d layers\n",
++                              engine->num_proc_hwl,
++                              engine->network->num_operations);
++
++      /* free operation descriptor from cache */
++      dla_reset_group(group);
++
++      /* if not hwl pending, means network completed */
++      if (engine->network->num_operations == engine->num_proc_hwl) {
++              dla_put_op_desc(op_desc);
++              goto exit;
++      }
++
++      next_group = &processor->groups[!group->id];
++      if (next_group->pending && !engine->status) {
++              /**
++               * Next group must be ready here for programming,
++               * if not means it is an error
++               */
++              if (!processor->is_ready(processor, next_group))
++                      goto dequeue_op;
++
++              ret = dla_program_operation(processor, next_group);
++              if (ret)
++                      goto exit;
++
++              if (next_group->op_desc->dependency_count != 0)
++                      goto dequeue_op;
++
++              ret = dla_enable_operation(processor,
++                                         next_group->op_desc);
++              if (ret)
++                      goto exit;
++      }
++
++dequeue_op:
++      /* dequeue operation from this processor */
++      ret = dla_dequeue_operation(engine, processor);
++
++exit:
++      dla_put_op_desc(op_desc);
++      dla_debug("Exit:%s processor %s group%u status=%d\n",
++                              __func__, processor->name,
++                              group->id, ret);
++
++      RETURN(ret);
++}
++
++/**
++ * Read network configuration from DRAM, network descriptor address
++ * is always first in the address list. Network configuration contains
++ * offset in address list for addresses of other lists used to
++ * execute network
++ *
++ * @engine: Engine instance
++ * @return: 0 for success
++ */
++static int
++dla_read_network_config(struct dla_engine *engine)
++{
++      int32_t ret;
++      uint64_t network_addr;
++      struct dla_task *task = engine->task;
++
++      dla_debug("Enter:%s\n", __func__);
++
++      /**
++       * Read address list from DRAM to DMEM
++       */
++      ret = dla_read_address_list(engine);
++      if (ret) {
++              dla_error("Failed to read address list");
++              goto exit;
++      }
++
++      /**
++       * Read network descriptor address from address list. It is always
++       * at index 0.
++       */
++      ret = dla_get_dma_address(engine->driver_context, task->task_data,
++                                              0, (void *)&network_addr,
++                                              DESTINATION_PROCESSOR);
++      if (ret) {
++              dla_error("Failed to read network desc address");
++              goto exit;
++      }
++
++      /**
++       * Read network descriptor, it has information for a network
++       * such as all address indexes.
++       */
++      ret = dla_data_read(engine->driver_context, task->task_data,
++                              network_addr, (void *)&network,
++                              sizeof(struct dla_network_desc),
++                              0);
++      if (ret) {
++              dla_error("Failed to read network descriptor");
++              goto exit;
++      }
++
++      dla_debug_network_desc(&network);
++
++      if (network.num_operations == 0)
++              goto exit;
++
++      /**
++       * Read operation descriptor list address from address list
++       */
++      ret = dla_get_dma_address(engine->driver_context, task->task_data,
++                              network.operation_desc_index,
++                              (void *)&task->operation_desc_addr,
++                              DESTINATION_PROCESSOR);
++      if (ret) {
++              dla_error("Failed to read operation desc list address");
++              goto exit;
++      }
++
++      /**
++       * Read surface descriptor list address from address list
++       */
++      ret = dla_get_dma_address(engine->driver_context, task->task_data,
++                              network.surface_desc_index,
++                              (void *)&task->surface_desc_addr,
++                              DESTINATION_PROCESSOR);
++      if (ret) {
++              dla_error("Failed to read surface desc list address");
++              goto exit;
++      }
++
++      /**
++       * Read dependency graph address from address list
++       */
++      ret = dla_get_dma_address(engine->driver_context, task->task_data,
++                              network.dependency_graph_index,
++                              (void *)&task->dependency_graph_addr,
++                              DESTINATION_PROCESSOR);
++      if (ret) {
++              dla_error("Failed to ready dependency graph address");
++              goto exit;
++      }
++
++      /**
++       * Read LUT data list address from address list
++       */
++      if (network.num_luts) {
++              ret = dla_get_dma_address(engine->driver_context,
++                                      task->task_data,
++                                      network.lut_data_index,
++                                      (void *)&task->lut_data_addr,
++                                      DESTINATION_PROCESSOR);
++              if (ret) {
++                      dla_error("Failed to read LUT list address");
++                      goto exit;
++              }
++      }
++
++      /**
++       * Read address for ROI information
++       */
++      if (network.dynamic_roi) {
++              /**
++               * Read ROI array address from address list
++               */
++              ret = dla_get_dma_address(engine->driver_context,
++                                      task->task_data,
++                                      network.roi_array_index,
++                                      (void *)&task->roi_array_addr,
++                                      DESTINATION_PROCESSOR);
++              if (ret) {
++                      dla_error("Failed to read ROI array address");
++                      goto exit;
++              }
++
++              ret = dla_data_read(engine->driver_context, task->task_data,
++                                      task->roi_array_addr,
++                                      (void *)&roi_array_length,
++                                      sizeof(uint64_t),
++                                      0);
++              if (ret) {
++                      dla_error("Failed to read ROI array length");
++                      goto exit;
++              }
++
++              /**
++               * Number of ROIs detected can't be greater than maximum number
++               * ROIs this network can process
++               */
++              if (roi_array_length > network.num_rois) {
++                      dla_error("Invalid number of ROIs detected");
++                      ret = ERR(INVALID_INPUT);
++                      goto exit;
++              }
++
++              network.num_rois = roi_array_length;
++
++              /**
++               * Read surface address from address list
++               */
++              ret = dla_get_dma_address(engine->driver_context,
++                                              task->task_data,
++                                              network.surface_index,
++                                              (void *)&task->surface_addr,
++                                              DESTINATION_DMA);
++              if (ret) {
++                      dla_error("Failed to read surface address");
++                      goto exit;
++              }
++      }
++
++#if STAT_ENABLE
++      if (network.stat_list_index != -1) {
++              ret = dla_get_dma_address(engine->driver_context,
++                                              task->task_data,
++                                              network.stat_list_index,
++                                              (void *)&task->stat_data_addr,
++                                              DESTINATION_PROCESSOR);
++              if (ret) {
++                      dla_error("Failed to read stat address");
++                      goto exit;
++              }
++      }
++#endif /* STAT_ENABLE */
++
++exit:
++      dla_debug("Exit:%s status=%d\n", __func__, ret);
++      RETURN(ret);
++}
++
++static int
++dla_initiate_processors(struct dla_engine *engine)
++{
++      int32_t i;
++      int32_t ret = 0;
++      int16_t index;
++      struct dla_processor *processor;
++      struct dla_common_op_desc *consumer;
++      struct dla_network_desc *nw;
++
++      dla_debug("Enter: %s\n", __func__);
++
++      if (!engine) {
++              ret = ERR(INVALID_INPUT);
++              goto exit;
++      }
++
++      nw = engine->network;
++
++      /* Validate operation heads before initiating processors */
++      for (i = 0; i < DLA_OP_NUM; i++) {
++              if (nw->op_head[i] >= nw->num_operations) {
++                      ret = ERR(INVALID_INPUT);
++                      dla_error("Invalid op_head %d for op %d",
++                                              nw->op_head[i], i);
++                      goto exit;
++              }
++      }
++
++      for (i = 0; i < DLA_OP_NUM; i++) {
++              index = nw->op_head[i];
++
++              /* If there is no op for this type then continue */
++              if (-1 == index)
++                      continue;
++
++              consumer = dla_get_op_desc(engine->task, index, i, 0);
++              /*
++               * if consumer is NULL, it means either data copy error
++               * or cache insufficient - we should fix it
++               **/
++              if (consumer == NULL) {
++                      dla_error("Failed to allocate memory for op_head[%d]=%d",
++                                                      i, index);
++                      ret = ERR(NO_MEM);
++                      goto exit;
++              }
++
++              processor = &engine->processors[consumer->op_type];
++
++              ret = dla_submit_operation(processor, consumer, 0);
++              dla_put_op_desc(consumer);
++              if (ret && ret != ERR(PROCESSOR_BUSY)) {
++                      dla_error("Failed to submit %s op from index %u\n",
++                                              processor->name, index);
++                      goto exit;
++              }
++
++              ret = dla_dequeue_operation(engine, processor);
++              if (ret) {
++                      dla_error("Failed to dequeue op for %s processor",
++                                                      processor->name);
++                      goto exit;
++              }
++      }
++exit:
++      dla_debug("Exit: %s status=%d\n", __func__, ret);
++      RETURN(ret);
++}
++
++static int
++dla_handle_events(struct dla_processor *processor)
++{
++      int32_t j;
++      int32_t ret = 0;
++      uint8_t group_id;
++      struct dla_processor_group *group;
++
++      dla_debug("Enter:%s, processor:%s\n", __func__, processor->name);
++
++      group_id = !processor->last_group;
++
++      for (j = 0; j < DLA_NUM_GROUPS; j++) {
++              group = &processor->groups[group_id];
++
++              if ((1 << DLA_EVENT_CDMA_WT_DONE) & group->events) {
++                      dla_info("Handle cdma weight done event, processor %s "
++                              "group %u\n", processor->name, group->id);
++
++                      ret = dla_update_consumers(group,
++                                                 group->op_desc,
++                                                 DLA_EVENT_CDMA_WT_DONE);
++                      if (ret)
++                              goto exit;
++              }
++
++              if ((1 << DLA_EVENT_CDMA_DT_DONE) & group->events) {
++                      dla_info("Handle cdma data done event, processor %s "
++                              "group %u\n", processor->name, group->id);
++
++                      ret = dla_update_consumers(group,
++                                                 group->op_desc,
++                                                 DLA_EVENT_CDMA_DT_DONE);
++                      if (ret)
++                              goto exit;
++              }
++
++              /**
++               * Handle complete after all other events
++               */
++              if ((1 << DLA_EVENT_OP_COMPLETED) & group->events) {
++                      dla_info("Handle op complete event, processor %s "
++                              "group %u\n", processor->name, group->id);
++
++                      ret = dla_op_completion(processor, group);
++                      if (ret)
++                              goto exit;
++              }
++
++              /**
++               * Clear all events
++               */
++              group->events = 0;
++              group_id = !group_id;
++      }
++exit:
++      dla_debug("Exit:%s, ret:%x\n", __func__, ret);
++      RETURN(ret);
++}
++
++int
++dla_process_events(void *engine_context, uint32_t *task_complete)
++{
++      int32_t i;
++      int32_t ret = 0;
++      struct dla_engine *engine = (struct dla_engine *)engine_context;
++
++      for (i = 0; i < DLA_OP_NUM; i++) {
++              struct dla_processor *processor;
++
++              processor = &engine->processors[i];
++              ret = dla_handle_events(processor);
++              /**
++               * Incase engine status is non-zero, then don't
++               * update the engine status. We should keep its
++               * status for later cleaning of engine.
++               */
++              if (!engine->status)
++                      engine->status = ret;
++      }
++
++      if (engine->network->num_operations == engine->num_proc_hwl)
++              *task_complete = 1;
++
++      RETURN(ret);
++}
++
++/**
++ * Execute task selected by task scheduler
++ *
++ * 1. Read network configuration for the task
++ * 2. Initiate processors with head of list for same op
++ * 3. Start processing events received
++ */
++int
++dla_execute_task(void *engine_context, void *task_data, void *config_data)
++{
++      int32_t ret;
++      struct dla_engine *engine = (struct dla_engine *)engine_context;
++
++      if (engine == NULL) {
++              dla_error("engine is NULL\n");
++              ret = ERR(INVALID_INPUT);
++              goto complete;
++      }
++
++      if (engine->task == NULL) {
++              dla_error("task is NULL\n");
++              ret = ERR(INVALID_INPUT);
++              goto complete;
++      }
++
++      if (engine->task->task_data != NULL) {
++              /* We have on the fly tasks running */
++              dla_warn("Already some task in progress");
++              ret = ERR(PROCESSOR_BUSY);
++              goto complete;
++      }
++
++      engine->task->task_data = task_data;
++      engine->config_data = config_data;
++      engine->network = &network;
++      engine->num_proc_hwl = 0;
++      engine->stat_enable = 0;
++
++      LOG_EVENT(0, 0, 0, LOG_TASK_START);
++
++      ret = dla_read_network_config(engine);
++      if (ret)
++              goto complete;
++
++      dla_debug_address_info(engine->task);
++
++      /**
++       * If no operations in a task means nothing to do, NULL task
++       */
++      if (engine->network->num_operations == 0)
++              goto complete;
++
++#if STAT_ENABLE
++      if (network.stat_list_index != -1)
++              engine->stat_enable = 1;
++#endif /* STAT_ENABLE */
++
++      ret = dla_initiate_processors(engine);
++      engine->status = ret;
++
++complete:
++      LOG_EVENT(0, 0, 0, LOG_TASK_END);
++
++      RETURN(ret);
++}
++
++void
++dla_clear_task(void *engine_context)
++{
++      int32_t i, j;
++      struct dla_engine *engine = (struct dla_engine *)engine_context;
++
++      for (i = 0; i < DLA_OP_NUM; i++) {
++              struct dla_processor *processor = &engine->processors[i];
++
++              processor->roi_index = 0;
++              processor->group_status = 0;
++              processor->rdma_status = 0;
++
++              processor->tail_op = NULL;
++
++              for (j = 0; j < DLA_NUM_GROUPS; j++) {
++                      struct dla_processor_group *group =
++                                              &processor->groups[j];
++
++                      group->rdma_id = group->id;
++                      group->active = 0;
++                      group->events = 0;
++                      group->roi_index = 0;
++                      group->is_rdma_needed = 0;
++                      group->lut_index = -1;
++              }
++      }
++
++      engine->task->task_data = NULL;
++      engine->network = NULL;
++      engine->num_proc_hwl = 0;
++      engine->status = 0;
++      engine->stat_enable = 0;
++
++      dla_info("reset engine done\n");
++}
+--- /dev/null
++++ b/drivers/nvdla/sdp.c
+@@ -0,0 +1,817 @@
++/*
++ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in the
++ *    documentation and/or other materials provided with the distribution.
++ *  * Neither the name of NVIDIA CORPORATION nor the names of its
++ *    contributors may be used to endorse or promote products derived
++ *    from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <opendla.h>
++#include <dla_debug.h>
++#include <dla_interface.h>
++
++#include "common.h"
++#include "dla_engine_internal.h"
++#include "engine_debug.h"
++
++static const uint8_t map_ena[] = {
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DISABLE, YES),
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DISABLE, NO),
++};
++
++static const uint8_t map_prelu[] = {
++      FIELD_ENUM(SDP_D_DP_BS_CFG_0, BS_MUL_PRELU, NO),
++      FIELD_ENUM(SDP_D_DP_BS_CFG_0, BS_MUL_PRELU, YES),
++};
++
++static const uint8_t map_bypass[] = {
++      FIELD_ENUM(SDP_D_DP_BS_CFG_0, BS_BYPASS, YES),
++      FIELD_ENUM(SDP_D_DP_BS_CFG_0, BS_BYPASS, NO),
++};
++
++static const uint8_t map_alu_op[] = {
++      FIELD_ENUM(SDP_D_DP_EW_CFG_0, EW_ALU_ALGO, MAX),
++      FIELD_ENUM(SDP_D_DP_EW_CFG_0, EW_ALU_ALGO, MIN),
++      FIELD_ENUM(SDP_D_DP_EW_CFG_0, EW_ALU_ALGO, SUM),
++      FIELD_ENUM(SDP_D_DP_EW_CFG_0, EW_ALU_ALGO, EQL),
++};
++
++static const uint8_t map_alu_src[] = {
++      FIELD_ENUM(SDP_D_DP_BS_ALU_CFG_0, BS_ALU_SRC, MEM),
++      FIELD_ENUM(SDP_D_DP_BS_ALU_CFG_0, BS_ALU_SRC, REG),
++};
++
++static const uint8_t map_fly[] = {
++      FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, FLYING_MODE, OFF),
++      FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, FLYING_MODE, ON),
++};
++
++static const uint8_t map_dst[] = {
++      FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, OUTPUT_DST, MEM),
++      FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, OUTPUT_DST, PDP),
++};
++
++
++static const uint8_t map_wg[] = {
++      FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, WINOGRAD, OFF),
++      FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, WINOGRAD, ON),
++};
++
++static const uint8_t map_precision[] = {
++      FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
++      FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT16),
++      FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, FP16),
++};
++
++static const uint32_t map_proc_precision[3][3] = {
++      {
++              FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
++              FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
++              FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, FP16),
++      },
++      {
++              FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
++              FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT16),
++              FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, FP16),
++      },
++      {
++              FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
++              FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT16),
++              FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, FP16),
++      },
++};
++
++static const uint8_t map_op_type[] = {
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_USE, MUL),
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_USE, MUL),
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_USE, ALU),
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_USE, BOTH),
++};
++
++static const uint8_t map_element_size[] = {
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_SIZE, ONE_BYTE),
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_SIZE, TWO_BYTE),
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_SIZE, TWO_BYTE),
++};
++
++static const uint8_t map_op_mode[] = {
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_MODE, PER_ELEMENT),
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_MODE, PER_KERNEL),
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_MODE, PER_ELEMENT),
++};
++
++static const uint8_t map_ram_type[] = {
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_RAM_TYPE, MC),
++      FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_RAM_TYPE, CV),
++};
++
++static const uint8_t map_perf_dma[] = {
++      FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_DMA_EN, NO),
++      FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_DMA_EN, YES),
++};
++
++static const uint8_t map_perf_lut[] = {
++      FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_LUT_EN, NO),
++      FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_LUT_EN, YES),
++};
++
++static const uint8_t map_perf_sat[] = {
++      FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_SAT_EN, NO),
++      FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_SAT_EN, YES),
++};
++
++static const uint8_t map_perf_nan_inf[] = {
++      FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_NAN_INF_COUNT_EN, NO),
++      FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_NAN_INF_COUNT_EN, YES),
++};
++
++#if STAT_ENABLE
++void
++dla_sdp_stat_data(struct dla_processor *processor,
++                                      struct dla_processor_group *group)
++{
++      uint64_t end_time = 0;
++      struct dla_sdp_stat_desc *sdp_stat;
++
++      sdp_stat = &processor->stat_data_desc->sdp_stat;
++
++      end_time = dla_get_time_us();
++
++      sdp_stat->nan_input_num = sdp_reg_read(D_STATUS_NAN_INPUT_NUM);
++      sdp_stat->inf_input_num = sdp_reg_read(D_STATUS_INF_INPUT_NUM);
++      sdp_stat->nan_output_num = sdp_reg_read(D_STATUS_NAN_OUTPUT_NUM);
++      sdp_stat->wdma_write_stall = sdp_reg_read(D_PERF_WDMA_WRITE_STALL);
++      sdp_stat->runtime = (uint32_t)(end_time - group->start_time);
++}
++
++void
++dla_sdp_dump_stat(struct dla_processor *processor)
++{
++      struct dla_sdp_stat_desc *sdp_stat;
++
++      sdp_stat = &processor->stat_data_desc->sdp_stat;
++
++      dla_debug_sdp_stats(sdp_stat);
++}
++#endif /* STAT_ENABLE */
++
++void
++dla_sdp_set_producer(int32_t group_id, int32_t rdma_group_id)
++{
++      uint32_t reg;
++
++      /**
++       * set producer pointer for all sub-modules
++       */
++      reg = group_id << SHIFT(SDP_S_POINTER_0, PRODUCER);
++      sdp_reg_write(S_POINTER, reg);
++      reg = rdma_group_id << SHIFT(SDP_RDMA_S_POINTER_0, PRODUCER);
++      sdp_rdma_reg_write(S_POINTER, reg);
++}
++
++int
++dla_sdp_enable(struct dla_processor_group *group)
++{
++      uint32_t reg;
++      uint8_t perf_reg;
++      struct dla_engine *engine = dla_get_engine();
++
++      dla_trace("Enter: %s", __func__);
++
++      if (engine->stat_enable == (uint32_t)1) {
++              perf_reg = (map_perf_dma[1] <<
++                      SHIFT(SDP_D_PERF_ENABLE_0, PERF_DMA_EN)) |
++                      (map_perf_lut[1] <<
++                      SHIFT(SDP_D_PERF_ENABLE_0, PERF_LUT_EN)) |
++                      (map_perf_sat[1] <<
++                      SHIFT(SDP_D_PERF_ENABLE_0, PERF_SAT_EN)) |
++                      (map_perf_nan_inf[1] <<
++                      SHIFT(SDP_D_PERF_ENABLE_0, PERF_NAN_INF_COUNT_EN));
++
++              sdp_reg_write(D_PERF_ENABLE, perf_reg);
++              group->start_time = dla_get_time_us();
++      }
++
++      /**
++       * enable all sub-modules
++       */
++      if (group->is_rdma_needed) {
++              reg = FIELD_ENUM(SDP_RDMA_D_OP_ENABLE_0, OP_EN, ENABLE);
++              sdp_rdma_reg_write(D_OP_ENABLE, reg);
++      }
++      reg = FIELD_ENUM(SDP_D_OP_ENABLE_0, OP_EN, ENABLE);
++      sdp_reg_write(D_OP_ENABLE, reg);
++
++      dla_trace("Exit: %s", __func__);
++
++      RETURN(0);
++}
++
++void
++dla_sdp_rdma_check(struct dla_processor_group *group)
++{
++      uint8_t x1_rdma_ena;
++      uint8_t x2_rdma_ena;
++      uint8_t y_rdma_ena;
++      uint8_t fly;
++      struct dla_sdp_op_desc *sdp_op;
++      struct dla_sdp_surface_desc *sdp_surface;
++
++      sdp_op = &group->operation_desc->sdp_op;
++      sdp_surface = &group->surface_desc->sdp_surface;
++
++      x1_rdma_ena = sdp_op->x1_op.enable;
++      x2_rdma_ena = sdp_op->x2_op.enable;
++      y_rdma_ena  = sdp_op->y_op.enable;
++
++      x1_rdma_ena &= (sdp_op->x1_op.mode != SDP_OP_PER_LAYER);
++      x2_rdma_ena &= (sdp_op->x2_op.mode != SDP_OP_PER_LAYER);
++      y_rdma_ena &= (sdp_op->y_op.mode != SDP_OP_PER_LAYER);
++
++      fly = sdp_surface->src_data.type == DLA_MEM_HW;
++
++      group->is_rdma_needed = (!fly) || (x1_rdma_ena ||
++                                      x2_rdma_ena || y_rdma_ena);
++}
++
++static int32_t
++processor_sdp_program(struct dla_processor_group *group)
++{
++      int32_t ret = 0;
++      uint64_t src_addr = -1, x1_addr = -1, x2_addr = -1;
++      uint64_t  y_addr = -1, dst_addr = -1;
++      uint32_t reg, high, low;
++      uint8_t fly;
++      uint32_t atom_size;
++      struct dla_sdp_op *x1_op;
++      struct dla_sdp_op *x2_op;
++      struct dla_sdp_op *y_op;
++      uint8_t x1_rdma_ena;
++      uint8_t x2_rdma_ena;
++      uint8_t y_rdma_ena;
++      uint8_t out_dma_ena;
++      struct dla_lut_param lut;
++      struct dla_engine *engine = dla_get_engine();
++      struct dla_sdp_op_desc *sdp_op;
++      struct dla_sdp_surface_desc *sdp_surface;
++
++      dla_trace("Enter: %s", __func__);
++      atom_size = engine->config_data->atom_size;
++
++      sdp_op = &group->operation_desc->sdp_op;
++      sdp_surface = &group->surface_desc->sdp_surface;
++
++      fly = sdp_surface->src_data.type == DLA_MEM_HW;
++      out_dma_ena = sdp_surface->dst_data.type != DLA_MEM_HW;
++      x1_op = &sdp_op->x1_op;
++      x2_op = &sdp_op->x2_op;
++      y_op = &sdp_op->y_op;
++      x1_rdma_ena = x1_op->enable && x1_op->type != SDP_OP_NONE;
++      x2_rdma_ena = x2_op->enable && x2_op->type != SDP_OP_NONE;
++      y_rdma_ena  = y_op->enable && y_op->type != SDP_OP_NONE;
++
++      /* load address */
++      if (!fly) {
++              ret = dla_read_input_address(&sdp_surface->src_data,
++                                              &src_addr,
++                                              group->op_desc->index,
++                                              group->roi_index,
++                                          1);
++              if (ret)
++                      goto exit;
++              CHECK_ALIGN(src_addr, atom_size);
++      }
++
++      if (out_dma_ena) {
++              dla_get_dma_cube_address(engine->driver_context,
++                                      engine->task->task_data,
++                                      sdp_surface->dst_data.address,
++                                      sdp_surface->dst_data.offset,
++                                      (void *)&dst_addr,
++                                      DESTINATION_DMA);
++              CHECK_ALIGN(dst_addr, atom_size);
++      }
++
++      if (sdp_op->lut_index >= 0) {
++              group->lut_index = sdp_op->lut_index;
++              dla_read_lut(engine, sdp_op->lut_index, (void *)&lut);
++              dla_debug_lut_params(&lut);
++      }
++
++
++      x1_rdma_ena &= (x1_op->mode != SDP_OP_PER_LAYER);
++      x2_rdma_ena &= (x2_op->mode != SDP_OP_PER_LAYER);
++      y_rdma_ena &= (y_op->mode != SDP_OP_PER_LAYER);
++
++      if (x1_rdma_ena) {
++              dla_get_dma_cube_address(engine->driver_context,
++                                      engine->task->task_data,
++                                      sdp_surface->x1_data.address,
++                                      sdp_surface->x1_data.offset,
++                                      (void *)&x1_addr,
++                                      DESTINATION_DMA);
++              CHECK_ALIGN(x1_addr, atom_size);
++      }
++      if (x2_rdma_ena) {
++              dla_get_dma_cube_address(engine->driver_context,
++                                      engine->task->task_data,
++                                      sdp_surface->x2_data.address,
++                                      sdp_surface->x2_data.offset,
++                                      (void *)&x2_addr,
++                                      DESTINATION_DMA);
++              CHECK_ALIGN(x2_addr, atom_size);
++      }
++      if (y_rdma_ena) {
++              dla_get_dma_cube_address(engine->driver_context,
++                                      engine->task->task_data,
++                                      sdp_surface->y_data.address,
++                                      sdp_surface->y_data.offset,
++                                      (void *)&y_addr,
++                                      DESTINATION_DMA);
++              CHECK_ALIGN(y_addr, atom_size);
++      }
++
++      reg = (map_fly[0] << SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, FLYING_MODE));
++      sdp_rdma_reg_write(D_FEATURE_MODE_CFG, reg);
++
++      reg = (map_ena[1] << SHIFT(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DISABLE));
++      sdp_rdma_reg_write(D_BRDMA_CFG, reg);
++      reg = (map_ena[1] << SHIFT(SDP_RDMA_D_NRDMA_CFG_0, NRDMA_DISABLE));
++      sdp_rdma_reg_write(D_NRDMA_CFG, reg);
++      reg = (map_ena[1] << SHIFT(SDP_RDMA_D_ERDMA_CFG_0, ERDMA_DISABLE));
++      sdp_rdma_reg_write(D_ERDMA_CFG, reg);
++
++      reg = (map_fly[fly] <<
++                      SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, FLYING_MODE)) |
++      (map_wg[sdp_op->conv_mode == CONV_MODE_WINOGRAD] <<
++                      SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, WINOGRAD)) |
++      (map_precision[sdp_op->src_precision] <<
++                      SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION)) |
++      (map_precision[sdp_op->dst_precision] <<
++                      SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, OUT_PRECISION)) |
++      (map_proc_precision[sdp_op->dst_precision][sdp_op->src_precision] <<
++                      SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, PROC_PRECISION)) |
++      ((sdp_op->batch_num-1) <<
++                      SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, BATCH_NUMBER));
++      sdp_rdma_reg_write(D_FEATURE_MODE_CFG, reg);
++
++      if (group->is_rdma_needed) {
++
++              sdp_rdma_reg_write(D_DATA_CUBE_WIDTH,
++                                      sdp_surface->src_data.width - 1);
++              sdp_rdma_reg_write(D_DATA_CUBE_HEIGHT,
++                                      sdp_surface->src_data.height - 1);
++              sdp_rdma_reg_write(D_DATA_CUBE_CHANNEL,
++                                      sdp_surface->src_data.channel - 1);
++
++              /* config SDP source info */
++              if (!fly) {
++                      /**
++                       * if not on-the-fly, we have to config
++                       * the source cube info
++                       */
++                      high = HIGH32BITS(src_addr);
++                      low = LOW32BITS(src_addr);
++                      sdp_rdma_reg_write(D_SRC_BASE_ADDR_LOW, low);
++                      sdp_rdma_reg_write(D_SRC_BASE_ADDR_HIGH, high);
++                      sdp_rdma_reg_write(D_SRC_LINE_STRIDE,
++                                      sdp_surface->src_data.line_stride);
++                      sdp_rdma_reg_write(D_SRC_SURFACE_STRIDE,
++                                      sdp_surface->src_data.surf_stride);
++                      sdp_rdma_reg_write(D_SRC_DMA_CFG,
++                              map_ram_type[sdp_surface->src_data.type]);
++              }
++
++              /* config x1 source info */
++              reg = (map_ena[x1_rdma_ena] <<
++                              SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
++                              BRDMA_DISABLE)) |
++                      (map_op_type[x1_op->type] <<
++                              SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
++                              BRDMA_DATA_USE)) |
++                      (map_element_size[x1_op->precision] <<
++                              SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
++                              BRDMA_DATA_SIZE)) |
++                      (map_op_mode[x1_op->mode] <<
++                              SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
++                              BRDMA_DATA_MODE)) |
++                      (map_ram_type[sdp_surface->x1_data.type] <<
++                              SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
++                              BRDMA_RAM_TYPE));
++              sdp_rdma_reg_write(D_BRDMA_CFG, reg);
++
++              if (x1_rdma_ena) {
++                      high = HIGH32BITS(x1_addr);
++                      low = LOW32BITS(x1_addr);
++                      sdp_rdma_reg_write(D_BS_BASE_ADDR_LOW,
++                                      low);
++                      sdp_rdma_reg_write(D_BS_BASE_ADDR_HIGH,
++                                      high);
++                      sdp_rdma_reg_write(D_BS_LINE_STRIDE,
++                                      sdp_surface->x1_data.line_stride);
++                      sdp_rdma_reg_write(D_BS_SURFACE_STRIDE,
++                                      sdp_surface->x1_data.surf_stride);
++              }
++
++              /* config x2 source info */
++              reg = (map_ena[x2_rdma_ena] <<
++                                      SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
++                                      NRDMA_DISABLE)) |
++                      (map_op_type[x2_op->type] <<
++                                      SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
++                                      NRDMA_DATA_USE)) |
++                      (map_element_size[x2_op->precision] <<
++                                      SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
++                                      NRDMA_DATA_SIZE)) |
++                      (map_op_mode[x2_op->mode] <<
++                                      SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
++                                      NRDMA_DATA_MODE)) |
++                      (map_ram_type[sdp_surface->x2_data.type] <<
++                                      SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
++                                      NRDMA_RAM_TYPE));
++
++              sdp_rdma_reg_write(D_NRDMA_CFG, reg);
++
++              if (x2_rdma_ena) {
++                      high = HIGH32BITS(x2_addr);
++                      low = LOW32BITS(x2_addr);
++                      sdp_rdma_reg_write(D_BN_BASE_ADDR_LOW,
++                                      low);
++                      sdp_rdma_reg_write(D_BN_BASE_ADDR_HIGH,
++                                      high);
++                      sdp_rdma_reg_write(D_BN_LINE_STRIDE,
++                                      sdp_surface->x2_data.line_stride);
++                      sdp_rdma_reg_write(D_BN_SURFACE_STRIDE,
++                                      sdp_surface->x2_data.surf_stride);
++              }
++
++              /* config y source info */
++              reg = (map_ena[y_rdma_ena] <<
++                              SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
++                              ERDMA_DISABLE)) |
++                      (map_op_type[y_op->type] <<
++                              SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
++                              ERDMA_DATA_USE)) |
++                      (map_element_size[y_op->precision] <<
++                              SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
++                              ERDMA_DATA_SIZE)) |
++                      (map_op_mode[y_op->mode] <<
++                              SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
++                              ERDMA_DATA_MODE)) |
++                      (map_ram_type[sdp_surface->y_data.type] <<
++                              SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
++                              ERDMA_RAM_TYPE));
++
++              sdp_rdma_reg_write(D_ERDMA_CFG, reg);
++              if (y_rdma_ena) {
++                      high = HIGH32BITS(y_addr);
++                      low = LOW32BITS(y_addr);
++                      sdp_rdma_reg_write(D_EW_BASE_ADDR_LOW,
++                                      low);
++                      sdp_rdma_reg_write(D_EW_BASE_ADDR_HIGH,
++                                      high);
++                      sdp_rdma_reg_write(D_EW_LINE_STRIDE,
++                                      sdp_surface->y_data.line_stride);
++                      sdp_rdma_reg_write(D_EW_SURFACE_STRIDE,
++                                      sdp_surface->y_data.surf_stride);
++              }
++      }
++
++      if (sdp_op->lut_index >= 0)
++              update_lut(SDP_S_LUT_ACCESS_CFG_0, &lut,
++                                      sdp_op->src_precision);
++
++      sdp_reg_write(D_DATA_CUBE_WIDTH, sdp_surface->src_data.width - 1);
++      sdp_reg_write(D_DATA_CUBE_HEIGHT, sdp_surface->src_data.height - 1);
++      sdp_reg_write(D_DATA_CUBE_CHANNEL, sdp_surface->src_data.channel - 1);
++
++      if (out_dma_ena) {
++              high = HIGH32BITS(dst_addr);
++              low = LOW32BITS(dst_addr);
++              sdp_reg_write(D_DST_BASE_ADDR_HIGH,
++                              high);
++              sdp_reg_write(D_DST_BASE_ADDR_LOW,
++                              low);
++              sdp_reg_write(D_DST_LINE_STRIDE,
++                              sdp_surface->dst_data.line_stride);
++              sdp_reg_write(D_DST_SURFACE_STRIDE,
++                              sdp_surface->dst_data.surf_stride);
++      }
++
++      /* Config BS module */
++      reg = (map_bypass[x1_op->enable] <<
++                      SHIFT(SDP_D_DP_BS_CFG_0,
++                      BS_BYPASS)) |
++              (map_bypass[x1_op->type != SDP_OP_MUL &&
++                              x1_op->type != SDP_OP_NONE] <<
++                      SHIFT(SDP_D_DP_BS_CFG_0,
++                      BS_ALU_BYPASS)) |
++              (map_alu_op[x1_op->alu_type] <<
++                      SHIFT(SDP_D_DP_BS_CFG_0,
++                      BS_ALU_ALGO)) |
++              (map_bypass[x1_op->type != SDP_OP_ADD &&
++                      x1_op->type != SDP_OP_NONE] <<
++                      SHIFT(SDP_D_DP_BS_CFG_0,
++                      BS_MUL_BYPASS)) |
++              (map_prelu[x1_op->act == ACTIVATION_PRELU]
++                      << SHIFT(SDP_D_DP_BS_CFG_0,
++                      BS_MUL_PRELU)) |
++              (map_bypass[x1_op->act == ACTIVATION_RELU] <<
++                      SHIFT(SDP_D_DP_BS_CFG_0,
++                      BS_RELU_BYPASS));
++      sdp_reg_write(D_DP_BS_CFG, reg);
++
++      if (x1_op->enable) {
++              if (x1_op->type == SDP_OP_ADD ||
++                              x1_op->type == SDP_OP_BOTH) {
++                      reg = (map_alu_src[x1_op->mode == SDP_OP_PER_LAYER] <<
++                                      SHIFT(SDP_D_DP_BS_ALU_CFG_0,
++                                      BS_ALU_SRC)) |
++                              (x1_op->shift_value <<
++                                      SHIFT(SDP_D_DP_BS_ALU_CFG_0,
++                                      BS_ALU_SHIFT_VALUE));
++                      sdp_reg_write(D_DP_BS_ALU_CFG, reg);
++              }
++
++              if (x1_op->mode == SDP_OP_PER_LAYER) {
++                      sdp_reg_write(D_DP_BS_ALU_SRC_VALUE,
++                                      x1_op->alu_operand);
++                      sdp_reg_write(D_DP_BS_MUL_SRC_VALUE,
++                                      x1_op->mul_operand);
++              }
++
++              /**
++               * MUL truncate will take effect no matter
++               * MUL is bypassed or not
++               */
++              reg = (map_alu_src[x1_op->mode == SDP_OP_PER_LAYER] <<
++                      SHIFT(SDP_D_DP_BS_MUL_CFG_0,
++                      BS_MUL_SRC)) |
++              (x1_op->truncate <<
++                      SHIFT(SDP_D_DP_BS_MUL_CFG_0,
++                      BS_MUL_SHIFT_VALUE));
++              sdp_reg_write(D_DP_BS_MUL_CFG, reg);
++      }
++
++      /* Config BN module */
++      reg = (map_bypass[x2_op->enable] <<
++                      SHIFT(SDP_D_DP_BN_CFG_0,
++                      BN_BYPASS)) |
++              (map_bypass[x2_op->type != SDP_OP_MUL &&
++                      x2_op->type != SDP_OP_NONE] <<
++                      SHIFT(SDP_D_DP_BN_CFG_0,
++                      BN_ALU_BYPASS)) |
++              (map_alu_op[x2_op->alu_type] <<
++                      SHIFT(SDP_D_DP_BN_CFG_0,
++                      BN_ALU_ALGO)) |
++              (map_bypass[x2_op->type != SDP_OP_ADD &&
++                      x2_op->type != SDP_OP_NONE] <<
++                      SHIFT(SDP_D_DP_BN_CFG_0,
++                      BN_MUL_BYPASS)) |
++              (map_prelu[x2_op->act == ACTIVATION_PRELU]
++                      << SHIFT(SDP_D_DP_BN_CFG_0,
++                      BN_MUL_PRELU)) |
++              (map_bypass[x2_op->act == ACTIVATION_RELU]
++                      << SHIFT(SDP_D_DP_BN_CFG_0,
++                      BN_RELU_BYPASS));
++      sdp_reg_write(D_DP_BN_CFG, reg);
++
++      if (x2_op->enable) {
++              if (x2_op->type == SDP_OP_ADD ||
++                      x2_op->type == SDP_OP_BOTH) {
++                      reg = (map_alu_src[x2_op->mode == SDP_OP_PER_LAYER] <<
++                                      SHIFT(SDP_D_DP_BN_ALU_CFG_0,
++                                      BN_ALU_SRC)) |
++                              (x2_op->shift_value <<
++                                      SHIFT(SDP_D_DP_BN_ALU_CFG_0,
++                                      BN_ALU_SHIFT_VALUE));
++                      sdp_reg_write(D_DP_BN_ALU_CFG, reg);
++              }
++
++              if (x2_op->mode == SDP_OP_PER_LAYER) {
++                      sdp_reg_write(D_DP_BN_ALU_SRC_VALUE,
++                                      x2_op->alu_operand);
++                      sdp_reg_write(D_DP_BN_MUL_SRC_VALUE,
++                                      x2_op->mul_operand);
++              }
++
++              reg = (map_alu_src[x2_op->mode == SDP_OP_PER_LAYER] <<
++                              SHIFT(SDP_D_DP_BN_MUL_CFG_0,
++                              BN_MUL_SRC)) |
++                      (x2_op->truncate <<
++                              SHIFT(SDP_D_DP_BN_MUL_CFG_0,
++                              BN_MUL_SHIFT_VALUE));
++              sdp_reg_write(D_DP_BN_MUL_CFG, reg);
++      }
++
++      /* Config EW module */
++      reg = (map_bypass[y_op->enable] <<
++                      SHIFT(SDP_D_DP_EW_CFG_0,
++                      EW_BYPASS)) |
++              (map_bypass[y_op->type != SDP_OP_MUL &&
++                      y_op->type != SDP_OP_NONE] <<
++                      SHIFT(SDP_D_DP_EW_CFG_0,
++                      EW_ALU_BYPASS)) |
++              (map_alu_op[y_op->alu_type] <<
++                      SHIFT(SDP_D_DP_EW_CFG_0,
++                      EW_ALU_ALGO)) |
++              (map_bypass[y_op->type != SDP_OP_ADD &&
++                      y_op->type != SDP_OP_NONE] <<
++                      SHIFT(SDP_D_DP_EW_CFG_0,
++                      EW_MUL_BYPASS)) |
++              ((map_prelu[y_op->act == ACTIVATION_PRELU]) <<
++                      SHIFT(SDP_D_DP_EW_CFG_0,
++                      EW_MUL_PRELU)) |
++              (map_bypass[y_op->act == ACTIVATION_LUT] <<
++                      SHIFT(SDP_D_DP_EW_CFG_0,
++                      EW_LUT_BYPASS));
++      sdp_reg_write(D_DP_EW_CFG, reg);
++
++      if (y_op->enable) {
++              if (y_op->type == SDP_OP_ADD || y_op->type == SDP_OP_BOTH) {
++                      reg = (map_alu_src[y_op->mode == SDP_OP_PER_LAYER] <<
++                                      SHIFT(SDP_D_DP_EW_ALU_CFG_0,
++                                      EW_ALU_SRC)) |
++                              (map_bypass[y_op->cvt.alu_cvt.enable] <<
++                                      SHIFT(SDP_D_DP_EW_ALU_CFG_0,
++                                      EW_ALU_CVT_BYPASS));
++                      sdp_reg_write(D_DP_EW_ALU_CFG, reg);
++
++                      if (y_op->mode == SDP_OP_PER_LAYER) {
++                              sdp_reg_write(D_DP_EW_ALU_SRC_VALUE,
++                                              y_op->alu_operand);
++                      } else {
++                              sdp_reg_write(D_DP_EW_ALU_CVT_OFFSET_VALUE,
++                                              y_op->cvt.alu_cvt.offset);
++                              sdp_reg_write(D_DP_EW_ALU_CVT_SCALE_VALUE,
++                                              y_op->cvt.alu_cvt.scale);
++                              sdp_reg_write(D_DP_EW_ALU_CVT_TRUNCATE_VALUE,
++                                              y_op->cvt.alu_cvt.truncate);
++                      }
++              }
++
++              if (y_op->type == SDP_OP_MUL || y_op->type == SDP_OP_BOTH) {
++                      reg = (map_alu_src[y_op->mode == SDP_OP_PER_LAYER] <<
++                                      SHIFT(SDP_D_DP_EW_MUL_CFG_0,
++                                      EW_MUL_SRC)) |
++                              (map_bypass[y_op->cvt.mul_cvt.enable] <<
++                                      SHIFT(SDP_D_DP_EW_MUL_CFG_0,
++                                      EW_MUL_CVT_BYPASS));
++                      sdp_reg_write(D_DP_EW_MUL_CFG, reg);
++
++                      if (y_op->mode == SDP_OP_PER_LAYER) {
++                              sdp_reg_write(D_DP_EW_MUL_SRC_VALUE,
++                                              y_op->mul_operand);
++                      } else {
++                              sdp_reg_write(D_DP_EW_MUL_CVT_OFFSET_VALUE,
++                                              y_op->cvt.mul_cvt.offset);
++                              sdp_reg_write(D_DP_EW_MUL_CVT_SCALE_VALUE,
++                                              y_op->cvt.mul_cvt.scale);
++                              sdp_reg_write(D_DP_EW_MUL_CVT_TRUNCATE_VALUE,
++                                              y_op->cvt.mul_cvt.truncate);
++                      }
++              }
++
++              sdp_reg_write(D_DP_EW_TRUNCATE_VALUE, y_op->truncate);
++      }
++
++      reg = (map_fly[sdp_surface->src_data.type == DLA_MEM_HW] <<
++                      SHIFT(SDP_D_FEATURE_MODE_CFG_0,
++                      FLYING_MODE)) |
++              (map_dst[sdp_surface->dst_data.type == DLA_MEM_HW] <<
++                      SHIFT(SDP_D_FEATURE_MODE_CFG_0,
++                      OUTPUT_DST)) |
++              (map_wg[sdp_op->conv_mode == CONV_MODE_WINOGRAD] <<
++                      SHIFT(SDP_D_FEATURE_MODE_CFG_0,
++                      WINOGRAD)) |
++              ((sdp_op->batch_num - 1) <<
++                      SHIFT(SDP_D_FEATURE_MODE_CFG_0,
++                      BATCH_NUMBER));
++      sdp_reg_write(D_FEATURE_MODE_CFG, reg);
++      sdp_reg_write(D_DST_DMA_CFG,
++                      map_ram_type[sdp_surface->dst_data.type]);
++      if (sdp_op->batch_num > 1)
++              sdp_reg_write(D_DST_BATCH_STRIDE, sdp_op->batch_stride);
++
++      reg =
++      (map_proc_precision[sdp_op->dst_precision][sdp_op->src_precision] <<
++                      SHIFT(SDP_D_DATA_FORMAT_0,
++                      PROC_PRECISION)) |
++              (map_precision[sdp_op->dst_precision] <<
++                      SHIFT(SDP_D_DATA_FORMAT_0,
++                      OUT_PRECISION));
++      sdp_reg_write(D_DATA_FORMAT, reg);
++      sdp_reg_write(D_CVT_OFFSET, sdp_op->out_cvt.offset);
++      sdp_reg_write(D_CVT_SCALE, sdp_op->out_cvt.scale);
++      sdp_reg_write(D_CVT_SHIFT, sdp_op->out_cvt.truncate);
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}
++
++int
++dla_sdp_is_ready(struct dla_processor *processor,
++                         struct dla_processor_group *group)
++{
++      struct dla_processor_group *next_group;
++      struct dla_sdp_op_desc *sdp_op;
++
++      sdp_op = &group->operation_desc->sdp_op;
++      next_group = &processor->groups[!group->id];
++
++      /**
++       * Single LUT is shared between two SDP groups, need to make
++       * sure that usage does not conflict. Also, LUT write
++       * access is locked when SDP sub-engine is active, so delay
++       * writing LUT when another group is active.
++       */
++
++      /**
++       * if no LUT required for current group then it can be programmed
++       * without further checks
++       */
++      if (sdp_op->lut_index == -1)
++              return 1;
++
++      /**
++       * if same LUT is used for both groups then it can be programmed
++       * without more checks. Even if another group is active and LUT
++       * is locked, it would have been programmed by another group.
++       */
++      if (next_group->lut_index == sdp_op->lut_index)
++              return 1;
++
++      /**
++       * if LUT index of another group is not -1 means some LUT is programmed,
++       * then do not program current LUT as we already know current LUT is not
++       * -1 and neither same as another group.
++       */
++      if (next_group->lut_index != -1)
++              return 0;
++
++      /**
++       * if current group needs LUT different than another group and that
++       * group is not active then program it.
++       */
++      if (!next_group->active)
++              return 1;
++
++      /**
++       * if control is here it means current group is using LUT different than
++       * another group and that group is active. Wait for another group to
++       * become idle.
++       */
++      return 0;
++}
++
++void
++dla_sdp_dump_config(struct dla_processor_group *group)
++{
++      struct dla_sdp_op_desc *sdp_op;
++      struct dla_sdp_surface_desc *sdp_surface;
++
++      sdp_surface = &group->surface_desc->sdp_surface;
++      sdp_op = &group->operation_desc->sdp_op;
++
++      dla_debug_sdp_surface_desc(sdp_surface, group->roi_index);
++      dla_debug_sdp_op_desc(sdp_op, group->roi_index);
++}
++
++int
++dla_sdp_program(struct dla_processor_group *group)
++{
++      int32_t ret;
++
++      dla_trace("Enter: %s", __func__);
++      dla_enable_intr(MASK(GLB_S_INTR_MASK_0, SDP_DONE_MASK1) |
++                      MASK(GLB_S_INTR_MASK_0, SDP_DONE_MASK0));
++
++      ret = processor_sdp_program(group);
++      if (ret)
++              goto exit;
++
++exit:
++      dla_trace("Exit: %s", __func__);
++      RETURN(ret);
++}

diff --git a/target/linux/visionfive/patches-5.15/0078-nvdla-Support-compilation-as-module.patch b/target/linux/visionfive/patches-5.15/0078-nvdla-Support-compilation-as-module.patch
new file mode 100644 (file)
index 0000000..9370063
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0078-nvdla-Support-compilation-as-module.patch
@@ -0,0 +1,72 @@
+From f326b59be0ccbbd7aeb6dc023547230736a76ada Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 25 Sep 2021 18:38:15 +0200
+Subject: [PATCH 78/84] nvdla: Support compilation as module
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/nvdla/Kconfig  |  3 +--
+ drivers/nvdla/Makefile | 36 +++++++++++++++++++-----------------
+ kernel/dma/coherent.c  |  1 +
+ 3 files changed, 21 insertions(+), 19 deletions(-)
+
+--- a/drivers/nvdla/Kconfig
++++ b/drivers/nvdla/Kconfig
+@@ -1,5 +1,4 @@
+ config NVDLA
+-      bool "The NVIDIA Deep Learning Accelerator"
+-      default n
++      tristate "The NVIDIA Deep Learning Accelerator"
+       depends on DRM
+       select DRM_GEM_CMA_HELPER
+--- a/drivers/nvdla/Makefile
++++ b/drivers/nvdla/Makefile
+@@ -1,19 +1,21 @@
+ 
+-ccflags-$(CONFIG_NVDLA) += -I$(srctree)/$(src)
+-ccflags-$(CONFIG_NVDLA) += -I$(srctree)/$(src)/include
++ccflags-y += -I$(srctree)/$(src)
++ccflags-y += -I$(srctree)/$(src)/include
+ 
+-obj-$(CONFIG_NVDLA) += scheduler.o
+-obj-$(CONFIG_NVDLA) += engine.o
+-obj-$(CONFIG_NVDLA) += bdma.o
+-obj-$(CONFIG_NVDLA) += conv.o
+-obj-$(CONFIG_NVDLA) += sdp.o
+-obj-$(CONFIG_NVDLA) += cdp.o
+-obj-$(CONFIG_NVDLA) += pdp.o
+-obj-$(CONFIG_NVDLA) += rubik.o
+-obj-$(CONFIG_NVDLA) += cache.o
+-obj-$(CONFIG_NVDLA) += common.o
+-obj-$(CONFIG_NVDLA) += engine_data.o
+-obj-$(CONFIG_NVDLA) += engine_isr.o
+-obj-$(CONFIG_NVDLA) += engine_debug.o
+-obj-$(CONFIG_NVDLA) += nvdla_core_callbacks.o
+-obj-$(CONFIG_NVDLA) += nvdla_gem.o
++nvdla-y := scheduler.o \
++         engine.o \
++         bdma.o \
++         conv.o \
++         sdp.o \
++         cdp.o \
++         pdp.o \
++         rubik.o \
++         cache.o \
++         common.o \
++         engine_data.o \
++         engine_isr.o \
++         engine_debug.o \
++         nvdla_core_callbacks.o \
++         nvdla_gem.o
++
++obj-$(CONFIG_NVDLA) += nvdla.o
+--- a/kernel/dma/coherent.c
++++ b/kernel/dma/coherent.c
+@@ -130,6 +130,7 @@ int dma_declare_coherent_memory(struct d
+               dma_release_coherent_memory(mem);
+       return ret;
+ }
++EXPORT_SYMBOL_GPL(dma_declare_coherent_memory);
+ 
+ static void *__dma_alloc_from_coherent(struct device *dev,
+                                      struct dma_coherent_mem *mem,

diff --git a/target/linux/visionfive/patches-5.15/0079-spi-cadence-quadspi-Allow-compilation-on-RISC-V.patch b/target/linux/visionfive/patches-5.15/0079-spi-cadence-quadspi-Allow-compilation-on-RISC-V.patch
new file mode 100644 (file)
index 0000000..da25fe9
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0079-spi-cadence-quadspi-Allow-compilation-on-RISC-V.patch
@@ -0,0 +1,24 @@
+From ecd7749f5e622f3e1ad3c775781f09bd7b655925 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Tue, 27 Apr 2021 17:05:57 +0200
+Subject: [PATCH 79/84] spi: cadence-quadspi: Allow compilation on RISC-V
+
+This IP is also used on the StarFive JH7100 riscv64 SoC and presumably
+also the upcoming JH7110 SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/spi/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -219,7 +219,7 @@ config SPI_CADENCE
+ 
+ config SPI_CADENCE_QUADSPI
+       tristate "Cadence Quad SPI controller"
+-      depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
++      depends on OF && (ARM || ARM64 || RISCV || X86 || COMPILE_TEST)
+       help
+         Enable support for the Cadence Quad SPI Flash controller.
+ 

diff --git a/target/linux/visionfive/patches-5.15/0080-RISC-V-Enable-SIFIVE_L2_FLUSH-for-StarFive-SoCs.patch b/target/linux/visionfive/patches-5.15/0080-RISC-V-Enable-SIFIVE_L2_FLUSH-for-StarFive-SoCs.patch
new file mode 100644 (file)
index 0000000..59cacc4
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0080-RISC-V-Enable-SIFIVE_L2_FLUSH-for-StarFive-SoCs.patch
@@ -0,0 +1,44 @@
+From b6cc26d9da9684b303705343d488cb0250da81cc Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Thu, 14 Oct 2021 20:03:06 +0200
+Subject: [PATCH 80/84] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/Kconfig.socs    | 2 ++
+ drivers/soc/Makefile       | 2 +-
+ drivers/soc/sifive/Kconfig | 2 +-
+ 3 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/riscv/Kconfig.socs
++++ b/arch/riscv/Kconfig.socs
+@@ -23,6 +23,8 @@ config SOC_STARFIVE
+       bool "StarFive SoCs"
+       select PINCTRL
+       select RESET_CONTROLLER
++      select SIFIVE_L2
++      select SIFIVE_L2_FLUSH
+       select SIFIVE_PLIC
+       help
+         This enables support for StarFive SoC platform hardware.
+--- a/drivers/soc/Makefile
++++ b/drivers/soc/Makefile
+@@ -22,7 +22,7 @@ obj-y                                += qcom/
+ obj-y                         += renesas/
+ obj-$(CONFIG_ARCH_ROCKCHIP)   += rockchip/
+ obj-$(CONFIG_SOC_SAMSUNG)     += samsung/
+-obj-$(CONFIG_SOC_SIFIVE)      += sifive/
++obj-y                         += sifive/
+ obj-y                         += sunxi/
+ obj-$(CONFIG_ARCH_TEGRA)      += tegra/
+ obj-y                         += ti/
+--- a/drivers/soc/sifive/Kconfig
++++ b/drivers/soc/sifive/Kconfig
+@@ -1,6 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
+-if SOC_SIFIVE
++if SOC_SIFIVE || SOC_STARFIVE
+ 
+ config SIFIVE_L2
+       bool "Sifive L2 Cache controller"

diff --git a/target/linux/visionfive/patches-5.15/0081-RISC-V-Support-non-coherent-DMA-operations.patch b/target/linux/visionfive/patches-5.15/0081-RISC-V-Support-non-coherent-DMA-operations.patch
new file mode 100644 (file)
index 0000000..7b95cf3
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0081-RISC-V-Support-non-coherent-DMA-operations.patch
@@ -0,0 +1,130 @@
+From 6328ac1b79eb6c158b4aa94bc27850517c89972a Mon Sep 17 00:00:00 2001
+From: Atish Patra <atish.patra@wdc.com>
+Date: Sat, 12 Jun 2021 16:48:31 -0700
+Subject: [PATCH 81/84] RISC-V: Support non-coherent DMA operations
+
+** Do not upstream **
+
+This is hacky fix just for testing. The actual patch would read the
+RISCV_UNCACHED_OFFSET from the DT for only the non-coherent devices.
+All other devices on beagleV and all other platform should just set
+dma_default_coherent to true.
+
+[Emil: remove spurious whitespace and fix format string warning]
+
+Signed-off-by: Atish Patra <atish.patra@wdc.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/Kconfig              | 14 ++++++++
+ arch/riscv/Kconfig.socs         |  1 +
+ arch/riscv/mm/Makefile          |  1 +
+ arch/riscv/mm/dma-noncoherent.c | 63 +++++++++++++++++++++++++++++++++
+ 4 files changed, 79 insertions(+)
+ create mode 100644 arch/riscv/mm/dma-noncoherent.c
+
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -217,6 +217,20 @@ config PGTABLE_LEVELS
+ config LOCKDEP_SUPPORT
+       def_bool y
+ 
++config RISCV_UNCACHED_OFFSET
++      hex "Base address of uncached alias"
++      default 0xF80000000 if ARCH_HAS_DMA_SET_UNCACHED && SOC_STARFIVE
++      default 0 if !ARCH_HAS_DMA_SET_UNCACHED
++
++config RISCV_DMA_NONCOHERENT
++      bool
++      select ARCH_HAS_DMA_PREP_COHERENT
++      select ARCH_HAS_SYNC_DMA_FOR_DEVICE
++      select ARCH_HAS_SYNC_DMA_FOR_CPU
++      select ARCH_HAS_DMA_SET_UNCACHED
++      select ARCH_HAS_DMA_CLEAR_UNCACHED
++      select ARCH_HAS_SETUP_DMA_OPS
++
+ source "arch/riscv/Kconfig.socs"
+ source "arch/riscv/Kconfig.erratas"
+ 
+--- a/arch/riscv/Kconfig.socs
++++ b/arch/riscv/Kconfig.socs
+@@ -23,6 +23,7 @@ config SOC_STARFIVE
+       bool "StarFive SoCs"
+       select PINCTRL
+       select RESET_CONTROLLER
++      select RISCV_DMA_NONCOHERENT
+       select SIFIVE_L2
+       select SIFIVE_L2_FLUSH
+       select SIFIVE_PLIC
+--- a/arch/riscv/mm/Makefile
++++ b/arch/riscv/mm/Makefile
+@@ -30,3 +30,4 @@ endif
+ endif
+ 
+ obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
++obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o
+--- /dev/null
++++ b/arch/riscv/mm/dma-noncoherent.c
+@@ -0,0 +1,63 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * DMA mapping implementation inspired from arm/mm/dma-mapping.c
++ *
++ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
++ */
++
++#include <linux/dma-direct.h>
++#include <linux/dma-map-ops.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/mm.h>
++#include <asm/cpu_ops.h>
++#include <asm/sbi.h>
++#include <asm/smp.h>
++
++//TODO Do it through SBI
++#include <soc/sifive/sifive_l2_cache.h>
++
++void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, enum dma_data_direction dir)
++{
++      sifive_l2_flush64_range(paddr, size);
++}
++
++void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, enum dma_data_direction dir)
++{
++      sifive_l2_flush64_range(paddr, size);
++}
++
++void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
++              const struct iommu_ops *iommu, bool coherent)
++{
++      dev_info(dev, "coherent device %d dev->dma_coherent %d\n", coherent, dev->dma_coherent);
++      dev->dma_coherent = coherent;
++}
++
++//TODO: We are supposed to invalidate the cache here
++void arch_dma_prep_coherent(struct page *page, size_t size)
++{
++      void *flush_addr = page_address(page);
++
++      memset(flush_addr, 0, size);
++      sifive_l2_flush64_range(__pa(flush_addr), size);
++}
++
++void arch_dma_clear_uncached(void *addr, size_t size)
++{
++      memunmap(addr);
++}
++
++void *arch_dma_set_uncached(void *addr, size_t size)
++{
++      phys_addr_t phys_addr = __pa(addr) + CONFIG_RISCV_UNCACHED_OFFSET;
++      void *mem_base = NULL;
++
++      mem_base = memremap(phys_addr, size, MEMREMAP_WT);
++      if (!mem_base) {
++              pr_err("%s memremap failed for addr %px\n", __func__, addr);
++              return ERR_PTR(-EINVAL);
++      }
++
++      return mem_base;
++}

diff --git a/target/linux/visionfive/patches-5.15/0082-riscv-dts-Add-full-JH7100-Starlight-and-VisionFive-s.patch b/target/linux/visionfive/patches-5.15/0082-riscv-dts-Add-full-JH7100-Starlight-and-VisionFive-s.patch
new file mode 100644 (file)
index 0000000..45045cc
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0082-riscv-dts-Add-full-JH7100-Starlight-and-VisionFive-s.patch
@@ -0,0 +1,1521 @@
+From d33e2465e8fb496f7f4f65067a0a6f07406b723d Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 31 Oct 2021 17:15:58 +0100
+Subject: [PATCH 82/84] riscv: dts: Add full JH7100, Starlight and VisionFive
+ support
+
+Based on the device tree in https://github.com/starfive-tech/u-boot/
+with contributions from:
+yanhong.wang <yanhong.wang@starfivetech.com>
+Huan.Feng <huan.feng@starfivetech.com>
+ke.zhu <ke.zhu@starfivetech.com>
+yiming.li <yiming.li@starfivetech.com>
+jack.zhu <jack.zhu@starfivetech.com>
+Samin Guo <samin.guo@starfivetech.com>
+Chenjieqin <Jessica.Chen@starfivetech.com>
+bo.li <bo.li@starfivetech.com>
+
+Rearranged, cleanups, fixes, pins and resets added by Emil.
+Cleanups, fixes, clocks added by Geert.
+Cleanups and GPIO fixes from Drew.
+Thermal zone added by Stephen.
+PWM pins added by Jianlong.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org>
+Signed-off-by: Drew Fustini <drew@beagleboard.org>
+Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
+---
+ arch/riscv/boot/dts/starfive/Makefile         |   2 +-
+ .../starfive/jh7100-beaglev-starlight-a1.dts  |  24 +
+ .../dts/starfive/jh7100-beaglev-starlight.dts | 154 +----
+ .../boot/dts/starfive/jh7100-common.dtsi      | 590 ++++++++++++++++++
+ .../jh7100-starfive-visionfive-v1.dts         |  32 +
+ arch/riscv/boot/dts/starfive/jh7100.dtsi      | 560 +++++++++++++++++
+ 6 files changed, 1213 insertions(+), 149 deletions(-)
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
+
+--- a/arch/riscv/boot/dts/starfive/Makefile
++++ b/arch/riscv/boot/dts/starfive/Makefile
+@@ -1,2 +1,2 @@
+ # SPDX-License-Identifier: GPL-2.0
+-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
++dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight-a1.dtb jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
+@@ -0,0 +1,24 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include "jh7100-common.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++      model = "BeagleV Starlight Beta A1";
++      compatible = "beagle,beaglev-starlight-jh7100-a1", "starfive,jh7100";
++
++      gpio-restart {
++              compatible = "gpio-restart";
++              gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
++              priority = <224>;
++      };
++};
++
++&gpio {
++      /* don't reset gpio mux for serial console and reset gpio */
++      starfive,keep-gpiomux = <13 14 63>;
++};
+--- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
++++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+@@ -1,164 +1,22 @@
+ // SPDX-License-Identifier: GPL-2.0 OR MIT
+ /*
+- * Copyright (C) 2021 StarFive Technology Co., Ltd.
+  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+  */
+ 
+ /dts-v1/;
+-#include "jh7100.dtsi"
++#include "jh7100-common.dtsi"
+ #include <dt-bindings/gpio/gpio.h>
+-#include <dt-bindings/leds/common.h>
+-#include <dt-bindings/pinctrl/pinctrl-starfive.h>
+ 
+ / {
+       model = "BeagleV Starlight Beta";
+       compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
+-
+-      aliases {
+-              serial0 = &uart3;
+-      };
+-
+-      chosen {
+-              stdout-path = "serial0:115200n8";
+-      };
+-
+-      cpus {
+-              timebase-frequency = <6250000>;
+-      };
+-
+-      memory@80000000 {
+-              device_type = "memory";
+-              reg = <0x0 0x80000000 0x2 0x0>;
+-      };
+-
+-      leds {
+-              compatible = "gpio-leds";
+-
+-              led-ack {
+-                      gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
+-                      color = <LED_COLOR_ID_GREEN>;
+-                      function = LED_FUNCTION_HEARTBEAT;
+-                      linux,default-trigger = "heartbeat";
+-                      label = "ack";
+-              };
+-      };
+ };
+ 
+-&gpio {
+-      i2c0_pins: i2c0-0 {
+-              i2c-pins {
+-                      pinmux = <GPIOMUX(62, GPO_LOW,
+-                                GPO_I2C0_PAD_SCK_OEN,
+-                                GPI_I2C0_PAD_SCK_IN)>,
+-                               <GPIOMUX(61, GPO_LOW,
+-                                GPO_I2C0_PAD_SDA_OEN,
+-                                GPI_I2C0_PAD_SDA_IN)>;
+-                      bias-disable; /* external pull-up */
+-                      input-enable;
+-                      input-schmitt-enable;
+-              };
+-      };
+-
+-      i2c1_pins: i2c1-0 {
+-              i2c-pins {
+-                      pinmux = <GPIOMUX(47, GPO_LOW,
+-                                GPO_I2C1_PAD_SCK_OEN,
+-                                GPI_I2C1_PAD_SCK_IN)>,
+-                               <GPIOMUX(48, GPO_LOW,
+-                                GPO_I2C1_PAD_SDA_OEN,
+-                                GPI_I2C1_PAD_SDA_IN)>;
+-                      bias-pull-up;
+-                      input-enable;
+-                      input-schmitt-enable;
+-              };
+-      };
+-
+-      i2c2_pins: i2c2-0 {
+-              i2c-pins {
+-                      pinmux = <GPIOMUX(60, GPO_LOW,
+-                                GPO_I2C2_PAD_SCK_OEN,
+-                                GPI_I2C2_PAD_SCK_IN)>,
+-                               <GPIOMUX(59, GPO_LOW,
+-                                GPO_I2C2_PAD_SDA_OEN,
+-                                GPI_I2C2_PAD_SDA_IN)>;
+-                      bias-disable; /* external pull-up */
+-                      input-enable;
+-                      input-schmitt-enable;
+-              };
+-      };
+-
+-      uart3_pins: uart3-0 {
+-              rx-pins {
+-                      pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
+-                                GPI_UART3_PAD_SIN)>;
+-                      bias-pull-up;
+-                      drive-strength = <14>;
+-                      input-enable;
+-                      input-schmitt-enable;
+-                      slew-rate = <0>;
+-              };
+-              tx-pins {
+-                      pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
+-                                GPO_ENABLE, GPI_NONE)>;
+-                      bias-disable;
+-                      drive-strength = <35>;
+-                      input-disable;
+-                      input-schmitt-disable;
+-                      slew-rate = <0>;
+-              };
+-      };
++&gmac {
++      snps,reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
+ };
+ 
+-&i2c0 {
+-      clock-frequency = <100000>;
+-      i2c-sda-hold-time-ns = <300>;
+-      i2c-sda-falling-time-ns = <500>;
+-      i2c-scl-falling-time-ns = <500>;
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&i2c0_pins>;
+-      status = "okay";
+-
+-      pmic@5e {
+-              compatible = "ti,tps65086";
+-              reg = <0x5e>;
+-              gpio-controller;
+-              #gpio-cells = <2>;
+-
+-              regulators {
+-              };
+-      };
+-};
+-
+-&i2c1 {
+-      clock-frequency = <400000>;
+-      i2c-sda-hold-time-ns = <300>;
+-      i2c-sda-falling-time-ns = <100>;
+-      i2c-scl-falling-time-ns = <100>;
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&i2c1_pins>;
+-      status = "okay";
+-};
+-
+-&i2c2 {
+-      clock-frequency = <100000>;
+-      i2c-sda-hold-time-ns = <300>;
+-      i2c-sda-falling-time-ns = <500>;
+-      i2c-scl-falling-time-ns = <500>;
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&i2c2_pins>;
+-      status = "okay";
+-};
+-
+-&osc_sys {
+-      clock-frequency = <25000000>;
+-};
+-
+-&osc_aud {
+-      clock-frequency = <27000000>;
+-};
+-
+-&uart3 {
+-      pinctrl-names = "default";
+-      pinctrl-0 = <&uart3_pins>;
+-      status = "okay";
++&gpio {
++      /* don't reset gpio mux for serial console on uart3 */
++      starfive,keep-gpiomux = <13 14>;
+ };
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+@@ -0,0 +1,590 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include "jh7100.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/pinctrl-starfive.h>
++
++/ {
++      aliases {
++              mshc0 = &sdio0;
++              mshc1 = &sdio1;
++              serial0 = &uart3;
++              serial1 = &uart0;
++      };
++
++      chosen {
++              stdout-path = "serial0:115200n8";
++      };
++
++      cpus {
++              timebase-frequency = <6250000>;
++      };
++
++      memory@80000000 {
++              device_type = "memory";
++              reg = <0x0 0x80000000 0x2 0x0>;
++      };
++
++      leds {
++              compatible = "gpio-leds";
++
++              led-ack {
++                      gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
++                      color = <LED_COLOR_ID_GREEN>;
++                      function = LED_FUNCTION_HEARTBEAT;
++                      linux,default-trigger = "heartbeat";
++                      label = "ack";
++              };
++      };
++
++      reserved-memory {
++              #address-cells = <2>;
++              #size-cells = <2>;
++              ranges;
++
++              linux,cma {
++                      compatible = "shared-dma-pool";
++                      reusable;
++                      size = <0x0 0x28000000>;
++                      alignment = <0x0 0x1000>;
++                      alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
++                      linux,cma-default;
++              };
++
++              jpu_reserved: framebuffer@c9000000 {
++                      reg = <0x0 0xc9000000 0x0 0x4000000>;
++              };
++
++              nvdla_reserved: framebuffer@d0000000 {
++                      no-map;
++                      reg = <0x0 0xd0000000 0x0 0x28000000>;
++              };
++
++              vin_reserved: framebuffer@f9000000 {
++                      compatible = "shared-dma-pool";
++                      no-map;
++                      reg = <0x0 0xf9000000 0x0 0x1000000>;
++              };
++
++              sffb_reserved: framebuffer@fb000000 {
++                      compatible = "shared-dma-pool";
++                      no-map;
++                      reg = <0x0 0xfb000000 0x0 0x2000000>;
++              };
++      };
++
++      wifi_pwrseq: wifi-pwrseq {
++              compatible = "mmc-pwrseq-simple";
++              reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
++      };
++};
++
++&display {
++      memory-region = <&sffb_reserved>;
++      status = "okay";
++};
++
++&crtc {
++      ddr-format = <4>; //<WIN_FMT_RGB565>;
++      status = "okay";
++
++      port: port@0 {
++              reg = <0>;
++
++              crtc_0_out: endpoint {
++                      remote-endpoint = <&hdmi_input0>;
++              };
++      };
++};
++
++&encoder {
++      encoder-type = <2>; // 2-TMDS, 3-LVDS, 6-DSI, 8-DPI
++      status = "okay";
++
++      ports {
++              port@0 {
++                      hdmi_out: endpoint {
++                              remote-endpoint = <&tda998x_0_input>;
++                      };
++              };
++
++              port@1 {
++                      hdmi_input0: endpoint {
++                              remote-endpoint = <&crtc_0_out>;
++                      };
++              };
++
++      };
++};
++
++&gmac {
++      pinctrl-names = "default";
++      pinctrl-0 = <&gmac_pins>;
++      status = "okay";
++};
++
++&gpio {
++      gmac_pins: gmac-0 {
++              gtxclk-pins {
++                      pins = <PAD_FUNC_SHARE(115)>;
++                      bias-pull-up;
++                      drive-strength = <35>;
++                      input-enable;
++                      input-schmitt-enable;
++                      slew-rate = <0>;
++              };
++              miitxclk-pins {
++                      pins = <PAD_FUNC_SHARE(116)>;
++                      bias-pull-up;
++                      drive-strength = <14>;
++                      input-enable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++              tx-pins {
++                      pins = <PAD_FUNC_SHARE(117)>,
++                             <PAD_FUNC_SHARE(119)>,
++                             <PAD_FUNC_SHARE(120)>,
++                             <PAD_FUNC_SHARE(121)>,
++                             <PAD_FUNC_SHARE(122)>,
++                             <PAD_FUNC_SHARE(123)>,
++                             <PAD_FUNC_SHARE(124)>,
++                             <PAD_FUNC_SHARE(125)>,
++                             <PAD_FUNC_SHARE(126)>;
++                      bias-pull-up;
++                      drive-strength = <35>;
++                      input-disable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++              rxclk-pins {
++                      pins = <PAD_FUNC_SHARE(127)>;
++                      bias-pull-up;
++                      drive-strength = <14>;
++                      input-enable;
++                      input-schmitt-disable;
++                      slew-rate = <6>;
++              };
++              rxer-pins {
++                      pins = <PAD_FUNC_SHARE(129)>;
++                      bias-pull-up;
++                      drive-strength = <14>;
++                      input-enable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++              rx-pins {
++                      pins = <PAD_FUNC_SHARE(128)>,
++                             <PAD_FUNC_SHARE(130)>,
++                             <PAD_FUNC_SHARE(131)>,
++                             <PAD_FUNC_SHARE(132)>,
++                             <PAD_FUNC_SHARE(133)>,
++                             <PAD_FUNC_SHARE(134)>,
++                             <PAD_FUNC_SHARE(135)>,
++                             <PAD_FUNC_SHARE(136)>,
++                             <PAD_FUNC_SHARE(137)>,
++                             <PAD_FUNC_SHARE(138)>,
++                             <PAD_FUNC_SHARE(139)>,
++                             <PAD_FUNC_SHARE(140)>,
++                             <PAD_FUNC_SHARE(141)>;
++                      bias-pull-up;
++                      drive-strength = <14>;
++                      input-enable;
++                      input-schmitt-enable;
++                      slew-rate = <0>;
++              };
++      };
++
++      i2c0_pins: i2c0-0 {
++              i2c-pins {
++                      pinmux = <GPIOMUX(62, GPO_LOW,
++                                GPO_I2C0_PAD_SCK_OEN,
++                                GPI_I2C0_PAD_SCK_IN)>,
++                               <GPIOMUX(61, GPO_LOW,
++                                GPO_I2C0_PAD_SDA_OEN,
++                                GPI_I2C0_PAD_SDA_IN)>;
++                      bias-disable; /* external pull-up */
++                      input-enable;
++                      input-schmitt-enable;
++              };
++      };
++
++      i2c1_pins: i2c1-0 {
++              i2c-pins {
++                      pinmux = <GPIOMUX(47, GPO_LOW,
++                                GPO_I2C1_PAD_SCK_OEN,
++                                GPI_I2C1_PAD_SCK_IN)>,
++                               <GPIOMUX(48, GPO_LOW,
++                                GPO_I2C1_PAD_SDA_OEN,
++                                GPI_I2C1_PAD_SDA_IN)>;
++                      bias-pull-up;
++                      input-enable;
++                      input-schmitt-enable;
++              };
++      };
++
++      i2c2_pins: i2c2-0 {
++              i2c-pins {
++                      pinmux = <GPIOMUX(60, GPO_LOW,
++                                GPO_I2C2_PAD_SCK_OEN,
++                                GPI_I2C2_PAD_SCK_IN)>,
++                               <GPIOMUX(59, GPO_LOW,
++                                GPO_I2C2_PAD_SDA_OEN,
++                                GPI_I2C2_PAD_SDA_IN)>;
++                      bias-disable; /* external pull-up */
++                      input-enable;
++                      input-schmitt-enable;
++              };
++      };
++
++      pwmdac_pins: pwmdac-0 {
++              pwmdac-pins {
++                      pinmux = <GPIOMUX(23, GPO_PWMDAC_LEFT_OUT,
++                                GPO_ENABLE, GPI_NONE)>,
++                               <GPIOMUX(24, GPO_PWMDAC_RIGHT_OUT,
++                                GPO_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      drive-strength = <35>;
++                      input-disable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++      };
++
++      pwm_pins: pwm-0 {
++              pwm-pins {
++                      pinmux = <GPIOMUX(7,
++                                GPO_PWM_PAD_OUT_BIT0,
++                                GPO_PWM_PAD_OE_N_BIT0,
++                                GPI_NONE)>,
++                               <GPIOMUX(5,
++                                GPO_PWM_PAD_OUT_BIT1,
++                                GPO_PWM_PAD_OE_N_BIT1,
++                                GPI_NONE)>,
++                               <GPIOMUX(45,
++                                GPO_PWM_PAD_OUT_BIT2,
++                                GPO_PWM_PAD_OE_N_BIT2,
++                                GPI_NONE)>;
++                      bias-disable;
++                      drive-strength = <35>;
++                      input-disable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++      };
++
++      sdio0_pins: sdio0-0 {
++              clk-pins {
++                      pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
++                                GPO_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      input-disable;
++                      input-schmitt-disable;
++              };
++              sdio-pins {
++                      pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
++                                GPI_SDIO0_PAD_CARD_DETECT_N)>,
++                               <GPIOMUX(53,
++                                GPO_SDIO0_PAD_CCMD_OUT,
++                                GPO_SDIO0_PAD_CCMD_OEN,
++                                GPI_SDIO0_PAD_CCMD_IN)>,
++                               <GPIOMUX(49,
++                                GPO_SDIO0_PAD_CDATA_OUT_BIT0,
++                                GPO_SDIO0_PAD_CDATA_OEN_BIT0,
++                                GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
++                               <GPIOMUX(50,
++                                GPO_SDIO0_PAD_CDATA_OUT_BIT1,
++                                GPO_SDIO0_PAD_CDATA_OEN_BIT1,
++                                GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
++                               <GPIOMUX(51,
++                                GPO_SDIO0_PAD_CDATA_OUT_BIT2,
++                                GPO_SDIO0_PAD_CDATA_OEN_BIT2,
++                                GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
++                               <GPIOMUX(52,
++                                GPO_SDIO0_PAD_CDATA_OUT_BIT3,
++                                GPO_SDIO0_PAD_CDATA_OEN_BIT3,
++                                GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
++                      bias-pull-up;
++                      input-enable;
++                      input-schmitt-enable;
++              };
++      };
++
++      sdio1_pins: sdio1-0 {
++              clk-pins {
++                      pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
++                                GPO_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      input-disable;
++                      input-schmitt-disable;
++              };
++              sdio-pins {
++                      pinmux = <GPIOMUX(29,
++                                GPO_SDIO1_PAD_CCMD_OUT,
++                                GPO_SDIO1_PAD_CCMD_OEN,
++                                GPI_SDIO1_PAD_CCMD_IN)>,
++                               <GPIOMUX(36,
++                                GPO_SDIO1_PAD_CDATA_OUT_BIT0,
++                                GPO_SDIO1_PAD_CDATA_OEN_BIT0,
++                                GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
++                               <GPIOMUX(30,
++                                GPO_SDIO1_PAD_CDATA_OUT_BIT1,
++                                GPO_SDIO1_PAD_CDATA_OEN_BIT1,
++                                GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
++                               <GPIOMUX(34,
++                                GPO_SDIO1_PAD_CDATA_OUT_BIT2,
++                                GPO_SDIO1_PAD_CDATA_OEN_BIT2,
++                                GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
++                               <GPIOMUX(31,
++                                GPO_SDIO1_PAD_CDATA_OUT_BIT3,
++                                GPO_SDIO1_PAD_CDATA_OEN_BIT3,
++                                GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
++                      bias-pull-up;
++                      input-enable;
++                      input-schmitt-enable;
++              };
++      };
++
++      spi2_pins: spi2-0 {
++              mosi-pins {
++                      pinmux = <GPIOMUX(18, GPO_SPI2_PAD_TXD,
++                                GPO_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      input-disable;
++                      input-schmitt-disable;
++              };
++              miso-pins {
++                      pinmux = <GPIOMUX(16, GPO_LOW, GPO_DISABLE,
++                                GPI_SPI2_PAD_RXD)>;
++                      bias-pull-up;
++                      input-enable;
++                      input-schmitt-enable;
++              };
++              sck-pins {
++                      pinmux = <GPIOMUX(12, GPO_SPI2_PAD_SCK_OUT,
++                                GPO_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      input-disable;
++                      input-schmitt-disable;
++              };
++              ss-pins {
++                      pinmux = <GPIOMUX(15, GPO_SPI2_PAD_SS_0_N,
++                                GPO_ENABLE, GPI_NONE)>,
++                               <GPIOMUX(11, GPO_SPI2_PAD_SS_1_N,
++                                GPO_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      input-disable;
++                      input-schmitt-disable;
++              };
++      };
++
++      uart0_pins: uart0-0 {
++              rx-pins {
++                      pinmux = <GPIOMUX(40, GPO_LOW, GPO_DISABLE,
++                                GPI_UART0_PAD_SIN)>,
++                               <GPIOMUX(39, GPO_LOW, GPO_DISABLE,
++                                GPI_UART0_PAD_CTSN)>;
++                      bias-pull-up;
++                      drive-strength = <14>;
++                      input-enable;
++                      input-schmitt-enable;
++              };
++              tx-pins {
++                      pinmux = <GPIOMUX(41, GPO_UART0_PAD_SOUT,
++                                GPO_ENABLE, GPI_NONE)>,
++                               <GPIOMUX(42, GPO_UART0_PAD_RTSN,
++                                GPO_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      drive-strength = <35>;
++                      input-disable;
++                      input-schmitt-disable;
++              };
++      };
++
++      uart3_pins: uart3-0 {
++              rx-pins {
++                      pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
++                                GPI_UART3_PAD_SIN)>;
++                      bias-pull-up;
++                      drive-strength = <14>;
++                      input-enable;
++                      input-schmitt-enable;
++                      slew-rate = <0>;
++              };
++              tx-pins {
++                      pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
++                                GPO_ENABLE, GPI_NONE)>;
++                      bias-disable;
++                      drive-strength = <35>;
++                      input-disable;
++                      input-schmitt-disable;
++                      slew-rate = <0>;
++              };
++      };
++};
++
++&i2c0 {
++      clock-frequency = <100000>;
++      i2c-sda-hold-time-ns = <300>;
++      i2c-sda-falling-time-ns = <500>;
++      i2c-scl-falling-time-ns = <500>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&i2c0_pins>;
++      status = "okay";
++
++      pmic@5e {
++              compatible = "ti,tps65086";
++              reg = <0x5e>;
++              gpio-controller;
++              #gpio-cells = <2>;
++
++              regulators {
++              };
++      };
++
++      tda998x@70 {
++              compatible = "nxp,tda998x";
++              reg = <0x70>;
++
++              port {
++                      tda998x_0_input: endpoint {
++                              remote-endpoint = <&hdmi_out>;
++                      };
++              };
++      };
++};
++
++&i2c1 {
++      clock-frequency = <400000>;
++      i2c-sda-hold-time-ns = <300>;
++      i2c-sda-falling-time-ns = <100>;
++      i2c-scl-falling-time-ns = <100>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&i2c1_pins>;
++      status = "okay";
++};
++
++&i2c2 {
++      clock-frequency = <100000>;
++      i2c-sda-hold-time-ns = <300>;
++      i2c-sda-falling-time-ns = <500>;
++      i2c-scl-falling-time-ns = <500>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&i2c2_pins>;
++      status = "okay";
++};
++
++&osc_sys {
++      clock-frequency = <25000000>;
++};
++
++&osc_aud {
++      clock-frequency = <27000000>;
++};
++
++&ptc {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pwm_pins>;
++      status = "okay";
++};
++
++&pwmdac {
++      pinctrl-names = "default";
++      pinctrl-0 = <&pwmdac_pins>;
++      status = "okay";
++};
++
++&qspi {
++      nor_flash: nor-flash@0 {
++              compatible = "spi-flash";
++              reg = <0>;
++              spi-max-frequency = <31250000>;
++              page-size = <256>;
++              block-size = <16>;
++              cdns,read-delay = <4>;
++              cdns,tshsl-ns = <1>;
++              cdns,tsd2d-ns = <1>;
++              cdns,tchsh-ns = <1>;
++              cdns,tslch-ns = <1>;
++              spi-tx-bus-width = <1>;
++              spi-rx-bus-width = <1>;
++      };
++
++      nand_flash: nand-flash@1 {
++              compatible = "spi-flash-nand";
++              reg = <1>;
++              spi-max-frequency = <31250000>;
++              page-size = <2048>;
++              block-size = <17>;
++              cdns,read-delay = <4>;
++              cdns,tshsl-ns = <1>;
++              cdns,tsd2d-ns = <1>;
++              cdns,tchsh-ns = <1>;
++              cdns,tslch-ns = <1>;
++              spi-tx-bus-width = <1>;
++              spi-rx-bus-width = <1>;
++      };
++};
++
++&sdio0 {
++      broken-cd;
++      bus-width = <4>;
++      cap-sd-highspeed;
++      pinctrl-names = "default";
++      pinctrl-0 = <&sdio0_pins>;
++      status = "okay";
++};
++
++&sdio1 {
++      #address-cells = <1>;
++      #size-cells = <0>;
++      bus-width = <4>;
++      cap-sd-highspeed;
++      cap-sdio-irq;
++      cap-power-off-card;
++      mmc-pwrseq = <&wifi_pwrseq>;
++      non-removable;
++      pinctrl-names = "default";
++      pinctrl-0 = <&sdio1_pins>;
++      status = "okay";
++
++      wifi@1 {
++              compatible = "brcm,bcm4329-fmac";
++              reg = <1>;
++      };
++};
++
++&spi2 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&spi2_pins>;
++      status = "okay";
++
++      spi_dev0: spi@0 {
++              compatible = "rohm,dh2228fv";
++              spi-max-frequency = <10000000>;
++              reg = <0>;
++      };
++};
++
++&uart0 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&uart0_pins>;
++      status = "okay";
++};
++
++&uart3 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&uart3_pins>;
++      status = "okay";
++};
++
++&usb3 {
++      dr_mode = "host";
++      status = "okay";
++};
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
+@@ -0,0 +1,32 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include "jh7100-common.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++      model = "StarFive VisionFive V1";
++      compatible = "starfive,visionfive-v1", "starfive,jh7100";
++
++      gpio-restart {
++              compatible = "gpio-restart";
++              gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
++              priority = <224>;
++      };
++};
++
++&gpio {
++      /* don't reset gpio mux for serial console and reset gpio */
++      starfive,keep-gpiomux = <13 14 63>;
++};
++
++&i2c0 {
++      eeprom@50 {
++              compatible = "atmel,24c04";
++              reg = <0x50>;
++              pagesize = <16>;
++      };
++};
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -6,7 +6,9 @@
+ 
+ /dts-v1/;
+ #include <dt-bindings/clock/starfive-jh7100.h>
++#include <dt-bindings/clock/starfive-jh7100-audio.h>
+ #include <dt-bindings/reset/starfive-jh7100.h>
++#include <dt-bindings/reset/starfive-jh7100-audio.h>
+ 
+ / {
+       compatible = "starfive,jh7100";
+@@ -32,7 +34,9 @@
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <32>;
+                       mmu-type = "riscv,sv39";
++                      next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc";
++                      starfive,itim = <&itim0>;
+                       tlb-split;
+ 
+                       cpu0_intc: interrupt-controller {
+@@ -57,7 +61,9 @@
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <32>;
+                       mmu-type = "riscv,sv39";
++                      next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc";
++                      starfive,itim = <&itim1>;
+                       tlb-split;
+ 
+                       cpu1_intc: interrupt-controller {
+@@ -103,6 +109,24 @@
+               #size-cells = <2>;
+               ranges;
+ 
++              dtim: dtim@1000000 {
++                      compatible = "starfive,dtim0";
++                      reg = <0x0 0x1000000 0x0 0x2000>;
++                      reg-names = "mem";
++              };
++
++              itim0: itim@1808000 {
++                      compatible = "starfive,itim0";
++                      reg = <0x0 0x1808000 0x0 0x8000>;
++                      reg-names = "mem";
++              };
++
++              itim1: itim@1820000 {
++                      compatible = "starfive,itim0";
++                      reg = <0x0 0x1820000 0x0 0x8000>;
++                      reg-names = "mem";
++              };
++
+               clint: clint@2000000 {
+                       compatible = "starfive,jh7100-clint", "sifive,clint0";
+                       reg = <0x0 0x2000000 0x0 0x10000>;
+@@ -110,6 +134,20 @@
+                                             <&cpu1_intc 3>, <&cpu1_intc 7>;
+               };
+ 
++              ccache: cache-controller@2010000 {
++                      compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
++                      reg = <0x0 0x2010000 0x0 0x1000>,
++                            <0x0 0x8000000 0x0 0x2000000>;
++                      reg-names = "control", "sideband";
++                      interrupts = <128>, <131>, <129>, <130>;
++                      cache-block-size = <64>;
++                      cache-level = <2>;
++                      cache-sets = <2048>;
++                      cache-size = <2097152>;
++                      cache-unified;
++                      /*next-level-cache = <&L40 &L36>;*/
++              };
++
+               plic: interrupt-controller@c000000 {
+                       compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
+                       reg = <0x0 0xc000000 0x0 0x4000000>;
+@@ -121,6 +159,179 @@
+                       riscv,ndev = <127>;
+               };
+ 
++              sdio0: mmc@10000000 {
++                      compatible = "snps,dw-mshc";
++                      reg = <0x0 0x10000000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
++                               <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
++                      clock-names = "biu", "ciu";
++                      interrupts = <4>;
++                      data-addr = <0>;
++                      fifo-depth = <32>;
++                      fifo-watermark-aligned;
++                      status = "disabled";
++              };
++
++              sdio1: mmc@10010000 {
++                      compatible = "snps,dw-mshc";
++                      reg = <0x0 0x10010000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
++                               <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
++                      clock-names = "biu", "ciu";
++                      interrupts = <5>;
++                      data-addr = <0>;
++                      fifo-depth = <32>;
++                      fifo-watermark-aligned;
++                      status = "disabled";
++              };
++
++              /* gmac device configuration */
++              stmmac_axi_setup: stmmac-axi-config {
++                      snps,wr_osr_lmt = <0xf>;
++                      snps,rd_osr_lmt = <0xf>;
++                      snps,blen = <256 128 64 32 0 0 0>;
++              };
++
++              gmac: ethernet@10020000 {
++                      compatible = "snps,dwmac";
++                      reg = <0x0 0x10020000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_GMAC_GTX>,
++                               <&clkgen JH7100_CLK_GMAC_AHB>,
++                               <&clkgen JH7100_CLK_GMAC_PTP_REF>;
++                      clock-names = "stmmaceth", "pclk", "ptp_ref";
++                      resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
++                      reset-names = "ahb";
++                      interrupts = <6>, <7>;
++                      interrupt-names = "macirq", "eth_wake_irq";
++                      max-frame-size = <9000>;
++                      phy-mode = "rgmii-txid";
++                      snps,multicast-filter-bins = <256>;
++                      snps,perfect-filter-entries = <128>;
++                      rx-fifo-depth = <32768>;
++                      tx-fifo-depth = <16384>;
++                      snps,axi-config = <&stmmac_axi_setup>;
++                      snps,fixed-burst;
++                      /*snps,force_sf_dma_mode;*/
++                      snps,force_thresh_dma_mode;
++                      snps,no-pbl-x8 = <1>;
++                      status = "disabled";
++              };
++
++              dma2p: dma-controller@100b0000 {
++                      compatible = "snps,axi-dma-1.01a";
++                      reg = <0x0 0x100b0000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
++                               <&clkgen JH7100_CLK_SGDMA2P_AHB>;
++                      clock-names = "core-clk", "cfgr-clk";
++                      interrupts = <2>;
++                      #dma-cells = <1>;
++                      dma-channels = <4>;
++                      snps,dma-masters = <1>;
++                      snps,data-width = <4>;
++                      snps,block-size = <4096 4096 4096 4096>;
++                      snps,priority = <0 1 2 3>;
++                      snps,axi-max-burst-len = <128>;
++                      dma-coherent;
++              };
++
++              crypto: crypto@100d0000 {
++                      compatible = "starfive,vic-sec";
++                      reg = <0x0 0x100d0000 0x0 0x20000>,
++                            <0x0 0x11800234 0x0 0xc>;
++                      reg-names = "secmem", "secclk";
++                      clocks = <&clkgen JH7100_CLK_SEC_AHB>;
++                      interrupts = <31>;
++              };
++
++              i2sadc0: i2sadc0@10400000 {
++                      compatible = "snps,designware-i2sadc0";
++                      reg = <0x0 0x10400000 0x0 0x1000>;
++                      clocks = <&clkgen JH7100_CLK_APB1_BUS>;
++                      clock-names = "i2sclk";
++                      interrupt-parent = <&plic>;
++                      #sound-dai-cells = <0>;
++                      dmas = <&dma2p 28>;
++                      dma-names = "rx";
++              };
++
++              i2svad: i2svad@10420000 {
++                      compatible = "starfive,sf-i2svad";
++                      reg = <0x0 0x10420000 0x0 0x1000> ;
++                      clocks = <&audclk JH7100_AUDCLK_I2SVAD_APB>;
++                      clock-names = "i2svad_apb";
++                      resets = <&audrst JH7100_AUDRSTN_I2SVAD_APB>,
++                               <&audrst JH7100_AUDRSTN_I2SVAD_SRST>;
++                      reset-names = "apb_i2svad", "i2svad_srst";
++                      interrupts = <60>, <61>;
++                      interrupt-names = "spintr", "slintr";
++                      #sound-dai-cells = <0>;
++              };
++
++              pwmdac: pwmdac@10440000 {
++                      compatible = "starfive,pwmdac";
++                      reg = <0x0 0x10440000 0x0 0x1000>;
++                      clocks = <&clkgen JH7100_CLK_AUDIO_ROOT>,
++                               <&clkgen JH7100_CLK_AUDIO_SRC>,
++                               <&clkgen JH7100_CLK_AUDIO_12288>,
++                               <&audclk JH7100_AUDCLK_DMA1P_AHB>,
++                               <&audclk JH7100_AUDCLK_PWMDAC_APB>,
++                               <&audclk JH7100_AUDCLK_DAC_MCLK>;
++                      clock-names = "audio_root",
++                                    "audio_src",
++                                    "audio_12288",
++                                    "dma1p_ahb",
++                                    "pwmdac_apb",
++                                    "dac_mclk";
++                      resets = <&audrst JH7100_AUDRSTN_APB_BUS>,
++                               <&audrst JH7100_AUDRSTN_DMA1P_AHB>,
++                               <&audrst JH7100_AUDRSTN_PWMDAC_APB>;
++                      reset-names = "apb_bus", "dma1p_ahb", "apb_pwmdac";
++                      dmas = <&dma2p 23>;
++                      dma-names = "tx";
++                      #sound-dai-cells = <0>;
++              };
++
++              i2sdac0: i2sdac0@10450000 {
++                      compatible = "snps,designware-i2sdac0";
++                      reg = <0x0 0x10450000 0x0 0x1000>;
++                      clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
++                               <&audclk JH7100_AUDCLK_I2SDAC_BCLK>,
++                               <&audclk JH7100_AUDCLK_I2SDAC_LRCLK>,
++                               <&audclk JH7100_AUDCLK_I2SDAC_APB>;
++                      clock-names = "dac_mclk", "i2sdac0_bclk", "i2sdac0_lrclk", "i2sdac_apb";
++                      resets = <&audrst JH7100_AUDRSTN_I2SDAC_APB>,
++                               <&audrst JH7100_AUDRSTN_I2SDAC_SRST>;
++                      reset-names = "apb_i2sdac", "i2sdac_srst";
++                      #sound-dai-cells = <0>;
++                      dmas = <&dma2p 30>;
++                      dma-names = "tx";
++              };
++
++              i2sdac1: i2sdac1@10460000 {
++                      compatible = "snps,designware-i2sdac1";
++                      reg = <0x0 0x10460000 0x0 0x1000>;
++                      clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
++                               <&audclk JH7100_AUDCLK_I2S1_BCLK>,
++                               <&audclk JH7100_AUDCLK_I2S1_LRCLK>,
++                               <&audclk JH7100_AUDCLK_I2S1_APB>;
++                      clock-names = "dac_mclk", "i2sdac1_bclk", "i2sdac1_lrclk", "i2s1_apb";
++                      resets = <&audrst JH7100_AUDRSTN_I2S1_APB>,
++                               <&audrst JH7100_AUDRSTN_I2S1_SRST>;
++                      #sound-dai-cells = <0>;
++                      dmas = <&dma2p 31>;
++                      dma-names = "tx";
++              };
++
++              i2sdac16k: i2sdac16k@10470000 {
++                      compatible = "snps,designware-i2sdac16k";
++                      reg = <0x0 0x10470000 0x0 0x1000>;
++                      clocks = <&clkgen JH7100_CLK_APB1_BUS>;
++                      clock-names = "i2sclk";
++                      #sound-dai-cells = <0>;
++                      dmas = <&dma2p 29>;
++                      dma-names = "tx";
++              };
++
+               audclk: clock-controller@10480000 {
+                       compatible = "starfive,jh7100-audclk";
+                       reg = <0x0 0x10480000 0x0 0x10000>;
+@@ -137,6 +348,79 @@
+                       #reset-cells = <1>;
+               };
+ 
++              spdif_transmitter: spdif-transmitter {
++                      compatible = "linux,spdif-dit";
++                      #sound-dai-cells = <0>;
++              };
++
++              spdif_receiver: spdif-receiver {
++                      compatible = "linux,spdif-dir";
++                      #sound-dai-cells = <0>;
++              };
++
++              pwmdac_codec: pwmdac-transmitter {
++                      compatible = "linux,pwmdac-dit";
++                      #sound-dai-cells = <0>;
++              };
++
++              dmic_codec: dmic {
++                      compatible = "dmic-codec";
++                      #sound-dai-cells = <0>;
++              };
++
++              sound: snd-card {
++                      compatible = "simple-audio-card";
++                      simple-audio-card,name = "Starfive-Multi-Sound-Card";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++
++                      /* pwmdac */
++                      simple-audio-card,dai-link@0 {
++                              reg = <0>;
++                              status = "okay";
++                              format = "left_j";
++                              bitclock-master = <&sndcpu0>;
++                              frame-master = <&sndcpu0>;
++
++                              sndcpu0: cpu {
++                                      sound-dai = <&pwmdac>;
++                              };
++
++                              codec {
++                                      sound-dai = <&pwmdac_codec>;
++                              };
++                      };
++              };
++
++              usb3: usb@104c0000 {
++                      compatible = "cdns,usb3";
++                      reg = <0x0 0x104c0000 0x0 0x10000>,     // memory area for HOST registers
++                            <0x0 0x104d0000 0x0 0x10000>,     // memory area for DEVICE registers
++                            <0x0 0x104e0000 0x0 0x10000>;     // memory area for OTG/DRD registers
++                      reg-names = "otg", "xhci", "dev";
++                      interrupts = <44>, <52>, <43>;
++                      interrupt-names = "host", "peripheral", "otg";
++                      phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
++                      maximum-speed = "super-speed";
++                      status = "disabled";
++              };
++
++              dma1p: dma-controller@10500000 {
++                      compatible = "snps,axi-dma-1.01a";
++                      reg = <0x0 0x10500000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
++                               <&clkgen JH7100_CLK_SGDMA1P_BUS>;
++                      clock-names = "core-clk", "cfgr-clk";
++                      interrupts = <1>;
++                      #dma-cells = <1>;
++                      dma-channels = <16>;
++                      snps,dma-masters = <1>;
++                      snps,data-width = <3>;
++                      snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
++                      snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++                      snps,axi-max-burst-len = <64>;
++              };
++
+               clkgen: clock-controller@11800000 {
+                       compatible = "starfive,jh7100-clkgen";
+                       reg = <0x0 0x11800000 0x0 0x10000>;
+@@ -145,12 +429,88 @@
+                       #clock-cells = <1>;
+               };
+ 
++              otp: otp@11810000 {
++                      compatible = "starfive,fu740-otp";
++                      reg = <0x0 0x11810000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_OTP_APB>;
++                      fuse-count = <0x200>;
++              };
++
+               rstgen: reset-controller@11840000 {
+                       compatible = "starfive,jh7100-reset";
+                       reg = <0x0 0x11840000 0x0 0x10000>;
+                       #reset-cells = <1>;
+               };
+ 
++              qspi: spi@11860000 {
++                      compatible = "cdns,qspi-nor";
++                      reg = <0x0 0x11860000 0x0 0x10000>,
++                            <0x0 0x20000000 0x0 0x20000000>;
++                      clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
++                      interrupts = <3>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      cdns,fifo-depth = <256>;
++                      cdns,fifo-width = <4>;
++                      cdns,trigger-address = <0x0>;
++                      spi-max-frequency = <250000000>;
++                      status = "disabled";
++              };
++
++              uart0: serial@11870000 {
++                      compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
++                      reg = <0x0 0x11870000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_UART0_CORE>,
++                               <&clkgen JH7100_CLK_UART0_APB>;
++                      clock-names = "baudclk", "apb_pclk";
++                      resets = <&rstgen JH7100_RSTN_UART0_APB>;
++                      interrupts = <92>;
++                      reg-io-width = <4>;
++                      reg-shift = <2>;
++                      status = "disabled";
++              };
++
++              uart1: serial@11880000 {
++                      compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
++                      reg = <0x0 0x11880000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_UART1_CORE>,
++                               <&clkgen JH7100_CLK_UART1_APB>;
++                      clock-names = "baudclk", "apb_pclk";
++                      resets = <&rstgen JH7100_RSTN_UART1_APB>;
++                      interrupts = <93>;
++                      reg-io-width = <4>;
++                      reg-shift = <2>;
++                      status = "disabled";
++              };
++
++              spi0: spi@11890000 {
++                      compatible = "snps,dw-apb-ssi";
++                      reg = <0x0 0x11890000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
++                               <&clkgen JH7100_CLK_SPI0_APB>;
++                      clock-names = "ssi_clk", "pclk";
++                      resets = <&rstgen JH7100_RSTN_SPI0_APB>;
++                      reset-names = "spi";
++                      interrupts = <94>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              spi1: spi@118a0000 {
++                      compatible = "snps,dw-apb-ssi";
++                      reg = <0x0 0x118a0000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
++                               <&clkgen JH7100_CLK_SPI1_APB>;
++                      clock-names = "ssi_clk", "pclk";
++                      resets = <&rstgen JH7100_RSTN_SPI1_APB>;
++                      reset-names = "spi";
++                      interrupts = <95>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
+               i2c0: i2c@118b0000 {
+                       compatible = "snps,designware-i2c";
+                       reg = <0x0 0x118b0000 0x0 0x10000>;
+@@ -177,6 +537,41 @@
+                       status = "disabled";
+               };
+ 
++              trng: trng@118d0000 {
++                      compatible = "starfive,vic-rng";
++                      reg = <0x0 0x118d0000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_TRNG_APB>;
++                      interrupts = <98>;
++              };
++
++              vpu_enc: vpu_enc@118e0000 {
++                      compatible = "cm,cm521-vpu";
++                      reg = <0x0 0x118e0000 0x0 0x4000>;
++                      reg-names = "control";
++                      clocks = <&clkgen JH7100_CLK_VP6_CORE>;
++                      clock-names = "vcodec";
++                      interrupts = <26>;
++              };
++
++              vpu_dec: vpu_dec@118f0000 {
++                      compatible = "c&m,cm511-vpu";
++                      reg = <0 0x118f0000 0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_VP6_CORE>;
++                      clock-names = "vcodec";
++                      interrupts = <23>;
++                      //memory-region = <&vpu_reserved>;
++              };
++
++              jpu: coadj12@11900000 {
++                      compatible = "cm,codaj12-jpu-1";
++                      reg = <0x0 0x11900000 0x0 0x300>;
++                      reg-names = "control";
++                      clocks = <&clkgen JH7100_CLK_JPEG_APB>;
++                      clock-names = "jpege";
++                      interrupts = <24>;
++                      memory-region = <&jpu_reserved>;
++              };
++
+               gpio: pinctrl@11910000 {
+                       compatible = "starfive,jh7100-pinctrl";
+                       reg = <0x0 0x11910000 0x0 0x10000>,
+@@ -191,6 +586,86 @@
+                       #interrupt-cells = <2>;
+               };
+ 
++              nvdla@11940000 {
++                      compatible = "nvidia,nvdla_os_initial";
++                      interrupts = <22>;
++                      memory-region = <&nvdla_reserved>;
++                      reg = <0x0 0x11940000 0x0 0x40000>;
++                      status = "okay";
++              };
++
++              display: display-subsystem {
++                      compatible = "starfive,display-subsystem";
++                      dma-coherent;
++                      status = "disabled";
++              };
++
++              encoder: display-encoder {
++                      compatible = "starfive,display-encoder";
++                      status = "disabled";
++              };
++
++              crtc: crtc@12000000 {
++                      compatible = "starfive,jh7100-crtc";
++                      reg = <0x0 0x12000000 0x0 0x10000>,
++                            <0x0 0x12040000 0x0 0x10000>,
++                            <0x0 0x12080000 0x0 0x10000>,
++                            <0x0 0x120c0000 0x0 0x10000>,
++                            <0x0 0x12240000 0x0 0x10000>,
++                            <0x0 0x12250000 0x0 0x10000>,
++                            <0x0 0x12260000 0x0 0x10000>;
++                      reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
++                      clocks = <&clkgen JH7100_CLK_DISP_AXI>, <&clkgen JH7100_CLK_VOUT_SRC>;
++                      clock-names = "disp_axi", "vout_src";
++                      resets = <&rstgen JH7100_RSTN_DISP_AXI>, <&rstgen JH7100_RSTN_VOUT_SRC>;
++                      reset-names = "disp_axi", "vout_src";
++                      interrupts = <101>, <103>;
++                      interrupt-names = "lcdc_irq", "vpp1_irq";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++
++                      pp1 {
++                              pp-id = <1>;
++                              fifo-out;
++                              //sys-bus-out;
++                              src-format = <11>; //<COLOR_RGB565>;
++                              src-width = <1920>;
++                              src-height = <1080>;
++                              dst-format = <7>; //<COLOR_RGB888_ARGB>;
++                              dst-width = <1920>;
++                              dst-height = <1080>;
++                      };
++              };
++
++              spi2: spi@12410000 {
++                      compatible = "snps,dw-apb-ssi";
++                      reg = <0x0 0x12410000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
++                               <&clkgen JH7100_CLK_SPI2_APB>;
++                      clock-names = "ssi_clk", "pclk";
++                      resets = <&rstgen JH7100_RSTN_SPI2_APB>;
++                      reset-names = "spi";
++                      interrupts = <70>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              spi3: spi@12420000 {
++                      compatible = "snps,dw-apb-ssi";
++                      reg = <0x0 0x12420000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
++                               <&clkgen JH7100_CLK_SPI3_APB>;
++                      clock-names = "ssi_clk", "pclk";
++                      resets = <&rstgen JH7100_RSTN_SPI3_APB>;
++                      reset-names = "spi";
++                      interrupts = <71>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
+               uart2: serial@12430000 {
+                       compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
+                       reg = <0x0 0x12430000 0x0 0x10000>;
+@@ -242,5 +717,90 @@
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
++
++              watchdog@12480000 {
++                      compatible = "starfive,si5-wdt";
++                      reg = <0x0 0x12480000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_WDT_CORE>,
++                               <&clkgen JH7100_CLK_WDTIMER_APB>;
++                      clock-names = "wdt_coreclk", "wdtimer_apb";
++                      resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
++                               <&rstgen JH7100_RSTN_WDT>;
++                      reset-names = "wdtimer_apb", "wdt";
++                      interrupts = <80>;
++              };
++
++              ptc: pwm@12490000 {
++                      compatible = "starfive,pwm0";
++                      reg = <0x0 0x12490000 0x0 0x10000>;
++                      reg-names = "control";
++                      clocks = <&clkgen JH7100_CLK_PWM_APB>;
++                      #pwm-cells = <3>;
++                      sifive,approx-period = <100000000>;
++                      sifive,npwm = <8>;
++                      status = "disabled";
++              };
++
++              sfctemp: tmon@124a0000 {
++                      compatible = "starfive,jh7100-temp";
++                      reg = <0x0 0x124a0000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
++                               <&clkgen JH7100_CLK_TEMP_APB>;
++                      clock-names = "sense", "bus";
++                      resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
++                               <&rstgen JH7100_RSTN_TEMP_APB>;
++                      reset-names = "sense", "bus";
++                      interrupts = <122>;
++                      #thermal-sensor-cells = <0>;
++              };
++
++              thermal-zones {
++                      cpu-thermal {
++                              polling-delay-passive = <250>;
++                              polling-delay = <15000>;
++
++                              thermal-sensors = <&sfctemp>;
++
++                              cooling-maps {
++                              };
++
++                              trips {
++                                      cpu_alert0: cpu_alert0 {
++                                              /* milliCelsius */
++                                              temperature = <75000>;
++                                              hysteresis = <2000>;
++                                              type = "passive";
++                                      };
++
++                                      cpu_crit: cpu_crit {
++                                              /* milliCelsius */
++                                              temperature = <90000>;
++                                              hysteresis = <2000>;
++                                              type = "critical";
++                                      };
++                              };
++                      };
++              };
++
++              xrp@f0000000 {
++                      compatible = "cdns,xrp";
++                      reg = <0x0  0xf0000000 0x0 0x01ffffff>,
++                            <0x10 0x72000000 0x0 0x00001000>,
++                            <0x10 0x72001000 0x0 0x00fff000>,
++                            <0x0  0x124b0000 0x0 0x00010000>;
++                      clocks = <&clkgen JH7100_CLK_VP6_CORE>;
++                      interrupts = <27>, <28>;
++                      firmware-name = "vp6_elf";
++                      dsp-irq = <19 20>;
++                      dsp-irq-src = <0x20 0x21>;
++                      intc-irq-mode = <1>;
++                      intc-irq = <0 1>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges = <0x40000000 0x0  0x40000000 0x01000000>,
++                               <0xb0000000 0x10 0x70000000 0x3000000>;
++                      dsp@0 {
++                      };
++              };
+       };
+ };

diff --git a/target/linux/visionfive/patches-5.15/0083-NOT-FOR-UPSTREAM-riscv-Add-StarFive-JH7100-Fedora-de.patch b/target/linux/visionfive/patches-5.15/0083-NOT-FOR-UPSTREAM-riscv-Add-StarFive-JH7100-Fedora-de.patch
new file mode 100644 (file)
index 0000000..b6d590b
--- /dev/null
+++ b/target/linux/visionfive/patches-5.15/0083-NOT-FOR-UPSTREAM-riscv-Add-StarFive-JH7100-Fedora-de.patch
@@ -0,0 +1,3127 @@
+From 76094bdf4ad2da485745fa89e6c5d25c4baae088 Mon Sep 17 00:00:00 2001
+From: Fu Wei <wefu@redhat.com>
+Date: Mon, 15 Nov 2021 23:10:31 +0800
+Subject: [PATCH 83/84] [NOT-FOR-UPSTREAM] riscv: Add StarFive JH7100 Fedora
+ defconfig
+
+Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
+---
+ .../configs/starfive_jh7100_fedora_defconfig  | 3112 +++++++++++++++++
+ 1 file changed, 3112 insertions(+)
+ create mode 100644 arch/riscv/configs/starfive_jh7100_fedora_defconfig
+
+--- /dev/null
++++ b/arch/riscv/configs/starfive_jh7100_fedora_defconfig
+@@ -0,0 +1,3112 @@
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_WATCH_QUEUE=y
++CONFIG_AUDIT=y
++CONFIG_NO_HZ_FULL=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_PREEMPT_VOLUNTARY=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_IKCONFIG=m
++CONFIG_IKCONFIG_PROC=y
++CONFIG_IKHEADERS=m
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CGROUP_HUGETLB=y
++CONFIG_CPUSETS=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_PERF=y
++CONFIG_CGROUP_BPF=y
++CONFIG_NAMESPACES=y
++CONFIG_USER_NS=y
++CONFIG_CHECKPOINT_RESTORE=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_EXPERT=y
++CONFIG_USERFAULTFD=y
++# CONFIG_COMPAT_BRK is not set
++CONFIG_SLAB_FREELIST_RANDOM=y
++CONFIG_SLAB_FREELIST_HARDENED=y
++CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
++CONFIG_PROFILING=y
++CONFIG_SOC_SIFIVE=y
++CONFIG_SOC_STARFIVE=y
++CONFIG_SOC_VIRT=y
++CONFIG_SMP=y
++CONFIG_NR_CPUS=32
++CONFIG_HOTPLUG_CPU=y
++CONFIG_HZ_100=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR_STRONG is not set
++CONFIG_COMPAT_32BIT_TIME=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_SIG_SHA512=y
++CONFIG_MODULE_COMPRESS_XZ=y
++CONFIG_BLK_DEV_ZONED=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_BLK_SED_OPAL=y
++CONFIG_BLK_INLINE_ENCRYPTION=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_AIX_PARTITION=y
++CONFIG_OSF_PARTITION=y
++CONFIG_AMIGA_PARTITION=y
++CONFIG_MAC_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++CONFIG_MINIX_SUBPARTITION=y
++CONFIG_SOLARIS_X86_PARTITION=y
++CONFIG_UNIXWARE_DISKLABEL=y
++CONFIG_LDM_PARTITION=y
++CONFIG_SGI_PARTITION=y
++CONFIG_SUN_PARTITION=y
++CONFIG_KARMA_PARTITION=y
++CONFIG_IOSCHED_BFQ=y
++CONFIG_BFQ_GROUP_IOSCHED=y
++CONFIG_BINFMT_MISC=m
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_KSM=y
++CONFIG_CLEANCACHE=y
++CONFIG_FRONTSWAP=y
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_ZSWAP=y
++CONFIG_Z3FOLD=y
++CONFIG_ZSMALLOC=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=m
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=m
++CONFIG_TLS=m
++CONFIG_TLS_DEVICE=y
++CONFIG_XFRM_USER=y
++CONFIG_XFRM_INTERFACE=m
++CONFIG_XFRM_SUB_POLICY=y
++CONFIG_XFRM_STATISTICS=y
++CONFIG_NET_KEY=m
++CONFIG_NET_KEY_MIGRATE=y
++CONFIG_SMC=m
++CONFIG_SMC_DIAG=m
++CONFIG_XDP_SOCKETS=y
++CONFIG_XDP_SOCKETS_DIAG=m
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_FIB_TRIE_STATS=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_NET_IPIP=m
++CONFIG_NET_IPGRE_DEMUX=m
++CONFIG_NET_IPGRE=m
++CONFIG_NET_IPGRE_BROADCAST=y
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IP_PIMSM_V1=y
++CONFIG_IP_PIMSM_V2=y
++CONFIG_NET_IPVTI=m
++CONFIG_NET_FOU_IP_TUNNELS=y
++CONFIG_INET_AH=m
++CONFIG_INET_ESP=m
++CONFIG_INET_ESP_OFFLOAD=m
++CONFIG_INET_ESPINTCP=y
++CONFIG_INET_IPCOMP=m
++CONFIG_INET_DIAG=m
++CONFIG_INET_UDP_DIAG=m
++CONFIG_INET_RAW_DIAG=m
++CONFIG_INET_DIAG_DESTROY=y
++CONFIG_TCP_CONG_ADVANCED=y
++CONFIG_TCP_CONG_HSTCP=m
++CONFIG_TCP_CONG_HYBLA=m
++CONFIG_TCP_CONG_NV=m
++CONFIG_TCP_CONG_SCALABLE=m
++CONFIG_TCP_CONG_LP=m
++CONFIG_TCP_CONG_VENO=m
++CONFIG_TCP_CONG_YEAH=m
++CONFIG_TCP_CONG_ILLINOIS=m
++CONFIG_TCP_CONG_DCTCP=m
++CONFIG_TCP_CONG_CDG=m
++CONFIG_TCP_CONG_BBR=m
++CONFIG_TCP_MD5SIG=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_ROUTE_INFO=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++CONFIG_INET6_AH=m
++CONFIG_INET6_ESP=m
++CONFIG_INET6_ESP_OFFLOAD=m
++CONFIG_INET6_ESPINTCP=y
++CONFIG_INET6_IPCOMP=m
++CONFIG_IPV6_MIP6=y
++CONFIG_IPV6_ILA=m
++CONFIG_IPV6_VTI=m
++CONFIG_IPV6_SIT=m
++CONFIG_IPV6_SIT_6RD=y
++CONFIG_IPV6_GRE=m
++CONFIG_IPV6_SUBTREES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IPV6_PIMSM_V2=y
++CONFIG_IPV6_SEG6_LWTUNNEL=y
++CONFIG_IPV6_SEG6_HMAC=y
++CONFIG_IPV6_RPL_LWTUNNEL=y
++CONFIG_NETLABEL=y
++CONFIG_MPTCP=y
++CONFIG_NETWORK_PHY_TIMESTAMPING=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_SECMARK=y
++CONFIG_NF_CONNTRACK_ZONES=y
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NF_CONNTRACK_TIMESTAMP=y
++CONFIG_NF_CONNTRACK_AMANDA=m
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SANE=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_FLOW_OFFLOAD=m
++CONFIG_NFT_COUNTER=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_OBJREF=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_COMPAT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_FIB_INET=m
++CONFIG_NFT_XFRM=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_TPROXY=m
++CONFIG_NFT_SYNPROXY=m
++CONFIG_NFT_DUP_NETDEV=m
++CONFIG_NFT_FWD_NETDEV=m
++CONFIG_NFT_FIB_NETDEV=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_NETFILTER_XTABLES=y
++CONFIG_NETFILTER_XT_SET=m
++CONFIG_NETFILTER_XT_TARGET_AUDIT=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
++CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
++CONFIG_NETFILTER_XT_TARGET_DSCP=m
++CONFIG_NETFILTER_XT_TARGET_HMARK=m
++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
++CONFIG_NETFILTER_XT_TARGET_LED=m
++CONFIG_NETFILTER_XT_TARGET_LOG=m
++CONFIG_NETFILTER_XT_TARGET_MARK=m
++CONFIG_NETFILTER_XT_TARGET_NFLOG=m
++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
++CONFIG_NETFILTER_XT_TARGET_TEE=m
++CONFIG_NETFILTER_XT_TARGET_TPROXY=m
++CONFIG_NETFILTER_XT_TARGET_TRACE=m
++CONFIG_NETFILTER_XT_TARGET_SECMARK=m
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
++CONFIG_NETFILTER_XT_MATCH_BPF=m
++CONFIG_NETFILTER_XT_MATCH_CGROUP=m
++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
++CONFIG_NETFILTER_XT_MATCH_COMMENT=m
++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_CPU=m
++CONFIG_NETFILTER_XT_MATCH_DCCP=m
++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
++CONFIG_NETFILTER_XT_MATCH_DSCP=m
++CONFIG_NETFILTER_XT_MATCH_ESP=m
++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_HELPER=m
++CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
++CONFIG_NETFILTER_XT_MATCH_IPVS=m
++CONFIG_NETFILTER_XT_MATCH_LENGTH=m
++CONFIG_NETFILTER_XT_MATCH_LIMIT=m
++CONFIG_NETFILTER_XT_MATCH_MAC=m
++CONFIG_NETFILTER_XT_MATCH_MARK=m
++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
++CONFIG_NETFILTER_XT_MATCH_NFACCT=m
++CONFIG_NETFILTER_XT_MATCH_OSF=m
++CONFIG_NETFILTER_XT_MATCH_OWNER=m
++CONFIG_NETFILTER_XT_MATCH_POLICY=m
++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
++CONFIG_NETFILTER_XT_MATCH_QUOTA=m
++CONFIG_NETFILTER_XT_MATCH_RATEEST=m
++CONFIG_NETFILTER_XT_MATCH_REALM=m
++CONFIG_NETFILTER_XT_MATCH_RECENT=m
++CONFIG_NETFILTER_XT_MATCH_SOCKET=m
++CONFIG_NETFILTER_XT_MATCH_STATE=m
++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
++CONFIG_NETFILTER_XT_MATCH_STRING=m
++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
++CONFIG_NETFILTER_XT_MATCH_TIME=m
++CONFIG_NETFILTER_XT_MATCH_U32=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_IP_VS=m
++CONFIG_IP_VS_IPV6=y
++CONFIG_IP_VS_PROTO_TCP=y
++CONFIG_IP_VS_PROTO_UDP=y
++CONFIG_IP_VS_PROTO_ESP=y
++CONFIG_IP_VS_PROTO_AH=y
++CONFIG_IP_VS_PROTO_SCTP=y
++CONFIG_IP_VS_RR=m
++CONFIG_IP_VS_WRR=m
++CONFIG_IP_VS_LC=m
++CONFIG_IP_VS_WLC=m
++CONFIG_IP_VS_FO=m
++CONFIG_IP_VS_OVF=m
++CONFIG_IP_VS_LBLC=m
++CONFIG_IP_VS_LBLCR=m
++CONFIG_IP_VS_DH=m
++CONFIG_IP_VS_SH=m
++CONFIG_IP_VS_MH=m
++CONFIG_IP_VS_SED=m
++CONFIG_IP_VS_NQ=m
++CONFIG_IP_VS_FTP=m
++CONFIG_IP_VS_PE_SIP=m
++CONFIG_NFT_DUP_IPV4=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_FLOW_TABLE_IPV4=m
++CONFIG_NF_LOG_ARP=m
++CONFIG_NF_LOG_IPV4=m
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_MATCH_AH=m
++CONFIG_IP_NF_MATCH_ECN=m
++CONFIG_IP_NF_MATCH_RPFILTER=m
++CONFIG_IP_NF_MATCH_TTL=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_IP_NF_TARGET_SYNPROXY=m
++CONFIG_IP_NF_NAT=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_TARGET_NETMAP=m
++CONFIG_IP_NF_TARGET_REDIRECT=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP_NF_TARGET_CLUSTERIP=m
++CONFIG_IP_NF_TARGET_ECN=m
++CONFIG_IP_NF_TARGET_TTL=m
++CONFIG_IP_NF_RAW=m
++CONFIG_IP_NF_SECURITY=m
++CONFIG_IP_NF_ARPTABLES=m
++CONFIG_IP_NF_ARPFILTER=m
++CONFIG_IP_NF_ARP_MANGLE=m
++CONFIG_NFT_DUP_IPV6=m
++CONFIG_NFT_FIB_IPV6=m
++CONFIG_NF_FLOW_TABLE_IPV6=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_MATCH_AH=m
++CONFIG_IP6_NF_MATCH_EUI64=m
++CONFIG_IP6_NF_MATCH_FRAG=m
++CONFIG_IP6_NF_MATCH_OPTS=m
++CONFIG_IP6_NF_MATCH_HL=m
++CONFIG_IP6_NF_MATCH_IPV6HEADER=m
++CONFIG_IP6_NF_MATCH_MH=m
++CONFIG_IP6_NF_MATCH_RPFILTER=m
++CONFIG_IP6_NF_MATCH_RT=m
++CONFIG_IP6_NF_MATCH_SRH=m
++CONFIG_IP6_NF_TARGET_HL=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_TARGET_SYNPROXY=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_RAW=m
++CONFIG_IP6_NF_SECURITY=m
++CONFIG_IP6_NF_NAT=m
++CONFIG_IP6_NF_TARGET_MASQUERADE=m
++CONFIG_IP6_NF_TARGET_NPT=m
++CONFIG_NF_TABLES_BRIDGE=m
++CONFIG_NFT_BRIDGE_META=m
++CONFIG_NFT_BRIDGE_REJECT=m
++CONFIG_NF_CONNTRACK_BRIDGE=m
++CONFIG_BRIDGE_NF_EBTABLES=m
++CONFIG_BRIDGE_EBT_BROUTE=m
++CONFIG_BRIDGE_EBT_T_FILTER=m
++CONFIG_BRIDGE_EBT_T_NAT=m
++CONFIG_BRIDGE_EBT_802_3=m
++CONFIG_BRIDGE_EBT_AMONG=m
++CONFIG_BRIDGE_EBT_ARP=m
++CONFIG_BRIDGE_EBT_IP=m
++CONFIG_BRIDGE_EBT_IP6=m
++CONFIG_BRIDGE_EBT_LIMIT=m
++CONFIG_BRIDGE_EBT_MARK=m
++CONFIG_BRIDGE_EBT_PKTTYPE=m
++CONFIG_BRIDGE_EBT_STP=m
++CONFIG_BRIDGE_EBT_VLAN=m
++CONFIG_BRIDGE_EBT_ARPREPLY=m
++CONFIG_BRIDGE_EBT_DNAT=m
++CONFIG_BRIDGE_EBT_MARK_T=m
++CONFIG_BRIDGE_EBT_REDIRECT=m
++CONFIG_BRIDGE_EBT_SNAT=m
++CONFIG_BRIDGE_EBT_LOG=m
++CONFIG_BRIDGE_EBT_NFLOG=m
++CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
++CONFIG_SCTP_COOKIE_HMAC_MD5=y
++CONFIG_RDS=m
++CONFIG_RDS_RDMA=m
++CONFIG_RDS_TCP=m
++CONFIG_TIPC=m
++CONFIG_ATM=m
++CONFIG_ATM_CLIP=m
++CONFIG_ATM_LANE=m
++CONFIG_ATM_BR2684=m
++CONFIG_L2TP=m
++CONFIG_L2TP_DEBUGFS=m
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=m
++CONFIG_L2TP_ETH=m
++CONFIG_BRIDGE=m
++CONFIG_BRIDGE_MRP=y
++CONFIG_NET_DSA=m
++CONFIG_NET_DSA_TAG_GSWIP=m
++CONFIG_NET_DSA_TAG_RTL4_A=m
++CONFIG_NET_DSA_TAG_SJA1105=m
++CONFIG_NET_DSA_TAG_TRAILER=m
++CONFIG_ATALK=m
++CONFIG_DEV_APPLETALK=m
++CONFIG_IPDDP=m
++CONFIG_IPDDP_ENCAP=y
++CONFIG_6LOWPAN=m
++CONFIG_6LOWPAN_DEBUGFS=y
++CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
++CONFIG_6LOWPAN_GHC_UDP=m
++CONFIG_6LOWPAN_GHC_ICMPV6=m
++CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
++CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
++CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
++CONFIG_IEEE802154=m
++CONFIG_IEEE802154_6LOWPAN=m
++CONFIG_MAC802154=m
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_CBQ=m
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_SCH_HFSC=m
++CONFIG_NET_SCH_ATM=m
++CONFIG_NET_SCH_PRIO=m
++CONFIG_NET_SCH_MULTIQ=m
++CONFIG_NET_SCH_RED=m
++CONFIG_NET_SCH_SFB=m
++CONFIG_NET_SCH_SFQ=m
++CONFIG_NET_SCH_TEQL=m
++CONFIG_NET_SCH_TBF=m
++CONFIG_NET_SCH_CBS=m
++CONFIG_NET_SCH_ETF=m
++CONFIG_NET_SCH_TAPRIO=m
++CONFIG_NET_SCH_GRED=m
++CONFIG_NET_SCH_DSMARK=m
++CONFIG_NET_SCH_NETEM=m
++CONFIG_NET_SCH_DRR=m
++CONFIG_NET_SCH_MQPRIO=m
++CONFIG_NET_SCH_CHOKE=m
++CONFIG_NET_SCH_QFQ=m
++CONFIG_NET_SCH_CODEL=m
++CONFIG_NET_SCH_FQ_CODEL=y
++CONFIG_NET_SCH_CAKE=m
++CONFIG_NET_SCH_FQ=m
++CONFIG_NET_SCH_HHF=m
++CONFIG_NET_SCH_PIE=m
++CONFIG_NET_SCH_INGRESS=m
++CONFIG_NET_SCH_PLUG=m
++CONFIG_NET_SCH_ETS=m
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_TCINDEX=m
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_U32=m
++CONFIG_CLS_U32_PERF=y
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_RSVP=m
++CONFIG_NET_CLS_RSVP6=m
++CONFIG_NET_CLS_FLOW=m
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_BPF=m
++CONFIG_NET_CLS_FLOWER=m
++CONFIG_NET_CLS_MATCHALL=m
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_CMP=m
++CONFIG_NET_EMATCH_NBYTE=m
++CONFIG_NET_EMATCH_U32=m
++CONFIG_NET_EMATCH_META=m
++CONFIG_NET_EMATCH_TEXT=m
++CONFIG_NET_EMATCH_CANID=m
++CONFIG_NET_EMATCH_IPSET=m
++CONFIG_NET_EMATCH_IPT=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=m
++CONFIG_NET_ACT_GACT=m
++CONFIG_GACT_PROB=y
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NET_ACT_SAMPLE=m
++CONFIG_NET_ACT_IPT=m
++CONFIG_NET_ACT_NAT=m
++CONFIG_NET_ACT_PEDIT=m
++CONFIG_NET_ACT_SIMP=m
++CONFIG_NET_ACT_SKBEDIT=m
++CONFIG_NET_ACT_CSUM=m
++CONFIG_NET_ACT_MPLS=m
++CONFIG_NET_ACT_VLAN=m
++CONFIG_NET_ACT_BPF=m
++CONFIG_NET_ACT_CONNMARK=m
++CONFIG_NET_ACT_CTINFO=m
++CONFIG_NET_ACT_SKBMOD=m
++CONFIG_NET_ACT_IFE=m
++CONFIG_NET_ACT_TUNNEL_KEY=m
++CONFIG_NET_ACT_CT=m
++CONFIG_NET_ACT_GATE=m
++CONFIG_NET_IFE_SKBMARK=m
++CONFIG_NET_IFE_SKBPRIO=m
++CONFIG_NET_IFE_SKBTCINDEX=m
++CONFIG_NET_TC_SKB_EXT=y
++CONFIG_DCB=y
++CONFIG_BATMAN_ADV=m
++CONFIG_BATMAN_ADV_NC=y
++CONFIG_BATMAN_ADV_TRACING=y
++CONFIG_OPENVSWITCH=m
++CONFIG_VSOCKETS=m
++CONFIG_VIRTIO_VSOCKETS=m
++CONFIG_NETLINK_DIAG=m
++CONFIG_MPLS_ROUTING=m
++CONFIG_MPLS_IPTUNNEL=m
++CONFIG_QRTR_SMD=m
++CONFIG_QRTR_TUN=m
++CONFIG_NET_NCSI=y
++CONFIG_NCSI_OEM_CMD_GET_MAC=y
++CONFIG_CGROUP_NET_PRIO=y
++CONFIG_BPF_STREAM_PARSER=y
++CONFIG_NET_PKTGEN=m
++CONFIG_NET_DROP_MONITOR=y
++CONFIG_HAMRADIO=y
++CONFIG_AX25=m
++CONFIG_NETROM=m
++CONFIG_ROSE=m
++CONFIG_MKISS=m
++CONFIG_6PACK=m
++CONFIG_BPQETHER=m
++CONFIG_BAYCOM_SER_FDX=m
++CONFIG_BAYCOM_SER_HDX=m
++CONFIG_YAM=m
++CONFIG_CAN=m
++CONFIG_CAN_VCAN=m
++CONFIG_CAN_VXCAN=m
++CONFIG_CAN_SLCAN=m
++CONFIG_CAN_C_CAN=m
++CONFIG_CAN_C_CAN_PLATFORM=m
++CONFIG_CAN_C_CAN_PCI=m
++CONFIG_CAN_CC770=m
++CONFIG_CAN_CC770_PLATFORM=m
++CONFIG_CAN_IFI_CANFD=m
++CONFIG_CAN_M_CAN=m
++CONFIG_CAN_PEAK_PCIEFD=m
++CONFIG_CAN_SJA1000=m
++CONFIG_CAN_EMS_PCI=m
++CONFIG_CAN_KVASER_PCI=m
++CONFIG_CAN_PEAK_PCI=m
++CONFIG_CAN_PLX_PCI=m
++CONFIG_CAN_SJA1000_PLATFORM=m
++CONFIG_CAN_SOFTING=m
++CONFIG_CAN_HI311X=m
++CONFIG_CAN_8DEV_USB=m
++CONFIG_CAN_EMS_USB=m
++CONFIG_CAN_ESD_USB2=m
++CONFIG_CAN_GS_USB=m
++CONFIG_CAN_KVASER_USB=m
++CONFIG_CAN_MCBA_USB=m
++CONFIG_CAN_PEAK_USB=m
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_HS=y
++CONFIG_BT_6LOWPAN=m
++CONFIG_BT_LEDS=y
++CONFIG_BT_MSFTEXT=y
++# CONFIG_BT_DEBUGFS is not set
++CONFIG_BT_HCIBTUSB=m
++CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
++CONFIG_BT_HCIBTSDIO=m
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_BCSP=y
++CONFIG_BT_HCIUART_ATH3K=y
++CONFIG_BT_HCIUART_LL=y
++CONFIG_BT_HCIUART_3WIRE=y
++CONFIG_BT_HCIUART_INTEL=y
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_BT_HCIUART_QCA=y
++CONFIG_BT_HCIUART_AG6XX=y
++CONFIG_BT_HCIUART_MRVL=y
++CONFIG_BT_HCIBCM203X=m
++CONFIG_BT_HCIBPA10X=m
++CONFIG_BT_HCIBFUSB=m
++CONFIG_BT_HCIDTL1=m
++CONFIG_BT_HCIBT3C=m
++CONFIG_BT_HCIBLUECARD=m
++CONFIG_BT_HCIVHCI=m
++CONFIG_BT_MRVL=m
++CONFIG_BT_MRVL_SDIO=m
++CONFIG_BT_ATH3K=m
++CONFIG_BT_MTKSDIO=m
++CONFIG_AF_RXRPC_IPV6=y
++CONFIG_AF_RXRPC_DEBUG=y
++CONFIG_RXKAD=y
++CONFIG_AF_KCM=m
++CONFIG_CFG80211=m
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_MAC80211=m
++CONFIG_MAC80211_MESH=y
++CONFIG_RFKILL=m
++CONFIG_RFKILL_GPIO=m
++CONFIG_NET_9P=m
++CONFIG_NET_9P_VIRTIO=m
++CONFIG_NET_9P_RDMA=m
++CONFIG_NFC=m
++CONFIG_NFC_DIGITAL=m
++CONFIG_NFC_NCI=m
++CONFIG_NFC_NCI_SPI=m
++CONFIG_NFC_HCI=m
++CONFIG_NFC_SHDLC=y
++CONFIG_NFC_TRF7970A=m
++CONFIG_NFC_SIM=m
++CONFIG_NFC_PORT100=m
++CONFIG_NFC_PN544_I2C=m
++CONFIG_NFC_PN533_USB=m
++CONFIG_NFC_PN533_I2C=m
++CONFIG_NFC_MICROREAD_I2C=m
++CONFIG_NFC_MRVL_USB=m
++CONFIG_NFC_ST21NFCA_I2C=m
++CONFIG_NFC_NXP_NCI=m
++CONFIG_NFC_NXP_NCI_I2C=m
++CONFIG_PCI=y
++CONFIG_PCIEPORTBUS=y
++CONFIG_HOTPLUG_PCI_PCIE=y
++CONFIG_PCIEAER=y
++CONFIG_PCIEAER_INJECT=m
++CONFIG_PCIE_ECRC=y
++CONFIG_PCIE_DPC=y
++CONFIG_PCIE_PTM=y
++CONFIG_PCI_STUB=y
++CONFIG_PCI_PF_STUB=m
++CONFIG_PCI_IOV=y
++CONFIG_PCI_PRI=y
++CONFIG_PCI_PASID=y
++CONFIG_HOTPLUG_PCI=y
++CONFIG_PCI_HOST_GENERIC=y
++CONFIG_PCIE_XILINX=y
++CONFIG_PCI_J721E_HOST=y
++CONFIG_PCI_SW_SWITCHTEC=m
++CONFIG_PCCARD=y
++CONFIG_YENTA=m
++CONFIG_PD6729=m
++CONFIG_I82092=m
++CONFIG_RAPIDIO=m
++CONFIG_RAPIDIO_TSI721=m
++CONFIG_RAPIDIO_DMA_ENGINE=y
++CONFIG_RAPIDIO_ENUM_BASIC=m
++CONFIG_RAPIDIO_CHMAN=m
++CONFIG_RAPIDIO_MPORT_CDEV=m
++CONFIG_RAPIDIO_TSI57X=m
++CONFIG_RAPIDIO_CPS_XX=m
++CONFIG_RAPIDIO_TSI568=m
++CONFIG_RAPIDIO_CPS_GEN2=m
++CONFIG_RAPIDIO_RXS_GEN3=m
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_FW_LOADER_USER_HELPER=y
++CONFIG_FW_LOADER_COMPRESS=y
++CONFIG_DEBUG_DEVRES=y
++CONFIG_CONNECTOR=y
++CONFIG_EFI_TEST=m
++CONFIG_GNSS=m
++CONFIG_GNSS_MTK_SERIAL=m
++CONFIG_GNSS_SIRF_SERIAL=m
++CONFIG_GNSS_UBX_SERIAL=m
++CONFIG_MTD=m
++CONFIG_MTD_BLOCK=m
++CONFIG_MTD_CFI=m
++CONFIG_MTD_CFI_INTELEXT=m
++CONFIG_MTD_CFI_AMDSTD=m
++CONFIG_MTD_CFI_STAA=m
++CONFIG_MTD_PHYSMAP=m
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_BLOCK2MTD=m
++CONFIG_MTD_RAW_NAND=m
++CONFIG_MTD_NAND_CADENCE=m
++CONFIG_MTD_NAND_NANDSIM=m
++CONFIG_MTD_SPI_NOR=m
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++CONFIG_MTD_UBI=m
++CONFIG_OF_OVERLAY=y
++CONFIG_BLK_DEV_NULL_BLK=m
++CONFIG_ZRAM=m
++CONFIG_BLK_DEV_LOOP=m
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
++CONFIG_BLK_DEV_DRBD=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_BLK_DEV_SX8=m
++CONFIG_BLK_DEV_RAM=m
++CONFIG_BLK_DEV_RAM_SIZE=16384
++CONFIG_CDROM_PKTCDVD=m
++CONFIG_ATA_OVER_ETH=m
++CONFIG_VIRTIO_BLK=m
++CONFIG_BLK_DEV_RBD=m
++CONFIG_BLK_DEV_RNBD_CLIENT=m
++CONFIG_BLK_DEV_RNBD_SERVER=m
++CONFIG_BLK_DEV_NVME=m
++CONFIG_NVME_MULTIPATH=y
++CONFIG_NVME_HWMON=y
++CONFIG_NVME_RDMA=m
++CONFIG_NVME_FC=m
++CONFIG_NVME_TCP=m
++CONFIG_NVME_TARGET=m
++CONFIG_NVME_TARGET_PASSTHRU=y
++CONFIG_NVME_TARGET_LOOP=m
++CONFIG_NVME_TARGET_RDMA=m
++CONFIG_NVME_TARGET_FC=m
++CONFIG_NVME_TARGET_FCLOOP=m
++CONFIG_NVME_TARGET_TCP=m
++CONFIG_ENCLOSURE_SERVICES=m
++CONFIG_APDS9802ALS=m
++CONFIG_ISL29003=m
++CONFIG_ISL29020=m
++CONFIG_SENSORS_TSL2550=m
++CONFIG_SENSORS_BH1770=m
++CONFIG_SENSORS_APDS990X=m
++CONFIG_HISI_HIKEY_USB=m
++CONFIG_EEPROM_AT24=m
++CONFIG_EEPROM_LEGACY=m
++CONFIG_EEPROM_MAX6875=m
++CONFIG_EEPROM_IDT_89HPESX=m
++CONFIG_EEPROM_EE1004=m
++CONFIG_SENSORS_LIS3_I2C=m
++CONFIG_ECHO=m
++CONFIG_MISC_ALCOR_PCI=m
++CONFIG_MISC_RTSX_PCI=m
++CONFIG_MISC_RTSX_USB=m
++CONFIG_UACCE=m
++CONFIG_PVPANIC=y
++CONFIG_BLK_DEV_SD=y
++CONFIG_CHR_DEV_ST=m
++CONFIG_BLK_DEV_SR=y
++CONFIG_CHR_DEV_SG=y
++CONFIG_CHR_DEV_SCH=m
++CONFIG_SCSI_ENCLOSURE=m
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++CONFIG_SCSI_FC_ATTRS=m
++CONFIG_SCSI_SAS_ATA=y
++CONFIG_ISCSI_TCP=m
++CONFIG_SCSI_CXGB3_ISCSI=m
++CONFIG_SCSI_CXGB4_ISCSI=m
++CONFIG_SCSI_BNX2_ISCSI=m
++CONFIG_SCSI_BNX2X_FCOE=m
++CONFIG_BE2ISCSI=m
++CONFIG_BLK_DEV_3W_XXXX_RAID=m
++CONFIG_SCSI_HPSA=m
++CONFIG_SCSI_3W_9XXX=m
++CONFIG_SCSI_3W_SAS=m
++CONFIG_SCSI_ACARD=m
++CONFIG_SCSI_AACRAID=m
++CONFIG_SCSI_AIC7XXX=m
++CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
++CONFIG_AIC7XXX_RESET_DELAY_MS=15000
++# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
++# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
++CONFIG_SCSI_AIC79XX=m
++CONFIG_AIC79XX_CMDS_PER_DEVICE=4
++CONFIG_AIC79XX_RESET_DELAY_MS=15000
++# CONFIG_AIC79XX_DEBUG_ENABLE is not set
++# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
++CONFIG_SCSI_MVSAS=m
++# CONFIG_SCSI_MVSAS_DEBUG is not set
++CONFIG_SCSI_MVSAS_TASKLET=y
++CONFIG_SCSI_MVUMI=m
++CONFIG_SCSI_ARCMSR=m
++CONFIG_SCSI_ESAS2R=m
++CONFIG_MEGARAID_NEWGEN=y
++CONFIG_MEGARAID_MM=m
++CONFIG_MEGARAID_MAILBOX=m
++CONFIG_MEGARAID_LEGACY=m
++CONFIG_MEGARAID_SAS=m
++CONFIG_SCSI_MPT2SAS=m
++CONFIG_SCSI_SMARTPQI=m
++CONFIG_SCSI_HPTIOP=m
++CONFIG_SCSI_MYRB=m
++CONFIG_SCSI_MYRS=m
++CONFIG_LIBFC=m
++CONFIG_LIBFCOE=m
++CONFIG_FCOE=m
++CONFIG_SCSI_SNIC=m
++CONFIG_SCSI_DMX3191D=m
++CONFIG_SCSI_FDOMAIN_PCI=m
++CONFIG_SCSI_IPS=m
++CONFIG_SCSI_INITIO=m
++CONFIG_SCSI_INIA100=m
++CONFIG_SCSI_STEX=m
++CONFIG_SCSI_SYM53C8XX_2=m
++CONFIG_SCSI_IPR=m
++CONFIG_SCSI_QLOGIC_1280=m
++CONFIG_SCSI_QLA_FC=m
++CONFIG_TCM_QLA2XXX=m
++CONFIG_SCSI_QLA_ISCSI=m
++CONFIG_QEDI=m
++CONFIG_QEDF=m
++CONFIG_SCSI_DC395x=m
++CONFIG_SCSI_AM53C974=m
++CONFIG_SCSI_WD719X=m
++CONFIG_SCSI_DEBUG=m
++CONFIG_SCSI_PMCRAID=m
++CONFIG_SCSI_PM8001=m
++CONFIG_SCSI_BFA_FC=m
++CONFIG_SCSI_VIRTIO=m
++CONFIG_SCSI_CHELSIO_FCOE=m
++CONFIG_SCSI_DH=y
++CONFIG_SCSI_DH_RDAC=m
++CONFIG_SCSI_DH_HP_SW=m
++CONFIG_SCSI_DH_EMC=m
++CONFIG_SCSI_DH_ALUA=m
++CONFIG_ATA=y
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_MOBILE_LPM_POLICY=3
++CONFIG_SATA_AHCI_PLATFORM=m
++CONFIG_SATA_INIC162X=m
++CONFIG_SATA_ACARD_AHCI=m
++CONFIG_SATA_SIL24=m
++CONFIG_PDC_ADMA=m
++CONFIG_SATA_QSTOR=m
++CONFIG_SATA_SX4=m
++CONFIG_ATA_PIIX=y
++CONFIG_SATA_MV=m
++CONFIG_SATA_NV=m
++CONFIG_SATA_PROMISE=m
++CONFIG_SATA_SIL=m
++CONFIG_SATA_SIS=m
++CONFIG_SATA_SVW=m
++CONFIG_SATA_ULI=m
++CONFIG_SATA_VIA=m
++CONFIG_SATA_VITESSE=m
++CONFIG_PATA_ALI=m
++CONFIG_PATA_AMD=m
++CONFIG_PATA_ARTOP=m
++CONFIG_PATA_ATP867X=m
++CONFIG_PATA_CMD64X=m
++CONFIG_PATA_EFAR=m
++CONFIG_PATA_HPT366=m
++CONFIG_PATA_HPT37X=m
++CONFIG_PATA_HPT3X2N=m
++CONFIG_PATA_HPT3X3=m
++CONFIG_PATA_IT8213=m
++CONFIG_PATA_IT821X=m
++CONFIG_PATA_JMICRON=m
++CONFIG_PATA_MARVELL=m
++CONFIG_PATA_NETCELL=m
++CONFIG_PATA_NINJA32=m
++CONFIG_PATA_NS87415=m
++CONFIG_PATA_OPTIDMA=m
++CONFIG_PATA_PDC2027X=m
++CONFIG_PATA_PDC_OLD=m
++CONFIG_PATA_SERVERWORKS=m
++CONFIG_PATA_SIL680=m
++CONFIG_PATA_VIA=m
++CONFIG_PATA_WINBOND=m
++CONFIG_PATA_CMD640_PCI=m
++CONFIG_PATA_NS87410=m
++CONFIG_PATA_OPTI=m
++CONFIG_PATA_PCMCIA=m
++CONFIG_ATA_GENERIC=m
++CONFIG_MD=y
++CONFIG_BLK_DEV_MD=y
++CONFIG_MD_LINEAR=m
++CONFIG_MD_MULTIPATH=m
++CONFIG_MD_FAULTY=m
++CONFIG_BCACHE=m
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_DEBUG=y
++CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y
++CONFIG_DM_UNSTRIPED=m
++CONFIG_DM_CRYPT=m
++CONFIG_DM_SNAPSHOT=y
++CONFIG_DM_THIN_PROVISIONING=m
++CONFIG_DM_CACHE=m
++CONFIG_DM_WRITECACHE=m
++CONFIG_DM_EBS=m
++CONFIG_DM_CLONE=m
++CONFIG_DM_MIRROR=y
++CONFIG_DM_LOG_USERSPACE=m
++CONFIG_DM_RAID=m
++CONFIG_DM_ZERO=y
++CONFIG_DM_MULTIPATH=m
++CONFIG_DM_MULTIPATH_QL=m
++CONFIG_DM_MULTIPATH_ST=m
++CONFIG_DM_MULTIPATH_HST=m
++CONFIG_DM_DELAY=m
++CONFIG_DM_DUST=m
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_DM_FLAKEY=m
++CONFIG_DM_VERITY=m
++CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
++CONFIG_DM_VERITY_FEC=y
++CONFIG_DM_SWITCH=m
++CONFIG_DM_LOG_WRITES=m
++CONFIG_DM_INTEGRITY=m
++CONFIG_DM_ZONED=m
++CONFIG_TARGET_CORE=m
++CONFIG_TCM_IBLOCK=m
++CONFIG_TCM_FILEIO=m
++CONFIG_TCM_PSCSI=m
++CONFIG_TCM_USER2=m
++CONFIG_LOOPBACK_TARGET=m
++CONFIG_TCM_FC=m
++CONFIG_ISCSI_TARGET=m
++CONFIG_ISCSI_TARGET_CXGB4=m
++CONFIG_SBP_TARGET=m
++CONFIG_FUSION=y
++CONFIG_FUSION_SPI=m
++CONFIG_FUSION_FC=m
++CONFIG_FUSION_SAS=m
++CONFIG_FUSION_MAX_SGE=40
++CONFIG_FUSION_CTL=m
++CONFIG_FUSION_LAN=m
++CONFIG_FUSION_LOGGING=y
++CONFIG_FIREWIRE=m
++CONFIG_FIREWIRE_OHCI=m
++CONFIG_FIREWIRE_SBP2=m
++CONFIG_FIREWIRE_NET=m
++CONFIG_FIREWIRE_NOSY=m
++CONFIG_BONDING=m
++CONFIG_DUMMY=m
++CONFIG_WIREGUARD=m
++CONFIG_EQUALIZER=m
++CONFIG_NET_FC=y
++CONFIG_IFB=m
++CONFIG_NET_TEAM=m
++CONFIG_NET_TEAM_MODE_BROADCAST=m
++CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
++CONFIG_NET_TEAM_MODE_RANDOM=m
++CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
++CONFIG_NET_TEAM_MODE_LOADBALANCE=m
++CONFIG_MACVLAN=m
++CONFIG_MACVTAP=m
++CONFIG_IPVLAN=m
++CONFIG_IPVTAP=m
++CONFIG_VXLAN=m
++CONFIG_GENEVE=m
++CONFIG_BAREUDP=m
++CONFIG_GTP=m
++CONFIG_MACSEC=m
++CONFIG_NETCONSOLE=m
++CONFIG_NETCONSOLE_DYNAMIC=y
++CONFIG_RIONET=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++CONFIG_VIRTIO_NET=m
++CONFIG_NLMON=m
++CONFIG_NET_VRF=m
++CONFIG_VSOCKMON=m
++CONFIG_ATM_TCP=m
++CONFIG_ATM_ENI=m
++CONFIG_ATM_NICSTAR=m
++CONFIG_ATM_HE=m
++CONFIG_ATM_SOLOS=m
++CONFIG_B53_SPI_DRIVER=m
++CONFIG_B53_MDIO_DRIVER=m
++CONFIG_B53_MMAP_DRIVER=m
++CONFIG_B53_SRAB_DRIVER=m
++CONFIG_B53_SERDES=m
++CONFIG_NET_DSA_BCM_SF2=m
++CONFIG_NET_DSA_LOOP=m
++CONFIG_NET_DSA_MT7530=m
++CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
++CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
++CONFIG_NET_DSA_MV88E6XXX=m
++CONFIG_NET_DSA_MV88E6XXX_PTP=y
++CONFIG_NET_DSA_QCA8K=m
++CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
++CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
++CONFIG_PCMCIA_3C574=m
++CONFIG_PCMCIA_3C589=m
++CONFIG_VORTEX=m
++CONFIG_TYPHOON=m
++CONFIG_ADAPTEC_STARFIRE=m
++CONFIG_ET131X=m
++# CONFIG_NET_VENDOR_ALACRITECH is not set
++CONFIG_ACENIC=m
++CONFIG_ALTERA_TSE=m
++CONFIG_AMD8111_ETH=m
++CONFIG_PCNET32=m
++CONFIG_PCMCIA_NMCLAN=m
++CONFIG_ATL2=m
++CONFIG_ATL1=m
++CONFIG_ATL1E=m
++CONFIG_ATL1C=m
++CONFIG_ALX=m
++CONFIG_B44=m
++CONFIG_BCMGENET=m
++CONFIG_TIGON3=m
++CONFIG_BNX2X=m
++CONFIG_BNXT=m
++CONFIG_BNXT_DCB=y
++CONFIG_BNA=m
++CONFIG_MACB=m
++CONFIG_MACB_PCI=m
++# CONFIG_NET_VENDOR_CAVIUM is not set
++CONFIG_CHELSIO_T1=m
++CONFIG_CHELSIO_T1_1G=y
++CONFIG_CHELSIO_T4_DCB=y
++CONFIG_CHELSIO_T4VF=m
++CONFIG_CHELSIO_IPSEC_INLINE=m
++CONFIG_CHELSIO_TLS_DEVICE=m
++CONFIG_ENIC=m
++# CONFIG_NET_VENDOR_CORTINA is not set
++CONFIG_DNET=m
++CONFIG_NET_TULIP=y
++CONFIG_DE2104X=m
++CONFIG_TULIP=m
++CONFIG_TULIP_MMIO=y
++CONFIG_WINBOND_840=m
++CONFIG_DM9102=m
++CONFIG_ULI526X=m
++CONFIG_PCMCIA_XIRCOM=m
++CONFIG_DL2K=m
++CONFIG_SUNDANCE=m
++# CONFIG_BE2NET_HWMON is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FUJITSU is not set
++# CONFIG_NET_VENDOR_HUAWEI is not set
++# CONFIG_NET_VENDOR_I825XX is not set
++CONFIG_E100=m
++CONFIG_E1000=m
++CONFIG_E1000E=m
++CONFIG_IGB=m
++CONFIG_IGBVF=m
++CONFIG_IXGB=m
++CONFIG_IXGBE=m
++CONFIG_IXGBE_DCB=y
++CONFIG_IXGBEVF=m
++CONFIG_I40E=m
++CONFIG_I40EVF=m
++CONFIG_ICE=m
++CONFIG_FM10K=m
++CONFIG_IGC=m
++CONFIG_JME=m
++CONFIG_MVMDIO=m
++CONFIG_SKGE=m
++CONFIG_SKGE_GENESIS=y
++CONFIG_SKY2=m
++CONFIG_MLX4_EN=m
++CONFIG_MLX5_CORE=m
++CONFIG_MLX5_CORE_EN=y
++CONFIG_MLX5_CORE_IPOIB=y
++CONFIG_MLX5_IPSEC=y
++CONFIG_MLX5_EN_IPSEC=y
++CONFIG_MLXSW_CORE=m
++CONFIG_KSZ884X_PCI=m
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_MICROSEMI is not set
++CONFIG_MYRI10GE=m
++CONFIG_FEALNX=m
++CONFIG_NATSEMI=m
++CONFIG_NS83820=m
++CONFIG_S2IO=m
++CONFIG_VXGE=m
++CONFIG_NFP=m
++# CONFIG_NFP_APP_ABM_NIC is not set
++# CONFIG_NET_VENDOR_NI is not set
++CONFIG_PCMCIA_AXNET=m
++CONFIG_NE2K_PCI=m
++CONFIG_PCMCIA_PCNET=m
++CONFIG_FORCEDETH=m
++CONFIG_ETHOC=m
++CONFIG_HAMACHI=m
++CONFIG_YELLOWFIN=m
++CONFIG_IONIC=m
++CONFIG_QLA3XXX=m
++CONFIG_QLCNIC=m
++CONFIG_NETXEN_NIC=m
++CONFIG_QED=m
++CONFIG_QEDE=m
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_R6040=m
++CONFIG_8139CP=m
++CONFIG_8139TOO=m
++# CONFIG_8139TOO_PIO is not set
++CONFIG_8139TOO_8129=y
++CONFIG_R8169=m
++# CONFIG_NET_VENDOR_RENESAS is not set
++CONFIG_ROCKER=m
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SOLARFLARE is not set
++CONFIG_SC92031=m
++CONFIG_SIS900=m
++CONFIG_SIS190=m
++CONFIG_PCMCIA_SMC91C92=m
++CONFIG_EPIC100=m
++CONFIG_SMSC911X=m
++CONFIG_SMSC9420=m
++# CONFIG_NET_VENDOR_SOCIONEXT is not set
++CONFIG_STMMAC_ETH=y
++CONFIG_DWMAC_DWC_QOS_ETH=m
++CONFIG_DWMAC_GENERIC=m
++CONFIG_DWMAC_INTEL_PLAT=m
++CONFIG_STMMAC_PCI=y
++CONFIG_HAPPYMEAL=m
++CONFIG_SUNGEM=m
++CONFIG_CASSINI=m
++CONFIG_NIU=m
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++CONFIG_TEHUTI=m
++CONFIG_TLAN=m
++CONFIG_VIA_RHINE=m
++CONFIG_VIA_RHINE_MMIO=y
++CONFIG_VIA_VELOCITY=m
++CONFIG_WIZNET_W5100=m
++CONFIG_WIZNET_W5300=m
++CONFIG_WIZNET_W5100_SPI=m
++CONFIG_XILINX_LL_TEMAC=m
++CONFIG_PCMCIA_XIRC2PS=m
++CONFIG_LED_TRIGGER_PHY=y
++CONFIG_SFP=m
++CONFIG_AMD_PHY=m
++CONFIG_ADIN_PHY=m
++CONFIG_AQUANTIA_PHY=m
++CONFIG_BROADCOM_PHY=m
++CONFIG_BCM54140_PHY=m
++CONFIG_BCM87XX_PHY=m
++CONFIG_CICADA_PHY=m
++CONFIG_CORTINA_PHY=m
++CONFIG_DAVICOM_PHY=m
++CONFIG_ICPLUS_PHY=m
++CONFIG_LXT_PHY=m
++CONFIG_INTEL_XWAY_PHY=m
++CONFIG_LSI_ET1011C_PHY=m
++CONFIG_MARVELL_PHY=y
++CONFIG_MARVELL_10G_PHY=m
++CONFIG_MICREL_PHY=m
++CONFIG_MICROSEMI_PHY=m
++CONFIG_NATIONAL_PHY=m
++CONFIG_AT803X_PHY=m
++CONFIG_QSEMI_PHY=m
++CONFIG_REALTEK_PHY=y
++CONFIG_STE10XP=m
++CONFIG_TERANETICS_PHY=m
++CONFIG_DP83822_PHY=m
++CONFIG_DP83848_PHY=m
++CONFIG_DP83869_PHY=m
++CONFIG_VITESSE_PHY=m
++CONFIG_XILINX_GMII2RGMII=m
++CONFIG_MDIO_BITBANG=m
++CONFIG_MDIO_MVUSB=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_PPP_MULTILINK=y
++CONFIG_PPPOATM=m
++CONFIG_PPPOE=m
++CONFIG_PPTP=m
++CONFIG_PPPOL2TP=m
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_SLIP=m
++CONFIG_SLIP_COMPRESSED=y
++CONFIG_SLIP_SMART=y
++CONFIG_USB_CATC=m
++CONFIG_USB_KAWETH=m
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_LAN78XX=m
++CONFIG_USB_NET_CDC_EEM=m
++CONFIG_USB_NET_HUAWEI_CDC_NCM=m
++CONFIG_USB_NET_CDC_MBIM=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_SR9700=m
++CONFIG_USB_NET_SMSC75XX=m
++CONFIG_USB_NET_SMSC95XX=m
++CONFIG_USB_NET_GL620A=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_USB_ALI_M5632=y
++CONFIG_USB_AN2720=y
++CONFIG_USB_EPSON2888=y
++CONFIG_USB_KC2190=y
++CONFIG_USB_NET_CX82310_ETH=m
++CONFIG_USB_NET_KALMIA=m
++CONFIG_USB_NET_QMI_WWAN=m
++CONFIG_USB_HSO=m
++CONFIG_USB_NET_INT51X1=m
++CONFIG_USB_IPHETH=m
++CONFIG_USB_SIERRA_NET=m
++CONFIG_USB_VL600=m
++CONFIG_USB_NET_CH9200=m
++CONFIG_USB_NET_AQC111=m
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++CONFIG_ATH5K=m
++CONFIG_ATH5K_DEBUG=y
++CONFIG_ATH9K=m
++CONFIG_ATH9K_AHB=y
++CONFIG_ATH9K_DEBUGFS=y
++CONFIG_ATH9K_PCI_NO_EEPROM=m
++CONFIG_ATH9K_HTC=m
++CONFIG_CARL9170=m
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_SDIO=m
++CONFIG_ATH6KL_USB=m
++CONFIG_ATH6KL_DEBUG=y
++CONFIG_AR5523=m
++CONFIG_WIL6210=m
++CONFIG_ATH10K=m
++CONFIG_ATH10K_PCI=m
++CONFIG_ATH10K_SDIO=m
++CONFIG_ATH10K_USB=m
++CONFIG_ATH10K_DEBUGFS=y
++CONFIG_WCN36XX=m
++CONFIG_ATH11K=m
++CONFIG_ATH11K_AHB=m
++CONFIG_ATH11K_PCI=m
++CONFIG_ATH11K_DEBUGFS=y
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_B43=m
++CONFIG_B43_SDIO=y
++CONFIG_B43LEGACY=m
++# CONFIG_B43LEGACY_DEBUG is not set
++CONFIG_BRCMSMAC=m
++CONFIG_BRCMFMAC=m
++CONFIG_BRCMFMAC_USB=y
++CONFIG_BRCMFMAC_PCIE=y
++# CONFIG_WLAN_VENDOR_CISCO is not set
++CONFIG_IWL4965=m
++CONFIG_IWL3945=m
++CONFIG_IWLEGACY_DEBUG=y
++CONFIG_IWLEGACY_DEBUGFS=y
++CONFIG_IWLWIFI=m
++CONFIG_IWLDVM=m
++CONFIG_IWLMVM=m
++CONFIG_IWLWIFI_DEBUG=y
++CONFIG_IWLWIFI_DEBUGFS=y
++# CONFIG_IWLWIFI_DEVICE_TRACING is not set
++CONFIG_HERMES=m
++CONFIG_HERMES_PRISM=y
++CONFIG_PLX_HERMES=m
++CONFIG_NORTEL_HERMES=m
++CONFIG_PCI_HERMES=m
++CONFIG_PCMCIA_HERMES=m
++CONFIG_ORINOCO_USB=m
++CONFIG_P54_COMMON=m
++CONFIG_P54_USB=m
++CONFIG_P54_PCI=m
++CONFIG_LIBERTAS=m
++CONFIG_LIBERTAS_USB=m
++CONFIG_LIBERTAS_CS=m
++CONFIG_LIBERTAS_SDIO=m
++CONFIG_LIBERTAS_MESH=y
++CONFIG_MWIFIEX=m
++CONFIG_MWIFIEX_SDIO=m
++CONFIG_MWIFIEX_PCIE=m
++CONFIG_MWIFIEX_USB=m
++CONFIG_MWL8K=m
++CONFIG_MT7601U=m
++CONFIG_MT76x0U=m
++CONFIG_MT76x0E=m
++CONFIG_MT76x2E=m
++CONFIG_MT76x2U=m
++CONFIG_MT7603E=m
++CONFIG_MT7615E=m
++CONFIG_MT7663U=m
++CONFIG_MT7663S=m
++CONFIG_MT7915E=m
++CONFIG_RT2X00=m
++CONFIG_RT2400PCI=m
++CONFIG_RT2500PCI=m
++CONFIG_RT61PCI=m
++CONFIG_RT2800PCI=m
++CONFIG_RT2500USB=m
++CONFIG_RT73USB=m
++CONFIG_RT2800USB=m
++CONFIG_RT2800USB_RT3573=y
++CONFIG_RT2800USB_RT53XX=y
++CONFIG_RT2800USB_RT55XX=y
++CONFIG_RT2800USB_UNKNOWN=y
++CONFIG_RT2X00_LIB_DEBUGFS=y
++CONFIG_RTL8180=m
++CONFIG_RTL8187=m
++CONFIG_RTL8192CE=m
++CONFIG_RTL8192SE=m
++CONFIG_RTL8192DE=m
++CONFIG_RTL8723AE=m
++CONFIG_RTL8723BE=m
++CONFIG_RTL8188EE=m
++CONFIG_RTL8192EE=m
++CONFIG_RTL8821AE=m
++CONFIG_RTL8192CU=m
++# CONFIG_RTLWIFI_DEBUG is not set
++CONFIG_RTL8XXXU=m
++CONFIG_RTL8XXXU_UNTESTED=y
++CONFIG_RTW88=m
++CONFIG_RTW88_8822BE=m
++CONFIG_RTW88_8822CE=m
++CONFIG_RTW88_8723DE=m
++CONFIG_RTW88_8821CE=m
++CONFIG_RSI_91X=m
++CONFIG_CW1200=m
++CONFIG_CW1200_WLAN_SDIO=m
++CONFIG_CW1200_WLAN_SPI=m
++CONFIG_WL1251=m
++CONFIG_WL1251_SPI=m
++CONFIG_WL1251_SDIO=m
++CONFIG_WL12XX=m
++CONFIG_WL18XX=m
++CONFIG_WLCORE_SPI=m
++CONFIG_WLCORE_SDIO=m
++CONFIG_ZD1211RW=m
++CONFIG_QTNFMAC_PCIE=m
++CONFIG_MAC80211_HWSIM=m
++CONFIG_USB_NET_RNDIS_WLAN=m
++CONFIG_VIRT_WIFI=m
++CONFIG_IEEE802154_FAKELB=m
++CONFIG_IEEE802154_AT86RF230=m
++CONFIG_IEEE802154_MRF24J40=m
++CONFIG_IEEE802154_CC2520=m
++CONFIG_IEEE802154_ATUSB=m
++CONFIG_IEEE802154_ADF7242=m
++CONFIG_IEEE802154_CA8210=m
++CONFIG_IEEE802154_MCR20A=m
++CONFIG_USB4_NET=m
++CONFIG_NETDEVSIM=m
++CONFIG_INPUT_SPARSEKMAP=m
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_JOYDEV=m
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_QT1050=m
++CONFIG_KEYBOARD_QT1070=m
++CONFIG_KEYBOARD_TM2_TOUCHKEY=m
++CONFIG_MOUSE_PS2_ELANTECH=y
++CONFIG_MOUSE_PS2_SENTELIC=y
++CONFIG_MOUSE_SERIAL=m
++CONFIG_MOUSE_APPLETOUCH=m
++CONFIG_MOUSE_BCM5974=m
++CONFIG_MOUSE_CYAPA=m
++CONFIG_MOUSE_ELAN_I2C=m
++CONFIG_MOUSE_ELAN_I2C_SMBUS=y
++CONFIG_MOUSE_VSXXXAA=m
++CONFIG_MOUSE_SYNAPTICS_I2C=m
++CONFIG_MOUSE_SYNAPTICS_USB=m
++CONFIG_INPUT_JOYSTICK=y
++CONFIG_JOYSTICK_ANALOG=m
++CONFIG_JOYSTICK_A3D=m
++CONFIG_JOYSTICK_ADC=m
++CONFIG_JOYSTICK_ADI=m
++CONFIG_JOYSTICK_COBRA=m
++CONFIG_JOYSTICK_GF2K=m
++CONFIG_JOYSTICK_GRIP=m
++CONFIG_JOYSTICK_GRIP_MP=m
++CONFIG_JOYSTICK_GUILLEMOT=m
++CONFIG_JOYSTICK_INTERACT=m
++CONFIG_JOYSTICK_SIDEWINDER=m
++CONFIG_JOYSTICK_TMDC=m
++CONFIG_JOYSTICK_IFORCE=m
++CONFIG_JOYSTICK_IFORCE_USB=m
++CONFIG_JOYSTICK_IFORCE_232=m
++CONFIG_JOYSTICK_JOYDUMP=m
++CONFIG_JOYSTICK_XPAD=m
++CONFIG_JOYSTICK_XPAD_FF=y
++CONFIG_JOYSTICK_XPAD_LEDS=y
++CONFIG_JOYSTICK_PSXPAD_SPI=m
++CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
++CONFIG_JOYSTICK_PXRC=m
++CONFIG_INPUT_TABLET=y
++CONFIG_TABLET_USB_ACECAD=m
++CONFIG_TABLET_USB_AIPTEK=m
++CONFIG_TABLET_USB_HANWANG=m
++CONFIG_TABLET_USB_KBTAB=m
++CONFIG_TABLET_USB_PEGASUS=m
++CONFIG_TABLET_SERIAL_WACOM4=m
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ATMEL_MXT=m
++CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
++CONFIG_TOUCHSCREEN_CY8CTMA140=m
++CONFIG_TOUCHSCREEN_DYNAPRO=m
++CONFIG_TOUCHSCREEN_EETI=m
++CONFIG_TOUCHSCREEN_EGALAX=m
++CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
++CONFIG_TOUCHSCREEN_FUJITSU=m
++CONFIG_TOUCHSCREEN_ILI210X=m
++CONFIG_TOUCHSCREEN_GUNZE=m
++CONFIG_TOUCHSCREEN_ELAN=m
++CONFIG_TOUCHSCREEN_ELO=m
++CONFIG_TOUCHSCREEN_WACOM_W8001=m
++CONFIG_TOUCHSCREEN_WACOM_I2C=m
++CONFIG_TOUCHSCREEN_MCS5000=m
++CONFIG_TOUCHSCREEN_MMS114=m
++CONFIG_TOUCHSCREEN_MTOUCH=m
++CONFIG_TOUCHSCREEN_INEXIO=m
++CONFIG_TOUCHSCREEN_MK712=m
++CONFIG_TOUCHSCREEN_PENMOUNT=m
++CONFIG_TOUCHSCREEN_EDT_FT5X06=m
++CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
++CONFIG_TOUCHSCREEN_TOUCHWIN=m
++CONFIG_TOUCHSCREEN_PIXCIR=m
++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
++CONFIG_TOUCHSCREEN_TOUCHIT213=m
++CONFIG_TOUCHSCREEN_TSC_SERIO=m
++CONFIG_TOUCHSCREEN_TSC2007=m
++CONFIG_TOUCHSCREEN_TSC2007_IIO=y
++CONFIG_TOUCHSCREEN_RM_TS=m
++CONFIG_TOUCHSCREEN_SILEAD=m
++CONFIG_TOUCHSCREEN_SIS_I2C=m
++CONFIG_TOUCHSCREEN_ST1232=m
++CONFIG_TOUCHSCREEN_ZET6223=m
++CONFIG_TOUCHSCREEN_ZFORCE=m
++CONFIG_TOUCHSCREEN_IQS5XX=m
++CONFIG_TOUCHSCREEN_ZINITIX=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_E3X0_BUTTON=m
++CONFIG_INPUT_MAX77650_ONKEY=m
++CONFIG_INPUT_GPIO_VIBRA=m
++CONFIG_INPUT_ATI_REMOTE2=m
++CONFIG_INPUT_KEYSPAN_REMOTE=m
++CONFIG_INPUT_KXTJ9=m
++CONFIG_INPUT_POWERMATE=m
++CONFIG_INPUT_YEALINK=m
++CONFIG_INPUT_CM109=m
++CONFIG_INPUT_REGULATOR_HAPTIC=m
++CONFIG_INPUT_UINPUT=m
++CONFIG_INPUT_PWM_BEEPER=m
++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
++CONFIG_INPUT_IQS269A=m
++CONFIG_INPUT_CMA3000=m
++CONFIG_INPUT_CMA3000_I2C=m
++CONFIG_RMI4_I2C=m
++CONFIG_RMI4_SPI=m
++CONFIG_RMI4_SMB=m
++CONFIG_RMI4_F34=y
++CONFIG_RMI4_F3A=y
++CONFIG_RMI4_F55=y
++CONFIG_SERIO_RAW=m
++CONFIG_SERIO_ALTERA_PS2=m
++CONFIG_SERIO_ARC_PS2=m
++CONFIG_GAMEPORT_NS558=m
++CONFIG_GAMEPORT_L4=m
++CONFIG_GAMEPORT_EMU10K1=m
++CONFIG_GAMEPORT_FM801=m
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_EXAR=m
++CONFIG_SERIAL_8250_CS=m
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_RUNTIME_UARTS=32
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_8250_RT288X=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
++CONFIG_SERIAL_JSM=m
++CONFIG_SERIAL_SC16IS7XX=m
++# CONFIG_SERIAL_SC16IS7XX_I2C is not set
++CONFIG_SERIAL_SC16IS7XX_SPI=y
++CONFIG_SERIAL_ARC=m
++CONFIG_SERIAL_NONSTANDARD=y
++CONFIG_SYNCLINK_GT=m
++CONFIG_N_HDLC=m
++CONFIG_N_GSM=m
++CONFIG_NOZOMI=m
++CONFIG_NULL_TTY=m
++CONFIG_HVC_RISCV_SBI=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_VIRTIO_CONSOLE=m
++CONFIG_IPMI_HANDLER=m
++CONFIG_IPMI_DEVICE_INTERFACE=m
++CONFIG_IPMI_SSIF=m
++CONFIG_IPMI_WATCHDOG=m
++CONFIG_IPMI_POWEROFF=m
++CONFIG_HW_RANDOM=y
++CONFIG_HW_RANDOM_TIMERIOMEM=m
++CONFIG_HW_RANDOM_VIRTIO=y
++CONFIG_HW_RANDOM_XIPHERA=m
++CONFIG_CARDMAN_4000=m
++CONFIG_CARDMAN_4040=m
++CONFIG_IPWIRELESS=m
++CONFIG_TCG_TIS=y
++CONFIG_TCG_TIS_SPI=m
++CONFIG_TCG_TIS_SPI_CR50=y
++CONFIG_TCG_ATMEL=m
++CONFIG_TCG_VTPM_PROXY=m
++CONFIG_XILLYBUS=m
++CONFIG_XILLYBUS_PCIE=m
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX_GPMUX=m
++CONFIG_I2C_MUX_LTC4306=m
++CONFIG_I2C_MUX_MLXCPLD=m
++CONFIG_I2C_NFORCE2=m
++CONFIG_I2C_NVIDIA_GPU=m
++CONFIG_I2C_DESIGNWARE_SLAVE=y
++CONFIG_I2C_DESIGNWARE_PLATFORM=y
++CONFIG_I2C_DESIGNWARE_PCI=m
++CONFIG_I2C_PCA_PLATFORM=m
++CONFIG_I2C_SIMTEC=m
++CONFIG_I2C_DIOLAN_U2C=m
++CONFIG_I2C_TINY_USB=m
++CONFIG_I2C_VIPERBOARD=m
++CONFIG_I2C_STUB=m
++CONFIG_I2C_SLAVE_EEPROM=m
++CONFIG_SPI=y
++CONFIG_SPI_CADENCE_QUADSPI=y
++CONFIG_SPI_DESIGNWARE=y
++CONFIG_SPI_DW_DMA=y
++CONFIG_SPI_DW_PCI=y
++CONFIG_SPI_DW_MMIO=y
++CONFIG_SPI_FSI=m
++CONFIG_SPI_SIFIVE=y
++CONFIG_SPI_MUX=m
++CONFIG_SPI_SPIDEV=y
++CONFIG_PPS_CLIENT_LDISC=m
++CONFIG_PPS_CLIENT_GPIO=m
++CONFIG_DP83640_PHY=m
++CONFIG_PTP_1588_CLOCK_IDT82P33=m
++CONFIG_PTP_1588_CLOCK_IDTCM=m
++CONFIG_GPIOLIB_FASTPATH_LIMIT=256
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_CADENCE=m
++CONFIG_GPIO_EXAR=m
++CONFIG_GPIO_SIFIVE=y
++CONFIG_GPIO_SYSCON=m
++CONFIG_GPIO_PCA953X=m
++CONFIG_GPIO_PCA9570=m
++CONFIG_GPIO_BD9571MWV=m
++CONFIG_GPIO_MAX77650=m
++CONFIG_GPIO_TPS65086=m
++CONFIG_GPIO_PCI_IDIO_16=m
++CONFIG_GPIO_VIPERBOARD=m
++CONFIG_GPIO_AGGREGATOR=m
++CONFIG_W1=m
++CONFIG_W1_MASTER_DS2490=m
++CONFIG_W1_MASTER_DS2482=m
++CONFIG_W1_SLAVE_THERM=m
++CONFIG_W1_SLAVE_SMEM=m
++CONFIG_W1_SLAVE_DS2405=m
++CONFIG_W1_SLAVE_DS2408=m
++# CONFIG_W1_SLAVE_DS2408_READBACK is not set
++CONFIG_W1_SLAVE_DS2413=m
++CONFIG_W1_SLAVE_DS2406=m
++CONFIG_W1_SLAVE_DS2423=m
++CONFIG_W1_SLAVE_DS2805=m
++CONFIG_W1_SLAVE_DS2430=m
++CONFIG_W1_SLAVE_DS2431=m
++CONFIG_W1_SLAVE_DS2433=m
++CONFIG_W1_SLAVE_DS2433_CRC=y
++CONFIG_W1_SLAVE_DS2438=m
++CONFIG_W1_SLAVE_DS2780=m
++CONFIG_W1_SLAVE_DS2781=m
++CONFIG_W1_SLAVE_DS28E04=m
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_POWER_RESET_GPIO_RESTART=y
++CONFIG_POWER_RESET_RESTART=y
++CONFIG_POWER_RESET_TPS65086=y
++CONFIG_SYSCON_REBOOT_MODE=y
++CONFIG_BATTERY_CW2015=m
++CONFIG_CHARGER_LT3651=m
++CONFIG_CHARGER_MAX77650=m
++CONFIG_CHARGER_BQ2515X=m
++CONFIG_CHARGER_SMB347=m
++CONFIG_CHARGER_UCS1002=m
++CONFIG_CHARGER_BD99954=m
++CONFIG_SENSORS_AD7314=m
++CONFIG_SENSORS_AD7414=m
++CONFIG_SENSORS_AD7418=m
++CONFIG_SENSORS_ADM1021=m
++CONFIG_SENSORS_ADM1025=m
++CONFIG_SENSORS_ADM1026=m
++CONFIG_SENSORS_ADM1029=m
++CONFIG_SENSORS_ADM1031=m
++CONFIG_SENSORS_ADM9240=m
++CONFIG_SENSORS_ADT7310=m
++CONFIG_SENSORS_ADT7410=m
++CONFIG_SENSORS_ADT7411=m
++CONFIG_SENSORS_ADT7462=m
++CONFIG_SENSORS_ADT7470=m
++CONFIG_SENSORS_ADT7475=m
++CONFIG_SENSORS_ASC7621=m
++CONFIG_SENSORS_AXI_FAN_CONTROL=m
++CONFIG_SENSORS_ASPEED=m
++CONFIG_SENSORS_ATXP1=m
++CONFIG_SENSORS_CORSAIR_CPRO=m
++CONFIG_SENSORS_DRIVETEMP=m
++CONFIG_SENSORS_DS620=m
++CONFIG_SENSORS_DS1621=m
++CONFIG_SENSORS_F71805F=m
++CONFIG_SENSORS_F71882FG=m
++CONFIG_SENSORS_F75375S=m
++CONFIG_SENSORS_FTSTEUTATES=m
++CONFIG_SENSORS_GL518SM=m
++CONFIG_SENSORS_GL520SM=m
++CONFIG_SENSORS_G760A=m
++CONFIG_SENSORS_G762=m
++CONFIG_SENSORS_IBMAEM=m
++CONFIG_SENSORS_IBMPEX=m
++CONFIG_SENSORS_IT87=m
++CONFIG_SENSORS_JC42=m
++CONFIG_SENSORS_POWR1220=m
++CONFIG_SENSORS_LINEAGE=m
++CONFIG_SENSORS_LTC2945=m
++CONFIG_SENSORS_LTC2947_I2C=m
++CONFIG_SENSORS_LTC2947_SPI=m
++CONFIG_SENSORS_LTC2990=m
++CONFIG_SENSORS_LTC4151=m
++CONFIG_SENSORS_LTC4215=m
++CONFIG_SENSORS_LTC4222=m
++CONFIG_SENSORS_LTC4245=m
++CONFIG_SENSORS_LTC4260=m
++CONFIG_SENSORS_LTC4261=m
++CONFIG_SENSORS_MAX1111=m
++CONFIG_SENSORS_MAX16065=m
++CONFIG_SENSORS_MAX1619=m
++CONFIG_SENSORS_MAX1668=m
++CONFIG_SENSORS_MAX197=m
++CONFIG_SENSORS_MAX31722=m
++CONFIG_SENSORS_MAX6639=m
++CONFIG_SENSORS_MAX6642=m
++CONFIG_SENSORS_MAX6650=m
++CONFIG_SENSORS_MAX6697=m
++CONFIG_SENSORS_MAX31790=m
++CONFIG_SENSORS_MCP3021=m
++CONFIG_SENSORS_TC654=m
++CONFIG_SENSORS_MR75203=m
++CONFIG_SENSORS_ADCXX=m
++CONFIG_SENSORS_LM63=m
++CONFIG_SENSORS_LM70=m
++CONFIG_SENSORS_LM73=m
++CONFIG_SENSORS_LM75=m
++CONFIG_SENSORS_LM77=m
++CONFIG_SENSORS_LM78=m
++CONFIG_SENSORS_LM80=m
++CONFIG_SENSORS_LM83=m
++CONFIG_SENSORS_LM85=m
++CONFIG_SENSORS_LM87=m
++CONFIG_SENSORS_LM90=m
++CONFIG_SENSORS_LM92=m
++CONFIG_SENSORS_LM93=m
++CONFIG_SENSORS_LM95234=m
++CONFIG_SENSORS_LM95241=m
++CONFIG_SENSORS_LM95245=m
++CONFIG_SENSORS_PC87360=m
++CONFIG_SENSORS_PC87427=m
++CONFIG_SENSORS_NTC_THERMISTOR=m
++CONFIG_SENSORS_NCT6683=m
++CONFIG_SENSORS_NCT6775=m
++CONFIG_SENSORS_NCT7802=m
++CONFIG_SENSORS_NCT7904=m
++CONFIG_SENSORS_NPCM7XX=m
++CONFIG_SENSORS_PCF8591=m
++CONFIG_PMBUS=m
++CONFIG_SENSORS_ADM1266=m
++CONFIG_SENSORS_ADM1275=m
++CONFIG_SENSORS_BEL_PFE=m
++CONFIG_SENSORS_LM25066=m
++CONFIG_SENSORS_LTC2978=m
++CONFIG_SENSORS_LTC3815=m
++CONFIG_SENSORS_MAX16064=m
++CONFIG_SENSORS_MAX20751=m
++CONFIG_SENSORS_MAX34440=m
++CONFIG_SENSORS_MAX8688=m
++CONFIG_SENSORS_MP2975=m
++CONFIG_SENSORS_TPS40422=m
++CONFIG_SENSORS_TPS53679=m
++CONFIG_SENSORS_UCD9000=m
++CONFIG_SENSORS_UCD9200=m
++CONFIG_SENSORS_ZL6100=m
++CONFIG_SENSORS_PWM_FAN=m
++CONFIG_SENSORS_SHT15=m
++CONFIG_SENSORS_SHT21=m
++CONFIG_SENSORS_SHT3x=m
++CONFIG_SENSORS_SHTC1=m
++CONFIG_SENSORS_SIS5595=m
++CONFIG_SENSORS_DME1737=m
++CONFIG_SENSORS_EMC1403=m
++CONFIG_SENSORS_EMC6W201=m
++CONFIG_SENSORS_SMSC47M1=m
++CONFIG_SENSORS_SMSC47M192=m
++CONFIG_SENSORS_SMSC47B397=m
++CONFIG_SENSORS_SCH5627=m
++CONFIG_SENSORS_SCH5636=m
++CONFIG_SENSORS_SFCTEMP=m
++CONFIG_SENSORS_ADC128D818=m
++CONFIG_SENSORS_ADS7828=m
++CONFIG_SENSORS_ADS7871=m
++CONFIG_SENSORS_AMC6821=m
++CONFIG_SENSORS_INA209=m
++CONFIG_SENSORS_INA2XX=m
++CONFIG_SENSORS_INA3221=m
++CONFIG_SENSORS_TC74=m
++CONFIG_SENSORS_THMC50=m
++CONFIG_SENSORS_TMP102=m
++CONFIG_SENSORS_TMP103=m
++CONFIG_SENSORS_TMP108=m
++CONFIG_SENSORS_TMP401=m
++CONFIG_SENSORS_TMP421=m
++CONFIG_SENSORS_TMP513=m
++CONFIG_SENSORS_VIA686A=m
++CONFIG_SENSORS_VT1211=m
++CONFIG_SENSORS_VT8231=m
++CONFIG_SENSORS_W83773G=m
++CONFIG_SENSORS_W83781D=m
++CONFIG_SENSORS_W83791D=m
++CONFIG_SENSORS_W83792D=m
++CONFIG_SENSORS_W83793=m
++CONFIG_SENSORS_W83795=m
++CONFIG_SENSORS_W83L785TS=m
++CONFIG_SENSORS_W83L786NG=m
++CONFIG_SENSORS_W83627HF=m
++CONFIG_SENSORS_W83627EHF=m
++CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
++CONFIG_THERMAL_NETLINK=y
++CONFIG_THERMAL_STATISTICS=y
++# CONFIG_THERMAL_OF is not set
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_CORE=y
++CONFIG_WATCHDOG_SYSFS=y
++CONFIG_SOFT_WATCHDOG=m
++CONFIG_ALIM7101_WDT=m
++CONFIG_I6300ESB_WDT=m
++CONFIG_STARFIVE_WATCHDOG=m
++CONFIG_PCIPCWATCHDOG=m
++CONFIG_WDTPCI=m
++CONFIG_USBPCWATCHDOG=m
++CONFIG_SSB_PCMCIAHOST=y
++CONFIG_SSB_DRIVER_GPIO=y
++CONFIG_BCMA_DRIVER_GMAC_CMN=y
++CONFIG_BCMA_DRIVER_GPIO=y
++CONFIG_MFD_BD9571MWV=m
++CONFIG_MFD_MAX77650=m
++CONFIG_MFD_VIPERBOARD=m
++CONFIG_MFD_SM501=m
++CONFIG_MFD_SM501_GPIO=y
++CONFIG_MFD_TPS65086=y
++CONFIG_MFD_VX855=m
++CONFIG_MFD_INTEL_M10_BMC=m
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=m
++CONFIG_REGULATOR_BD9571MWV=m
++CONFIG_REGULATOR_MAX77650=m
++CONFIG_REGULATOR_MP5416=m
++CONFIG_REGULATOR_MP886X=m
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_RT4801=m
++CONFIG_REGULATOR_RTMV20=m
++CONFIG_REGULATOR_VCTRL=m
++CONFIG_RC_CORE=y
++CONFIG_RC_MAP=m
++CONFIG_LIRC=y
++CONFIG_BPF_LIRC_MODE2=y
++CONFIG_RC_DECODERS=y
++CONFIG_IR_NEC_DECODER=m
++CONFIG_IR_RC5_DECODER=m
++CONFIG_IR_RC6_DECODER=m
++CONFIG_IR_JVC_DECODER=m
++CONFIG_IR_SONY_DECODER=m
++CONFIG_IR_SANYO_DECODER=m
++CONFIG_IR_SHARP_DECODER=m
++CONFIG_IR_MCE_KBD_DECODER=m
++CONFIG_IR_XMP_DECODER=m
++CONFIG_IR_IMON_DECODER=m
++CONFIG_IR_RCMM_DECODER=m
++CONFIG_RC_DEVICES=y
++CONFIG_RC_ATI_REMOTE=m
++CONFIG_IR_HIX5HD2=m
++CONFIG_IR_IMON=m
++CONFIG_IR_IMON_RAW=m
++CONFIG_IR_MCEUSB=m
++CONFIG_IR_REDRAT3=m
++CONFIG_IR_SPI=m
++CONFIG_IR_STREAMZAP=m
++CONFIG_IR_IGORPLUGUSB=m
++CONFIG_IR_IGUANA=m
++CONFIG_IR_TTUSBIR=m
++CONFIG_RC_LOOPBACK=m
++CONFIG_IR_GPIO_CIR=m
++CONFIG_IR_GPIO_TX=m
++CONFIG_IR_PWM_TX=m
++CONFIG_IR_SERIAL=m
++CONFIG_IR_SERIAL_TRANSMITTER=y
++CONFIG_RC_XBOX_DVD=m
++CONFIG_IR_TOY=m
++CONFIG_MEDIA_CEC_RC=y
++CONFIG_CEC_CH7322=m
++CONFIG_USB_PULSE8_CEC=m
++CONFIG_USB_RAINSHADOW_CEC=m
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_PWC=m
++CONFIG_VIDEO_CPIA2=m
++CONFIG_USB_ZR364XX=m
++CONFIG_USB_STKWEBCAM=m
++CONFIG_USB_S2255=m
++CONFIG_VIDEO_USBTV=m
++CONFIG_VIDEO_PVRUSB2=m
++CONFIG_VIDEO_HDPVR=m
++CONFIG_VIDEO_STK1160_COMMON=m
++CONFIG_VIDEO_GO7007=m
++CONFIG_VIDEO_GO7007_USB=m
++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
++CONFIG_VIDEO_AU0828=m
++CONFIG_VIDEO_CX231XX=m
++CONFIG_VIDEO_CX231XX_ALSA=m
++CONFIG_VIDEO_CX231XX_DVB=m
++CONFIG_VIDEO_TM6000=m
++CONFIG_VIDEO_TM6000_ALSA=m
++CONFIG_VIDEO_TM6000_DVB=m
++CONFIG_DVB_USB=m
++CONFIG_DVB_USB_A800=m
++CONFIG_DVB_USB_DIBUSB_MB=m
++CONFIG_DVB_USB_DIBUSB_MC=m
++CONFIG_DVB_USB_DIB0700=m
++CONFIG_DVB_USB_UMT_010=m
++CONFIG_DVB_USB_CXUSB=m
++CONFIG_DVB_USB_CXUSB_ANALOG=y
++CONFIG_DVB_USB_M920X=m
++CONFIG_DVB_USB_DIGITV=m
++CONFIG_DVB_USB_VP7045=m
++CONFIG_DVB_USB_VP702X=m
++CONFIG_DVB_USB_GP8PSK=m
++CONFIG_DVB_USB_NOVA_T_USB2=m
++CONFIG_DVB_USB_TTUSB2=m
++CONFIG_DVB_USB_DTT200U=m
++CONFIG_DVB_USB_OPERA1=m
++CONFIG_DVB_USB_AF9005=m
++CONFIG_DVB_USB_AF9005_REMOTE=m
++CONFIG_DVB_USB_PCTV452E=m
++CONFIG_DVB_USB_DW2102=m
++CONFIG_DVB_USB_CINERGY_T2=m
++CONFIG_DVB_USB_DTV5100=m
++CONFIG_DVB_USB_AZ6027=m
++CONFIG_DVB_USB_TECHNISAT_USB2=m
++CONFIG_DVB_USB_V2=m
++CONFIG_DVB_USB_AF9015=m
++CONFIG_DVB_USB_AF9035=m
++CONFIG_DVB_USB_ANYSEE=m
++CONFIG_DVB_USB_AU6610=m
++CONFIG_DVB_USB_AZ6007=m
++CONFIG_DVB_USB_CE6230=m
++CONFIG_DVB_USB_EC168=m
++CONFIG_DVB_USB_GL861=m
++CONFIG_DVB_USB_LME2510=m
++CONFIG_DVB_USB_MXL111SF=m
++CONFIG_DVB_USB_RTL28XXU=m
++CONFIG_DVB_USB_DVBSKY=m
++CONFIG_DVB_USB_ZD1301=m
++CONFIG_DVB_TTUSB_BUDGET=m
++CONFIG_DVB_TTUSB_DEC=m
++CONFIG_SMS_USB_DRV=m
++CONFIG_DVB_B2C2_FLEXCOP_USB=m
++CONFIG_DVB_AS102=m
++CONFIG_VIDEO_EM28XX=m
++CONFIG_VIDEO_EM28XX_V4L2=m
++CONFIG_VIDEO_EM28XX_ALSA=m
++CONFIG_VIDEO_EM28XX_DVB=m
++CONFIG_MEDIA_PCI_SUPPORT=y
++CONFIG_VIDEO_SOLO6X10=m
++CONFIG_VIDEO_TW686X=m
++CONFIG_VIDEO_IVTV=m
++CONFIG_VIDEO_FB_IVTV=m
++CONFIG_VIDEO_HEXIUM_GEMINI=m
++CONFIG_VIDEO_HEXIUM_ORION=m
++CONFIG_VIDEO_MXB=m
++CONFIG_VIDEO_CX18=m
++CONFIG_VIDEO_CX18_ALSA=m
++CONFIG_VIDEO_CX23885=m
++CONFIG_MEDIA_ALTERA_CI=m
++CONFIG_VIDEO_CX88=m
++CONFIG_VIDEO_CX88_ALSA=m
++CONFIG_VIDEO_CX88_BLACKBIRD=m
++CONFIG_VIDEO_CX88_DVB=m
++CONFIG_VIDEO_BT848=m
++CONFIG_DVB_BT8XX=m
++CONFIG_VIDEO_SAA7134=m
++CONFIG_VIDEO_SAA7134_ALSA=m
++CONFIG_VIDEO_SAA7134_DVB=m
++CONFIG_VIDEO_SAA7134_GO7007=m
++CONFIG_VIDEO_SAA7164=m
++CONFIG_DVB_BUDGET_CORE=m
++CONFIG_DVB_BUDGET=m
++CONFIG_DVB_BUDGET_CI=m
++CONFIG_DVB_BUDGET_AV=m
++CONFIG_DVB_B2C2_FLEXCOP_PCI=m
++CONFIG_DVB_PLUTO2=m
++CONFIG_DVB_DM1105=m
++CONFIG_DVB_PT1=m
++CONFIG_MANTIS_CORE=m
++CONFIG_DVB_MANTIS=m
++CONFIG_DVB_HOPPER=m
++CONFIG_DVB_NGENE=m
++CONFIG_DVB_DDBRIDGE=m
++CONFIG_DVB_SMIPCIE=m
++CONFIG_DVB_NETUP_UNIDVB=m
++CONFIG_RADIO_SI470X=m
++CONFIG_USB_SI470X=m
++CONFIG_I2C_SI470X=m
++CONFIG_RADIO_SI4713=m
++CONFIG_USB_MR800=m
++CONFIG_USB_DSBR=m
++CONFIG_RADIO_MAXIRADIO=m
++CONFIG_RADIO_SHARK=m
++CONFIG_RADIO_SHARK2=m
++CONFIG_USB_KEENE=m
++CONFIG_USB_MA901=m
++CONFIG_RADIO_TEA5764=m
++CONFIG_RADIO_SAA7706H=m
++CONFIG_RADIO_WL1273=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_SMS_SDIO_DRV=m
++CONFIG_DVB_FIREDTV=m
++CONFIG_VIDEO_HI556=m
++CONFIG_VIDEO_IMX214=m
++CONFIG_VIDEO_IMX219=m
++CONFIG_VIDEO_IMX258=m
++CONFIG_VIDEO_IMX274=m
++CONFIG_VIDEO_IMX290=m
++CONFIG_VIDEO_IMX319=m
++CONFIG_VIDEO_IMX355=m
++CONFIG_VIDEO_OV2659=m
++CONFIG_VIDEO_OV2680=m
++CONFIG_VIDEO_OV2685=m
++CONFIG_VIDEO_OV5640=m
++CONFIG_VIDEO_OV5645=m
++CONFIG_VIDEO_OV5647=m
++CONFIG_VIDEO_OV6650=m
++CONFIG_VIDEO_OV5670=m
++CONFIG_VIDEO_OV5675=m
++CONFIG_VIDEO_OV5695=m
++CONFIG_VIDEO_OV7251=m
++CONFIG_VIDEO_OV772X=m
++CONFIG_VIDEO_OV7670=m
++CONFIG_VIDEO_OV7740=m
++CONFIG_VIDEO_OV8856=m
++CONFIG_VIDEO_OV9640=m
++CONFIG_VIDEO_OV9650=m
++CONFIG_VIDEO_OV13858=m
++CONFIG_VIDEO_VS6624=m
++CONFIG_VIDEO_MT9M001=m
++CONFIG_VIDEO_MT9M032=m
++CONFIG_VIDEO_MT9P031=m
++CONFIG_VIDEO_MT9T001=m
++CONFIG_VIDEO_MT9T112=m
++CONFIG_VIDEO_MT9V032=m
++CONFIG_VIDEO_MT9V111=m
++CONFIG_VIDEO_SR030PC30=m
++CONFIG_VIDEO_NOON010PC30=m
++CONFIG_VIDEO_M5MOLS=m
++CONFIG_VIDEO_RDACM20=m
++CONFIG_VIDEO_RJ54N1=m
++CONFIG_VIDEO_S5K6AA=m
++CONFIG_VIDEO_S5K6A3=m
++CONFIG_VIDEO_S5K4ECGX=m
++CONFIG_VIDEO_S5K5BAF=m
++CONFIG_VIDEO_ET8EK8=m
++CONFIG_VIDEO_S5C73M3=m
++CONFIG_VIDEO_AD5820=m
++CONFIG_VIDEO_AK7375=m
++CONFIG_VIDEO_DW9714=m
++CONFIG_VIDEO_DW9768=m
++CONFIG_VIDEO_DW9807_VCM=m
++CONFIG_VIDEO_ADP1653=m
++CONFIG_VIDEO_LM3560=m
++CONFIG_VIDEO_LM3646=m
++CONFIG_DRM=y
++CONFIG_DRM_DP_AUX_CHARDEV=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_DP_CEC=y
++CONFIG_DRM_I2C_NXP_TDA998X=y
++CONFIG_DRM_I2C_NXP_TDA9950=y
++CONFIG_DRM_RADEON=m
++CONFIG_DRM_RADEON_USERPTR=y
++CONFIG_DRM_AMDGPU=m
++CONFIG_DRM_AMDGPU_SI=y
++CONFIG_DRM_AMDGPU_CIK=y
++CONFIG_DRM_AMDGPU_USERPTR=y
++CONFIG_DRM_AMD_ACP=y
++CONFIG_DRM_AMD_DC_HDCP=y
++CONFIG_DRM_AMD_DC_SI=y
++CONFIG_DRM_NOUVEAU=m
++# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set
++CONFIG_DRM_VGEM=m
++CONFIG_DRM_UDL=m
++CONFIG_DRM_AST=m
++CONFIG_DRM_MGAG200=m
++CONFIG_DRM_STARFIVE=y
++CONFIG_DRM_QXL=m
++CONFIG_DRM_VIRTIO_GPU=m
++CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
++CONFIG_DRM_PANEL_ELIDA_KD35T133=m
++CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
++CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
++CONFIG_DRM_PANEL_NOVATEK_NT35510=m
++CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
++CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
++CONFIG_DRM_PANEL_RONBO_RB070D30=m
++CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
++CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
++CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
++CONFIG_DRM_PANEL_VISIONOX_RM69299=m
++CONFIG_DRM_CHRONTEL_CH7033=m
++CONFIG_DRM_DISPLAY_CONNECTOR=m
++CONFIG_DRM_PARADE_PS8640=m
++CONFIG_DRM_SII9234=m
++CONFIG_DRM_SIMPLE_BRIDGE=m
++CONFIG_DRM_TOSHIBA_TC358762=m
++CONFIG_DRM_TOSHIBA_TC358764=m
++CONFIG_DRM_TOSHIBA_TC358768=m
++CONFIG_DRM_TOSHIBA_TC358775=m
++CONFIG_DRM_TI_TFP410=m
++CONFIG_DRM_TI_SN65DSI86=m
++CONFIG_DRM_TI_TPD12S015=m
++CONFIG_DRM_ANALOGIX_ANX6345=m
++CONFIG_DRM_ANALOGIX_ANX78XX=m
++CONFIG_DRM_BOCHS=m
++CONFIG_DRM_CIRRUS_QEMU=m
++CONFIG_DRM_GM12U320=m
++CONFIG_TINYDRM_ILI9486=m
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++CONFIG_FB_TILEBLITTING=y
++CONFIG_FB_EFI=y
++CONFIG_FB_VIRTUAL=m
++CONFIG_FB_SSD1307=m
++CONFIG_LCD_CLASS_DEVICE=m
++CONFIG_LCD_PLATFORM=m
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_KTD253=m
++CONFIG_BACKLIGHT_PWM=m
++CONFIG_BACKLIGHT_LP855X=m
++CONFIG_BACKLIGHT_ARCXCNN=m
++CONFIG_BACKLIGHT_LED=m
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=m
++CONFIG_SND=m
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=m
++CONFIG_SND_PCM_OSS=m
++CONFIG_SND_HRTIMER=m
++# CONFIG_SND_SUPPORT_OLD_API is not set
++CONFIG_SND_SEQUENCER=m
++CONFIG_SND_SEQ_DUMMY=m
++CONFIG_SND_SEQUENCER_OSS=m
++CONFIG_SND_DUMMY=m
++CONFIG_SND_ALOOP=m
++CONFIG_SND_VIRMIDI=m
++CONFIG_SND_MTPAV=m
++CONFIG_SND_SERIAL_U16550=m
++CONFIG_SND_MPU401=m
++CONFIG_SND_AC97_POWER_SAVE=y
++CONFIG_SND_AD1889=m
++CONFIG_SND_ATIIXP=m
++CONFIG_SND_ATIIXP_MODEM=m
++CONFIG_SND_AU8810=m
++CONFIG_SND_AU8820=m
++CONFIG_SND_AU8830=m
++CONFIG_SND_BT87X=m
++CONFIG_SND_CA0106=m
++CONFIG_SND_CMIPCI=m
++CONFIG_SND_OXYGEN=m
++CONFIG_SND_CS4281=m
++CONFIG_SND_CS46XX=m
++CONFIG_SND_CTXFI=m
++CONFIG_SND_DARLA20=m
++CONFIG_SND_GINA20=m
++CONFIG_SND_LAYLA20=m
++CONFIG_SND_DARLA24=m
++CONFIG_SND_GINA24=m
++CONFIG_SND_LAYLA24=m
++CONFIG_SND_MONA=m
++CONFIG_SND_MIA=m
++CONFIG_SND_ECHO3G=m
++CONFIG_SND_INDIGO=m
++CONFIG_SND_INDIGOIO=m
++CONFIG_SND_INDIGODJ=m
++CONFIG_SND_INDIGOIOX=m
++CONFIG_SND_INDIGODJX=m
++CONFIG_SND_ENS1370=m
++CONFIG_SND_ENS1371=m
++CONFIG_SND_FM801=m
++CONFIG_SND_FM801_TEA575X_BOOL=y
++CONFIG_SND_HDSP=m
++CONFIG_SND_HDSPM=m
++CONFIG_SND_ICE1724=m
++CONFIG_SND_KORG1212=m
++CONFIG_SND_LOLA=m
++CONFIG_SND_LX6464ES=m
++CONFIG_SND_MIXART=m
++CONFIG_SND_NM256=m
++CONFIG_SND_PCXHR=m
++CONFIG_SND_RIPTIDE=m
++CONFIG_SND_RME32=m
++CONFIG_SND_RME96=m
++CONFIG_SND_RME9652=m
++CONFIG_SND_VIRTUOSO=m
++CONFIG_SND_VX222=m
++CONFIG_SND_YMFPCI=m
++CONFIG_SND_HDA_INTEL=m
++CONFIG_SND_HDA_HWDEP=y
++CONFIG_SND_HDA_INPUT_BEEP=y
++CONFIG_SND_HDA_INPUT_BEEP_MODE=0
++CONFIG_SND_HDA_PATCH_LOADER=y
++CONFIG_SND_HDA_CODEC_REALTEK=m
++CONFIG_SND_HDA_CODEC_ANALOG=m
++CONFIG_SND_HDA_CODEC_SIGMATEL=m
++CONFIG_SND_HDA_CODEC_VIA=m
++CONFIG_SND_HDA_CODEC_HDMI=m
++CONFIG_SND_HDA_CODEC_CIRRUS=m
++CONFIG_SND_HDA_CODEC_CONEXANT=m
++CONFIG_SND_HDA_CODEC_CA0110=m
++CONFIG_SND_HDA_CODEC_CA0132=m
++CONFIG_SND_HDA_CODEC_CMEDIA=m
++CONFIG_SND_HDA_CODEC_SI3054=m
++CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y
++CONFIG_SND_HDA_PREALLOC_SIZE=4096
++# CONFIG_SND_SPI is not set
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_USB_UA101=m
++CONFIG_SND_USB_CAIAQ=m
++CONFIG_SND_USB_CAIAQ_INPUT=y
++CONFIG_SND_USB_6FIRE=m
++CONFIG_SND_USB_HIFACE=m
++CONFIG_SND_BCD2000=m
++CONFIG_SND_USB_POD=m
++CONFIG_SND_USB_PODHD=m
++CONFIG_SND_USB_TONEPORT=m
++CONFIG_SND_USB_VARIAX=m
++CONFIG_SND_DICE=m
++CONFIG_SND_OXFW=m
++CONFIG_SND_ISIGHT=m
++CONFIG_SND_FIREWORKS=m
++CONFIG_SND_BEBOB=m
++CONFIG_SND_FIREWIRE_DIGI00X=m
++CONFIG_SND_FIREWIRE_TASCAM=m
++CONFIG_SND_FIREWIRE_MOTU=m
++CONFIG_SND_FIREFACE=m
++# CONFIG_SND_PCMCIA is not set
++CONFIG_SND_SOC=m
++CONFIG_SND_SOC_AMD_ACP=m
++CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
++CONFIG_SND_DESIGNWARE_I2S=m
++CONFIG_SND_DESIGNWARE_PCM=y
++CONFIG_SND_I2S_HI6210_I2S=m
++CONFIG_SND_SOC_SOF_TOPLEVEL=y
++CONFIG_SND_SOC_SOF_PCI=m
++CONFIG_SND_STARFIVE_PWMDAC=m
++CONFIG_SND_SOC_AC97_CODEC=m
++CONFIG_SND_SOC_ADAU1761_I2C=m
++CONFIG_SND_SOC_ADAU1761_SPI=m
++CONFIG_SND_SOC_ADAU7002=m
++CONFIG_SND_SOC_ADAU7118_HW=m
++CONFIG_SND_SOC_ADAU7118_I2C=m
++CONFIG_SND_SOC_AK5558=m
++CONFIG_SND_SOC_BD28623=m
++CONFIG_SND_SOC_CS35L34=m
++CONFIG_SND_SOC_CS35L35=m
++CONFIG_SND_SOC_CS35L36=m
++CONFIG_SND_SOC_CS42L42=m
++CONFIG_SND_SOC_CS4234=m
++CONFIG_SND_SOC_CS43130=m
++CONFIG_SND_SOC_CX2072X=m
++CONFIG_SND_SOC_DA7213=m
++CONFIG_SND_SOC_DMIC=m
++CONFIG_SND_SOC_ES7134=m
++CONFIG_SND_SOC_ES8328_I2C=m
++CONFIG_SND_SOC_ES8328_SPI=m
++CONFIG_SND_SOC_MAX98088=m
++CONFIG_SND_SOC_MAX98357A=m
++CONFIG_SND_SOC_MAX9867=m
++CONFIG_SND_SOC_MAX98927=m
++CONFIG_SND_SOC_MAX98373_I2C=m
++CONFIG_SND_SOC_MAX98373_SDW=m
++CONFIG_SND_SOC_MAX98390=m
++CONFIG_SND_SOC_PCM1789_I2C=m
++CONFIG_SND_SOC_PCM186X_I2C=m
++CONFIG_SND_SOC_PCM186X_SPI=m
++CONFIG_SND_SOC_PCM3060_I2C=m
++CONFIG_SND_SOC_PCM3060_SPI=m
++CONFIG_SND_SOC_RT1308_SDW=m
++CONFIG_SND_SOC_RT5682_SDW=m
++CONFIG_SND_SOC_RT700_SDW=m
++CONFIG_SND_SOC_RT711_SDW=m
++CONFIG_SND_SOC_RT715_SDW=m
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
++CONFIG_SND_SOC_SPDIF=m
++CONFIG_SND_SOC_TAS2562=m
++CONFIG_SND_SOC_TAS2764=m
++CONFIG_SND_SOC_TAS2770=m
++CONFIG_SND_SOC_TAS6424=m
++CONFIG_SND_SOC_TDA7419=m
++CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
++CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
++CONFIG_SND_SOC_TLV320ADCX140=m
++CONFIG_SND_SOC_TSCS42XX=m
++CONFIG_SND_SOC_WM8524=m
++CONFIG_SND_SOC_ZL38060=m
++CONFIG_SND_SOC_MAX9759=m
++CONFIG_SND_SOC_NAU8824=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_HID_BATTERY_STRENGTH=y
++CONFIG_HIDRAW=y
++CONFIG_UHID=m
++CONFIG_HID_A4TECH=m
++CONFIG_HID_ACCUTOUCH=m
++CONFIG_HID_ACRUX=m
++CONFIG_HID_ACRUX_FF=y
++CONFIG_HID_APPLE=m
++CONFIG_HID_APPLEIR=m
++CONFIG_HID_AUREAL=m
++CONFIG_HID_BELKIN=m
++CONFIG_HID_BETOP_FF=m
++CONFIG_HID_BIGBEN_FF=m
++CONFIG_HID_CHERRY=m
++CONFIG_HID_CHICONY=m
++CONFIG_HID_CORSAIR=m
++CONFIG_HID_COUGAR=m
++CONFIG_HID_MACALLY=m
++CONFIG_HID_PRODIKEYS=m
++CONFIG_HID_CMEDIA=m
++CONFIG_HID_CP2112=m
++CONFIG_HID_CREATIVE_SB0540=m
++CONFIG_HID_CYPRESS=m
++CONFIG_HID_DRAGONRISE=m
++CONFIG_DRAGONRISE_FF=y
++CONFIG_HID_EMS_FF=m
++CONFIG_HID_ELAN=m
++CONFIG_HID_ELECOM=m
++CONFIG_HID_ELO=m
++CONFIG_HID_EZKEY=m
++CONFIG_HID_GEMBIRD=m
++CONFIG_HID_GFRM=m
++CONFIG_HID_GLORIOUS=m
++CONFIG_HID_HOLTEK=m
++CONFIG_HOLTEK_FF=y
++CONFIG_HID_VIVALDI=m
++CONFIG_HID_GT683R=m
++CONFIG_HID_KEYTOUCH=m
++CONFIG_HID_KYE=m
++CONFIG_HID_UCLOGIC=m
++CONFIG_HID_WALTOP=m
++CONFIG_HID_VIEWSONIC=m
++CONFIG_HID_GYRATION=m
++CONFIG_HID_ICADE=m
++CONFIG_HID_ITE=m
++CONFIG_HID_JABRA=m
++CONFIG_HID_TWINHAN=m
++CONFIG_HID_KENSINGTON=m
++CONFIG_HID_LCPOWER=m
++CONFIG_HID_LENOVO=m
++CONFIG_HID_LOGITECH=m
++CONFIG_HID_LOGITECH_DJ=m
++CONFIG_LOGITECH_FF=y
++CONFIG_LOGIRUMBLEPAD2_FF=y
++CONFIG_LOGIG940_FF=y
++CONFIG_HID_MAGICMOUSE=y
++CONFIG_HID_MALTRON=m
++CONFIG_HID_MAYFLASH=m
++CONFIG_HID_MICROSOFT=m
++CONFIG_HID_MONTEREY=m
++CONFIG_HID_MULTITOUCH=m
++CONFIG_HID_NTI=m
++CONFIG_HID_NTRIG=y
++CONFIG_HID_ORTEK=m
++CONFIG_HID_PANTHERLORD=m
++CONFIG_PANTHERLORD_FF=y
++CONFIG_HID_PENMOUNT=m
++CONFIG_HID_PETALYNX=m
++CONFIG_HID_PICOLCD=m
++CONFIG_HID_PLANTRONICS=m
++CONFIG_HID_PRIMAX=m
++CONFIG_HID_RETRODE=m
++CONFIG_HID_ROCCAT=m
++CONFIG_HID_SAITEK=m
++CONFIG_HID_SAMSUNG=m
++CONFIG_HID_SONY=m
++CONFIG_SONY_FF=y
++CONFIG_HID_SPEEDLINK=m
++CONFIG_HID_STEAM=m
++CONFIG_HID_STEELSERIES=m
++CONFIG_HID_SUNPLUS=m
++CONFIG_HID_RMI=m
++CONFIG_HID_GREENASIA=m
++CONFIG_GREENASIA_FF=y
++CONFIG_HID_SMARTJOYPLUS=m
++CONFIG_SMARTJOYPLUS_FF=y
++CONFIG_HID_TIVO=m
++CONFIG_HID_TOPSEED=m
++CONFIG_HID_THINGM=m
++CONFIG_HID_THRUSTMASTER=m
++CONFIG_THRUSTMASTER_FF=y
++CONFIG_HID_UDRAW_PS3=m
++CONFIG_HID_U2FZERO=m
++CONFIG_HID_WACOM=m
++CONFIG_HID_WIIMOTE=m
++CONFIG_HID_XINMO=m
++CONFIG_HID_ZEROPLUS=m
++CONFIG_ZEROPLUS_FF=y
++CONFIG_HID_ZYDACRON=m
++CONFIG_HID_SENSOR_HUB=m
++CONFIG_HID_ALPS=m
++CONFIG_HID_MCP2221=m
++CONFIG_HID_PID=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB_ULPI_BUS=m
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_MON=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DBGCAP=y
++CONFIG_USB_XHCI_PCI_RENESAS=m
++CONFIG_USB_XHCI_PLATFORM=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_ROOT_HUB_TT=y
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_UHCI_HCD=y
++CONFIG_USB_SL811_HCD=m
++CONFIG_USB_SL811_HCD_ISO=y
++CONFIG_USB_PRINTER=m
++CONFIG_USB_TMC=m
++CONFIG_USB_STORAGE=m
++CONFIG_USB_STORAGE_REALTEK=m
++CONFIG_USB_STORAGE_DATAFAB=m
++CONFIG_USB_STORAGE_FREECOM=m
++CONFIG_USB_STORAGE_ISD200=m
++CONFIG_USB_STORAGE_USBAT=m
++CONFIG_USB_STORAGE_SDDR09=m
++CONFIG_USB_STORAGE_SDDR55=m
++CONFIG_USB_STORAGE_JUMPSHOT=m
++CONFIG_USB_STORAGE_ALAUDA=m
++CONFIG_USB_STORAGE_ONETOUCH=m
++CONFIG_USB_STORAGE_KARMA=m
++CONFIG_USB_STORAGE_CYPRESS_ATACB=m
++CONFIG_USB_STORAGE_ENE_UB6250=m
++CONFIG_USB_UAS=m
++CONFIG_USB_MDC800=m
++CONFIG_USB_MICROTEK=m
++CONFIG_USBIP_CORE=m
++CONFIG_USBIP_VHCI_HCD=m
++CONFIG_USBIP_HOST=m
++CONFIG_USB_CDNS_SUPPORT=m
++CONFIG_USB_CDNS3=m
++CONFIG_USB_CDNS3_HOST=y
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CONSOLE=y
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_SIMPLE=m
++CONFIG_USB_SERIAL_AIRCABLE=m
++CONFIG_USB_SERIAL_ARK3116=m
++CONFIG_USB_SERIAL_BELKIN=m
++CONFIG_USB_SERIAL_CH341=m
++CONFIG_USB_SERIAL_WHITEHEAT=m
++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_CYPRESS_M8=m
++CONFIG_USB_SERIAL_EMPEG=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_VISOR=m
++CONFIG_USB_SERIAL_IPAQ=m
++CONFIG_USB_SERIAL_IR=m
++CONFIG_USB_SERIAL_EDGEPORT=m
++CONFIG_USB_SERIAL_EDGEPORT_TI=m
++CONFIG_USB_SERIAL_F8153X=m
++CONFIG_USB_SERIAL_GARMIN=m
++CONFIG_USB_SERIAL_IPW=m
++CONFIG_USB_SERIAL_IUU=m
++CONFIG_USB_SERIAL_KEYSPAN_PDA=m
++CONFIG_USB_SERIAL_KEYSPAN=m
++CONFIG_USB_SERIAL_KLSI=m
++CONFIG_USB_SERIAL_KOBIL_SCT=m
++CONFIG_USB_SERIAL_MCT_U232=m
++CONFIG_USB_SERIAL_MOS7720=m
++CONFIG_USB_SERIAL_MOS7840=m
++CONFIG_USB_SERIAL_NAVMAN=m
++CONFIG_USB_SERIAL_PL2303=m
++CONFIG_USB_SERIAL_OTI6858=m
++CONFIG_USB_SERIAL_QCAUX=m
++CONFIG_USB_SERIAL_QUALCOMM=m
++CONFIG_USB_SERIAL_SPCP8X5=m
++CONFIG_USB_SERIAL_SAFE=m
++CONFIG_USB_SERIAL_SAFE_PADDED=y
++CONFIG_USB_SERIAL_SIERRAWIRELESS=m
++CONFIG_USB_SERIAL_SYMBOL=m
++CONFIG_USB_SERIAL_TI=m
++CONFIG_USB_SERIAL_CYBERJACK=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_SERIAL_OMNINET=m
++CONFIG_USB_SERIAL_OPTICON=m
++CONFIG_USB_SERIAL_XSENS_MT=m
++CONFIG_USB_SERIAL_SSU100=m
++CONFIG_USB_SERIAL_QT2=m
++CONFIG_USB_SERIAL_UPD78F0730=m
++CONFIG_USB_SERIAL_DEBUG=m
++CONFIG_USB_EMI62=m
++CONFIG_USB_EMI26=m
++CONFIG_USB_ADUTUX=m
++CONFIG_USB_SEVSEG=m
++CONFIG_USB_LEGOTOWER=m
++CONFIG_USB_LCD=m
++CONFIG_USB_IDMOUSE=m
++CONFIG_USB_FTDI_ELAN=m
++CONFIG_USB_APPLEDISPLAY=m
++CONFIG_APPLE_MFI_FASTCHARGE=m
++CONFIG_USB_SISUSBVGA=m
++CONFIG_USB_LD=m
++CONFIG_USB_TRANCEVIBRATOR=m
++CONFIG_USB_IOWARRIOR=m
++CONFIG_USB_ISIGHTFW=m
++CONFIG_USB_YUREX=m
++CONFIG_USB_HUB_USB251XB=m
++CONFIG_USB_HSIC_USB3503=m
++CONFIG_USB_HSIC_USB4604=m
++CONFIG_USB_CHAOSKEY=m
++CONFIG_USB_ATM=m
++CONFIG_USB_SPEEDTOUCH=m
++CONFIG_USB_CXACRU=m
++CONFIG_USB_UEAGLEATM=m
++CONFIG_USB_XUSBATM=m
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_TYPEC=m
++CONFIG_TYPEC_TCPM=m
++CONFIG_TYPEC_TCPCI=m
++CONFIG_TYPEC_TCPCI_MAXIM=m
++CONFIG_TYPEC_FUSB302=m
++CONFIG_TYPEC_UCSI=m
++CONFIG_UCSI_CCG=m
++CONFIG_TYPEC_TPS6598X=m
++CONFIG_TYPEC_HD3SS3220=m
++CONFIG_TYPEC_STUSB160X=m
++CONFIG_TYPEC_MUX_PI3USB30532=m
++CONFIG_TYPEC_DP_ALTMODE=m
++CONFIG_TYPEC_NVIDIA_ALTMODE=m
++CONFIG_USB_ROLE_SWITCH=y
++CONFIG_MMC=y
++CONFIG_PWRSEQ_SD8787=m
++CONFIG_PWRSEQ_SIMPLE=m
++CONFIG_SDIO_UART=m
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PCI=m
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_OF_DWCMSHC=y
++CONFIG_MMC_SDHCI_CADENCE=m
++CONFIG_MMC_ALCOR=m
++CONFIG_MMC_TIFM_SD=m
++CONFIG_MMC_SPI=y
++CONFIG_MMC_SDRICOH_CS=m
++CONFIG_MMC_CB710=m
++CONFIG_MMC_VIA_SDMMC=m
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_PCI=y
++CONFIG_MMC_VUB300=m
++CONFIG_MMC_USHC=m
++CONFIG_MMC_REALTEK_PCI=m
++CONFIG_MMC_REALTEK_USB=m
++CONFIG_MMC_CQHCI=y
++CONFIG_MMC_HSQ=y
++CONFIG_MMC_SDHCI_XENON=m
++CONFIG_MEMSTICK=m
++CONFIG_MSPRO_BLOCK=m
++CONFIG_MEMSTICK_TIFM_MS=m
++CONFIG_MEMSTICK_JMICRON_38X=m
++CONFIG_MEMSTICK_R592=m
++CONFIG_MEMSTICK_REALTEK_PCI=m
++CONFIG_MEMSTICK_REALTEK_USB=m
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=m
++CONFIG_LEDS_CLASS_MULTICOLOR=m
++CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
++CONFIG_LEDS_AN30259A=m
++CONFIG_LEDS_CR0014114=m
++CONFIG_LEDS_LM3530=m
++CONFIG_LEDS_LM3532=m
++CONFIG_LEDS_LM3692X=m
++CONFIG_LEDS_PCA9532=m
++CONFIG_LEDS_PCA9532_GPIO=y
++CONFIG_LEDS_GPIO=m
++CONFIG_LEDS_LP3944=m
++CONFIG_LEDS_LP3952=m
++CONFIG_LEDS_LP50XX=m
++CONFIG_LEDS_PWM=m
++CONFIG_LEDS_REGULATOR=m
++CONFIG_LEDS_LT3593=m
++CONFIG_LEDS_MAX77650=m
++CONFIG_LEDS_IS31FL32XX=m
++CONFIG_LEDS_BLINKM=m
++CONFIG_LEDS_SYSCON=y
++CONFIG_LEDS_MLXREG=m
++CONFIG_LEDS_USER=m
++CONFIG_LEDS_AS3645A=m
++CONFIG_LEDS_LM3601X=m
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_ONESHOT=m
++CONFIG_LEDS_TRIGGER_DISK=y
++CONFIG_LEDS_TRIGGER_MTD=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_LEDS_TRIGGER_BACKLIGHT=m
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=m
++CONFIG_LEDS_TRIGGER_GPIO=m
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
++CONFIG_LEDS_TRIGGER_TRANSIENT=m
++CONFIG_LEDS_TRIGGER_CAMERA=m
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=m
++CONFIG_LEDS_TRIGGER_PATTERN=m
++CONFIG_ACCESSIBILITY=y
++CONFIG_A11Y_BRAILLE_CONSOLE=y
++CONFIG_SPEAKUP=m
++CONFIG_SPEAKUP_SYNTH_ACNTSA=m
++CONFIG_SPEAKUP_SYNTH_APOLLO=m
++CONFIG_SPEAKUP_SYNTH_AUDPTR=m
++CONFIG_SPEAKUP_SYNTH_BNS=m
++CONFIG_SPEAKUP_SYNTH_DECTLK=m
++CONFIG_SPEAKUP_SYNTH_LTLK=m
++CONFIG_SPEAKUP_SYNTH_SOFT=m
++CONFIG_SPEAKUP_SYNTH_SPKOUT=m
++CONFIG_SPEAKUP_SYNTH_TXPRT=m
++CONFIG_INFINIBAND=m
++CONFIG_INFINIBAND_USER_MAD=m
++CONFIG_INFINIBAND_USER_ACCESS=m
++CONFIG_INFINIBAND_MTHCA=m
++CONFIG_INFINIBAND_CXGB4=m
++CONFIG_INFINIBAND_EFA=m
++CONFIG_MLX4_INFINIBAND=m
++CONFIG_MLX5_INFINIBAND=m
++CONFIG_INFINIBAND_OCRDMA=m
++CONFIG_INFINIBAND_QEDR=m
++CONFIG_RDMA_RXE=m
++CONFIG_RDMA_SIW=m
++CONFIG_INFINIBAND_IPOIB=m
++CONFIG_INFINIBAND_IPOIB_CM=y
++CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y
++CONFIG_INFINIBAND_SRP=m
++CONFIG_INFINIBAND_SRPT=m
++CONFIG_INFINIBAND_ISER=m
++CONFIG_INFINIBAND_ISERT=m
++CONFIG_INFINIBAND_RTRS_CLIENT=m
++CONFIG_INFINIBAND_RTRS_SERVER=m
++CONFIG_EDAC=y
++CONFIG_EDAC_SIFIVE=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_SYSTOHC is not set
++CONFIG_RTC_DRV_ABEOZ9=m
++CONFIG_RTC_DRV_ABX80X=m
++CONFIG_RTC_DRV_DS1307=m
++CONFIG_RTC_DRV_DS1374=m
++CONFIG_RTC_DRV_DS1374_WDT=y
++CONFIG_RTC_DRV_DS1672=m
++CONFIG_RTC_DRV_MAX6900=m
++CONFIG_RTC_DRV_RS5C372=m
++CONFIG_RTC_DRV_ISL1208=m
++CONFIG_RTC_DRV_ISL12022=m
++CONFIG_RTC_DRV_ISL12026=m
++CONFIG_RTC_DRV_X1205=m
++CONFIG_RTC_DRV_PCF8523=m
++CONFIG_RTC_DRV_PCF85063=m
++CONFIG_RTC_DRV_PCF8563=m
++CONFIG_RTC_DRV_PCF8583=m
++CONFIG_RTC_DRV_M41T80=m
++CONFIG_RTC_DRV_M41T80_WDT=y
++CONFIG_RTC_DRV_BQ32K=m
++CONFIG_RTC_DRV_FM3130=m
++CONFIG_RTC_DRV_RX8010=m
++CONFIG_RTC_DRV_RX8581=m
++CONFIG_RTC_DRV_RX8025=m
++CONFIG_RTC_DRV_EM3027=m
++CONFIG_RTC_DRV_RV3028=m
++CONFIG_RTC_DRV_RV3032=m
++CONFIG_RTC_DRV_SD3078=m
++CONFIG_RTC_DRV_M41T93=m
++CONFIG_RTC_DRV_M41T94=m
++CONFIG_RTC_DRV_DS1305=m
++CONFIG_RTC_DRV_DS1343=m
++CONFIG_RTC_DRV_DS1347=m
++CONFIG_RTC_DRV_DS1390=m
++CONFIG_RTC_DRV_MAX6916=m
++CONFIG_RTC_DRV_R9701=m
++CONFIG_RTC_DRV_RX4581=m
++CONFIG_RTC_DRV_RS5C348=m
++CONFIG_RTC_DRV_MAX6902=m
++CONFIG_RTC_DRV_PCF2123=m
++CONFIG_RTC_DRV_MCP795=m
++CONFIG_RTC_DRV_DS3232=m
++# CONFIG_RTC_DRV_DS3232_HWMON is not set
++CONFIG_RTC_DRV_PCF2127=m
++CONFIG_RTC_DRV_RV3029C2=m
++CONFIG_RTC_DRV_DS1286=m
++CONFIG_RTC_DRV_DS1511=m
++CONFIG_RTC_DRV_DS1553=m
++CONFIG_RTC_DRV_DS1685_FAMILY=m
++CONFIG_RTC_DRV_DS1742=m
++CONFIG_RTC_DRV_DS2404=m
++CONFIG_RTC_DRV_EFI=y
++CONFIG_RTC_DRV_STK17TA8=m
++CONFIG_RTC_DRV_M48T35=m
++CONFIG_RTC_DRV_M48T59=m
++CONFIG_RTC_DRV_MSM6242=m
++CONFIG_RTC_DRV_BQ4802=m
++CONFIG_RTC_DRV_RP5C01=m
++CONFIG_RTC_DRV_V3020=m
++CONFIG_RTC_DRV_R7301=m
++CONFIG_DMADEVICES=y
++CONFIG_ALTERA_MSGDMA=m
++CONFIG_DW_AXI_DMAC=y
++CONFIG_DW_DMAC=m
++CONFIG_DW_DMAC_PCI=m
++CONFIG_DW_EDMA_PCIE=m
++CONFIG_SF_PDMA=y
++CONFIG_ASYNC_TX_DMA=y
++CONFIG_UDMABUF=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_AUXDISPLAY=y
++CONFIG_HD44780=m
++CONFIG_HT16K33=m
++CONFIG_UIO_CIF=m
++CONFIG_UIO_AEC=m
++CONFIG_UIO_SERCOS3=m
++CONFIG_UIO_PCI_GENERIC=m
++CONFIG_VFIO=m
++CONFIG_VFIO_PCI=m
++CONFIG_VFIO_MDEV=m
++CONFIG_VIRTIO_PCI=y
++CONFIG_VIRTIO_VDPA=m
++CONFIG_VIRTIO_BALLOON=m
++CONFIG_VIRTIO_INPUT=m
++CONFIG_VIRTIO_MMIO=m
++CONFIG_VDPA=m
++CONFIG_VDPA_SIM=m
++CONFIG_IFCVF=m
++CONFIG_MLX5_VDPA_NET=m
++CONFIG_VHOST_NET=m
++CONFIG_VHOST_SCSI=m
++CONFIG_VHOST_VSOCK=m
++CONFIG_VHOST_VDPA=m
++CONFIG_STAGING=y
++CONFIG_RTLLIB=m
++CONFIG_RTL8192E=m
++CONFIG_RTL8723BS=m
++CONFIG_R8712U=m
++CONFIG_STAGING_MEDIA=y
++CONFIG_DVB_AV7110=m
++CONFIG_DVB_BUDGET_PATCH=m
++CONFIG_QLGE=m
++CONFIG_COMMON_CLK_SI544=m
++CONFIG_COMMON_CLK_PWM=m
++CONFIG_XILINX_VCU=m
++CONFIG_HWSPINLOCK=y
++CONFIG_REMOTEPROC=y
++CONFIG_RPMSG_CHAR=m
++CONFIG_RPMSG_VIRTIO=m
++CONFIG_SOUNDWIRE=y
++CONFIG_PM_DEVFREQ=y
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m
++CONFIG_IIO=m
++CONFIG_IIO_SW_DEVICE=m
++CONFIG_IIO_SW_TRIGGER=m
++CONFIG_IIO_TRIGGERED_EVENT=m
++CONFIG_ADXL372_SPI=m
++CONFIG_ADXL372_I2C=m
++CONFIG_BMC150_ACCEL=m
++CONFIG_DA280=m
++CONFIG_DA311=m
++CONFIG_DMARD10=m
++CONFIG_HID_SENSOR_ACCEL_3D=m
++CONFIG_IIO_ST_ACCEL_3AXIS=m
++CONFIG_KXCJK1013=m
++CONFIG_MMA7660=m
++CONFIG_MXC4005=m
++CONFIG_MXC6255=m
++CONFIG_AD7124=m
++CONFIG_AD7292=m
++CONFIG_AD7766=m
++CONFIG_AD7949=m
++CONFIG_AD9467=m
++CONFIG_ADI_AXI_ADC=m
++CONFIG_ENVELOPE_DETECTOR=m
++CONFIG_MAX1241=m
++CONFIG_MAX1363=m
++CONFIG_MCP3911=m
++CONFIG_TI_ADC128S052=m
++CONFIG_TI_ADS1015=m
++CONFIG_TI_ADS8344=m
++CONFIG_IIO_RESCALE=m
++CONFIG_HMC425=m
++CONFIG_BME680=m
++CONFIG_PMS7003=m
++CONFIG_SCD30_CORE=m
++CONFIG_SCD30_I2C=m
++CONFIG_SCD30_SERIAL=m
++CONFIG_AD5770R=m
++CONFIG_DPOT_DAC=m
++CONFIG_LTC1660=m
++CONFIG_TI_DAC7311=m
++CONFIG_ADXRS290=m
++CONFIG_FXAS21002C=m
++CONFIG_HID_SENSOR_GYRO_3D=m
++CONFIG_MPU3050_I2C=m
++CONFIG_IIO_ST_GYRO_3AXIS=m
++CONFIG_MAX30100=m
++CONFIG_DHT11=m
++CONFIG_HDC2010=m
++CONFIG_HID_SENSOR_HUMIDITY=m
++CONFIG_HTS221=m
++CONFIG_ADIS16475=m
++CONFIG_FXOS8700_I2C=m
++CONFIG_FXOS8700_SPI=m
++CONFIG_INV_ICM42600_I2C=m
++CONFIG_INV_ICM42600_SPI=m
++CONFIG_IIO_ST_LSM6DSX=m
++CONFIG_ADUX1020=m
++CONFIG_AL3010=m
++CONFIG_BH1750=m
++CONFIG_CM32181=m
++CONFIG_CM3605=m
++CONFIG_GP2AP002=m
++CONFIG_HID_SENSOR_ALS=m
++CONFIG_RPR0521=m
++CONFIG_LTR501=m
++CONFIG_LV0104CS=m
++CONFIG_MAX44009=m
++CONFIG_OPT3001=m
++CONFIG_PA12203001=m
++CONFIG_STK3310=m
++CONFIG_ST_UVIS25=m
++CONFIG_TSL2772=m
++CONFIG_VCNL4035=m
++CONFIG_VEML6030=m
++CONFIG_VL6180=m
++CONFIG_ZOPT2201=m
++CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
++CONFIG_IIO_ST_MAGN_3AXIS=m
++CONFIG_SENSORS_RM3100_I2C=m
++CONFIG_SENSORS_RM3100_SPI=m
++CONFIG_IIO_MUX=m
++CONFIG_HID_SENSOR_INCLINOMETER_3D=m
++CONFIG_HID_SENSOR_DEVICE_ROTATION=m
++CONFIG_IIO_INTERRUPT_TRIGGER=m
++CONFIG_IIO_TIGHTLOOP_TRIGGER=m
++CONFIG_AD5272=m
++CONFIG_MCP4018=m
++CONFIG_MCP41010=m
++CONFIG_LMP91000=m
++CONFIG_ABP060MG=m
++CONFIG_BMP280=m
++CONFIG_ICP10100=m
++CONFIG_MPL115_I2C=m
++CONFIG_MB1232=m
++CONFIG_SX9310=m
++CONFIG_VCNL3020=m
++CONFIG_VL53L0X_I2C=m
++CONFIG_LTC2983=m
++CONFIG_MAXIM_THERMOCOUPLE=m
++CONFIG_HID_SENSOR_TEMP=m
++CONFIG_MLX90614=m
++CONFIG_MLX90632=m
++CONFIG_MAX31856=m
++CONFIG_PWM_SIFIVE=y
++CONFIG_PWM_SIFIVE_PTC=y
++CONFIG_PHY_CADENCE_TORRENT=m
++CONFIG_PHY_CADENCE_SIERRA=m
++CONFIG_PHY_CADENCE_SALVO=m
++CONFIG_POWERCAP=y
++CONFIG_USB4=y
++CONFIG_FPGA=m
++CONFIG_ALTERA_PR_IP_CORE=m
++CONFIG_ALTERA_PR_IP_CORE_PLAT=m
++CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
++CONFIG_FPGA_MGR_ALTERA_CVP=m
++CONFIG_FPGA_MGR_XILINX_SPI=m
++CONFIG_FPGA_MGR_ICE40_SPI=m
++CONFIG_FPGA_MGR_MACHXO2_SPI=m
++CONFIG_XILINX_PR_DECOUPLER=m
++CONFIG_OF_FPGA_REGION=m
++CONFIG_FPGA_DFL=m
++CONFIG_FPGA_DFL_FME=m
++CONFIG_FPGA_DFL_FME_MGR=m
++CONFIG_FPGA_DFL_FME_BRIDGE=m
++CONFIG_FPGA_DFL_FME_REGION=m
++CONFIG_FPGA_DFL_AFU=m
++CONFIG_FPGA_DFL_PCI=m
++CONFIG_FSI=m
++CONFIG_FSI_MASTER_GPIO=m
++CONFIG_FSI_MASTER_HUB=m
++CONFIG_FSI_SCOM=m
++CONFIG_MUX_ADG792A=m
++CONFIG_MUX_GPIO=m
++CONFIG_MUX_MMIO=m
++CONFIG_INTERCONNECT=y
++CONFIG_NVDLA=m
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_REISERFS_FS=m
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_XFS_ONLINE_SCRUB=y
++CONFIG_GFS2_FS=m
++CONFIG_GFS2_FS_LOCKING_DLM=y
++CONFIG_OCFS2_FS=m
++# CONFIG_OCFS2_FS_STATS is not set
++# CONFIG_OCFS2_DEBUG_MASKLOG is not set
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_NILFS2_FS=m
++CONFIG_F2FS_FS=m
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_DAX=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
++CONFIG_FS_VERITY=y
++CONFIG_FANOTIFY=y
++CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++# CONFIG_PRINT_QUOTA_WARNING is not set
++CONFIG_QFMT_V2=y
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=m
++CONFIG_CUSE=m
++CONFIG_VIRTIO_FS=m
++CONFIG_OVERLAY_FS=m
++CONFIG_FSCACHE=m
++CONFIG_FSCACHE_STATS=y
++CONFIG_CACHEFILES=m
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=m
++CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
++CONFIG_EXFAT_FS=m
++CONFIG_PROC_KCORE=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_INODE64=y
++CONFIG_HUGETLBFS=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_EFIVAR_FS=y
++CONFIG_ORANGEFS_FS=m
++CONFIG_AFFS_FS=m
++CONFIG_ECRYPT_FS=m
++CONFIG_HFS_FS=m
++CONFIG_HFSPLUS_FS=m
++CONFIG_BEFS_FS=m
++CONFIG_JFFS2_FS=m
++CONFIG_JFFS2_SUMMARY=y
++CONFIG_JFFS2_FS_XATTR=y
++CONFIG_UBIFS_FS=m
++CONFIG_UBIFS_ATIME_SUPPORT=y
++CONFIG_UBIFS_FS_AUTHENTICATION=y
++CONFIG_CRAMFS=m
++CONFIG_SQUASHFS=m
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++CONFIG_MINIX_FS=m
++CONFIG_ROMFS_FS=m
++CONFIG_PSTORE=y
++CONFIG_PSTORE_LZO_COMPRESS=m
++CONFIG_PSTORE_LZ4_COMPRESS=m
++CONFIG_PSTORE_LZ4HC_COMPRESS=m
++CONFIG_PSTORE_842_COMPRESS=y
++CONFIG_PSTORE_RAM=m
++CONFIG_SYSV_FS=m
++CONFIG_UFS_FS=m
++CONFIG_EROFS_FS=m
++CONFIG_NFS_FS=m
++# CONFIG_NFS_V2 is not set
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=m
++CONFIG_NFS_SWAP=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_NFS_FSCACHE=y
++# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set
++CONFIG_NFSD=m
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++CONFIG_NFSD_BLOCKLAYOUT=y
++CONFIG_NFSD_SCSILAYOUT=y
++CONFIG_NFSD_FLEXFILELAYOUT=y
++CONFIG_NFSD_V4_2_INTER_SSC=y
++CONFIG_NFSD_V4_SECURITY_LABEL=y
++CONFIG_SUNRPC_DEBUG=y
++CONFIG_CEPH_FS=m
++CONFIG_CEPH_FSCACHE=y
++CONFIG_CEPH_FS_POSIX_ACL=y
++CONFIG_CEPH_FS_SECURITY_LABEL=y
++CONFIG_CIFS=m
++# CONFIG_CIFS_STATS2 is not set
++CONFIG_CIFS_UPCALL=y
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++CONFIG_CIFS_DFS_UPCALL=y
++CONFIG_CIFS_FSCACHE=y
++CONFIG_CODA_FS=m
++CONFIG_AFS_FS=m
++CONFIG_AFS_DEBUG=y
++CONFIG_AFS_FSCACHE=y
++CONFIG_9P_FS=m
++CONFIG_9P_FSCACHE=y
++CONFIG_9P_FS_POSIX_ACL=y
++CONFIG_9P_FS_SECURITY=y
++CONFIG_NLS_DEFAULT="utf8"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=m
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=m
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++CONFIG_NLS_MAC_ROMAN=m
++CONFIG_NLS_MAC_CELTIC=m
++CONFIG_NLS_MAC_CENTEURO=m
++CONFIG_NLS_MAC_CROATIAN=m
++CONFIG_NLS_MAC_CYRILLIC=m
++CONFIG_NLS_MAC_GAELIC=m
++CONFIG_NLS_MAC_GREEK=m
++CONFIG_NLS_MAC_ICELAND=m
++CONFIG_NLS_MAC_INUIT=m
++CONFIG_NLS_MAC_ROMANIAN=m
++CONFIG_NLS_MAC_TURKISH=m
++CONFIG_DLM=m
++CONFIG_DLM_DEBUG=y
++CONFIG_UNICODE=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_TRUSTED_KEYS=m
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_KEY_NOTIFICATIONS=y
++CONFIG_SECURITY=y
++CONFIG_SECURITY_NETWORK=y
++CONFIG_SECURITY_INFINIBAND=y
++CONFIG_SECURITY_NETWORK_XFRM=y
++CONFIG_HARDENED_USERCOPY=y
++CONFIG_SECURITY_SELINUX=y
++CONFIG_SECURITY_SELINUX_BOOTPARAM=y
++CONFIG_SECURITY_YAMA=y
++CONFIG_SECURITY_LOCKDOWN_LSM=y
++CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
++CONFIG_INTEGRITY_SIGNATURE=y
++CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
++CONFIG_IMA=y
++CONFIG_IMA_DEFAULT_HASH_SHA256=y
++CONFIG_IMA_WRITE_POLICY=y
++CONFIG_IMA_APPRAISE=y
++CONFIG_IMA_APPRAISE_MODSIG=y
++# CONFIG_IMA_TRUSTED_KEYRING is not set
++CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY=y
++CONFIG_EVM=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_CRYPTO_FIPS=y
++CONFIG_CRYPTO_USER=m
++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
++CONFIG_CRYPTO_PCRYPT=m
++CONFIG_CRYPTO_TEST=m
++CONFIG_CRYPTO_ECRDSA=m
++CONFIG_CRYPTO_SM2=m
++CONFIG_CRYPTO_CURVE25519=m
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_CHACHA20POLY1305=m
++CONFIG_CRYPTO_AEGIS128=m
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_CFB=m
++CONFIG_CRYPTO_LRW=m
++CONFIG_CRYPTO_OFB=m
++CONFIG_CRYPTO_KEYWRAP=m
++CONFIG_CRYPTO_ADIANTUM=m
++CONFIG_CRYPTO_XCBC=m
++CONFIG_CRYPTO_VMAC=m
++CONFIG_CRYPTO_BLAKE2S=m
++CONFIG_CRYPTO_RMD160=m
++CONFIG_CRYPTO_SHA3=m
++CONFIG_CRYPTO_WP512=m
++CONFIG_CRYPTO_AES_TI=m
++CONFIG_CRYPTO_BLOWFISH=m
++CONFIG_CRYPTO_CAMELLIA=m
++CONFIG_CRYPTO_CAST5=m
++CONFIG_CRYPTO_CAST6=m
++CONFIG_CRYPTO_DES=m
++CONFIG_CRYPTO_SERPENT=m
++CONFIG_CRYPTO_SM4=m
++CONFIG_CRYPTO_TWOFISH=m
++CONFIG_CRYPTO_ANSI_CPRNG=m
++CONFIG_CRYPTO_DRBG_HASH=y
++CONFIG_CRYPTO_DRBG_CTR=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set
++CONFIG_CRYPTO_STATS=y
++CONFIG_CRYPTO_DEV_ATMEL_ECC=m
++CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
++CONFIG_CRYPTO_DEV_CHELSIO=m
++CONFIG_CRYPTO_DEV_VIRTIO=m
++CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
++CONFIG_TPM_KEY_PARSER=m
++CONFIG_SIGNED_PE_FILE_VERIFICATION=y
++CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
++CONFIG_SECONDARY_TRUSTED_KEYRING=y
++CONFIG_SYSTEM_BLACKLIST_KEYRING=y
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=32
++CONFIG_PRINTK_TIME=y
++CONFIG_CONSOLE_LOGLEVEL_QUIET=3
++CONFIG_BOOT_PRINTK_DELAY=y
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_DEBUG_INFO=y
++CONFIG_DEBUG_INFO_BTF=y
++CONFIG_STRIP_ASM_SYMS=y
++CONFIG_HEADERS_INSTALL=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
++CONFIG_KGDB=y
++CONFIG_KGDB_TESTS=y
++# CONFIG_DEBUG_MISC is not set
++CONFIG_DEBUG_RODATA_TEST=y
++CONFIG_DEBUG_WX=y
++CONFIG_DEBUG_VM=y
++# CONFIG_DEBUG_VM_PGTABLE is not set
++CONFIG_DEBUG_SHIRQ=y
++CONFIG_SOFTLOCKUP_DETECTOR=y
++# CONFIG_DETECT_HUNG_TASK is not set
++CONFIG_BUG_ON_DATA_CORRUPTION=y
++CONFIG_RCU_TORTURE_TEST=m
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_TRACE is not set
++CONFIG_LATENCYTOP=y
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_PROFILER=y
++CONFIG_STACK_TRACER=y
++CONFIG_SCHED_TRACER=y
++CONFIG_HWLAT_TRACER=y
++CONFIG_FTRACE_SYSCALLS=y
++CONFIG_BLK_DEV_IO_TRACE=y
++CONFIG_SYNTH_EVENTS=y
++CONFIG_RING_BUFFER_BENCHMARK=m
++CONFIG_TRACE_EVAL_MAP_FILE=y
++# CONFIG_STRICT_DEVMEM is not set
++CONFIG_ATOMIC64_SELFTEST=y
++CONFIG_ASYNC_RAID6_TEST=m
++CONFIG_TEST_KSTRTOX=y