uboot-d1: add bootloader for upcoming d1 target
[openwrt/staging/mans0n.git] / package / boot / uboot-d1 / patches / 0026-sunxi-psci-Avoid-hanging-when-CPU-0-is-hot-unplugged.patch
1 From ca1e6f4491981432c3e88441131c8e25067da95e Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Sat, 9 Oct 2021 22:00:22 -0500
4 Subject: [PATCH 26/90] sunxi: psci: Avoid hanging when CPU 0 is hot-unplugged
5
6 Do not try to send an SGI from CPU 0 to itself. Since FIQs are masked
7 when entering monitor mode, this will hang. Plus, CPU 0 cannot fully
8 power itself off anyway. Instead, have it turn FIQs back on and continue
9 servicing SGIs from other cores.
10
11 Signed-off-by: Samuel Holland <samuel@sholland.org>
12 ---
13 arch/arm/cpu/armv7/sunxi/psci.c | 20 +++++++++++++++++---
14 1 file changed, 17 insertions(+), 3 deletions(-)
15
16 --- a/arch/arm/cpu/armv7/sunxi/psci.c
17 +++ b/arch/arm/cpu/armv7/sunxi/psci.c
18 @@ -38,6 +38,15 @@
19 #define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
20 #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
21
22 +static inline u32 __secure cp15_read_mpidr(void)
23 +{
24 + u32 val;
25 +
26 + asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
27 +
28 + return val;
29 +}
30 +
31 static void __secure cp15_write_cntp_tval(u32 tval)
32 {
33 asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
34 @@ -281,9 +290,14 @@ s32 __secure psci_cpu_off(void)
35 {
36 psci_cpu_off_common();
37
38 - /* Ask CPU0 via SGI15 to pull the rug... */
39 - writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
40 - dsb();
41 + if (cp15_read_mpidr() & 3) {
42 + /* Ask CPU0 via SGI15 to pull the rug... */
43 + writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
44 + dsb();
45 + } else {
46 + /* Unmask FIQs to service SGI15. */
47 + asm volatile ("cpsie f");
48 + }
49
50 /* Wait to be turned off */
51 while (1)