target/linux/starfive/patches-6.1/0034-clk-starfive-jh7110-sys-Modify-PLL-clocks-source.patch

   1 From ffd7ee4fbd69d477a2156d9cba6ae80434a4c894 Mon Sep 17 00:00:00 2001
   2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
   3 Date: Tue, 14 Mar 2023 17:16:07 +0800
   4 Subject: [PATCH 034/122] clk: starfive: jh7110-sys: Modify PLL clocks source
   5
   6 Modify PLL clocks source to be got from dts instead of
   7 the fixed factor clocks.
   8
   9 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  10 ---
  11  drivers/clk/starfive/Kconfig                  |  1 +
  12  .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++---------------
  13  2 files changed, 7 insertions(+), 25 deletions(-)
  14
  15 --- a/drivers/clk/starfive/Kconfig
  16 +++ b/drivers/clk/starfive/Kconfig
  17 @@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS
  18         select AUXILIARY_BUS
  19         select CLK_STARFIVE_JH71X0
  20         select RESET_STARFIVE_JH7110
  21 +       select CLK_STARFIVE_JH7110_PLL
  22         default ARCH_STARFIVE
  23         help
  24           Say yes here to support the system clock controller on the
  25 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
  26 +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
  27 @@ -404,29 +404,6 @@ static int __init jh7110_syscrg_probe(st
  28
  29         dev_set_drvdata(priv->dev, (void *)(&priv->base));
  30
  31 -       /*
  32 -        * These PLL clocks are not actually fixed factor clocks and can be
  33 -        * controlled by the syscon registers of JH7110. They will be dropped
  34 -        * and registered in the PLL clock driver instead.
  35 -        */
  36 -       /* 24MHz -> 1000.0MHz */
  37 -       priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
  38 -                                                        "osc", 0, 125, 3);
  39 -       if (IS_ERR(priv->pll[0]))
  40 -               return PTR_ERR(priv->pll[0]);
  41 -
  42 -       /* 24MHz -> 1066.0MHz */
  43 -       priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
  44 -                                                        "osc", 0, 533, 12);
  45 -       if (IS_ERR(priv->pll[1]))
  46 -               return PTR_ERR(priv->pll[1]);
  47 -
  48 -       /* 24MHz -> 1188.0MHz */
  49 -       priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
  50 -                                                        "osc", 0, 99, 2);
  51 -       if (IS_ERR(priv->pll[2]))
  52 -               return PTR_ERR(priv->pll[2]);
  53 -
  54         for (idx = 0; idx < JH7110_SYSCLK_END; idx++) {
  55                 u32 max = jh7110_sysclk_data[idx].max;
  56                 struct clk_parent_data parents[4] = {};
  57 @@ -464,8 +441,12 @@ static int __init jh7110_syscrg_probe(st
  58                                 parents[i].fw_name = "tdm_ext";
  59                         else if (pidx == JH7110_SYSCLK_MCLK_EXT)
  60                                 parents[i].fw_name = "mclk_ext";
  61 -                       else
  62 -                               parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
  63 +                       else if (pidx == JH7110_SYSCLK_PLL0_OUT)
  64 +                               parents[i].fw_name = "pll0_out";
  65 +                       else if (pidx == JH7110_SYSCLK_PLL1_OUT)
  66 +                               parents[i].fw_name = "pll1_out";
  67 +                       else if (pidx == JH7110_SYSCLK_PLL2_OUT)
  68 +                               parents[i].fw_name = "pll2_out";
  69                 }
  70
  71                 clk->hw.init = &init;