1 From 4c72279c90469971ca5ec627a76e50bf51bf076f Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Sun, 7 Aug 2022 10:59:29 -0500
4 Subject: [PATCH 090/117] riscv: dts: allwinner: d1: Add DSI pipeline
6 Signed-off-by: Samuel Holland <samuel@sholland.org>
8 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 49 ++++++++++++++++++++
9 1 file changed, 49 insertions(+)
11 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
12 +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
14 #interrupt-cells = <3>;
17 + dsi_4lane_pins: dsi-4lane-pins {
18 + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
19 + "PD6", "PD7", "PD8", "PD9";
20 + drive-strength = <30>;
25 i2c0_pb10_pins: i2c0-pb10-pins {
26 pins = "PB10", "PB11";
33 + compatible = "allwinner,sun20i-d1-mipi-dsi",
34 + "allwinner,sun50i-a100-mipi-dsi";
35 + reg = <0x5450000 0x1000>;
36 + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
37 + clocks = <&ccu CLK_BUS_MIPI_DSI>,
38 + <&tcon_top CLK_TCON_TOP_DSI>;
39 + clock-names = "bus", "mod";
40 + resets = <&ccu RST_BUS_MIPI_DSI>;
43 + status = "disabled";
44 + #address-cells = <1>;
48 + dsi_in_tcon_lcd0: endpoint {
49 + remote-endpoint = <&tcon_lcd0_out_dsi>;
55 + compatible = "allwinner,sun20i-d1-mipi-dphy",
56 + "allwinner,sun50i-a100-mipi-dphy";
57 + reg = <0x5451000 0x1000>;
58 + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
59 + clocks = <&ccu CLK_BUS_MIPI_DSI>,
60 + <&ccu CLK_MIPI_DSI>;
61 + clock-names = "bus", "mod";
62 + resets = <&ccu RST_BUS_MIPI_DSI>;
66 tcon_top: tcon-top@5460000 {
67 compatible = "allwinner,sun20i-d1-tcon-top";
68 reg = <0x5460000 0x1000>;
69 @@ -1022,6 +1064,13 @@
71 tcon_lcd0_out: port@1 {
73 + #address-cells = <1>;
76 + tcon_lcd0_out_dsi: endpoint@1 {
78 + remote-endpoint = <&dsi_in_tcon_lcd0>;