plat/bcm/include/bcm963xx/6858_map_part.h

   1 /*
   2 <:copyright-BRCM:2015:DUAL/GPL:standard
   3
   4    Copyright (c) 2015 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22
  23 */
  24
  25 #ifndef __BCM6858_MAP_PART_H
  26 #define __BCM6858_MAP_PART_H
  27
  28 #ifdef __cplusplus
  29 extern "C" {
  30 #endif
  31
  32 #include "bcmtypes.h"
  33
  34 #define MEMC_PHYS_BASE          0x80180000
  35 #define MEMC_SIZE               0x24000
  36
  37 #define PMC_PHYS_BASE           0x80200000
  38 #define PMC_SIZE                0x5000
  39 #define PROC_MON_PHYS_BASE      0x80280000
  40 #define PROC_MON_SIZE           0x1000
  41
  42 #define PERF_PHYS_BASE          0xff800000
  43 #define PERF_SIZE               0x3000
  44 #define TIMR_OFFSET             0x2700
  45 #define WDTIMR0_OFFSET          0x2780
  46 #define WDTIMR1_OFFSET          0x27c0
  47
  48 #define BIUCFG_PHYS_BASE        0x81060000
  49 #define BIUCFG_SIZE             0x3000
  50 #define BIUCFG_OFFSET           0x0000
  51
  52 #define GIC_PHYS_BASE           0x81000000
  53 #define GIC_SIZE                0x10000
  54 #define GIC_OFFSET              0x0000
  55 #define GICD_OFFSET             0x1000
  56 #define GICC_OFFSET             0x2000
  57
  58 #define PMC_BASE                (PMC_PHYS_BASE + 0)
  59 #define PROC_MON_BASE           (PROC_MON_PHYS_BASE + 0)
  60
  61 #define WDTIMR0_BASE            (PERF_PHYS_BASE + WDTIMR0_OFFSET)
  62 #define TIMR_BASE               (PERF_PHYS_BASE + TIMR_OFFSET)
  63
  64 #define BIUCFG_BASE             (BIUCFG_PHYS_BASE + BIUCFG_OFFSET)
  65
  66 #ifndef __ASSEMBLER__
  67 /*
  68  * Power Management Control
  69  */
  70 typedef struct PmcCtrlReg {
  71     /* 0x00 */
  72     uint32 l1Irq4keMask;
  73     uint32 l1Irq4keStatus;
  74     uint32 l1IrqMipsMask;
  75     uint32 l1IrqMipsStatus;
  76     /* 0x10 */
  77     uint32 l2IrqGpMask;
  78     uint32 l2IrqGpStatus;
  79     uint32 gpTmr0Ctl;
  80     uint32 gpTmr0Cnt;
  81     /* 0x20 */
  82     uint32 gpTmr1Ctl;
  83     uint32 gpTmr1Cnt;
  84     uint32 hostMboxIn;
  85     uint32 hostMboxOut;
  86     /* 0x30 */
  87 #define PMC_CTRL_GP_FLASH_BOOT_STALL    0x00000080
  88     uint32 gpOut;
  89     uint32 gpIn;
  90     uint32 gpInIrqMask;
  91     uint32 gpInIrqStatus;
  92     /* 0x40 */
  93     uint32 dmaCtrl;
  94     uint32 dmaStatus;
  95     uint32 dma0_3FifoStatus;
  96     uint32 unused0[3];                  /* 0x4c-0x57 */
  97     /* 0x58 */
  98     uint32 l1IrqMips1Mask;
  99     uint32 diagControl;
 100     /* 0x60 */
 101     uint32 diagHigh;
 102     uint32 diagLow;
 103     uint32 badAddr;
 104     uint32 addr1WndwMask;
 105     /* 0x70 */
 106     uint32 addr1WndwBaseIn;
 107     uint32 addr1WndwBaseOut;
 108     uint32 addr2WndwMask;
 109     uint32 addr2WndwBaseIn;
 110     /* 0x80 */
 111     uint32 addr2WndwBaseOut;
 112     uint32 scratch;
 113     uint32 tm;
 114     uint32 softResets;
 115     /* 0x90 */
 116     uint32 eb2ubusTimeout;
 117     uint32 m4keCoreStatus;
 118     uint32 gpInIrqSense;
 119     uint32 ubSlaveTimeout;
 120     /* 0xa0 */
 121     uint32 diagEn;
 122     uint32 devTimeout;
 123     uint32 ubusErrorOutMask;
 124     uint32 diagCaptStopMask;
 125     /* 0xb0 */
 126     uint32 revId;
 127     uint32 gpTmr2Ctl;
 128     uint32 gpTmr2Cnt;
 129     uint32 legacyMode;
 130     /* 0xc0 */
 131     uint32 smisbMonitor;
 132     uint32 diagCtrl;
 133     uint32 diagStat;
 134     uint32 diagMask;
 135     /* 0xd0 */
 136     uint32 diagRslt;
 137     uint32 diagCmp;
 138     uint32 diagCapt;
 139     uint32 diagCnt;
 140     /* 0xe0 */
 141     uint32 diagEdgeCnt;
 142     uint32 unused1[4];                  /* 0xe4-0xf3 */
 143     /* 0xf4 */
 144     uint32 iopPeriphBaseAddr;
 145     uint32 lfsr;
 146     uint32 unused2;                     /* 0xfc-0xff */
 147 } PmcCtrlReg;
 148
 149 typedef struct PmcOutFifoReg {
 150     uint32 msgCtrl;                     /* 0x00 */
 151     uint32 msgSts;                      /* 0x04 */
 152     uint32 unused[14];                  /* 0x08-0x3f */
 153     uint32 msgData[16];                 /* 0x40-0x7c */
 154 } PmcOutFifoReg;
 155
 156 typedef struct PmcInFifoReg {
 157     uint32 msgCtrl;                     /* 0x00 */
 158     uint32 msgSts;                      /* 0x04 */
 159     uint32 unused[13];                  /* 0x08-0x3b */
 160     uint32 msgLast;                     /* 0x3c */
 161     uint32 msgData[16];                 /* 0x40-0x7c */
 162 } PmcInFifoReg;
 163
 164 typedef struct PmcDmaReg {
 165     /* 0x00 */
 166     uint32 src;
 167     uint32 dest;
 168     uint32 cmdList;
 169     uint32 lenCtl;
 170     /* 0x10 */
 171     uint32 rsltSrc;
 172     uint32 rsltDest;
 173     uint32 rsltHcs;
 174     uint32 rsltLenStat;
 175 } PmcDmaReg;
 176
 177 typedef struct PmcTokenReg {
 178     /* 0x00 */
 179     uint32 bufSize;
 180     uint32 bufBase;
 181     uint32 idx2ptrIdx;
 182     uint32 idx2ptrPtr;
 183     /* 0x10 */
 184     uint32 unused[2];
 185     uint32 bufSize2;
 186 } PmcTokenReg;
 187
 188 typedef struct PmcPerfPowReg {
 189     /* 0x00 */
 190     uint32 dcacheHit;
 191     uint32 dcacheMiss;
 192     uint32 icacheHit;
 193     uint32 icacheMiss;
 194     /* 0x10 */
 195     uint32 instnComplete;
 196     uint32 wtbMerge;
 197     uint32 wtbNoMerge;
 198     uint32 itlbHit;
 199     /* 0x20 */
 200     uint32 itlbMiss;
 201     uint32 dtlbHit;
 202     uint32 dtlbMiss;
 203     uint32 jtlbHit;
 204     /* 0x30 */
 205     uint32 jtlbMiss;
 206     uint32 powerSubZone;
 207     uint32 powerMemPda;
 208     uint32 freqScalarCtrl;
 209     /* 0x40 */
 210     uint32 freqScalarMask;
 211 } PmcPerfPowReg;
 212
 213 typedef struct PmcDQMReg {
 214     /* 0x00 */
 215     uint32 cfg;
 216     uint32 _4keLowWtmkIrqMask;
 217     uint32 mipsLowWtmkIrqMask;
 218     uint32 lowWtmkIrqMask;
 219     /* 0x10 */
 220     uint32 _4keNotEmptyIrqMask;
 221     uint32 mipsNotEmptyIrqMask;
 222     uint32 notEmptyIrqSts;
 223     uint32 queueRst;
 224     /* 0x20 */
 225     uint32 notEmptySts;
 226     uint32 nextAvailMask;
 227     uint32 nextAvailQueue;
 228     uint32 mips1LowWtmkIrqMask;
 229     /* 0x30 */
 230     uint32 mips1NotEmptyIrqMask;
 231     uint32 autoSrcPidInsert;
 232 } PmcDQMReg;
 233
 234 typedef struct PmcCntReg {
 235     uint32 cntr[10];
 236     uint32 unused[6];   /* 0x28-0x3f */
 237     uint32 cntrIrqMask;
 238     uint32 cntrIrqSts;
 239 } PmcCntReg;
 240
 241 typedef struct PmcDqmQCtrlReg {
 242     uint32 size;
 243     uint32 cfga;
 244     uint32 cfgb;
 245     uint32 cfgc;
 246 } PmcDqmQCtrlReg;
 247
 248 typedef struct PmcDqmQDataReg {
 249     uint32 word[4];
 250 } PmcDqmQDataReg;
 251
 252 typedef struct PmcDqmQMibReg {
 253     uint32 qNumFull[32];
 254     uint32 qNumEmpty[32];
 255     uint32 qNumPushed[32];
 256 } PmcDqmQMibReg;
 257
 258 typedef struct Pmc {
 259     uint32 baseReserved;                /* 0x0000 */
 260     uint32 unused0[1023];
 261     PmcCtrlReg ctrl;                    /* 0x1000 */
 262
 263     PmcOutFifoReg outFifo;              /* 0x1100 */
 264     uint32 unused1[32];                 /* 0x1180-0x11ff */
 265     PmcInFifoReg inFifo;                /* 0x1200 */
 266     uint32 unused2[32];                 /* 0x1280-0x12ff */
 267
 268     PmcDmaReg dma[2];                   /* 0x1300 */
 269     uint32 unused3[48];                 /* 0x1340-0x13ff */
 270
 271     PmcTokenReg token;                  /* 0x1400 */
 272     uint32 unused4[121];                /* 0x141c-0x15ff */
 273
 274     PmcPerfPowReg perfPower;            /* 0x1600 */
 275     uint32 unused5[47];                 /* 0x1644-0x16ff */
 276
 277     uint32 msgId[32];                   /* 0x1700 */
 278     uint32 unused6[32];                 /* 0x1780-0x17ff */
 279
 280     PmcDQMReg dqm;                      /* 0x1800 */
 281     uint32 unused7[50];                 /* 0x1838-0x18ff */
 282
 283     PmcCntReg hwCounter;                /* 0x1900 */
 284     uint32 unused8[46];                 /* 0x1948-0x19ff */
 285
 286     PmcDqmQCtrlReg dqmQCtrl[32];        /* 0x1a00 */
 287     PmcDqmQDataReg dqmQData[32];        /* 0x1c00 */
 288     uint32 unused9[64];                 /* 0x1e00-0x1eff */
 289
 290     uint32 qStatus[32];                 /* 0x1f00 */
 291     uint32 unused10[32];                /* 0x1f80-0x1fff */
 292
 293     PmcDqmQMibReg qMib;                 /* 0x2000 */
 294     uint32 unused11[1952];              /* 0x2180-0x3ffff */
 295
 296     uint32 sharedMem[8192];             /* 0x4000-0xbffc */
 297 } Pmc;
 298
 299 #define PMC ((volatile Pmc * const) PMC_BASE)
 300
 301 /*
 302  * Process Monitor Module
 303  */
 304 typedef struct PMRingOscillatorControl {
 305     uint32 control;
 306     uint32 en_lo;
 307     uint32 en_mid;
 308     uint32 en_hi;
 309     uint32 idle_lo;
 310     uint32 idle_mid;
 311     uint32 idle_hi;
 312 } PMRingOscillatorControl;
 313
 314 #define RCAL_0P25UM_HORZ                0
 315 #define RCAL_0P25UM_VERT                1
 316 #define RCAL_0P5UM_HORZ                 2
 317 #define RCAL_0P5UM_VERT                 3
 318 #define RCAL_1UM_HORZ                   4
 319 #define RCAL_1UM_VERT                   5
 320 #define PMMISC_RMON_EXT_REG             ((RCAL_1UM_VERT + 1)/2)
 321 #define PMMISC_RMON_VALID_MASK          (0x1<<16)
 322 typedef struct PMMiscControl {
 323     uint32 gp_out;
 324     uint32 clock_select;
 325     uint32 unused[2];
 326     uint32 misc[4];
 327 } PMMiscControl;
 328
 329 typedef struct PMSSBMasterControl {
 330     uint32 control;
 331     uint32 wr_data;
 332     uint32 rd_data;
 333 } PMSSBMasterControl;
 334
 335 typedef struct PMEctrControl {
 336     uint32 control;
 337     uint32 interval;
 338     uint32 thresh_lo;
 339     uint32 thresh_hi;
 340     uint32 count;
 341 } PMEctrControl;
 342
 343 typedef struct PMBMaster {
 344     uint32 ctrl;
 345 #define PMC_PMBM_START                  (1 << 31)
 346 #define PMC_PMBM_TIMEOUT                (1 << 30)
 347 #define PMC_PMBM_SLAVE_ERR              (1 << 29)
 348 #define PMC_PMBM_BUSY                   (1 << 28)
 349 #define PMC_PMBM_Read                   (0 << 20)
 350 #define PMC_PMBM_Write                  (1 << 20)
 351     uint32 wr_data;
 352     uint32 timeout;
 353     uint32 rd_data;
 354     uint32 unused[4];
 355 } PMBMaster;
 356
 357 typedef struct PMAPVTMONControl {
 358     uint32 control;
 359     uint32 reserved;
 360     uint32 cfg_lo;
 361     uint32 cfg_hi;
 362     uint32 data;
 363     uint32 vref_data;
 364     uint32 unused[2];
 365     uint32 ascan_cfg;
 366     uint32 warn_temp;
 367     uint32 reset_temp;
 368     uint32 temp_value;
 369     uint32 data1_value;
 370     uint32 data2_value;
 371     uint32 data3_value;
 372 } PMAPVTMONControl;
 373
 374 typedef struct PMUBUSCfg {
 375     uint32 window[8];
 376     uint32 control;
 377 } PMUBUSCfg;
 378
 379 typedef struct ProcessMonitorRegs {
 380     uint32 MonitorCtrl;                 /* 0x00 */
 381     uint32 unused0[7];
 382     PMRingOscillatorControl ROSC;       /* 0x20 */
 383     uint32 unused1;
 384     PMMiscControl Misc;                 /* 0x40 */
 385     PMSSBMasterControl SSBMaster;       /* 0x60 */
 386     uint32 unused2[5];
 387     PMEctrControl Ectr;                 /* 0x80 */
 388     uint32 unused3[11];
 389     PMBMaster PMBM[2];                  /* 0xc0 */
 390     PMAPVTMONControl APvtmonCtrl;       /* 0x100 */
 391     uint32 unused4[9];
 392     PMUBUSCfg UBUSCfg;                  /* 0x160 */
 393 } ProcessMonitorRegs;
 394
 395 #define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE)
 396
 397
 398 /*
 399 ** Timer
 400 */
 401 #define TIMER_64BIT
 402 typedef struct Timer {
 403     uint64        TimerCtl0;
 404     uint64        TimerCtl1;
 405     uint64        TimerCtl2;
 406     uint64        TimerCtl3;
 407 #define TIMERENABLE     (1ULL << 63)
 408 #define RSTCNTCLR       (1ULL << 62)
 409     uint64        TimerCnt0;
 410     uint64        TimerCnt1;
 411     uint64        TimerCnt2;
 412     uint64        TimerCnt3;
 413 #define TIMER_COUNT_MASK   0x3FFFFFFFFFFFFFFFULL
 414     uint32        TimerMask;
 415 #define TIMER0EN        0x01
 416 #define TIMER1EN        0x02
 417 #define TIMER2EN        0x04
 418 #define TIMER3EN        0x08
 419     uint32        TimerInts;
 420 #define TIMER0          0x01
 421 #define TIMER1          0x02
 422 #define TIMER2          0x04
 423 #define TIMER3          0x08
 424     uint32        ResetStatus;
 425 #define PCIE_RESET_STATUS       0x10000000
 426 #define SW_RESET_STATUS         0x20000000
 427 #define HW_RESET_STATUS         0x40000000
 428 #define POR_RESET_STATUS        0x80000000
 429 #define RESET_STATUS_MASK       0xF0000000
 430     uint32        ResetReason;
 431 #define SW_INI_RESET            0x00000001
 432     uint32        spare[3];
 433 } Timer;
 434
 435 typedef struct WDTimer {
 436     uint32        WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer
 437      * Write 0xee00 0x00ee to Stop and re-load default count
 438      *      * Read from this register returns current watch dog count
 439      *           */
 440     uint32        WatchDogCtl;
 441
 442     /* Number of 50-MHz ticks for WD Reset pulse to last */
 443     uint32        WDResetCount;
 444
 445     uint32        SoftRst;
 446 #define SOFT_RESET              0x00000001
 447     uint32        WDAccessCtl;
 448 } WDTimer;
 449
 450 #define TIMER ((volatile Timer * const) TIMR_BASE)
 451 #define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE)
 452
 453 typedef struct BIUCFG_Access {
 454     uint32 permission;        /* 0x0 */
 455     uint32 sbox;              /* 0x4 */
 456     uint32 cpu_defeature;     /* 0x8 */
 457     uint32 dbg_security;      /* 0xc */
 458     uint32 rsvd1[32];         /* 0x10 - 0x8f */
 459     uint64 violation[2];      /* 0x90 - 0x9f */
 460     uint32 ts_access[2];      /* 0xa0 - 0xa7 */
 461     uint32 rsvd2[22];         /* 0xa8 - 0xff */
 462 }BIUCFG_Access;
 463
 464 typedef struct BIUCFG_Cluster {
 465     uint32 permission;        /* 0x0 */
 466     uint32 config;            /* 0x4 */
 467     uint32 status;            /* 0x8 */
 468     uint32 control;           /* 0xc */
 469     uint32 cpucfg;            /* 0x10 */
 470     uint32 dbgrom;            /* 0x14 */
 471     uint32 rsvd1[2];          /* 0x18 - 0x1f */
 472     uint32 rvbar_addr[4];     /* 0x20 - 0x2f */
 473     uint32 rsvd2[52];         /* 0x30 - 0xff */
 474 }BIUCFG_Cluster;
 475
 476 typedef struct BIUCFG_AuxClkCtrl {
 477     uint32 clk_control;       /* 0x0 */
 478     uint32 clk_ramp;          /* 0x4 */
 479     uint32 clk_pattern;       /* 0x8 */
 480     uint32 rsvd;              /* 0xC */
 481 } BIUCFG_AuxClkCtrl;
 482
 483 typedef struct BIUCFG_Aux {
 484     uint32            permission;         /* 0 */
 485     uint32            rsvd1[3];           /* 0x04 - 0x0c */
 486     BIUCFG_AuxClkCtrl cluster_clkctrl[2]; /* 0x10 - 0x2c */
 487     uint32            rsvd2[52];          /* 0x30 - 0xFF */
 488 } BIUCFG_Aux;
 489
 490 typedef struct BIUCFG {
 491     BIUCFG_Access  access;        /* 0x0 - 0xff*/
 492     BIUCFG_Cluster cluster[1];    /* 0x100 - 0x1ff*/
 493     uint32         rsvd1[320];    /* 0x200 - 0x6ff */
 494     BIUCFG_Aux     aux;           /* 0x700 - 0x7ff */
 495     uint32         rsvd2[2560];   /* 0x800 - 0x2fff */
 496
 497 }BIUCFG;
 498 #define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
 499
 500 #endif /* __ASSEMBLER__ */
 501
 502 #ifdef __cplusplus
 503 }
 504 #endif
 505
 506 #endif