target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts

   1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 #include "mt7622.dtsi"
   8 #include "mt6380.dtsi"
   9
  10 / {
  11         model = "TOTOLINK A8000RU";
  12         compatible = "totolink,a8000ru", "mediatek,mt7622";
  13
  14         aliases {
  15                 label-mac-device = &gmac0;
  16                 led-boot = &led_status;
  17                 led-failsafe = &led_status;
  18                 led-running = &led_status;
  19                 led-upgrade = &led_status;
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 reset {
  44                         label = "reset";
  45                         linux,code = <KEY_RESTART>;
  46                         gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  47                 };
  48
  49                 wps {
  50                         label = "wps";
  51                         linux,code = <KEY_WPS_BUTTON>;
  52                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  53                 };
  54         };
  55
  56         gpio-leds {
  57                 compatible = "gpio-leds";
  58
  59                 led_status: status_red {
  60                         label = "red:status";
  61                         gpios = <&pio 81 GPIO_ACTIVE_LOW>;
  62                         default-state = "on";
  63                 };
  64         };
  65
  66         reg_1p8v: regulator-1p8v {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "fixed-1.8V";
  69                 regulator-min-microvolt = <1800000>;
  70                 regulator-max-microvolt = <1800000>;
  71                 regulator-always-on;
  72         };
  73
  74         reg_3p3v: regulator-3p3v {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "fixed-3.3V";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 regulator-boot-on;
  80                 regulator-always-on;
  81         };
  82
  83         rtkgsw: rtkgsw@0 {
  84                 compatible = "mediatek,rtk-gsw";
  85                 mediatek,ethsys = <&ethsys>;
  86                 mediatek,mdio = <&mdio>;
  87                 mediatek,reset-pin = <&pio 54 0>;
  88                 status = "okay";
  89         };
  90 };
  91
  92 &pcie0 {
  93         pinctrl-names = "default";
  94         pinctrl-0 = <&pcie0_pins>;
  95         status = "okay";
  96 };
  97
  98 &slot0 {
  99         mt7615@0,0 {
 100                 reg = <0x0000 0 0 0 0>;
 101                 mediatek,mtd-eeprom = <&factory 0x5000>;
 102                 ieee80211-freq-limit = <5490000 6000000>;
 103         };
 104 };
 105
 106 &pcie1 {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pcie1_pins>;
 109         status = "okay";
 110 };
 111
 112 &slot1 {
 113         mt7615@0,0 {
 114                 reg = <0x0000 0 0 0 0>;
 115                 mediatek,mtd-eeprom = <&factory 0x10000>;
 116                 ieee80211-freq-limit = <5000000 5490000>;
 117         };
 118 };
 119
 120 &pio {
 121         eth_pins: eth-pins {
 122                 mux {
 123                         function = "eth";
 124                         groups = "mdc_mdio", "rgmii_via_gmac2";
 125                 };
 126         };
 127
 128         pcie0_pins: pcie0-pins {
 129                 mux {
 130                         function = "pcie";
 131                         groups = "pcie0_pad_perst",
 132                                  "pcie0_1_waken",
 133                                  "pcie0_1_clkreq";
 134                 };
 135         };
 136
 137         pcie1_pins: pcie1-pins {
 138                 mux {
 139                         function = "pcie";
 140                         groups = "pcie1_pad_perst",
 141                                  "pcie1_0_waken",
 142                                  "pcie1_0_clkreq";
 143                 };
 144         };
 145
 146         pmic_bus_pins: pmic-bus-pins {
 147                 mux {
 148                         function = "pmic";
 149                         groups = "pmic_bus";
 150                 };
 151         };
 152
 153         /* serial NAND is shared pin with SPI-NOR */
 154         serial_nand_pins: serial-nand-pins {
 155                 mux {
 156                         function = "flash";
 157                         groups = "snfi";
 158                 };
 159         };
 160
 161         uart0_pins: uart0-pins {
 162                 mux {
 163                         function = "uart";
 164                         groups = "uart0_0_tx_rx" ;
 165                 };
 166         };
 167
 168         watchdog_pins: watchdog-pins {
 169                 mux {
 170                         function = "watchdog";
 171                         groups = "watchdog";
 172                 };
 173         };
 174
 175         epa_elna_pins: epa-elna-pins {
 176                 mux {
 177                         function = "antsel";
 178                         groups = "antsel0", "antsel1", "antsel2", "antsel3",
 179                                 "antsel4", "antsel5", "antsel6", "antsel7",
 180                                 "antsel8", "antsel9", "antsel12", "antsel13",
 181                                 "antsel14", "antsel15", "antsel16", "antsel17";
 182                 };
 183         };
 184 };
 185
 186 &eth {
 187         status = "okay";
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&eth_pins>;
 190
 191         gmac0: mac@0 {
 192                 compatible = "mediatek,eth-mac";
 193                 reg = <0>;
 194                 nvmem-cells = <&macaddr_factory_2a>;
 195                 nvmem-cell-names = "mac-address";
 196                 phy-connection-type = "2500base-x";
 197                 fixed-link {
 198                         speed = <2500>;
 199                         full-duplex;
 200                         pause;
 201                 };
 202         };
 203
 204         gmac1: mac@1 {
 205                 compatible = "mediatek,eth-mac";
 206                 reg = <1>;
 207                 phy-mode = "rgmii";
 208                 nvmem-cells = <&macaddr_factory_24>;
 209                 nvmem-cell-names = "mac-address";
 210                 fixed-link {
 211                         speed = <1000>;
 212                         full-duplex;
 213                         pause;
 214                 };
 215         };
 216
 217         mdio: mdio-bus {
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220         };
 221 };
 222
 223 &pwrap {
 224         pinctrl-names = "default";
 225         pinctrl-0 = <&pmic_bus_pins>;
 226         status = "okay";
 227 };
 228
 229 &bch {
 230         status = "okay";
 231 };
 232
 233 &snfi {
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&serial_nand_pins>;
 236         status = "okay";
 237         flash@0 {
 238                 compatible = "spi-nand";
 239                 reg = <0>;
 240                 spi-tx-bus-width = <4>;
 241                 spi-rx-bus-width = <4>;
 242                 nand-ecc-engine = <&snfi>;
 243                 mediatek,bmt-v2;
 244
 245                 partitions {
 246                         compatible = "fixed-partitions";
 247                         #address-cells = <1>;
 248                         #size-cells = <1>;
 249
 250                         partition@0 {
 251                                 label = "Preloader";
 252                                 reg = <0x0 0x80000>;
 253                                 read-only;
 254                         };
 255
 256                         partition@80000 {
 257                                 label = "ATF";
 258                                 reg = <0x80000 0x40000>;
 259                                 read-only;
 260                         };
 261
 262                         partition@c0000 {
 263                                 label = "u-boot";
 264                                 reg = <0xc0000 0x80000>;
 265                                 read-only;
 266                         };
 267
 268                         partition@140000 {
 269                                 label = "u-boot-env";
 270                                 reg = <0x140000 0x80000>;
 271                                 read-only;
 272                         };
 273
 274                         factory: partition@1c0000 {
 275                                 label = "factory";
 276                                 reg = <0x1c0000 0x40000>;
 277                                 read-only;
 278                         };
 279
 280                         partition@200000 {
 281                                 label = "ubi";
 282                                 reg = <0x200000 0x6400000>;
 283                         };
 284
 285                         partition@6600000 {
 286                                 label = "User_data";
 287                                 reg = <0x6600000 0x100000>;
 288                         };
 289
 290                         /* size of this partition varies due to BMT & bad blocks. */
 291                         partition@6700000 {
 292                                 label = "reserved";
 293                                 reg = <0x6700000 0>;
 294                         };
 295                 };
 296         };
 297 };
 298
 299 &factory {
 300         compatible = "nvmem-cells";
 301         #address-cells = <1>;
 302         #size-cells = <1>;
 303
 304         macaddr_factory_24: macaddr@24 {
 305                 reg = <0x24 0x6>;
 306         };
 307
 308         macaddr_factory_2a: macaddr@2a {
 309                 reg = <0x2a 0x6>;
 310         };
 311 };
 312
 313 &ssusb {
 314         vusb33-supply = <&reg_3p3v>;
 315         status = "okay";
 316 };
 317
 318 &u3phy {
 319         status = "okay";
 320 };
 321
 322 &uart0 {
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&uart0_pins>;
 325         status = "okay";
 326 };
 327
 328 &watchdog {
 329         pinctrl-names = "default";
 330         pinctrl-0 = <&watchdog_pins>;
 331         status = "okay";
 332 };
 333
 334 &wmac {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&epa_elna_pins>;
 337         mediatek,mtd-eeprom = <&factory 0x0>;
 338         status = "okay";
 339 };