realtek: clock driver: switch RTL930X DT syntax PR-930X-CLK
authorMarkus Stockhausen <markus.stockhausen@gmx.de>
Tue, 6 Sep 2022 09:47:54 +0000 (11:47 +0200)
committerSander Vanheule <sander@svanheule.net>
Mon, 26 Dec 2022 19:29:36 +0000 (20:29 +0100)
Use new DT clockdriver syntax for RTL930X target. To make it work we
need to change some nodes:

- define SRAM
- add clock controller
- Add second CPU node for future SMP use
- map all devices to new clocks
- Remove dummy LXB clock
- add CPU OPP table

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
target/linux/realtek/dts-5.10/rtl930x.dtsi

index c2a992a174c77ccc542b51c28d3b1dc8ffa72f40..60ec28866ede08bcbfbd9bd1f070cde0c479559f 100644 (file)
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include <dt-bindings/clock/rtl83xx-clk.h>
+
 /dts-v1/;
 
 / {
 
        compatible = "realtek,rtl838x-soc";
 
+       ccu: clock-controller {
+               compatible = "realtek,rtl9300-clock";
+               #clock-cells = <1>;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               frequency = <800000000>;
 
                cpu@0 {
                        compatible = "mips,mips34Kc";
                        reg = <0>;
+                       clocks = <&ccu CLK_CPU>;
+                       operating-points-v2 = <&cpu_opp_table>;
+               };
+       };
+
+       cpu_opp_table: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp00 {
+                       opp-hz = /bits/ 64 <625000000>;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <650000000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <675000000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <700000000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <725000000>;
+               };
+               opp05 {
+                       opp-hz = /bits/ 64 <750000000>;
+               };
+               opp06 {
+                       opp-hz = /bits/ 64 <775000000>;
+               };
+               opp07 {
+                       opp-hz = /bits/ 64 <800000000>;
                };
        };
 
                interrupt-controller;
        };
 
-       lx_clk: lx_clk {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency  = <175000000>;
-       };
-
        soc: soc {
                compatible = "simple-bus";
                #address-cells = <1>;
                        compatible = "ns16550a";
                        reg = <0x2000 0x100>;
 
-                       clocks = <&lx_clk>;
+                       clocks = <&ccu CLK_LXB>;
 
                        interrupt-parent = <&intc>;
                        interrupts = <30 1>;
                        compatible = "ns16550a";
                        reg = <0x2100 0x100>;
 
-                       clocks = <&lx_clk>;
+                       clocks = <&ccu CLK_LXB>;
 
                        interrupt-parent = <&intc>;
                        interrupts = <31 0>;
 
                        realtek,reset-mode = "soc";
 
-                       clocks = <&lx_clk>;
+                       clocks = <&ccu CLK_LXB>;
                        timeout-sec = <30>;
 
                        interrupt-parent = <&intc>;
                };
        };
 
+       sram0: sram@9f000000 {
+               compatible = "mmio-sram";
+               reg = <0x9f000000 0x10000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x9f000000 0x10000>;
+
+               sram_scratch: scratch-sram@0 {
+                       compatible = "realtek,scratch";
+                       reg = <0x0 0x20>;
+                       pool;
+               };
+       };
+
        switch0: switch@1b000000 {
                compatible = "realtek,rtl83xx-switch";
                status = "okay";