lantiq: pcie: fix inverted gpio reset logic

Asserting the reset should be logic 1 and subsequently deasserting the
reset should be logic 0.

While at it remove the calls to gpio_direction_output(). While getting
the GPIO the direction is already set.

Signed-off-by: Mathias Kresin <dev@kresin.me>

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts
index fea1e1c5b4255651984b8fe23808f11cbd814937..e7937c1952e129edf1ed1a98204701e57c7850f9 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts
@@ -154,5 +154,5 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_LOW>;
 };

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts
index c924a2b2751dc63f29a206f3e6f0647705e66f0d..9c43c1486199d310bf17fa1de1fa27a03e77ece3 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts
@@ -222,7 +222,7 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
 &usb_phy0 {

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts
index bf56dc8fbc9507158c3eafb52fba5f73d3e727f5..93d3a9feb4141a13659a0b955b857a407c0d162b 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts
@@ -143,5 +143,5 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_LOW>;
 };

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi
index 615cd9dcbff97caf0aeddec55e66e667efb967fd..a69b7b68b235d779cc77e8048417914039afc9b2 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi
@@ -210,7 +210,7 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
 &pcie_bridge0 {

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts
index 9511e36413b710d0ee91d1b44972f25f87026aec..d887e10c456f97b4b477a7691ecaa99a3c3d634c 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts
@@ -290,7 +290,7 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
+       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
 };
 
 &pcie_bridge0 {

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi
index f4bfcf5e6c55413319c1e601c2acf8a821ca3dc9..064c5c25af9636dcd34110e7ec528932fcccf670 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi
@@ -179,7 +179,7 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
+       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
 };
 
 &pcie_bridge0 {

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts
index 69ad8fef25124fa2b9965eb66748e8d3ab696221..37929a2febeac151cb3537b852d1860c75111b35 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts
@@ -147,7 +147,7 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 11 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 11 GPIO_ACTIVE_LOW>;
 };
 
 &pcie_bridge0 {

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts
index 8c43416ace1b536e8fe7b18a856e6ffd11d10dfa..5d53cd5092e860f01642f27fffd859e47b6b07d5 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts
@@ -159,7 +159,7 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 11 GPIO_ACTIVE_LOW>;
+       gpio-reset = <&gpio 11 GPIO_ACTIVE_HIGH>;
 };
 
 &pcie_bridge0 {

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts
index c311be25949cb60be31b3546c924284d083edfca..3afe801c36d511b1ac93796a9018ad51e6960020 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts
@@ -273,7 +273,7 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_LOW>;
 };
 
 &usb_phy0 {

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts
index edb02267e8dc215d7b228bcd12ce8dcf7c3b5d75..3fbcd8ef4084e1372274b57e0b7c0bae4d53bcf5 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts
@@ -311,5 +311,5 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_LOW>;
 };

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi
index da8a00d719115baf45911525bbce53df47f694d4..df835d72a99174eeee75047148d7be31d0f37cec 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi
@@ -281,5 +281,5 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_LOW>;
 };

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi
index 0af05751b56f0e4d25ed9bcc9f06edc16fa3386a..70ae5314ef430e4fbbdeeb0e54bb384e06968391 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi
@@ -201,7 +201,7 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_LOW>;
 };
 
 &pcie_bridge0 {

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
index 6b3a814f8d9fa21bc16298f60f92d06ed91371fe..346f026878544ded94742c03be81632f1651e502 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
@@ -191,7 +191,7 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_LOW>;
 };
 
 &pcie_bridge0 {

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts
index 1810334fd4706a53b08eb33559d330dea0a3695c..e52fbb0668d63a3d8f032c4f225552f4abb96ab9 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts
@@ -72,5 +72,5 @@
 
 &pcie0 {
        status = "okay";
-       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_LOW>;
 };

diff --git a/target/linux/lantiq/patches-5.10/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.10/0151-lantiq-ifxmips_pcie-use-of.patch
index 10633199e67ffc241ec5fca4143149274d43c764..794ff23cc7791b821a1c331fbfc2dc6c3cc4f23e 100644 (file)
--- a/target/linux/lantiq/patches-5.10/0151-lantiq-ifxmips_pcie-use-of.patch
+++ b/target/linux/lantiq/patches-5.10/0151-lantiq-ifxmips_pcie-use-of.patch
@@ -27,30 +27,29 @@
  
  static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
      {
-@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ...
+@@ -82,6 +93,21 @@ void ifx_pcie_debug(const char *fmt, ...
        printk("%s", buf);
  }
  
 +static inline void pcie_ep_gpio_rst_init(int pcie_port)
 +{
-+      gpio_direction_output(pcie_reset_gpio, 1);
-+      gpio_set_value(pcie_reset_gpio, 1);
++      gpio_set_value(pcie_reset_gpio, 0);
 +}
 +
 +static inline void pcie_device_rst_assert(int pcie_port)
 +{
-+      gpio_set_value(pcie_reset_gpio, 0);
++      gpio_set_value(pcie_reset_gpio, 1);
 +}
 +
 +static inline void pcie_device_rst_deassert(int pcie_port)
 +{
 +      mdelay(100);
-+      gpio_direction_output(pcie_reset_gpio, 1);
++      gpio_set_value(pcie_reset_gpio, 0);
 +}
  
  static inline int pcie_ltssm_enable(int pcie_port)
  {
-@@ -988,10 +1015,22 @@ int  ifx_pcie_bios_plat_dev_init(struct
+@@ -988,10 +1014,22 @@ int  ifx_pcie_bios_plat_dev_init(struct
  static int
  pcie_rc_initialize(int pcie_port)
  {
@@ -75,7 +74,7 @@
  
        pcie_ep_gpio_rst_init(pcie_port);
  
-@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port)
+@@ -1000,26 +1038,21 @@ pcie_rc_initialize(int pcie_port)
        * reset PCIe PHY will solve this issue 
        */
        for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
@@ -112,7 +111,7 @@
  
                /* Enable PCIe PHY and Clock */
                pcie_core_pmu_setup(pcie_port);
-@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port)
+@@ -1035,6 +1068,10 @@ pcie_rc_initialize(int pcie_port)
                /* Once link is up, break out */
                if (pcie_app_loigc_setup(pcie_port) == 0)
                        break;
@@ -123,7 +122,7 @@
        }
        if (i >= IFX_PCIE_PHY_LOOP_CNT) {
                printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
-@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port)
+@@ -1045,17 +1082,67 @@ pcie_rc_initialize(int pcie_port)
        return 0;
  }
  
@@ -187,13 +186,13 @@
 +            dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
 +            return ret;
 +        }
-+        gpio_direction_output(pcie_reset_gpio, 1);
++        gpio_direction_output(pcie_reset_gpio, 0);
 +    }
 +
      for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
        if (pcie_rc_initialize(pcie_port) == 0) {
            IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
-@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1067,6 +1154,7 @@ static int __init ifx_pcie_bios_init(voi
                  return -ENOMEM;
              }
              ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
@@ -201,7 +200,7 @@
  
              register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
              /* XXX, clear error status */
-@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1083,6 +1171,30 @@ static int __init ifx_pcie_bios_init(voi
  
      return 0;
  }

diff --git a/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch
index bc02a58b1c7344fe133da70d219f0e1ec5744f79..b4ef88e94f9f46efc1ec450edb1d63ad6306abfc 100644 (file)
--- a/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch
+++ b/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch
@@ -27,30 +27,29 @@
  
  static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
      {
-@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ...
+@@ -82,6 +93,21 @@ void ifx_pcie_debug(const char *fmt, ...
        printk("%s", buf);
  }
  
 +static inline void pcie_ep_gpio_rst_init(int pcie_port)
 +{
-+      gpio_direction_output(pcie_reset_gpio, 1);
-+      gpio_set_value(pcie_reset_gpio, 1);
++      gpio_set_value(pcie_reset_gpio, 0);
 +}
 +
 +static inline void pcie_device_rst_assert(int pcie_port)
 +{
-+      gpio_set_value(pcie_reset_gpio, 0);
++      gpio_set_value(pcie_reset_gpio, 1);
 +}
 +
 +static inline void pcie_device_rst_deassert(int pcie_port)
 +{
 +      mdelay(100);
-+      gpio_direction_output(pcie_reset_gpio, 1);
++      gpio_set_value(pcie_reset_gpio, 0);
 +}
  
  static inline int pcie_ltssm_enable(int pcie_port)
  {
-@@ -988,10 +1015,22 @@ int  ifx_pcie_bios_plat_dev_init(struct
+@@ -988,10 +1014,22 @@ int  ifx_pcie_bios_plat_dev_init(struct
  static int
  pcie_rc_initialize(int pcie_port)
  {
@@ -75,7 +74,7 @@
  
        pcie_ep_gpio_rst_init(pcie_port);
  
-@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port)
+@@ -1000,26 +1038,21 @@ pcie_rc_initialize(int pcie_port)
        * reset PCIe PHY will solve this issue 
        */
        for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
@@ -112,7 +111,7 @@
  
                /* Enable PCIe PHY and Clock */
                pcie_core_pmu_setup(pcie_port);
-@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port)
+@@ -1035,6 +1068,10 @@ pcie_rc_initialize(int pcie_port)
                /* Once link is up, break out */
                if (pcie_app_loigc_setup(pcie_port) == 0)
                        break;
@@ -123,7 +122,7 @@
        }
        if (i >= IFX_PCIE_PHY_LOOP_CNT) {
                printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
-@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port)
+@@ -1045,17 +1082,67 @@ pcie_rc_initialize(int pcie_port)
        return 0;
  }
  
@@ -187,13 +186,13 @@
 +            dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
 +            return ret;
 +        }
-+        gpio_direction_output(pcie_reset_gpio, 1);
++        gpio_direction_output(pcie_reset_gpio, 0);
 +    }
 +
      for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
        if (pcie_rc_initialize(pcie_port) == 0) {
            IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
-@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1067,6 +1154,7 @@ static int __init ifx_pcie_bios_init(voi
                  return -ENOMEM;
              }
              ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
@@ -201,7 +200,7 @@
  
              register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
              /* XXX, clear error status */
-@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1083,6 +1171,30 @@ static int __init ifx_pcie_bios_init(voi
  
      return 0;
  }