--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
-@@ -369,6 +369,8 @@ static unsigned long __init bootmap_byte
+@@ -377,6 +377,8 @@ static unsigned long __init bootmap_byte
return ALIGN(bytes, sizeof(long));
}
static void __init bootmem_init(void)
{
unsigned long reserved_end;
-@@ -442,7 +444,7 @@ static void __init bootmem_init(void)
+@@ -456,7 +458,7 @@ static void __init bootmem_init(void)
/*
* Reserve any memory between the start of RAM and PHYS_OFFSET
*/
add_memory_region(PHYS_OFFSET, ramstart - PHYS_OFFSET,
BOOT_MEM_RESERVED);
-@@ -652,8 +654,6 @@ static void __init bootmem_init(void)
+@@ -665,8 +667,6 @@ static void __init bootmem_init(void)
* initialization hook for anything else was introduced.
*/
+++ /dev/null
-From 7768798964eb0e4f95eaecffb93b5d0ca28a38af Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 3 Jun 2017 20:00:03 +0200
-Subject: [PATCH] MIPS: pci-mt7620: enabled PCIe on MT7688
-To: linux-mips@linux-mips.org,
- John Crispin <john@phrozen.org>
-Cc: Wei Yongjun <yongjun_wei@trendmicro.com.cn>,
- Ralf Baechle <ralf@linux-mips.org>,
- linux-mediatek@lists.infradead.org
-
-Use PCIe support for MT7628AN also on MT7688.
-Tested on WRTNODE2R.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- arch/mips/pci/pci-mt7620.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/pci/pci-mt7620.c
-+++ b/arch/mips/pci/pci-mt7620.c
-@@ -316,6 +316,7 @@ static int mt7620_pci_probe(struct platf
- break;
-
- case MT762X_SOC_MT7628AN:
-+ case MT762X_SOC_MT7688:
- if (mt7628_pci_hw_init(pdev))
- return -1;
- break;
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
-@@ -910,7 +910,6 @@ static void __init arch_mem_init(char **
+@@ -932,7 +932,6 @@ static void __init arch_mem_init(char **
crashk_res.end - crashk_res.start + 1,
BOOTMEM_DEFAULT);
#endif
sparse_init();
plat_swiotlb_setup();
-@@ -1026,6 +1025,7 @@ void __init setup_arch(char **cmdline_p)
+@@ -1051,6 +1050,7 @@ void __init setup_arch(char **cmdline_p)
cpu_cache_init();
paging_init();
#include "gpiolib.h"
-@@ -513,3 +515,68 @@ void of_gpiochip_remove(struct gpio_chip
+@@ -660,3 +662,68 @@ void of_gpiochip_remove(struct gpio_chip
gpiochip_remove_pin_ranges(chip);
of_node_put(chip->of_node);
}
+module_platform_driver(gpio_export_driver);
--- a/drivers/gpio/gpiolib-sysfs.c
+++ b/drivers/gpio/gpiolib-sysfs.c
-@@ -553,7 +553,7 @@ static struct class gpio_class = {
+@@ -568,7 +568,7 @@ static struct class gpio_class = {
*
* Returns zero on success, else an error.
*/
{
struct gpio_chip *chip;
struct gpio_device *gdev;
-@@ -615,6 +615,8 @@ int gpiod_export(struct gpio_desc *desc,
+@@ -630,6 +630,8 @@ int gpiod_export(struct gpio_desc *desc,
offset = gpio_chip_hwgpio(desc);
if (chip->names && chip->names[offset])
ioname = chip->names[offset];
dev = device_create_with_groups(&gpio_class, &gdev->dev,
MKDEV(0, 0), data, gpio_groups,
-@@ -636,6 +638,12 @@ err_unlock:
+@@ -651,6 +653,12 @@ err_unlock:
gpiod_dbg(desc, "%s: status %d\n", __func__, status);
return status;
}
{
--- a/include/linux/gpio/consumer.h
+++ b/include/linux/gpio/consumer.h
-@@ -451,6 +451,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_
+@@ -533,6 +533,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_
#if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
int gpiod_export_link(struct device *dev, const char *name,
struct gpio_desc *desc);
-@@ -458,6 +459,13 @@ void gpiod_unexport(struct gpio_desc *de
+@@ -540,6 +541,13 @@ void gpiod_unexport(struct gpio_desc *de
#else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
-@@ -629,6 +629,8 @@ config RALINK
+@@ -623,6 +623,8 @@ config RALINK
select CLKDEV_LOOKUP
select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER
bool "SGI IP22 (Indy/Indigo2)"
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
-@@ -143,6 +143,11 @@ config PINCTRL_LPC18XX
+@@ -138,6 +138,11 @@ config PINCTRL_LPC18XX
help
Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
depends on SOC_FALCON
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
-@@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-
+@@ -26,6 +26,7 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
+#endif /* __ASM_MACH_RALINK_GPIO_H */
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
-@@ -398,6 +398,12 @@ config GPIO_REG
+@@ -439,6 +439,12 @@ config GPIO_REG
A 32-bit single register GPIO fixed in/out implementation. This
can be used to represent any register as a set of GPIO signals.
depends on PLAT_SPEAR
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
-@@ -98,6 +98,7 @@ obj-$(CONFIG_GPIO_PCI_IDIO_16) += gpio-p
- obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o
+@@ -104,6 +104,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr
obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
+ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
+++ /dev/null
-From 61ac7d9b4228de8c332900902c2b93189b042eab Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 11:00:32 +0100
-Subject: [PATCH 28/53] GPIO: ralink: add mt7621 gpio controller
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/Kconfig | 3 +
- drivers/gpio/Kconfig | 6 +
- drivers/gpio/Makefile | 1 +
- drivers/gpio/gpio-mt7621.c | 354 ++++++++++++++++++++++++++++++++++++++++++++
- 4 files changed, 364 insertions(+)
- create mode 100644 drivers/gpio/gpio-mt7621.c
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -631,6 +631,9 @@ config RALINK
- select RESET_CONTROLLER
- select PINCTRL
- select PINCTRL_RT2880
-+ select ARCH_HAS_RESET_CONTROLLER
-+ select RESET_CONTROLLER
-+ select ARCH_REQUIRE_GPIOLIB
-
- config SGI_IP22
- bool "SGI IP22 (Indy/Indigo2)"
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -298,6 +298,12 @@ config GPIO_MENZ127
- help
- Say yes here to support the MEN 16Z127 GPIO Controller
-
-+config GPIO_MT7621
-+ bool "Mediatek GPIO Support"
-+ depends on SOC_MT7620 || SOC_MT7621
-+ help
-+ Say yes here to support the Mediatek SoC GPIO device
-+
- config GPIO_MM_LANTIQ
- bool "Lantiq Memory mapped GPIOs"
- depends on LANTIQ && SOC_XWAY
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -152,3 +152,4 @@ obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
- obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
- obj-$(CONFIG_GPIO_ZX) += gpio-zx.o
- obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o
-+obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
---- /dev/null
-+++ b/drivers/gpio/gpio-mt7621.c
-@@ -0,0 +1,354 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/io.h>
-+#include <linux/err.h>
-+#include <linux/gpio.h>
-+#include <linux/module.h>
-+#include <linux/of_irq.h>
-+#include <linux/spinlock.h>
-+#include <linux/irqdomain.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+
-+#define MTK_MAX_BANK 3
-+#define MTK_BANK_WIDTH 32
-+
-+enum mediatek_gpio_reg {
-+ GPIO_REG_CTRL = 0,
-+ GPIO_REG_POL,
-+ GPIO_REG_DATA,
-+ GPIO_REG_DSET,
-+ GPIO_REG_DCLR,
-+ GPIO_REG_REDGE,
-+ GPIO_REG_FEDGE,
-+ GPIO_REG_HLVL,
-+ GPIO_REG_LLVL,
-+ GPIO_REG_STAT,
-+ GPIO_REG_EDGE,
-+};
-+
-+static void __iomem *mediatek_gpio_membase;
-+static int mediatek_gpio_irq;
-+static struct irq_domain *mediatek_gpio_irq_domain;
-+static atomic_t irq_refcount = ATOMIC_INIT(0);
-+
-+struct mtk_gc {
-+ struct gpio_chip chip;
-+ spinlock_t lock;
-+ int bank;
-+ u32 rising;
-+ u32 falling;
-+} *gc_map[MTK_MAX_BANK];
-+
-+static inline struct mtk_gc
-+*to_mediatek_gpio(struct gpio_chip *chip)
-+{
-+ struct mtk_gc *mgc;
-+
-+ mgc = container_of(chip, struct mtk_gc, chip);
-+
-+ return mgc;
-+}
-+
-+static inline void
-+mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
-+{
-+ iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
-+}
-+
-+static inline u32
-+mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
-+{
-+ return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
-+}
-+
-+static void
-+mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+
-+ mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
-+}
-+
-+static int
-+mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+
-+ return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
-+}
-+
-+static int
-+mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
-+ t &= ~BIT(offset);
-+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int
-+mediatek_gpio_direction_output(struct gpio_chip *chip,
-+ unsigned offset, int value)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
-+ t |= BIT(offset);
-+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
-+ mediatek_gpio_set(chip, offset, value);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int
-+mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ if (t & BIT(offset))
-+ return 0;
-+
-+ return 1;
-+}
-+
-+static int
-+mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+
-+ return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH));
-+}
-+
-+static int
-+mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
-+{
-+ const __be32 *id = of_get_property(bank, "reg", NULL);
-+ struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
-+ sizeof(struct mtk_gc), GFP_KERNEL);
-+
-+ if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK)
-+ return -ENOMEM;
-+
-+ gc_map[be32_to_cpu(*id)] = rg;
-+
-+ memset(rg, 0, sizeof(struct mtk_gc));
-+
-+ spin_lock_init(&rg->lock);
-+
-+ rg->chip.parent = &pdev->dev;
-+ rg->chip.label = dev_name(&pdev->dev);
-+ rg->chip.of_node = bank;
-+ rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
-+ rg->chip.ngpio = MTK_BANK_WIDTH;
-+ rg->chip.direction_input = mediatek_gpio_direction_input;
-+ rg->chip.direction_output = mediatek_gpio_direction_output;
-+ rg->chip.get_direction = mediatek_gpio_get_direction;
-+ rg->chip.get = mediatek_gpio_get;
-+ rg->chip.set = mediatek_gpio_set;
-+ if (mediatek_gpio_irq_domain)
-+ rg->chip.to_irq = mediatek_gpio_to_irq;
-+ rg->bank = be32_to_cpu(*id);
-+
-+ /* set polarity to low for all gpios */
-+ mtk_gpio_w32(rg, GPIO_REG_POL, 0);
-+
-+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
-+
-+ return gpiochip_add(&rg->chip);
-+}
-+
-+static void
-+mediatek_gpio_irq_handler(struct irq_desc *desc)
-+{
-+ int i;
-+
-+ for (i = 0; i < MTK_MAX_BANK; i++) {
-+ struct mtk_gc *rg = gc_map[i];
-+ unsigned long pending;
-+ int bit;
-+
-+ if (!rg)
-+ continue;
-+
-+ pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
-+
-+ for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
-+ u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit);
-+
-+ generic_handle_irq(map);
-+ mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
-+ }
-+ }
-+}
-+
-+static void
-+mediatek_gpio_irq_unmask(struct irq_data *d)
-+{
-+ int pin = d->hwirq;
-+ int bank = pin / 32;
-+ struct mtk_gc *rg = gc_map[bank];
-+ unsigned long flags;
-+ u32 rise, fall;
-+
-+ if (!rg)
-+ return;
-+
-+ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
-+ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising));
-+ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static void
-+mediatek_gpio_irq_mask(struct irq_data *d)
-+{
-+ int pin = d->hwirq;
-+ int bank = pin / 32;
-+ struct mtk_gc *rg = gc_map[bank];
-+ unsigned long flags;
-+ u32 rise, fall;
-+
-+ if (!rg)
-+ return;
-+
-+ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
-+ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq));
-+ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static int
-+mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
-+{
-+ int pin = d->hwirq;
-+ int bank = pin / 32;
-+ struct mtk_gc *rg = gc_map[bank];
-+ u32 mask = BIT(d->hwirq);
-+
-+ if (!rg)
-+ return -1;
-+
-+ if (type == IRQ_TYPE_PROBE) {
-+ if ((rg->rising | rg->falling) & mask)
-+ return 0;
-+
-+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-+ }
-+
-+ if (type & IRQ_TYPE_EDGE_RISING)
-+ rg->rising |= mask;
-+ else
-+ rg->rising &= ~mask;
-+
-+ if (type & IRQ_TYPE_EDGE_FALLING)
-+ rg->falling |= mask;
-+ else
-+ rg->falling &= ~mask;
-+
-+ return 0;
-+}
-+
-+static struct irq_chip mediatek_gpio_irq_chip = {
-+ .name = "GPIO",
-+ .irq_unmask = mediatek_gpio_irq_unmask,
-+ .irq_mask = mediatek_gpio_irq_mask,
-+ .irq_mask_ack = mediatek_gpio_irq_mask,
-+ .irq_set_type = mediatek_gpio_irq_type,
-+};
-+
-+static int
-+mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq);
-+ irq_set_handler_data(irq, d);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = mediatek_gpio_gpio_map,
-+};
-+
-+static int
-+mediatek_gpio_probe(struct platform_device *pdev)
-+{
-+ struct device_node *bank, *np = pdev->dev.of_node;
-+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+ mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(mediatek_gpio_membase))
-+ return PTR_ERR(mediatek_gpio_membase);
-+
-+ mediatek_gpio_irq = irq_of_parse_and_map(np, 0);
-+ if (mediatek_gpio_irq) {
-+ mediatek_gpio_irq_domain = irq_domain_add_linear(np,
-+ MTK_MAX_BANK * MTK_BANK_WIDTH,
-+ &irq_domain_ops, NULL);
-+ if (!mediatek_gpio_irq_domain)
-+ dev_err(&pdev->dev, "irq_domain_add_linear failed\n");
-+ }
-+
-+ for_each_child_of_node(np, bank)
-+ if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
-+ mediatek_gpio_bank_probe(pdev, bank);
-+
-+ if (mediatek_gpio_irq_domain)
-+ irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mediatek_gpio_match[] = {
-+ { .compatible = "mtk,mt7621-gpio" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
-+
-+static struct platform_driver mediatek_gpio_driver = {
-+ .probe = mediatek_gpio_probe,
-+ .driver = {
-+ .name = "mt7621_gpio",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mediatek_gpio_match,
-+ },
-+};
-+
-+static int __init
-+mediatek_gpio_init(void)
-+{
-+ return platform_driver_register(&mediatek_gpio_driver);
-+}
-+
-+subsys_initcall(mediatek_gpio_init);
--- a/drivers/media/usb/uvc/uvc_driver.c
+++ b/drivers/media/usb/uvc/uvc_driver.c
-@@ -2735,6 +2735,18 @@ static const struct usb_device_id uvc_id
+@@ -2831,6 +2831,18 @@ static const struct usb_device_id uvc_id
.bInterfaceSubClass = 1,
.bInterfaceProtocol = 0,
- .driver_info = UVC_QUIRK_FORCE_Y8 },
+ .driver_info = (kernel_ulong_t)&uvc_quirk_force_y8 },
+ /* iPassion iP2970 */
+ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE
+ | USB_DEVICE_ID_MATCH_INT_INFO,
+ .bInterfaceClass = USB_CLASS_VIDEO,
+ .bInterfaceSubClass = 1,
+ .bInterfaceProtocol = 0,
-+ .driver_info = UVC_QUIRK_PROBE_MINMAX
++ .driver_info = UVC_QUIRK_INFO(UVC_QUIRK_PROBE_MINMAX
+ | UVC_QUIRK_STREAM_NO_FID
+ | UVC_QUIRK_MOTION
-+ | UVC_QUIRK_SINGLE_ISO },
++ | UVC_QUIRK_SINGLE_ISO) },
/* Generic USB Video Class */
{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) },
{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) },
--- a/drivers/media/usb/uvc/uvc_status.c
+++ b/drivers/media/usb/uvc/uvc_status.c
-@@ -139,6 +139,7 @@ static void uvc_status_complete(struct u
- switch (dev->status[0] & 0x0f) {
- case UVC_STATUS_TYPE_CONTROL:
- uvc_event_control(dev, dev->status, len);
+@@ -228,6 +228,7 @@ static void uvc_status_complete(struct u
+ if (uvc_event_control(urb, status, len))
+ /* The URB will be resubmitted in work context. */
+ return;
+ dev->motion = 1;
break;
+ }
- case UVC_STATUS_TYPE_STREAMING:
-@@ -182,6 +183,7 @@ int uvc_status_init(struct uvc_device *d
+@@ -276,6 +277,7 @@ int uvc_status_init(struct uvc_device *d
}
pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);
#include <media/v4l2-common.h>
-@@ -1101,9 +1106,149 @@ static void uvc_video_decode_data(struct
+@@ -1126,9 +1131,149 @@ static void uvc_video_decode_data(struct
}
}
+
+#define MOTION_FLAG_OFFSET 4
static void uvc_video_decode_end(struct uvc_streaming *stream,
- struct uvc_buffer *buf, const __u8 *data, int len)
+ struct uvc_buffer *buf, const u8 *data, int len)
{
+ if ((stream->dev->quirks & UVC_QUIRK_MOTION) &&
+ (data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) {
/* Mark the buffer as done if the EOF marker is set. */
if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {
uvc_trace(UVC_TRACE_FRAME, "Frame complete (EOF found).\n");
-@@ -1518,6 +1663,8 @@ static int uvc_init_video_isoc(struct uv
+@@ -1656,6 +1801,8 @@ static int uvc_init_video_isoc(struct uv
if (npackets == 0)
return -ENOMEM;
for (i = 0; i < UVC_URBS; ++i) {
--- a/drivers/media/usb/uvc/uvcvideo.h
+++ b/drivers/media/usb/uvc/uvcvideo.h
-@@ -186,7 +186,9 @@
+@@ -195,7 +195,9 @@
#define UVC_QUIRK_RESTRICT_FRAME_RATE 0x00000200
#define UVC_QUIRK_RESTORE_CTRLS_ON_INIT 0x00000400
#define UVC_QUIRK_FORCE_Y8 0x00000800
/* Format flags */
#define UVC_FMT_FLAG_COMPRESSED 0x00000001
#define UVC_FMT_FLAG_STREAM 0x00000002
-@@ -584,6 +586,7 @@ struct uvc_device {
- __u8 *status;
+@@ -606,6 +608,7 @@ struct uvc_device {
+ u8 *status;
struct input_dev *input;
char input_phys[64];
+ int motion;
- };
- enum uvc_handle_state {
+ struct uvc_ctrl_work {
+ struct work_struct work;
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
-@@ -48,6 +48,7 @@
+@@ -49,6 +49,7 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
#include <linux/usb/ch11.h>
-@@ -5215,6 +5216,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
+@@ -5165,6 +5166,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
retval = -ENOMEM;
+ device_reset(hsotg->dev);
+
- hcfg = dwc2_readl(hsotg->regs + HCFG);
+ hcfg = dwc2_readl(hsotg, HCFG);
dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
-@@ -913,7 +913,10 @@ void phy_state_machine(struct work_struc
+@@ -966,7 +966,10 @@ void phy_state_machine(struct work_struc
/* If the link is down, give up on negotiation for now */
if (!phydev->link) {
phydev->state = PHY_NOLINK;
break;
}
-@@ -1000,7 +1003,10 @@ void phy_state_machine(struct work_struc
+@@ -1053,13 +1056,19 @@ void phy_state_machine(struct work_struc
phy_link_up(phydev);
} else {
phydev->state = PHY_NOLINK;
+ else
+ phy_link_down(phydev, false);
}
-
- if (phy_interrupt_is_valid(phydev))
-@@ -1010,7 +1016,10 @@ void phy_state_machine(struct work_struc
+ break;
case PHY_HALTED:
if (phydev->link) {
phydev->link = 0;
break;
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
-@@ -412,6 +412,7 @@ struct phy_device {
- bool suspended;
- bool sysfs_links;
- bool loopback_enabled;
-+ bool no_auto_carrier_off;
+@@ -417,6 +417,7 @@ struct phy_device {
+ unsigned autoneg:1;
+ /* The most recently read link state */
+ unsigned link:1;
++ unsigned no_auto_carrier_off:1;
enum phy_state state;
/* Atmel chips don't use the same PRI format as AMD chips */
static void fixup_convert_atmel_pri(struct mtd_info *mtd)
-@@ -1792,6 +1796,7 @@ static int cfi_amdstd_write_words(struct
+@@ -1791,6 +1795,7 @@ static int cfi_amdstd_write_words(struct
/*
* FIXME: interleaved mode not tested, and probably not supported!
*/
static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
unsigned long adr, const u_char *buf,
int len)
-@@ -1920,7 +1925,6 @@ static int __xipram do_write_buffer(stru
+@@ -1919,7 +1924,6 @@ static int __xipram do_write_buffer(stru
return ret;
}
static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
-@@ -1995,6 +1999,7 @@ static int cfi_amdstd_write_buffers(stru
+@@ -1994,6 +1998,7 @@ static int cfi_amdstd_write_buffers(stru
return 0;
}
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -2577,7 +2577,7 @@ static int nand_write_page_syndrome(stru
+--- a/drivers/mtd/nand/raw/nand_base.c
++++ b/drivers/mtd/nand/raw/nand_base.c
+@@ -4308,7 +4308,7 @@ static int nand_write_page_syndrome(stru
}
/**
* @mtd: MTD device structure
* @chip: NAND chip descriptor
* @offset: address offset within the page
-@@ -2761,9 +2761,9 @@ static int nand_do_write_ops(struct mtd_
+@@ -4481,9 +4481,9 @@ static int nand_do_write_ops(struct mtd_
memset(chip->oob_poi, 0xff, mtd->oobsize);
}
if (ret)
break;
-@@ -4719,6 +4719,9 @@ int nand_scan_tail(struct mtd_info *mtd)
+@@ -6495,6 +6495,9 @@ static int nand_scan_tail(struct mtd_inf
}
}
* selected and we have 256 byte pagesize fallback to software ECC
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
-@@ -862,6 +862,7 @@ struct nand_manufacturer_ops {
+@@ -1276,6 +1276,7 @@ int nand_op_parser_exec_op(struct nand_c
* structure which is shared among multiple independent
* devices.
* @priv: [OPTIONAL] pointer to private chip data
+ * @write_page: [REPLACEABLE] High-level page write function
* @manufacturer: [INTERN] Contains manufacturer information
- */
-
-@@ -885,6 +886,9 @@ struct nand_chip {
- int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
+ * @manufacturer.desc: [INTERN] Contains manufacturer's description
+ * @manufacturer.priv: [INTERN] Contains manufacturer private information
+@@ -1303,6 +1304,9 @@ struct nand_chip {
+ const struct nand_operation *op,
+ bool check_only);
int (*erase)(struct mtd_info *mtd, int page);
- int (*scan_bbt)(struct mtd_info *mtd);
+ int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+ uint32_t offset, int data_len, const uint8_t *buf,
+ int oob_required, int page, int raw);
- int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
- int feature_addr, uint8_t *subfeature_para);
- int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
+ int (*set_features)(struct mtd_info *mtd, struct nand_chip *chip,
+ int feature_addr, uint8_t *subfeature_para);
+ int (*get_features)(struct mtd_info *mtd, struct nand_chip *chip,
create mode 100644 drivers/mtd/nand/nand_device_list.h
create mode 100644 drivers/mtd/nand/partition.h
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -563,4 +563,10 @@ config MTD_NAND_MTK
- Enables support for NAND controller on MTK SoCs.
- This controller is found on mt27xx, mt81xx, mt65xx SoCs.
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -561,4 +561,10 @@ config MTD_NAND_TEGRA
+ is supported. Extra OOB bytes when using HW ECC are currently
+ not supported.
+config MTK_MTD_NAND
+ tristate "Support for MTK SoC NAND controller"
+ select MTD_NAND_ECC
+
endif # MTD_NAND
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -60,6 +60,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) +
- obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcm
obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
- obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o mtk_ecc.o
+ obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+ obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
+obj-$(CONFIG_MTK_MTD_NAND) += mtk_nand2.o bmt.o
nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
nand-objs += nand_amd.o
--- /dev/null
-+++ b/drivers/mtd/nand/bmt.c
++++ b/drivers/mtd/nand/raw/bmt.c
@@ -0,0 +1,750 @@
+#include "bmt.h"
+
+MODULE_DESCRIPTION("Bad Block mapping management for MediaTek NAND Flash Driver");
+#endif
--- /dev/null
-+++ b/drivers/mtd/nand/bmt.h
++++ b/drivers/mtd/nand/raw/bmt.h
@@ -0,0 +1,80 @@
+#ifndef __BMT_H__
+#define __BMT_H__
+
+#endif // #ifndef __BMT_H__
--- /dev/null
-+++ b/drivers/mtd/nand/dev-nand.c
++++ b/drivers/mtd/nand/raw/dev-nand.c
@@ -0,0 +1,63 @@
+#include <linux/init.h>
+#include <linux/kernel.h>
+}
+arch_initcall(mtk_nand_register);
--- /dev/null
-+++ b/drivers/mtd/nand/mt6575_typedefs.h
++++ b/drivers/mtd/nand/raw/mt6575_typedefs.h
@@ -0,0 +1,340 @@
+/* Copyright Statement:
+ *
+#endif // _MT6575_TYPEDEFS_H
+
--- /dev/null
-+++ b/drivers/mtd/nand/mtk_nand2.c
++++ b/drivers/mtd/nand/raw/mtk_nand2.c
@@ -0,0 +1,2345 @@
+/******************************************************************************
+* mtk_nand2.c - MTK NAND Flash Device Driver
+module_exit(mtk_nand_exit);
+MODULE_LICENSE("GPL");
--- /dev/null
-+++ b/drivers/mtd/nand/mtk_nand2.h
++++ b/drivers/mtd/nand/raw/mtk_nand2.h
@@ -0,0 +1,452 @@
+#ifndef __MTK_NAND_H
+#define __MTK_NAND_H
+extern u32 CFG_BLOCKSIZE;
+#endif
+#endif
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
+--- a/drivers/mtd/nand/raw/nand_base.c
++++ b/drivers/mtd/nand/raw/nand_base.c
@@ -48,7 +48,7 @@
#include <linux/mtd/partitions.h>
#include <linux/of.h>
{
struct nand_chip *chip = mtd_to_nand(mtd);
-@@ -968,7 +968,7 @@ static void panic_nand_get_device(struct
+@@ -1042,7 +1042,7 @@ static void panic_nand_get_device(struct
*
* Get the device and lock it for exclusive access
*/
{
struct nand_chip *chip = mtd_to_nand(mtd);
--- /dev/null
-+++ b/drivers/mtd/nand/nand_def.h
++++ b/drivers/mtd/nand/raw/nand_def.h
@@ -0,0 +1,123 @@
+#ifndef __NAND_DEF_H__
+#define __NAND_DEF_H__
+
+#endif /* __NAND_DEF_H__ */
--- /dev/null
-+++ b/drivers/mtd/nand/nand_device_list.h
++++ b/drivers/mtd/nand/raw/nand_device_list.h
@@ -0,0 +1,59 @@
+/* Copyright Statement:
+ *
+
+#endif
--- /dev/null
-+++ b/drivers/mtd/nand/partition.h
++++ b/drivers/mtd/nand/raw/partition.h
@@ -0,0 +1,115 @@
+/* Copyright Statement:
+ *
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -1908,6 +1908,9 @@ static int nand_do_read_ops(struct mtd_i
- __func__, buf);
-
- read_retry:
+--- a/drivers/mtd/nand/raw/nand_base.c
++++ b/drivers/mtd/nand/raw/nand_base.c
+@@ -3588,6 +3588,9 @@ read_retry:
+ * Now read the page into the buffer. Absent an error,
+ * the read methods return max bitflips per ecc step.
+ */
+#ifdef CONFIG_MTK_MTD_NAND
+ ret = chip->read_page(mtd, chip, bufpoi, page);
+#else
- if (nand_standard_page_accessors(&chip->ecc))
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
-
-@@ -1927,6 +1930,7 @@ read_retry:
+ if (unlikely(ops->mode == MTD_OPS_RAW))
+ ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
+ oob_required,
+@@ -3600,6 +3603,7 @@ read_retry:
else
ret = chip->ecc.read_page(mtd, chip, bufpoi,
oob_required, page);
/* Invalidate page cache */
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
-@@ -897,6 +897,9 @@ struct nand_chip {
- int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
- const struct nand_data_interface *conf);
+@@ -1443,6 +1443,9 @@ static inline void *nand_get_manufacture
+ #define NAND_MFR_ATO 0x9b
+ #define NAND_MFR_WINBOND 0xef
+#ifdef CONFIG_MTK_MTD_NAND
+ int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, u8 *buf, int page);
+#endif /* CONFIG_MTK_MTD_NAND */
- int chip_delay;
- unsigned int options;
+ /*
+ * A helper for defining older NAND chips where the second ID byte fully
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
-@@ -563,6 +563,12 @@ config SPI_QUP
+@@ -533,6 +533,12 @@ config SPI_QUP
This driver can also be built as a module. If so, the module
will be called spi_qup.
depends on ARCH_S3C24XX
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
-@@ -81,6 +81,7 @@ obj-$(CONFIG_SPI_QUP) += spi-qup.o
+@@ -78,6 +78,7 @@ obj-$(CONFIG_SPI_QUP) += spi-qup.o
obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
-@@ -569,6 +569,12 @@ config SPI_RT2880
+@@ -539,6 +539,12 @@ config SPI_RT2880
help
This selects a driver for the Ralink RT288x/RT305x SPI Controller.
depends on ARCH_S3C24XX
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
-@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
+@@ -57,6 +57,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
+};
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
-@@ -863,6 +863,11 @@ config I2C_RK3X
+@@ -876,6 +876,11 @@ config I2C_RK3X
This driver can also be built as a module. If so, the module will
be called i2c-rk3x.
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
+obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
+ obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
- obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ralink.c
@@ -0,0 +1,435 @@
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
-@@ -868,6 +868,11 @@ config I2C_RALINK
+@@ -881,6 +881,11 @@ config I2C_RALINK
depends on RALINK && !SOC_MT7621
select OF_I2C
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
+obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o
+ obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
- obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
--- /dev/null
+++ b/drivers/i2c/busses/i2c-mt7621.c
@@ -0,0 +1,433 @@
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
-@@ -901,3 +901,5 @@ config MMC_SDHCI_XENON
- This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
+@@ -943,3 +943,5 @@ config MMC_SDHCI_OMAP
If you have a controller with this interface, say Y or M here.
+
If unsure, say N.
+
+source "drivers/mmc/host/mtk-mmc/Kconfig"
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
-@@ -71,6 +71,8 @@ obj-$(CONFIG_TI_EDMA) += edma.o
+@@ -72,6 +72,8 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
+obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
+obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+ obj-y += mediatek/
obj-y += qcom/
- obj-y += xilinx/
--- /dev/null
+++ b/drivers/dma/ralink-gdma.c
@@ -0,0 +1,928 @@
+MODULE_LICENSE("GPL v2");
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
-@@ -525,6 +525,7 @@ static inline void dma_set_unmap(struct
+@@ -534,6 +534,7 @@ static inline void dma_set_unmap(struct
struct dmaengine_unmap_data *
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
__iomem void *plat_of_remap_node(const char *node)
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
-@@ -59,6 +59,7 @@ source "sound/soc/mxs/Kconfig"
+@@ -62,6 +62,7 @@ source "sound/soc/mxs/Kconfig"
source "sound/soc/pxa/Kconfig"
source "sound/soc/qcom/Kconfig"
source "sound/soc/rockchip/Kconfig"
source "sound/soc/sirf/Kconfig"
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
-@@ -40,6 +40,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
+@@ -46,6 +46,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
obj-$(CONFIG_SND_SOC) += pxa/
obj-$(CONFIG_SND_SOC) += qcom/
obj-$(CONFIG_SND_SOC) += rockchip/
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
-@@ -428,6 +428,9 @@ uart_get_baud_rate(struct uart_port *por
+@@ -415,6 +415,9 @@ uart_get_baud_rate(struct uart_port *por
break;
}
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
-@@ -302,6 +302,15 @@ config PWM_MEDIATEK
+@@ -293,6 +293,15 @@ config PWM_MEDIATEK
To compile this driver as a module, choose M here: the module
will be called pwm-mediatek.
depends on ARCH_MXS && OF
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
-@@ -28,6 +28,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p
+@@ -27,6 +27,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p
obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
obj-$(CONFIG_PWM_MESON) += pwm-meson.o
obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
+ * Like SPI_NOR_4B_OPCODES, but for read
+ * op code only.
+ */
- };
- #define JEDEC_MFR(info) ((info)->id[0])
-@@ -240,6 +244,15 @@ static inline u8 spi_nor_convert_3to4_er
+ int (*quad_enable)(struct spi_nor *nor);
+ };
+@@ -242,6 +246,15 @@ static inline u8 spi_nor_convert_3to4_er
ARRAY_SIZE(spi_nor_3to4_erase));
}
static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
const struct flash_info *info)
{
-@@ -467,6 +480,36 @@ static int spi_nor_erase_sector(struct s
+@@ -497,6 +510,36 @@ static int spi_nor_erase_sector(struct s
return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
}
/*
* Erase an address range on the nor chip. The address range may extend
* one or more erase sectors. Return an error is there is a problem erasing.
-@@ -492,6 +535,10 @@ static int spi_nor_erase(struct mtd_info
+@@ -522,6 +565,10 @@ static int spi_nor_erase(struct mtd_info
if (ret)
return ret;
/* whole-chip erase? */
if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
unsigned long timeout;
-@@ -542,6 +589,7 @@ static int spi_nor_erase(struct mtd_info
+@@ -572,6 +619,7 @@ static int spi_nor_erase(struct mtd_info
write_disable(nor);
erase_err:
+ spi_nor_check_ext_addr(nor, 0);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
- instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
-@@ -834,7 +882,9 @@ static int spi_nor_lock(struct mtd_info
+ return ret;
+@@ -872,7 +920,9 @@ static int spi_nor_lock(struct mtd_info
if (ret)
return ret;
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
return ret;
-@@ -849,7 +899,9 @@ static int spi_nor_unlock(struct mtd_inf
+@@ -887,7 +937,9 @@ static int spi_nor_unlock(struct mtd_inf
if (ret)
return ret;
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
return ret;
-@@ -1177,7 +1229,7 @@ static const struct flash_info spi_nor_i
+@@ -1252,7 +1304,7 @@ static const struct flash_info spi_nor_i
{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
-@@ -1237,6 +1289,9 @@ static int spi_nor_read(struct mtd_info
+@@ -1312,6 +1364,9 @@ static int spi_nor_read(struct mtd_info
if (ret)
return ret;
while (len) {
loff_t addr = from;
-@@ -1261,6 +1316,18 @@ static int spi_nor_read(struct mtd_info
+@@ -1336,6 +1391,18 @@ static int spi_nor_read(struct mtd_info
ret = 0;
read_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
return ret;
}
-@@ -1362,6 +1429,10 @@ static int spi_nor_write(struct mtd_info
+@@ -1437,6 +1504,10 @@ static int spi_nor_write(struct mtd_info
if (ret)
return ret;
for (i = 0; i < len; ) {
ssize_t written;
loff_t addr = to + i;
-@@ -1402,6 +1473,7 @@ static int spi_nor_write(struct mtd_info
+@@ -1477,6 +1548,7 @@ static int spi_nor_write(struct mtd_info
}
write_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
return ret;
}
-@@ -2818,8 +2890,10 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -2955,8 +3027,10 @@ int spi_nor_scan(struct spi_nor *nor, co
} else if (mtd->size > 0x1000000) {
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
+ else if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
+ info->flags & SPI_NOR_4B_OPCODES)
spi_nor_set_4byte_opcodes(nor, info);
- else
- set_4byte(nor, info, 1);
+ } else {
+ nor->addr_width = 3;
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
-@@ -102,6 +102,7 @@
+@@ -105,6 +105,7 @@
/* Used for Macronix and Winbond flashes. */
#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
-@@ -229,6 +230,7 @@ enum spi_nor_option_flags {
- SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
+@@ -236,6 +237,7 @@ enum spi_nor_option_flags {
SNOR_F_READY_XSR_RDY = BIT(4),
SNOR_F_USE_CLSR = BIT(5),
-+ SNOR_F_4B_EXT_ADDR = BIT(6),
+ SNOR_F_BROKEN_RESET = BIT(6),
++ SNOR_F_4B_EXT_ADDR = BIT(7),
};
/**
-@@ -280,6 +282,7 @@ struct spi_nor {
+@@ -296,6 +298,7 @@ struct spi_nor {
enum spi_nor_protocol reg_proto;
bool sst_write_second;
u32 flags;
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -142,20 +142,29 @@ static int read_fsr(struct spi_nor *nor)
+@@ -144,20 +144,29 @@ static int read_fsr(struct spi_nor *nor)
* location. Return the configuration register value.
* Returns negative if error occurred.
*/
/*
* Write status register 1 byte
* Returns negative if error occurred.
-@@ -2890,9 +2899,16 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -3027,9 +3036,16 @@ int spi_nor_scan(struct spi_nor *nor, co
} else if (mtd->size > 0x1000000) {
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
+ } else if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
info->flags & SPI_NOR_4B_OPCODES)
spi_nor_set_4byte_opcodes(nor, info);
- else
+ } else {
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
-@@ -103,6 +103,7 @@
+@@ -106,6 +106,7 @@
#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
#define SPINOR_OP_WREAR 0xc5 /* Write extended address register */
/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
-@@ -135,6 +136,7 @@
+@@ -141,6 +142,7 @@
/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
-@@ -406,6 +406,12 @@ static int dwc2_driver_probe(struct plat
- if (retval)
- return retval;
+@@ -438,6 +438,12 @@ static int dwc2_driver_probe(struct plat
+
+ hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
+ /* Enable USB port before any regs access */
+ if (dwc2_readl(hsotg->regs + PCGCTL) & 0x0f) {
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
-@@ -58,6 +58,7 @@ choice
+@@ -57,6 +57,7 @@ choice
select COMMON_CLK
select CLKSRC_MIPS_GIC
select HW_HAS_PCI
+++ /dev/null
---- a/arch/mips/pci/pci-mt7620.c
-+++ b/arch/mips/pci/pci-mt7620.c
-@@ -33,7 +33,6 @@
- #define RALINK_GPIOMODE 0x60
-
- #define PPLL_CFG1 0x9c
--#define PDRV_SW_SET BIT(23)
-
- #define PPLL_DRV 0xa0
- #define PDRV_SW_SET (1<<31)
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
-@@ -57,6 +57,7 @@ obj-$(CONFIG_CXL_BASE) += cxl/
+@@ -57,5 +57,6 @@ obj-$(CONFIG_CXL_BASE) += cxl/
obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
+obj-$(CONFIG_SOC_MT7620) += linkit.o
-
- lkdtm-$(CONFIG_LKDTM) += lkdtm_core.o
- lkdtm-$(CONFIG_LKDTM) += lkdtm_bugs.o
+ obj-$(CONFIG_OCXL) += ocxl/
+ obj-$(CONFIG_MISC_RTSX) += cardreader/
--- /dev/null
+++ b/drivers/misc/linkit.c
@@ -0,0 +1,84 @@
void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
-@@ -59,6 +59,7 @@ choice
+@@ -58,6 +58,7 @@ choice
select CLKSRC_MIPS_GIC
select HW_HAS_PCI
select WEAK_REORDERING_BEYOND_LLSC
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -1061,6 +1061,11 @@ static const struct flash_info spi_nor_i
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+@@ -1113,6 +1113,11 @@ static const struct flash_info spi_nor_i
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ .quad_enable = macronix_quad_enable,
},
+ {
+ "gd25q512", INFO(0xc84020, 0, 64 * 1024, 1024,
+++ /dev/null
---- a/drivers/mtd/spi-nor/spi-nor.c
-+++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -1100,7 +1100,7 @@ static const struct flash_info spi_nor_i
- { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
- { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
-- { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-+ { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
- { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
- { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -1098,6 +1098,7 @@ static const struct flash_info spi_nor_i
- { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
- { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
+@@ -1160,6 +1160,7 @@ static const struct flash_info spi_nor_i
+ { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "mx25l25635f", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-@@ -1267,11 +1268,12 @@ static const struct flash_info spi_nor_i
+@@ -1342,11 +1343,12 @@ static const struct flash_info spi_nor_i
{ },
};
tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
if (tmp < 0) {
-@@ -1282,10 +1284,16 @@ static const struct flash_info *spi_nor_
+@@ -1357,10 +1359,16 @@ static const struct flash_info *spi_nor_
for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
info = &spi_nor_ids[tmp];
if (info->id_len) {
dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
id[0], id[1], id[2]);
return ERR_PTR(-ENODEV);
-@@ -2765,7 +2773,7 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -2914,7 +2922,7 @@ int spi_nor_scan(struct spi_nor *nor, co
info = spi_nor_match_id(name);
/* Try to auto-detect if chip name wasn't specified or not found */
if (!info)
if (IS_ERR_OR_NULL(info))
return -ENOENT;
-@@ -2776,7 +2784,7 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -2925,7 +2933,7 @@ int spi_nor_scan(struct spi_nor *nor, co
if (name && info->id_len) {
const struct flash_info *jinfo;
#define PPLL_CFG1 0x9c
#define PPLL_DRV 0xa0
-+#define PPLL_LD (1<<23)
- #define PDRV_SW_SET (1<<31)
- #define LC_CKDRVPD (1<<19)
- #define LC_CKDRVOHZ (1<<18)
++#define PPLL_LD BIT(23)
+ #define PDRV_SW_SET BIT(31)
+ #define LC_CKDRVPD BIT(19)
+ #define LC_CKDRVOHZ BIT(18)
@@ -242,8 +243,8 @@ static int mt7620_pci_hw_init(struct pla
rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
mdelay(100);
projects / openwrt / staging / ynezz.git / commitdiff