ath79: fix eth0 PLL registers on WD My Net Wi-Fi Range Extender
authorJonathan A. Kollasch <jakllsch@kollasch.net>
Fri, 11 Sep 2020 19:33:39 +0000 (14:33 -0500)
committerAdrian Schmutzler <freifunk@adrianschmutzler.de>
Sat, 12 Jun 2021 09:01:43 +0000 (11:01 +0200)
commit0794a784e905e14f673fee6120e86be67bb4862d
tree1b9c7738bf1f1d0420bd9271761602a554f604c0
parent1a8de9cbf91fe1f2550140f4254bc310a99ccd39
ath79: fix eth0 PLL registers on WD My Net Wi-Fi Range Extender

This replaces the register bits for RGMII delay on the MAC side in favor
of having the RGMII delay on the PHY side by setting the phy-mode
property to rgmii-id (RGMII internal delay), which is supported by the
at803x driver.  Speed 1000 is fixed as a result, so now all ethernet
speeds function.

Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit f36990eae77c3a22842a2c418378c5dd40dec366)
target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts