starfive: refresh patches
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0036-soc-starfive-Add-StarFive-JH71XX-pmu-driver.patch
1 From 3e3b85a1064b07a5107504af1e8f0a42ff9d1fc1 Mon Sep 17 00:00:00 2001
2 From: Walker Chen <walker.chen@starfivetech.com>
3 Date: Thu, 19 Jan 2023 17:44:47 +0800
4 Subject: [PATCH 036/122] soc: starfive: Add StarFive JH71XX pmu driver
5
6 Add pmu driver for the StarFive JH71XX SoC.
7
8 As the power domains provider, the Power Management Unit (PMU) is
9 designed for including multiple PM domains that can be used for power
10 gating of selected IP blocks for power saving by reduced leakage
11 current. It accepts software encourage command to switch the power mode
12 of SoC.
13
14 Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
15 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
16 Reviewed-by: Heiko Stuebner <heiko@sntech.de>
17 ---
18 MAINTAINERS | 14 ++
19 drivers/soc/Kconfig | 1 +
20 drivers/soc/Makefile | 1 +
21 drivers/soc/starfive/Kconfig | 12 +
22 drivers/soc/starfive/Makefile | 3 +
23 drivers/soc/starfive/jh71xx_pmu.c | 383 ++++++++++++++++++++++++++++++
24 6 files changed, 414 insertions(+)
25 create mode 100644 drivers/soc/starfive/Kconfig
26 create mode 100644 drivers/soc/starfive/Makefile
27 create mode 100644 drivers/soc/starfive/jh71xx_pmu.c
28
29 --- a/MAINTAINERS
30 +++ b/MAINTAINERS
31 @@ -19689,6 +19689,20 @@ F: Documentation/devicetree/bindings/res
32 F: drivers/reset/starfive/reset-starfive-jh71*
33 F: include/dt-bindings/reset/starfive?jh71*.h
34
35 +STARFIVE SOC DRIVER
36 +M: Conor Dooley <conor@kernel.org>
37 +S: Maintained
38 +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
39 +F: drivers/soc/starfive/
40 +F: include/soc/starfive/
41 +
42 +STARFIVE JH71XX PMU CONTROLLER DRIVER
43 +M: Walker Chen <walker.chen@starfivetech.com>
44 +S: Supported
45 +F: Documentation/devicetree/bindings/power/starfive*
46 +F: drivers/soc/starfive/jh71xx_pmu.c
47 +F: include/dt-bindings/power/starfive,jh7110-pmu.h
48 +
49 STATIC BRANCH/CALL
50 M: Peter Zijlstra <peterz@infradead.org>
51 M: Josh Poimboeuf <jpoimboe@kernel.org>
52 --- a/drivers/soc/Kconfig
53 +++ b/drivers/soc/Kconfig
54 @@ -21,6 +21,7 @@ source "drivers/soc/renesas/Kconfig"
55 source "drivers/soc/rockchip/Kconfig"
56 source "drivers/soc/samsung/Kconfig"
57 source "drivers/soc/sifive/Kconfig"
58 +source "drivers/soc/starfive/Kconfig"
59 source "drivers/soc/sunxi/Kconfig"
60 source "drivers/soc/tegra/Kconfig"
61 source "drivers/soc/ti/Kconfig"
62 --- a/drivers/soc/Makefile
63 +++ b/drivers/soc/Makefile
64 @@ -27,6 +27,7 @@ obj-y += renesas/
65 obj-y += rockchip/
66 obj-$(CONFIG_SOC_SAMSUNG) += samsung/
67 obj-$(CONFIG_SOC_SIFIVE) += sifive/
68 +obj-$(CONFIG_SOC_STARFIVE) += starfive/
69 obj-y += sunxi/
70 obj-$(CONFIG_ARCH_TEGRA) += tegra/
71 obj-y += ti/
72 --- /dev/null
73 +++ b/drivers/soc/starfive/Kconfig
74 @@ -0,0 +1,12 @@
75 +# SPDX-License-Identifier: GPL-2.0
76 +
77 +config JH71XX_PMU
78 + bool "Support PMU for StarFive JH71XX Soc"
79 + depends on PM
80 + depends on SOC_STARFIVE || COMPILE_TEST
81 + default SOC_STARFIVE
82 + select PM_GENERIC_DOMAINS
83 + help
84 + Say 'y' here to enable support power domain support.
85 + In order to meet low power requirements, a Power Management Unit (PMU)
86 + is designed for controlling power resources in StarFive JH71XX SoCs.
87 --- /dev/null
88 +++ b/drivers/soc/starfive/Makefile
89 @@ -0,0 +1,3 @@
90 +# SPDX-License-Identifier: GPL-2.0
91 +
92 +obj-$(CONFIG_JH71XX_PMU) += jh71xx_pmu.o
93 --- /dev/null
94 +++ b/drivers/soc/starfive/jh71xx_pmu.c
95 @@ -0,0 +1,383 @@
96 +// SPDX-License-Identifier: GPL-2.0-or-later
97 +/*
98 + * StarFive JH71XX PMU (Power Management Unit) Controller Driver
99 + *
100 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
101 + */
102 +
103 +#include <linux/interrupt.h>
104 +#include <linux/io.h>
105 +#include <linux/iopoll.h>
106 +#include <linux/module.h>
107 +#include <linux/of.h>
108 +#include <linux/of_device.h>
109 +#include <linux/platform_device.h>
110 +#include <linux/pm_domain.h>
111 +#include <dt-bindings/power/starfive,jh7110-pmu.h>
112 +
113 +/* register offset */
114 +#define JH71XX_PMU_SW_TURN_ON_POWER 0x0C
115 +#define JH71XX_PMU_SW_TURN_OFF_POWER 0x10
116 +#define JH71XX_PMU_SW_ENCOURAGE 0x44
117 +#define JH71XX_PMU_TIMER_INT_MASK 0x48
118 +#define JH71XX_PMU_CURR_POWER_MODE 0x80
119 +#define JH71XX_PMU_EVENT_STATUS 0x88
120 +#define JH71XX_PMU_INT_STATUS 0x8C
121 +
122 +/* sw encourage cfg */
123 +#define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05
124 +#define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50
125 +#define JH71XX_PMU_SW_ENCOURAGE_DIS_LO 0x0A
126 +#define JH71XX_PMU_SW_ENCOURAGE_DIS_HI 0xA0
127 +#define JH71XX_PMU_SW_ENCOURAGE_ON 0xFF
128 +
129 +/* pmu int status */
130 +#define JH71XX_PMU_INT_SEQ_DONE BIT(0)
131 +#define JH71XX_PMU_INT_HW_REQ BIT(1)
132 +#define JH71XX_PMU_INT_SW_FAIL GENMASK(3, 2)
133 +#define JH71XX_PMU_INT_HW_FAIL GENMASK(5, 4)
134 +#define JH71XX_PMU_INT_PCH_FAIL GENMASK(8, 6)
135 +#define JH71XX_PMU_INT_ALL_MASK GENMASK(8, 0)
136 +
137 +/*
138 + * The time required for switching power status is based on the time
139 + * to turn on the largest domain's power, which is at microsecond level
140 + */
141 +#define JH71XX_PMU_TIMEOUT_US 100
142 +
143 +struct jh71xx_domain_info {
144 + const char * const name;
145 + unsigned int flags;
146 + u8 bit;
147 +};
148 +
149 +struct jh71xx_pmu_match_data {
150 + const struct jh71xx_domain_info *domain_info;
151 + int num_domains;
152 +};
153 +
154 +struct jh71xx_pmu {
155 + struct device *dev;
156 + const struct jh71xx_pmu_match_data *match_data;
157 + void __iomem *base;
158 + struct generic_pm_domain **genpd;
159 + struct genpd_onecell_data genpd_data;
160 + int irq;
161 + spinlock_t lock; /* protects pmu reg */
162 +};
163 +
164 +struct jh71xx_pmu_dev {
165 + const struct jh71xx_domain_info *domain_info;
166 + struct jh71xx_pmu *pmu;
167 + struct generic_pm_domain genpd;
168 +};
169 +
170 +static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on)
171 +{
172 + struct jh71xx_pmu *pmu = pmd->pmu;
173 +
174 + if (!mask)
175 + return -EINVAL;
176 +
177 + *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
178 +
179 + return 0;
180 +}
181 +
182 +static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
183 +{
184 + struct jh71xx_pmu *pmu = pmd->pmu;
185 + unsigned long flags;
186 + u32 val;
187 + u32 mode;
188 + u32 encourage_lo;
189 + u32 encourage_hi;
190 + bool is_on;
191 + int ret;
192 +
193 + ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
194 + if (ret) {
195 + dev_dbg(pmu->dev, "unable to get current state for %s\n",
196 + pmd->genpd.name);
197 + return ret;
198 + }
199 +
200 + if (is_on == on) {
201 + dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
202 + pmd->genpd.name, on ? "en" : "dis");
203 + return 0;
204 + }
205 +
206 + spin_lock_irqsave(&pmu->lock, flags);
207 +
208 + /*
209 + * The PMU accepts software encourage to switch power mode in the following 2 steps:
210 + *
211 + * 1.Configure the register SW_TURN_ON_POWER (offset 0x0c) by writing 1 to
212 + * the bit corresponding to the power domain that will be turned on
213 + * and writing 0 to the others.
214 + * Likewise, configure the register SW_TURN_OFF_POWER (offset 0x10) by
215 + * writing 1 to the bit corresponding to the power domain that will be
216 + * turned off and writing 0 to the others.
217 + */
218 + if (on) {
219 + mode = JH71XX_PMU_SW_TURN_ON_POWER;
220 + encourage_lo = JH71XX_PMU_SW_ENCOURAGE_EN_LO;
221 + encourage_hi = JH71XX_PMU_SW_ENCOURAGE_EN_HI;
222 + } else {
223 + mode = JH71XX_PMU_SW_TURN_OFF_POWER;
224 + encourage_lo = JH71XX_PMU_SW_ENCOURAGE_DIS_LO;
225 + encourage_hi = JH71XX_PMU_SW_ENCOURAGE_DIS_HI;
226 + }
227 +
228 + writel(mask, pmu->base + mode);
229 +
230 + /*
231 + * 2.Write SW encourage command sequence to the Software Encourage Reg (offset 0x44)
232 + * First write SW_MODE_ENCOURAGE_ON to JH71XX_PMU_SW_ENCOURAGE. This will reset
233 + * the state machine which parses the command sequence. This register must be
234 + * written every time software wants to power on/off a domain.
235 + * Then write the lower bits of the command sequence, followed by the upper
236 + * bits. The sequence differs between powering on & off a domain.
237 + */
238 + writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
239 + writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
240 + writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
241 +
242 + spin_unlock_irqrestore(&pmu->lock, flags);
243 +
244 + /* Wait for the power domain bit to be enabled / disabled */
245 + if (on) {
246 + ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
247 + val, val & mask,
248 + 1, JH71XX_PMU_TIMEOUT_US);
249 + } else {
250 + ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
251 + val, !(val & mask),
252 + 1, JH71XX_PMU_TIMEOUT_US);
253 + }
254 +
255 + if (ret) {
256 + dev_err(pmu->dev, "%s: failed to power %s\n",
257 + pmd->genpd.name, on ? "on" : "off");
258 + return -ETIMEDOUT;
259 + }
260 +
261 + return 0;
262 +}
263 +
264 +static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
265 +{
266 + struct jh71xx_pmu_dev *pmd = container_of(genpd,
267 + struct jh71xx_pmu_dev, genpd);
268 + u32 pwr_mask = BIT(pmd->domain_info->bit);
269 +
270 + return jh71xx_pmu_set_state(pmd, pwr_mask, true);
271 +}
272 +
273 +static int jh71xx_pmu_off(struct generic_pm_domain *genpd)
274 +{
275 + struct jh71xx_pmu_dev *pmd = container_of(genpd,
276 + struct jh71xx_pmu_dev, genpd);
277 + u32 pwr_mask = BIT(pmd->domain_info->bit);
278 +
279 + return jh71xx_pmu_set_state(pmd, pwr_mask, false);
280 +}
281 +
282 +static void jh71xx_pmu_int_enable(struct jh71xx_pmu *pmu, u32 mask, bool enable)
283 +{
284 + u32 val;
285 + unsigned long flags;
286 +
287 + spin_lock_irqsave(&pmu->lock, flags);
288 + val = readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK);
289 +
290 + if (enable)
291 + val &= ~mask;
292 + else
293 + val |= mask;
294 +
295 + writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK);
296 + spin_unlock_irqrestore(&pmu->lock, flags);
297 +}
298 +
299 +static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
300 +{
301 + struct jh71xx_pmu *pmu = data;
302 + u32 val;
303 +
304 + val = readl(pmu->base + JH71XX_PMU_INT_STATUS);
305 +
306 + if (val & JH71XX_PMU_INT_SEQ_DONE)
307 + dev_dbg(pmu->dev, "sequence done.\n");
308 + if (val & JH71XX_PMU_INT_HW_REQ)
309 + dev_dbg(pmu->dev, "hardware encourage requestion.\n");
310 + if (val & JH71XX_PMU_INT_SW_FAIL)
311 + dev_err(pmu->dev, "software encourage fail.\n");
312 + if (val & JH71XX_PMU_INT_HW_FAIL)
313 + dev_err(pmu->dev, "hardware encourage fail.\n");
314 + if (val & JH71XX_PMU_INT_PCH_FAIL)
315 + dev_err(pmu->dev, "p-channel fail event.\n");
316 +
317 + /* clear interrupts */
318 + writel(val, pmu->base + JH71XX_PMU_INT_STATUS);
319 + writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS);
320 +
321 + return IRQ_HANDLED;
322 +}
323 +
324 +static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
325 +{
326 + struct jh71xx_pmu_dev *pmd;
327 + u32 pwr_mask;
328 + int ret;
329 + bool is_on = false;
330 +
331 + pmd = devm_kzalloc(pmu->dev, sizeof(*pmd), GFP_KERNEL);
332 + if (!pmd)
333 + return -ENOMEM;
334 +
335 + pmd->domain_info = &pmu->match_data->domain_info[index];
336 + pmd->pmu = pmu;
337 + pwr_mask = BIT(pmd->domain_info->bit);
338 +
339 + pmd->genpd.name = pmd->domain_info->name;
340 + pmd->genpd.flags = pmd->domain_info->flags;
341 +
342 + ret = jh71xx_pmu_get_state(pmd, pwr_mask, &is_on);
343 + if (ret)
344 + dev_warn(pmu->dev, "unable to get current state for %s\n",
345 + pmd->genpd.name);
346 +
347 + pmd->genpd.power_on = jh71xx_pmu_on;
348 + pmd->genpd.power_off = jh71xx_pmu_off;
349 + pm_genpd_init(&pmd->genpd, NULL, !is_on);
350 +
351 + pmu->genpd_data.domains[index] = &pmd->genpd;
352 +
353 + return 0;
354 +}
355 +
356 +static int jh71xx_pmu_probe(struct platform_device *pdev)
357 +{
358 + struct device *dev = &pdev->dev;
359 + struct device_node *np = dev->of_node;
360 + const struct jh71xx_pmu_match_data *match_data;
361 + struct jh71xx_pmu *pmu;
362 + unsigned int i;
363 + int ret;
364 +
365 + pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
366 + if (!pmu)
367 + return -ENOMEM;
368 +
369 + pmu->base = devm_platform_ioremap_resource(pdev, 0);
370 + if (IS_ERR(pmu->base))
371 + return PTR_ERR(pmu->base);
372 +
373 + pmu->irq = platform_get_irq(pdev, 0);
374 + if (pmu->irq < 0)
375 + return pmu->irq;
376 +
377 + ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
378 + 0, pdev->name, pmu);
379 + if (ret)
380 + dev_err(dev, "failed to request irq\n");
381 +
382 + match_data = of_device_get_match_data(dev);
383 + if (!match_data)
384 + return -EINVAL;
385 +
386 + pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
387 + sizeof(struct generic_pm_domain *),
388 + GFP_KERNEL);
389 + if (!pmu->genpd)
390 + return -ENOMEM;
391 +
392 + pmu->dev = dev;
393 + pmu->match_data = match_data;
394 + pmu->genpd_data.domains = pmu->genpd;
395 + pmu->genpd_data.num_domains = match_data->num_domains;
396 +
397 + for (i = 0; i < match_data->num_domains; i++) {
398 + ret = jh71xx_pmu_init_domain(pmu, i);
399 + if (ret) {
400 + dev_err(dev, "failed to initialize power domain\n");
401 + return ret;
402 + }
403 + }
404 +
405 + spin_lock_init(&pmu->lock);
406 + jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
407 +
408 + ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
409 + if (ret) {
410 + dev_err(dev, "failed to register genpd driver: %d\n", ret);
411 + return ret;
412 + }
413 +
414 + dev_dbg(dev, "registered %u power domains\n", i);
415 +
416 + return 0;
417 +}
418 +
419 +static const struct jh71xx_domain_info jh7110_power_domains[] = {
420 + [JH7110_PD_SYSTOP] = {
421 + .name = "SYSTOP",
422 + .bit = 0,
423 + .flags = GENPD_FLAG_ALWAYS_ON,
424 + },
425 + [JH7110_PD_CPU] = {
426 + .name = "CPU",
427 + .bit = 1,
428 + .flags = GENPD_FLAG_ALWAYS_ON,
429 + },
430 + [JH7110_PD_GPUA] = {
431 + .name = "GPUA",
432 + .bit = 2,
433 + },
434 + [JH7110_PD_VDEC] = {
435 + .name = "VDEC",
436 + .bit = 3,
437 + },
438 + [JH7110_PD_VOUT] = {
439 + .name = "VOUT",
440 + .bit = 4,
441 + },
442 + [JH7110_PD_ISP] = {
443 + .name = "ISP",
444 + .bit = 5,
445 + },
446 + [JH7110_PD_VENC] = {
447 + .name = "VENC",
448 + .bit = 6,
449 + },
450 +};
451 +
452 +static const struct jh71xx_pmu_match_data jh7110_pmu = {
453 + .num_domains = ARRAY_SIZE(jh7110_power_domains),
454 + .domain_info = jh7110_power_domains,
455 +};
456 +
457 +static const struct of_device_id jh71xx_pmu_of_match[] = {
458 + {
459 + .compatible = "starfive,jh7110-pmu",
460 + .data = (void *)&jh7110_pmu,
461 + }, {
462 + /* sentinel */
463 + }
464 +};
465 +
466 +static struct platform_driver jh71xx_pmu_driver = {
467 + .probe = jh71xx_pmu_probe,
468 + .driver = {
469 + .name = "jh71xx-pmu",
470 + .of_match_table = jh71xx_pmu_of_match,
471 + .suppress_bind_attrs = true,
472 + },
473 +};
474 +builtin_platform_driver(jh71xx_pmu_driver);
475 +
476 +MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
477 +MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
478 +MODULE_LICENSE("GPL");