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starfive: refresh patches
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0028-pinctrl-starfive-Add-StarFive-JH7110-sys-controller-.patch
1 From 4dba3156173e59131d234d702388ee7283bac8a9 Mon Sep 17 00:00:00 2001
2 From: Jianlong Huang <jianlong.huang@starfivetech.com>
3 Date: Thu, 9 Feb 2023 22:37:01 +0800
4 Subject: [PATCH 028/122] pinctrl: starfive: Add StarFive JH7110 sys controller
5 driver
6
7 Add pinctrl driver for StarFive JH7110 SoC sys pinctrl controller.
8
9 Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
10 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
11 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
12 Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
13 ---
14 MAINTAINERS | 2 +-
15 drivers/pinctrl/starfive/Kconfig | 21 +
16 drivers/pinctrl/starfive/Makefile | 3 +
17 .../starfive/pinctrl-starfive-jh7110-sys.c | 449 ++++++++
18 .../starfive/pinctrl-starfive-jh7110.c | 982 ++++++++++++++++++
19 .../starfive/pinctrl-starfive-jh7110.h | 70 ++
20 6 files changed, 1526 insertions(+), 1 deletion(-)
21 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
22 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
23 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h
24
25 --- a/MAINTAINERS
26 +++ b/MAINTAINERS
27 @@ -19671,7 +19671,7 @@ M: Jianlong Huang <jianlong.huang@starfi
28 L: linux-gpio@vger.kernel.org
29 S: Maintained
30 F: Documentation/devicetree/bindings/pinctrl/starfive,jh71*.yaml
31 -F: drivers/pinctrl/starfive/
32 +F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
33 F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
34 F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
35
36 --- a/drivers/pinctrl/starfive/Kconfig
37 +++ b/drivers/pinctrl/starfive/Kconfig
38 @@ -16,3 +16,24 @@ config PINCTRL_STARFIVE_JH7100
39 This also provides an interface to the GPIO pins not used by other
40 peripherals supporting inputs, outputs, configuring pull-up/pull-down
41 and interrupts on input changes.
42 +
43 +config PINCTRL_STARFIVE_JH7110
44 + bool
45 + select GENERIC_PINCTRL_GROUPS
46 + select GENERIC_PINMUX_FUNCTIONS
47 + select GENERIC_PINCONF
48 + select GPIOLIB
49 + select GPIOLIB_IRQCHIP
50 + select OF_GPIO
51 +
52 +config PINCTRL_STARFIVE_JH7110_SYS
53 + tristate "System pinctrl and GPIO driver for the StarFive JH7110 SoC"
54 + depends on SOC_STARFIVE || COMPILE_TEST
55 + depends on OF
56 + select PINCTRL_STARFIVE_JH7110
57 + default SOC_STARFIVE
58 + help
59 + Say yes here to support system pin control on the StarFive JH7110 SoC.
60 + This also provides an interface to the GPIO pins not used by other
61 + peripherals supporting inputs, outputs, configuring pull-up/pull-down
62 + and interrupts on input changes.
63 --- a/drivers/pinctrl/starfive/Makefile
64 +++ b/drivers/pinctrl/starfive/Makefile
65 @@ -1,3 +1,6 @@
66 # SPDX-License-Identifier: GPL-2.0
67
68 obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o
69 +
70 +obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o
71 +obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o
72 --- /dev/null
73 +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
74 @@ -0,0 +1,449 @@
75 +// SPDX-License-Identifier: GPL-2.0
76 +/*
77 + * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller
78 + *
79 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
80 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
81 + */
82 +
83 +#include <linux/bits.h>
84 +#include <linux/clk.h>
85 +#include <linux/gpio/driver.h>
86 +#include <linux/io.h>
87 +#include <linux/mod_devicetable.h>
88 +#include <linux/module.h>
89 +#include <linux/mutex.h>
90 +#include <linux/of.h>
91 +#include <linux/of_device.h>
92 +#include <linux/platform_device.h>
93 +#include <linux/reset.h>
94 +#include <linux/spinlock.h>
95 +
96 +#include <linux/pinctrl/pinctrl.h>
97 +#include <linux/pinctrl/pinmux.h>
98 +
99 +#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
100 +
101 +#include "../core.h"
102 +#include "../pinctrl-utils.h"
103 +#include "../pinmux.h"
104 +#include "../pinconf.h"
105 +#include "pinctrl-starfive-jh7110.h"
106 +
107 +#define JH7110_SYS_NGPIO 64
108 +#define JH7110_SYS_GC_BASE 0
109 +
110 +/* registers */
111 +#define JH7110_SYS_DOEN 0x000
112 +#define JH7110_SYS_DOUT 0x040
113 +#define JH7110_SYS_GPI 0x080
114 +#define JH7110_SYS_GPIOIN 0x118
115 +
116 +#define JH7110_SYS_GPIOEN 0x0dc
117 +#define JH7110_SYS_GPIOIS0 0x0e0
118 +#define JH7110_SYS_GPIOIS1 0x0e4
119 +#define JH7110_SYS_GPIOIC0 0x0e8
120 +#define JH7110_SYS_GPIOIC1 0x0ec
121 +#define JH7110_SYS_GPIOIBE0 0x0f0
122 +#define JH7110_SYS_GPIOIBE1 0x0f4
123 +#define JH7110_SYS_GPIOIEV0 0x0f8
124 +#define JH7110_SYS_GPIOIEV1 0x0fc
125 +#define JH7110_SYS_GPIOIE0 0x100
126 +#define JH7110_SYS_GPIOIE1 0x104
127 +#define JH7110_SYS_GPIORIS0 0x108
128 +#define JH7110_SYS_GPIORIS1 0x10c
129 +#define JH7110_SYS_GPIOMIS0 0x110
130 +#define JH7110_SYS_GPIOMIS1 0x114
131 +
132 +#define JH7110_SYS_GPO_PDA_0_74_CFG 0x120
133 +#define JH7110_SYS_GPO_PDA_89_94_CFG 0x284
134 +
135 +static const struct pinctrl_pin_desc jh7110_sys_pins[] = {
136 + PINCTRL_PIN(PAD_GPIO0, "GPIO0"),
137 + PINCTRL_PIN(PAD_GPIO1, "GPIO1"),
138 + PINCTRL_PIN(PAD_GPIO2, "GPIO2"),
139 + PINCTRL_PIN(PAD_GPIO3, "GPIO3"),
140 + PINCTRL_PIN(PAD_GPIO4, "GPIO4"),
141 + PINCTRL_PIN(PAD_GPIO5, "GPIO5"),
142 + PINCTRL_PIN(PAD_GPIO6, "GPIO6"),
143 + PINCTRL_PIN(PAD_GPIO7, "GPIO7"),
144 + PINCTRL_PIN(PAD_GPIO8, "GPIO8"),
145 + PINCTRL_PIN(PAD_GPIO9, "GPIO9"),
146 + PINCTRL_PIN(PAD_GPIO10, "GPIO10"),
147 + PINCTRL_PIN(PAD_GPIO11, "GPIO11"),
148 + PINCTRL_PIN(PAD_GPIO12, "GPIO12"),
149 + PINCTRL_PIN(PAD_GPIO13, "GPIO13"),
150 + PINCTRL_PIN(PAD_GPIO14, "GPIO14"),
151 + PINCTRL_PIN(PAD_GPIO15, "GPIO15"),
152 + PINCTRL_PIN(PAD_GPIO16, "GPIO16"),
153 + PINCTRL_PIN(PAD_GPIO17, "GPIO17"),
154 + PINCTRL_PIN(PAD_GPIO18, "GPIO18"),
155 + PINCTRL_PIN(PAD_GPIO19, "GPIO19"),
156 + PINCTRL_PIN(PAD_GPIO20, "GPIO20"),
157 + PINCTRL_PIN(PAD_GPIO21, "GPIO21"),
158 + PINCTRL_PIN(PAD_GPIO22, "GPIO22"),
159 + PINCTRL_PIN(PAD_GPIO23, "GPIO23"),
160 + PINCTRL_PIN(PAD_GPIO24, "GPIO24"),
161 + PINCTRL_PIN(PAD_GPIO25, "GPIO25"),
162 + PINCTRL_PIN(PAD_GPIO26, "GPIO26"),
163 + PINCTRL_PIN(PAD_GPIO27, "GPIO27"),
164 + PINCTRL_PIN(PAD_GPIO28, "GPIO28"),
165 + PINCTRL_PIN(PAD_GPIO29, "GPIO29"),
166 + PINCTRL_PIN(PAD_GPIO30, "GPIO30"),
167 + PINCTRL_PIN(PAD_GPIO31, "GPIO31"),
168 + PINCTRL_PIN(PAD_GPIO32, "GPIO32"),
169 + PINCTRL_PIN(PAD_GPIO33, "GPIO33"),
170 + PINCTRL_PIN(PAD_GPIO34, "GPIO34"),
171 + PINCTRL_PIN(PAD_GPIO35, "GPIO35"),
172 + PINCTRL_PIN(PAD_GPIO36, "GPIO36"),
173 + PINCTRL_PIN(PAD_GPIO37, "GPIO37"),
174 + PINCTRL_PIN(PAD_GPIO38, "GPIO38"),
175 + PINCTRL_PIN(PAD_GPIO39, "GPIO39"),
176 + PINCTRL_PIN(PAD_GPIO40, "GPIO40"),
177 + PINCTRL_PIN(PAD_GPIO41, "GPIO41"),
178 + PINCTRL_PIN(PAD_GPIO42, "GPIO42"),
179 + PINCTRL_PIN(PAD_GPIO43, "GPIO43"),
180 + PINCTRL_PIN(PAD_GPIO44, "GPIO44"),
181 + PINCTRL_PIN(PAD_GPIO45, "GPIO45"),
182 + PINCTRL_PIN(PAD_GPIO46, "GPIO46"),
183 + PINCTRL_PIN(PAD_GPIO47, "GPIO47"),
184 + PINCTRL_PIN(PAD_GPIO48, "GPIO48"),
185 + PINCTRL_PIN(PAD_GPIO49, "GPIO49"),
186 + PINCTRL_PIN(PAD_GPIO50, "GPIO50"),
187 + PINCTRL_PIN(PAD_GPIO51, "GPIO51"),
188 + PINCTRL_PIN(PAD_GPIO52, "GPIO52"),
189 + PINCTRL_PIN(PAD_GPIO53, "GPIO53"),
190 + PINCTRL_PIN(PAD_GPIO54, "GPIO54"),
191 + PINCTRL_PIN(PAD_GPIO55, "GPIO55"),
192 + PINCTRL_PIN(PAD_GPIO56, "GPIO56"),
193 + PINCTRL_PIN(PAD_GPIO57, "GPIO57"),
194 + PINCTRL_PIN(PAD_GPIO58, "GPIO58"),
195 + PINCTRL_PIN(PAD_GPIO59, "GPIO59"),
196 + PINCTRL_PIN(PAD_GPIO60, "GPIO60"),
197 + PINCTRL_PIN(PAD_GPIO61, "GPIO61"),
198 + PINCTRL_PIN(PAD_GPIO62, "GPIO62"),
199 + PINCTRL_PIN(PAD_GPIO63, "GPIO63"),
200 + PINCTRL_PIN(PAD_SD0_CLK, "SD0_CLK"),
201 + PINCTRL_PIN(PAD_SD0_CMD, "SD0_CMD"),
202 + PINCTRL_PIN(PAD_SD0_DATA0, "SD0_DATA0"),
203 + PINCTRL_PIN(PAD_SD0_DATA1, "SD0_DATA1"),
204 + PINCTRL_PIN(PAD_SD0_DATA2, "SD0_DATA2"),
205 + PINCTRL_PIN(PAD_SD0_DATA3, "SD0_DATA3"),
206 + PINCTRL_PIN(PAD_SD0_DATA4, "SD0_DATA4"),
207 + PINCTRL_PIN(PAD_SD0_DATA5, "SD0_DATA5"),
208 + PINCTRL_PIN(PAD_SD0_DATA6, "SD0_DATA6"),
209 + PINCTRL_PIN(PAD_SD0_DATA7, "SD0_DATA7"),
210 + PINCTRL_PIN(PAD_SD0_STRB, "SD0_STRB"),
211 + PINCTRL_PIN(PAD_GMAC1_MDC, "GMAC1_MDC"),
212 + PINCTRL_PIN(PAD_GMAC1_MDIO, "GMAC1_MDIO"),
213 + PINCTRL_PIN(PAD_GMAC1_RXD0, "GMAC1_RXD0"),
214 + PINCTRL_PIN(PAD_GMAC1_RXD1, "GMAC1_RXD1"),
215 + PINCTRL_PIN(PAD_GMAC1_RXD2, "GMAC1_RXD2"),
216 + PINCTRL_PIN(PAD_GMAC1_RXD3, "GMAC1_RXD3"),
217 + PINCTRL_PIN(PAD_GMAC1_RXDV, "GMAC1_RXDV"),
218 + PINCTRL_PIN(PAD_GMAC1_RXC, "GMAC1_RXC"),
219 + PINCTRL_PIN(PAD_GMAC1_TXD0, "GMAC1_TXD0"),
220 + PINCTRL_PIN(PAD_GMAC1_TXD1, "GMAC1_TXD1"),
221 + PINCTRL_PIN(PAD_GMAC1_TXD2, "GMAC1_TXD2"),
222 + PINCTRL_PIN(PAD_GMAC1_TXD3, "GMAC1_TXD3"),
223 + PINCTRL_PIN(PAD_GMAC1_TXEN, "GMAC1_TXEN"),
224 + PINCTRL_PIN(PAD_GMAC1_TXC, "GMAC1_TXC"),
225 + PINCTRL_PIN(PAD_QSPI_SCLK, "QSPI_SCLK"),
226 + PINCTRL_PIN(PAD_QSPI_CS0, "QSPI_CS0"),
227 + PINCTRL_PIN(PAD_QSPI_DATA0, "QSPI_DATA0"),
228 + PINCTRL_PIN(PAD_QSPI_DATA1, "QSPI_DATA1"),
229 + PINCTRL_PIN(PAD_QSPI_DATA2, "QSPI_DATA2"),
230 + PINCTRL_PIN(PAD_QSPI_DATA3, "QSPI_DATA3"),
231 +};
232 +
233 +struct jh7110_func_sel {
234 + u16 offset;
235 + u8 shift;
236 + u8 max;
237 +};
238 +
239 +static const struct jh7110_func_sel
240 + jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
241 + [PAD_GMAC1_RXC] = { 0x29c, 0, 1 },
242 + [PAD_GPIO10] = { 0x29c, 2, 3 },
243 + [PAD_GPIO11] = { 0x29c, 5, 3 },
244 + [PAD_GPIO12] = { 0x29c, 8, 3 },
245 + [PAD_GPIO13] = { 0x29c, 11, 3 },
246 + [PAD_GPIO14] = { 0x29c, 14, 3 },
247 + [PAD_GPIO15] = { 0x29c, 17, 3 },
248 + [PAD_GPIO16] = { 0x29c, 20, 3 },
249 + [PAD_GPIO17] = { 0x29c, 23, 3 },
250 + [PAD_GPIO18] = { 0x29c, 26, 3 },
251 + [PAD_GPIO19] = { 0x29c, 29, 3 },
252 +
253 + [PAD_GPIO20] = { 0x2a0, 0, 3 },
254 + [PAD_GPIO21] = { 0x2a0, 3, 3 },
255 + [PAD_GPIO22] = { 0x2a0, 6, 3 },
256 + [PAD_GPIO23] = { 0x2a0, 9, 3 },
257 + [PAD_GPIO24] = { 0x2a0, 12, 3 },
258 + [PAD_GPIO25] = { 0x2a0, 15, 3 },
259 + [PAD_GPIO26] = { 0x2a0, 18, 3 },
260 + [PAD_GPIO27] = { 0x2a0, 21, 3 },
261 + [PAD_GPIO28] = { 0x2a0, 24, 3 },
262 + [PAD_GPIO29] = { 0x2a0, 27, 3 },
263 +
264 + [PAD_GPIO30] = { 0x2a4, 0, 3 },
265 + [PAD_GPIO31] = { 0x2a4, 3, 3 },
266 + [PAD_GPIO32] = { 0x2a4, 6, 3 },
267 + [PAD_GPIO33] = { 0x2a4, 9, 3 },
268 + [PAD_GPIO34] = { 0x2a4, 12, 3 },
269 + [PAD_GPIO35] = { 0x2a4, 15, 3 },
270 + [PAD_GPIO36] = { 0x2a4, 17, 3 },
271 + [PAD_GPIO37] = { 0x2a4, 20, 3 },
272 + [PAD_GPIO38] = { 0x2a4, 23, 3 },
273 + [PAD_GPIO39] = { 0x2a4, 26, 3 },
274 + [PAD_GPIO40] = { 0x2a4, 29, 3 },
275 +
276 + [PAD_GPIO41] = { 0x2a8, 0, 3 },
277 + [PAD_GPIO42] = { 0x2a8, 3, 3 },
278 + [PAD_GPIO43] = { 0x2a8, 6, 3 },
279 + [PAD_GPIO44] = { 0x2a8, 9, 3 },
280 + [PAD_GPIO45] = { 0x2a8, 12, 3 },
281 + [PAD_GPIO46] = { 0x2a8, 15, 3 },
282 + [PAD_GPIO47] = { 0x2a8, 18, 3 },
283 + [PAD_GPIO48] = { 0x2a8, 21, 3 },
284 + [PAD_GPIO49] = { 0x2a8, 24, 3 },
285 + [PAD_GPIO50] = { 0x2a8, 27, 3 },
286 + [PAD_GPIO51] = { 0x2a8, 30, 3 },
287 +
288 + [PAD_GPIO52] = { 0x2ac, 0, 3 },
289 + [PAD_GPIO53] = { 0x2ac, 2, 3 },
290 + [PAD_GPIO54] = { 0x2ac, 4, 3 },
291 + [PAD_GPIO55] = { 0x2ac, 6, 3 },
292 + [PAD_GPIO56] = { 0x2ac, 9, 3 },
293 + [PAD_GPIO57] = { 0x2ac, 12, 3 },
294 + [PAD_GPIO58] = { 0x2ac, 15, 3 },
295 + [PAD_GPIO59] = { 0x2ac, 18, 3 },
296 + [PAD_GPIO60] = { 0x2ac, 21, 3 },
297 + [PAD_GPIO61] = { 0x2ac, 24, 3 },
298 + [PAD_GPIO62] = { 0x2ac, 27, 3 },
299 + [PAD_GPIO63] = { 0x2ac, 30, 3 },
300 +
301 + [PAD_GPIO6] = { 0x2b0, 0, 3 },
302 + [PAD_GPIO7] = { 0x2b0, 2, 3 },
303 + [PAD_GPIO8] = { 0x2b0, 5, 3 },
304 + [PAD_GPIO9] = { 0x2b0, 8, 3 },
305 +};
306 +
307 +struct jh7110_vin_group_sel {
308 + u16 offset;
309 + u8 shift;
310 + u8 group;
311 +};
312 +
313 +static const struct jh7110_vin_group_sel
314 + jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
315 + [PAD_GPIO6] = { 0x2b4, 21, 0 },
316 + [PAD_GPIO7] = { 0x2b4, 18, 0 },
317 + [PAD_GPIO8] = { 0x2b4, 15, 0 },
318 + [PAD_GPIO9] = { 0x2b0, 11, 0 },
319 + [PAD_GPIO10] = { 0x2b0, 20, 0 },
320 + [PAD_GPIO11] = { 0x2b0, 23, 0 },
321 + [PAD_GPIO12] = { 0x2b0, 26, 0 },
322 + [PAD_GPIO13] = { 0x2b0, 29, 0 },
323 + [PAD_GPIO14] = { 0x2b4, 0, 0 },
324 + [PAD_GPIO15] = { 0x2b4, 3, 0 },
325 + [PAD_GPIO16] = { 0x2b4, 6, 0 },
326 + [PAD_GPIO17] = { 0x2b4, 9, 0 },
327 + [PAD_GPIO18] = { 0x2b4, 12, 0 },
328 + [PAD_GPIO19] = { 0x2b0, 14, 0 },
329 + [PAD_GPIO20] = { 0x2b0, 17, 0 },
330 +
331 + [PAD_GPIO21] = { 0x2b4, 21, 1 },
332 + [PAD_GPIO22] = { 0x2b4, 18, 1 },
333 + [PAD_GPIO23] = { 0x2b4, 15, 1 },
334 + [PAD_GPIO24] = { 0x2b0, 11, 1 },
335 + [PAD_GPIO25] = { 0x2b0, 20, 1 },
336 + [PAD_GPIO26] = { 0x2b0, 23, 1 },
337 + [PAD_GPIO27] = { 0x2b0, 26, 1 },
338 + [PAD_GPIO28] = { 0x2b0, 29, 1 },
339 + [PAD_GPIO29] = { 0x2b4, 0, 1 },
340 + [PAD_GPIO30] = { 0x2b4, 3, 1 },
341 + [PAD_GPIO31] = { 0x2b4, 6, 1 },
342 + [PAD_GPIO32] = { 0x2b4, 9, 1 },
343 + [PAD_GPIO33] = { 0x2b4, 12, 1 },
344 + [PAD_GPIO34] = { 0x2b0, 14, 1 },
345 + [PAD_GPIO35] = { 0x2b0, 17, 1 },
346 +
347 + [PAD_GPIO36] = { 0x2b4, 21, 2 },
348 + [PAD_GPIO37] = { 0x2b4, 18, 2 },
349 + [PAD_GPIO38] = { 0x2b4, 15, 2 },
350 + [PAD_GPIO39] = { 0x2b0, 11, 2 },
351 + [PAD_GPIO40] = { 0x2b0, 20, 2 },
352 + [PAD_GPIO41] = { 0x2b0, 23, 2 },
353 + [PAD_GPIO42] = { 0x2b0, 26, 2 },
354 + [PAD_GPIO43] = { 0x2b0, 29, 2 },
355 + [PAD_GPIO44] = { 0x2b4, 0, 2 },
356 + [PAD_GPIO45] = { 0x2b4, 3, 2 },
357 + [PAD_GPIO46] = { 0x2b4, 6, 2 },
358 + [PAD_GPIO47] = { 0x2b4, 9, 2 },
359 + [PAD_GPIO48] = { 0x2b4, 12, 2 },
360 + [PAD_GPIO49] = { 0x2b0, 14, 2 },
361 + [PAD_GPIO50] = { 0x2b0, 17, 2 },
362 +};
363 +
364 +static void jh7110_set_function(struct jh7110_pinctrl *sfp,
365 + unsigned int pin, u32 func)
366 +{
367 + const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin];
368 + unsigned long flags;
369 + void __iomem *reg;
370 + u32 mask;
371 +
372 + if (!fs->offset)
373 + return;
374 +
375 + if (func > fs->max)
376 + return;
377 +
378 + reg = sfp->base + fs->offset;
379 + func = func << fs->shift;
380 + mask = 0x3U << fs->shift;
381 +
382 + raw_spin_lock_irqsave(&sfp->lock, flags);
383 + func |= readl_relaxed(reg) & ~mask;
384 + writel_relaxed(func, reg);
385 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
386 +}
387 +
388 +static void jh7110_set_vin_group(struct jh7110_pinctrl *sfp,
389 + unsigned int pin)
390 +{
391 + const struct jh7110_vin_group_sel *gs = &jh7110_sys_vin_group_sel[pin];
392 + unsigned long flags;
393 + void __iomem *reg;
394 + u32 mask;
395 + u32 grp;
396 +
397 + if (!gs->offset)
398 + return;
399 +
400 + reg = sfp->base + gs->offset;
401 + grp = gs->group << gs->shift;
402 + mask = 0x3U << gs->shift;
403 +
404 + raw_spin_lock_irqsave(&sfp->lock, flags);
405 + grp |= readl_relaxed(reg) & ~mask;
406 + writel_relaxed(grp, reg);
407 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
408 +}
409 +
410 +static int jh7110_sys_set_one_pin_mux(struct jh7110_pinctrl *sfp,
411 + unsigned int pin,
412 + unsigned int din, u32 dout,
413 + u32 doen, u32 func)
414 +{
415 + if (pin < sfp->gc.ngpio && func == 0)
416 + jh7110_set_gpiomux(sfp, pin, din, dout, doen);
417 +
418 + jh7110_set_function(sfp, pin, func);
419 +
420 + if (pin < sfp->gc.ngpio && func == 2)
421 + jh7110_set_vin_group(sfp, pin);
422 +
423 + return 0;
424 +}
425 +
426 +static int jh7110_sys_get_padcfg_base(struct jh7110_pinctrl *sfp,
427 + unsigned int pin)
428 +{
429 + if (pin < PAD_GMAC1_MDC)
430 + return JH7110_SYS_GPO_PDA_0_74_CFG;
431 + else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3)
432 + return JH7110_SYS_GPO_PDA_89_94_CFG;
433 + else
434 + return -1;
435 +}
436 +
437 +static void jh7110_sys_irq_handler(struct irq_desc *desc)
438 +{
439 + struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc);
440 + struct irq_chip *chip = irq_desc_get_chip(desc);
441 + unsigned long mis;
442 + unsigned int pin;
443 +
444 + chained_irq_enter(chip, desc);
445 +
446 + mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0);
447 + for_each_set_bit(pin, &mis, 32)
448 + generic_handle_domain_irq(sfp->gc.irq.domain, pin);
449 +
450 + mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1);
451 + for_each_set_bit(pin, &mis, 32)
452 + generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
453 +
454 + chained_irq_exit(chip, desc);
455 +}
456 +
457 +static int jh7110_sys_init_hw(struct gpio_chip *gc)
458 +{
459 + struct jh7110_pinctrl *sfp = container_of(gc,
460 + struct jh7110_pinctrl, gc);
461 +
462 + /* mask all GPIO interrupts */
463 + writel(0U, sfp->base + JH7110_SYS_GPIOIE0);
464 + writel(0U, sfp->base + JH7110_SYS_GPIOIE1);
465 + /* clear edge interrupt flags */
466 + writel(~0U, sfp->base + JH7110_SYS_GPIOIC0);
467 + writel(~0U, sfp->base + JH7110_SYS_GPIOIC1);
468 + /* enable GPIO interrupts */
469 + writel(1U, sfp->base + JH7110_SYS_GPIOEN);
470 + return 0;
471 +}
472 +
473 +static const struct jh7110_gpio_irq_reg jh7110_sys_irq_reg = {
474 + .is_reg_base = JH7110_SYS_GPIOIS0,
475 + .ic_reg_base = JH7110_SYS_GPIOIC0,
476 + .ibe_reg_base = JH7110_SYS_GPIOIBE0,
477 + .iev_reg_base = JH7110_SYS_GPIOIEV0,
478 + .ie_reg_base = JH7110_SYS_GPIOIE0,
479 + .ris_reg_base = JH7110_SYS_GPIORIS0,
480 + .mis_reg_base = JH7110_SYS_GPIOMIS0,
481 +};
482 +
483 +static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = {
484 + .pins = jh7110_sys_pins,
485 + .npins = ARRAY_SIZE(jh7110_sys_pins),
486 + .ngpios = JH7110_SYS_NGPIO,
487 + .gc_base = JH7110_SYS_GC_BASE,
488 + .dout_reg_base = JH7110_SYS_DOUT,
489 + .dout_mask = GENMASK(6, 0),
490 + .doen_reg_base = JH7110_SYS_DOEN,
491 + .doen_mask = GENMASK(5, 0),
492 + .gpi_reg_base = JH7110_SYS_GPI,
493 + .gpi_mask = GENMASK(6, 0),
494 + .gpioin_reg_base = JH7110_SYS_GPIOIN,
495 + .irq_reg = &jh7110_sys_irq_reg,
496 + .jh7110_set_one_pin_mux = jh7110_sys_set_one_pin_mux,
497 + .jh7110_get_padcfg_base = jh7110_sys_get_padcfg_base,
498 + .jh7110_gpio_irq_handler = jh7110_sys_irq_handler,
499 + .jh7110_gpio_init_hw = jh7110_sys_init_hw,
500 +};
501 +
502 +static const struct of_device_id jh7110_sys_pinctrl_of_match[] = {
503 + {
504 + .compatible = "starfive,jh7110-sys-pinctrl",
505 + .data = &jh7110_sys_pinctrl_info,
506 + },
507 + { /* sentinel */ }
508 +};
509 +MODULE_DEVICE_TABLE(of, jh7110_sys_pinctrl_of_match);
510 +
511 +static struct platform_driver jh7110_sys_pinctrl_driver = {
512 + .probe = jh7110_pinctrl_probe,
513 + .driver = {
514 + .name = "starfive-jh7110-sys-pinctrl",
515 + .of_match_table = jh7110_sys_pinctrl_of_match,
516 + },
517 +};
518 +module_platform_driver(jh7110_sys_pinctrl_driver);
519 +
520 +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC sys controller");
521 +MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
522 +MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
523 +MODULE_LICENSE("GPL");
524 --- /dev/null
525 +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
526 @@ -0,0 +1,982 @@
527 +// SPDX-License-Identifier: GPL-2.0
528 +/*
529 + * Pinctrl / GPIO driver for StarFive JH7110 SoC
530 + *
531 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
532 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
533 + */
534 +
535 +#include <linux/bits.h>
536 +#include <linux/clk.h>
537 +#include <linux/gpio/driver.h>
538 +#include <linux/io.h>
539 +#include <linux/mod_devicetable.h>
540 +#include <linux/module.h>
541 +#include <linux/mutex.h>
542 +#include <linux/of.h>
543 +#include <linux/of_device.h>
544 +#include <linux/platform_device.h>
545 +#include <linux/reset.h>
546 +#include <linux/seq_file.h>
547 +#include <linux/spinlock.h>
548 +
549 +#include <linux/pinctrl/consumer.h>
550 +#include <linux/pinctrl/pinconf.h>
551 +#include <linux/pinctrl/pinctrl.h>
552 +#include <linux/pinctrl/pinmux.h>
553 +
554 +#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
555 +
556 +#include "../core.h"
557 +#include "../pinctrl-utils.h"
558 +#include "../pinmux.h"
559 +#include "../pinconf.h"
560 +#include "pinctrl-starfive-jh7110.h"
561 +
562 +/* pad control bits */
563 +#define JH7110_PADCFG_POS BIT(7)
564 +#define JH7110_PADCFG_SMT BIT(6)
565 +#define JH7110_PADCFG_SLEW BIT(5)
566 +#define JH7110_PADCFG_PD BIT(4)
567 +#define JH7110_PADCFG_PU BIT(3)
568 +#define JH7110_PADCFG_BIAS (JH7110_PADCFG_PD | JH7110_PADCFG_PU)
569 +#define JH7110_PADCFG_DS_MASK GENMASK(2, 1)
570 +#define JH7110_PADCFG_DS_2MA (0U << 1)
571 +#define JH7110_PADCFG_DS_4MA BIT(1)
572 +#define JH7110_PADCFG_DS_8MA (2U << 1)
573 +#define JH7110_PADCFG_DS_12MA (3U << 1)
574 +#define JH7110_PADCFG_IE BIT(0)
575 +
576 +/*
577 + * The packed pinmux values from the device tree look like this:
578 + *
579 + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
580 + * | din | dout | doen | function | pin |
581 + */
582 +static unsigned int jh7110_pinmux_din(u32 v)
583 +{
584 + return (v & GENMASK(31, 24)) >> 24;
585 +}
586 +
587 +static u32 jh7110_pinmux_dout(u32 v)
588 +{
589 + return (v & GENMASK(23, 16)) >> 16;
590 +}
591 +
592 +static u32 jh7110_pinmux_doen(u32 v)
593 +{
594 + return (v & GENMASK(15, 10)) >> 10;
595 +}
596 +
597 +static u32 jh7110_pinmux_function(u32 v)
598 +{
599 + return (v & GENMASK(9, 8)) >> 8;
600 +}
601 +
602 +static unsigned int jh7110_pinmux_pin(u32 v)
603 +{
604 + return v & GENMASK(7, 0);
605 +}
606 +
607 +static struct jh7110_pinctrl *jh7110_from_irq_data(struct irq_data *d)
608 +{
609 + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
610 +
611 + return container_of(gc, struct jh7110_pinctrl, gc);
612 +}
613 +
614 +struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc)
615 +{
616 + struct gpio_chip *gc = irq_desc_get_handler_data(desc);
617 +
618 + return container_of(gc, struct jh7110_pinctrl, gc);
619 +}
620 +EXPORT_SYMBOL_GPL(jh7110_from_irq_desc);
621 +
622 +#ifdef CONFIG_DEBUG_FS
623 +static void jh7110_pin_dbg_show(struct pinctrl_dev *pctldev,
624 + struct seq_file *s, unsigned int pin)
625 +{
626 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
627 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
628 +
629 + seq_printf(s, "%s", dev_name(pctldev->dev));
630 +
631 + if (pin < sfp->gc.ngpio) {
632 + unsigned int offset = 4 * (pin / 4);
633 + unsigned int shift = 8 * (pin % 4);
634 + u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);
635 + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
636 + u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);
637 +
638 + dout = (dout >> shift) & info->dout_mask;
639 + doen = (doen >> shift) & info->doen_mask;
640 + gpi = ((gpi >> shift) - 2) & info->gpi_mask;
641 +
642 + seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi);
643 + }
644 +}
645 +#else
646 +#define jh7110_pin_dbg_show NULL
647 +#endif
648 +
649 +static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
650 + struct device_node *np,
651 + struct pinctrl_map **maps,
652 + unsigned int *num_maps)
653 +{
654 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
655 + struct device *dev = sfp->gc.parent;
656 + struct device_node *child;
657 + struct pinctrl_map *map;
658 + const char **pgnames;
659 + const char *grpname;
660 + int ngroups;
661 + int nmaps;
662 + int ret;
663 +
664 + ngroups = 0;
665 + for_each_child_of_node(np, child)
666 + ngroups += 1;
667 + nmaps = 2 * ngroups;
668 +
669 + pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
670 + if (!pgnames)
671 + return -ENOMEM;
672 +
673 + map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
674 + if (!map)
675 + return -ENOMEM;
676 +
677 + nmaps = 0;
678 + ngroups = 0;
679 + mutex_lock(&sfp->mutex);
680 + for_each_child_of_node(np, child) {
681 + int npins = of_property_count_u32_elems(child, "pinmux");
682 + int *pins;
683 + u32 *pinmux;
684 + int i;
685 +
686 + if (npins < 1) {
687 + dev_err(dev,
688 + "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",
689 + np, child);
690 + ret = -EINVAL;
691 + goto put_child;
692 + }
693 +
694 + grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
695 + if (!grpname) {
696 + ret = -ENOMEM;
697 + goto put_child;
698 + }
699 +
700 + pgnames[ngroups++] = grpname;
701 +
702 + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
703 + if (!pins) {
704 + ret = -ENOMEM;
705 + goto put_child;
706 + }
707 +
708 + pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
709 + if (!pinmux) {
710 + ret = -ENOMEM;
711 + goto put_child;
712 + }
713 +
714 + ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
715 + if (ret)
716 + goto put_child;
717 +
718 + for (i = 0; i < npins; i++)
719 + pins[i] = jh7110_pinmux_pin(pinmux[i]);
720 +
721 + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
722 + map[nmaps].data.mux.function = np->name;
723 + map[nmaps].data.mux.group = grpname;
724 + nmaps += 1;
725 +
726 + ret = pinctrl_generic_add_group(pctldev, grpname,
727 + pins, npins, pinmux);
728 + if (ret < 0) {
729 + dev_err(dev, "error adding group %s: %d\n", grpname, ret);
730 + goto put_child;
731 + }
732 +
733 + ret = pinconf_generic_parse_dt_config(child, pctldev,
734 + &map[nmaps].data.configs.configs,
735 + &map[nmaps].data.configs.num_configs);
736 + if (ret) {
737 + dev_err(dev, "error parsing pin config of group %s: %d\n",
738 + grpname, ret);
739 + goto put_child;
740 + }
741 +
742 + /* don't create a map if there are no pinconf settings */
743 + if (map[nmaps].data.configs.num_configs == 0)
744 + continue;
745 +
746 + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
747 + map[nmaps].data.configs.group_or_pin = grpname;
748 + nmaps += 1;
749 + }
750 +
751 + ret = pinmux_generic_add_function(pctldev, np->name,
752 + pgnames, ngroups, NULL);
753 + if (ret < 0) {
754 + dev_err(dev, "error adding function %s: %d\n", np->name, ret);
755 + goto free_map;
756 + }
757 + mutex_unlock(&sfp->mutex);
758 +
759 + *maps = map;
760 + *num_maps = nmaps;
761 + return 0;
762 +
763 +put_child:
764 + of_node_put(child);
765 +free_map:
766 + pinctrl_utils_free_map(pctldev, map, nmaps);
767 + mutex_unlock(&sfp->mutex);
768 + return ret;
769 +}
770 +
771 +static const struct pinctrl_ops jh7110_pinctrl_ops = {
772 + .get_groups_count = pinctrl_generic_get_group_count,
773 + .get_group_name = pinctrl_generic_get_group_name,
774 + .get_group_pins = pinctrl_generic_get_group_pins,
775 + .pin_dbg_show = jh7110_pin_dbg_show,
776 + .dt_node_to_map = jh7110_dt_node_to_map,
777 + .dt_free_map = pinctrl_utils_free_map,
778 +};
779 +
780 +void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
781 + unsigned int din, u32 dout, u32 doen)
782 +{
783 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
784 +
785 + unsigned int offset = 4 * (pin / 4);
786 + unsigned int shift = 8 * (pin % 4);
787 + u32 dout_mask = info->dout_mask << shift;
788 + u32 done_mask = info->doen_mask << shift;
789 + u32 ival, imask;
790 + void __iomem *reg_dout;
791 + void __iomem *reg_doen;
792 + void __iomem *reg_din;
793 + unsigned long flags;
794 +
795 + reg_dout = sfp->base + info->dout_reg_base + offset;
796 + reg_doen = sfp->base + info->doen_reg_base + offset;
797 + dout <<= shift;
798 + doen <<= shift;
799 + if (din != GPI_NONE) {
800 + unsigned int ioffset = 4 * (din / 4);
801 + unsigned int ishift = 8 * (din % 4);
802 +
803 + reg_din = sfp->base + info->gpi_reg_base + ioffset;
804 + ival = (pin + 2) << ishift;
805 + imask = info->gpi_mask << ishift;
806 + } else {
807 + reg_din = NULL;
808 + }
809 +
810 + raw_spin_lock_irqsave(&sfp->lock, flags);
811 + dout |= readl_relaxed(reg_dout) & ~dout_mask;
812 + writel_relaxed(dout, reg_dout);
813 + doen |= readl_relaxed(reg_doen) & ~done_mask;
814 + writel_relaxed(doen, reg_doen);
815 + if (reg_din) {
816 + ival |= readl_relaxed(reg_din) & ~imask;
817 + writel_relaxed(ival, reg_din);
818 + }
819 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
820 +}
821 +EXPORT_SYMBOL_GPL(jh7110_set_gpiomux);
822 +
823 +static int jh7110_set_mux(struct pinctrl_dev *pctldev,
824 + unsigned int fsel, unsigned int gsel)
825 +{
826 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
827 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
828 + const struct group_desc *group;
829 + const u32 *pinmux;
830 + unsigned int i;
831 +
832 + group = pinctrl_generic_get_group(pctldev, gsel);
833 + if (!group)
834 + return -EINVAL;
835 +
836 + pinmux = group->data;
837 + for (i = 0; i < group->num_pins; i++) {
838 + u32 v = pinmux[i];
839 +
840 + if (info->jh7110_set_one_pin_mux)
841 + info->jh7110_set_one_pin_mux(sfp,
842 + jh7110_pinmux_pin(v),
843 + jh7110_pinmux_din(v),
844 + jh7110_pinmux_dout(v),
845 + jh7110_pinmux_doen(v),
846 + jh7110_pinmux_function(v));
847 + }
848 +
849 + return 0;
850 +}
851 +
852 +static const struct pinmux_ops jh7110_pinmux_ops = {
853 + .get_functions_count = pinmux_generic_get_function_count,
854 + .get_function_name = pinmux_generic_get_function_name,
855 + .get_function_groups = pinmux_generic_get_function_groups,
856 + .set_mux = jh7110_set_mux,
857 + .strict = true,
858 +};
859 +
860 +static const u8 jh7110_drive_strength_mA[4] = { 2, 4, 8, 12 };
861 +
862 +static u32 jh7110_padcfg_ds_to_mA(u32 padcfg)
863 +{
864 + return jh7110_drive_strength_mA[(padcfg >> 1) & 3U];
865 +}
866 +
867 +static u32 jh7110_padcfg_ds_from_mA(u32 v)
868 +{
869 + int i;
870 +
871 + for (i = 0; i < 3; i++) {
872 + if (v <= jh7110_drive_strength_mA[i])
873 + break;
874 + }
875 + return i << 1;
876 +}
877 +
878 +static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp,
879 + unsigned int pin, u32 mask, u32 value)
880 +{
881 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
882 + void __iomem *reg;
883 + unsigned long flags;
884 + int padcfg_base;
885 +
886 + if (!info->jh7110_get_padcfg_base)
887 + return;
888 +
889 + padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
890 + if (padcfg_base < 0)
891 + return;
892 +
893 + reg = sfp->base + padcfg_base + 4 * pin;
894 + value &= mask;
895 +
896 + raw_spin_lock_irqsave(&sfp->lock, flags);
897 + value |= readl_relaxed(reg) & ~mask;
898 + writel_relaxed(value, reg);
899 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
900 +}
901 +
902 +static int jh7110_pinconf_get(struct pinctrl_dev *pctldev,
903 + unsigned int pin, unsigned long *config)
904 +{
905 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
906 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
907 + int param = pinconf_to_config_param(*config);
908 + u32 padcfg, arg;
909 + bool enabled;
910 + int padcfg_base;
911 +
912 + if (!info->jh7110_get_padcfg_base)
913 + return 0;
914 +
915 + padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
916 + if (padcfg_base < 0)
917 + return 0;
918 +
919 + padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
920 + switch (param) {
921 + case PIN_CONFIG_BIAS_DISABLE:
922 + enabled = !(padcfg & JH7110_PADCFG_BIAS);
923 + arg = 0;
924 + break;
925 + case PIN_CONFIG_BIAS_PULL_DOWN:
926 + enabled = padcfg & JH7110_PADCFG_PD;
927 + arg = 1;
928 + break;
929 + case PIN_CONFIG_BIAS_PULL_UP:
930 + enabled = padcfg & JH7110_PADCFG_PU;
931 + arg = 1;
932 + break;
933 + case PIN_CONFIG_DRIVE_STRENGTH:
934 + enabled = true;
935 + arg = jh7110_padcfg_ds_to_mA(padcfg);
936 + break;
937 + case PIN_CONFIG_INPUT_ENABLE:
938 + enabled = padcfg & JH7110_PADCFG_IE;
939 + arg = enabled;
940 + break;
941 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
942 + enabled = padcfg & JH7110_PADCFG_SMT;
943 + arg = enabled;
944 + break;
945 + case PIN_CONFIG_SLEW_RATE:
946 + enabled = true;
947 + arg = !!(padcfg & JH7110_PADCFG_SLEW);
948 + break;
949 + default:
950 + return -ENOTSUPP;
951 + }
952 +
953 + *config = pinconf_to_config_packed(param, arg);
954 + return enabled ? 0 : -EINVAL;
955 +}
956 +
957 +static int jh7110_pinconf_group_get(struct pinctrl_dev *pctldev,
958 + unsigned int gsel,
959 + unsigned long *config)
960 +{
961 + const struct group_desc *group;
962 +
963 + group = pinctrl_generic_get_group(pctldev, gsel);
964 + if (!group)
965 + return -EINVAL;
966 +
967 + return jh7110_pinconf_get(pctldev, group->pins[0], config);
968 +}
969 +
970 +static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev,
971 + unsigned int gsel,
972 + unsigned long *configs,
973 + unsigned int num_configs)
974 +{
975 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
976 + const struct group_desc *group;
977 + u16 mask, value;
978 + int i;
979 +
980 + group = pinctrl_generic_get_group(pctldev, gsel);
981 + if (!group)
982 + return -EINVAL;
983 +
984 + mask = 0;
985 + value = 0;
986 + for (i = 0; i < num_configs; i++) {
987 + int param = pinconf_to_config_param(configs[i]);
988 + u32 arg = pinconf_to_config_argument(configs[i]);
989 +
990 + switch (param) {
991 + case PIN_CONFIG_BIAS_DISABLE:
992 + mask |= JH7110_PADCFG_BIAS;
993 + value &= ~JH7110_PADCFG_BIAS;
994 + break;
995 + case PIN_CONFIG_BIAS_PULL_DOWN:
996 + if (arg == 0)
997 + return -ENOTSUPP;
998 + mask |= JH7110_PADCFG_BIAS;
999 + value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PD;
1000 + break;
1001 + case PIN_CONFIG_BIAS_PULL_UP:
1002 + if (arg == 0)
1003 + return -ENOTSUPP;
1004 + mask |= JH7110_PADCFG_BIAS;
1005 + value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PU;
1006 + break;
1007 + case PIN_CONFIG_DRIVE_STRENGTH:
1008 + mask |= JH7110_PADCFG_DS_MASK;
1009 + value = (value & ~JH7110_PADCFG_DS_MASK) |
1010 + jh7110_padcfg_ds_from_mA(arg);
1011 + break;
1012 + case PIN_CONFIG_INPUT_ENABLE:
1013 + mask |= JH7110_PADCFG_IE;
1014 + if (arg)
1015 + value |= JH7110_PADCFG_IE;
1016 + else
1017 + value &= ~JH7110_PADCFG_IE;
1018 + break;
1019 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1020 + mask |= JH7110_PADCFG_SMT;
1021 + if (arg)
1022 + value |= JH7110_PADCFG_SMT;
1023 + else
1024 + value &= ~JH7110_PADCFG_SMT;
1025 + break;
1026 + case PIN_CONFIG_SLEW_RATE:
1027 + mask |= JH7110_PADCFG_SLEW;
1028 + if (arg)
1029 + value |= JH7110_PADCFG_SLEW;
1030 + else
1031 + value &= ~JH7110_PADCFG_SLEW;
1032 + break;
1033 + default:
1034 + return -ENOTSUPP;
1035 + }
1036 + }
1037 +
1038 + for (i = 0; i < group->num_pins; i++)
1039 + jh7110_padcfg_rmw(sfp, group->pins[i], mask, value);
1040 +
1041 + return 0;
1042 +}
1043 +
1044 +#ifdef CONFIG_DEBUG_FS
1045 +static void jh7110_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1046 + struct seq_file *s, unsigned int pin)
1047 +{
1048 + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
1049 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1050 + u32 value;
1051 + int padcfg_base;
1052 +
1053 + if (!info->jh7110_get_padcfg_base)
1054 + return;
1055 +
1056 + padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
1057 + if (padcfg_base < 0)
1058 + return;
1059 +
1060 + value = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
1061 + seq_printf(s, " (0x%02x)", value);
1062 +}
1063 +#else
1064 +#define jh7110_pinconf_dbg_show NULL
1065 +#endif
1066 +
1067 +static const struct pinconf_ops jh7110_pinconf_ops = {
1068 + .pin_config_get = jh7110_pinconf_get,
1069 + .pin_config_group_get = jh7110_pinconf_group_get,
1070 + .pin_config_group_set = jh7110_pinconf_group_set,
1071 + .pin_config_dbg_show = jh7110_pinconf_dbg_show,
1072 + .is_generic = true,
1073 +};
1074 +
1075 +static int jh7110_gpio_request(struct gpio_chip *gc, unsigned int gpio)
1076 +{
1077 + return pinctrl_gpio_request(gc->base + gpio);
1078 +}
1079 +
1080 +static void jh7110_gpio_free(struct gpio_chip *gc, unsigned int gpio)
1081 +{
1082 + pinctrl_gpio_free(gc->base + gpio);
1083 +}
1084 +
1085 +static int jh7110_gpio_get_direction(struct gpio_chip *gc,
1086 + unsigned int gpio)
1087 +{
1088 + struct jh7110_pinctrl *sfp = container_of(gc,
1089 + struct jh7110_pinctrl, gc);
1090 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1091 + unsigned int offset = 4 * (gpio / 4);
1092 + unsigned int shift = 8 * (gpio % 4);
1093 + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
1094 +
1095 + doen = (doen >> shift) & info->doen_mask;
1096 +
1097 + return doen == GPOEN_ENABLE ?
1098 + GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1099 +}
1100 +
1101 +static int jh7110_gpio_direction_input(struct gpio_chip *gc,
1102 + unsigned int gpio)
1103 +{
1104 + struct jh7110_pinctrl *sfp = container_of(gc,
1105 + struct jh7110_pinctrl, gc);
1106 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1107 +
1108 + /* enable input and schmitt trigger */
1109 + jh7110_padcfg_rmw(sfp, gpio,
1110 + JH7110_PADCFG_IE | JH7110_PADCFG_SMT,
1111 + JH7110_PADCFG_IE | JH7110_PADCFG_SMT);
1112 +
1113 + if (info->jh7110_set_one_pin_mux)
1114 + info->jh7110_set_one_pin_mux(sfp, gpio,
1115 + GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);
1116 +
1117 + return 0;
1118 +}
1119 +
1120 +static int jh7110_gpio_direction_output(struct gpio_chip *gc,
1121 + unsigned int gpio, int value)
1122 +{
1123 + struct jh7110_pinctrl *sfp = container_of(gc,
1124 + struct jh7110_pinctrl, gc);
1125 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1126 +
1127 + if (info->jh7110_set_one_pin_mux)
1128 + info->jh7110_set_one_pin_mux(sfp, gpio,
1129 + GPI_NONE, value ? GPOUT_HIGH : GPOUT_LOW,
1130 + GPOEN_ENABLE, 0);
1131 +
1132 + /* disable input, schmitt trigger and bias */
1133 + jh7110_padcfg_rmw(sfp, gpio,
1134 + JH7110_PADCFG_IE | JH7110_PADCFG_SMT |
1135 + JH7110_PADCFG_BIAS, 0);
1136 + return 0;
1137 +}
1138 +
1139 +static int jh7110_gpio_get(struct gpio_chip *gc, unsigned int gpio)
1140 +{
1141 + struct jh7110_pinctrl *sfp = container_of(gc,
1142 + struct jh7110_pinctrl, gc);
1143 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1144 + void __iomem *reg = sfp->base + info->gpioin_reg_base
1145 + + 4 * (gpio / 32);
1146 +
1147 + return !!(readl_relaxed(reg) & BIT(gpio % 32));
1148 +}
1149 +
1150 +static void jh7110_gpio_set(struct gpio_chip *gc,
1151 + unsigned int gpio, int value)
1152 +{
1153 + struct jh7110_pinctrl *sfp = container_of(gc,
1154 + struct jh7110_pinctrl, gc);
1155 + const struct jh7110_pinctrl_soc_info *info = sfp->info;
1156 + unsigned int offset = 4 * (gpio / 4);
1157 + unsigned int shift = 8 * (gpio % 4);
1158 + void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset;
1159 + u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift;
1160 + u32 mask = info->dout_mask << shift;
1161 + unsigned long flags;
1162 +
1163 + raw_spin_lock_irqsave(&sfp->lock, flags);
1164 + dout |= readl_relaxed(reg_dout) & ~mask;
1165 + writel_relaxed(dout, reg_dout);
1166 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1167 +}
1168 +
1169 +static int jh7110_gpio_set_config(struct gpio_chip *gc,
1170 + unsigned int gpio, unsigned long config)
1171 +{
1172 + struct jh7110_pinctrl *sfp = container_of(gc,
1173 + struct jh7110_pinctrl, gc);
1174 + u32 arg = pinconf_to_config_argument(config);
1175 + u32 value;
1176 + u32 mask;
1177 +
1178 + switch (pinconf_to_config_param(config)) {
1179 + case PIN_CONFIG_BIAS_DISABLE:
1180 + mask = JH7110_PADCFG_BIAS;
1181 + value = 0;
1182 + break;
1183 + case PIN_CONFIG_BIAS_PULL_DOWN:
1184 + if (arg == 0)
1185 + return -ENOTSUPP;
1186 + mask = JH7110_PADCFG_BIAS;
1187 + value = JH7110_PADCFG_PD;
1188 + break;
1189 + case PIN_CONFIG_BIAS_PULL_UP:
1190 + if (arg == 0)
1191 + return -ENOTSUPP;
1192 + mask = JH7110_PADCFG_BIAS;
1193 + value = JH7110_PADCFG_PU;
1194 + break;
1195 + case PIN_CONFIG_DRIVE_PUSH_PULL:
1196 + return 0;
1197 + case PIN_CONFIG_INPUT_ENABLE:
1198 + mask = JH7110_PADCFG_IE;
1199 + value = arg ? JH7110_PADCFG_IE : 0;
1200 + break;
1201 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1202 + mask = JH7110_PADCFG_SMT;
1203 + value = arg ? JH7110_PADCFG_SMT : 0;
1204 + break;
1205 + default:
1206 + return -ENOTSUPP;
1207 + }
1208 +
1209 + jh7110_padcfg_rmw(sfp, gpio, mask, value);
1210 + return 0;
1211 +}
1212 +
1213 +static int jh7110_gpio_add_pin_ranges(struct gpio_chip *gc)
1214 +{
1215 + struct jh7110_pinctrl *sfp = container_of(gc,
1216 + struct jh7110_pinctrl, gc);
1217 +
1218 + sfp->gpios.name = sfp->gc.label;
1219 + sfp->gpios.base = sfp->gc.base;
1220 + sfp->gpios.pin_base = 0;
1221 + sfp->gpios.npins = sfp->gc.ngpio;
1222 + sfp->gpios.gc = &sfp->gc;
1223 + pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
1224 + return 0;
1225 +}
1226 +
1227 +static void jh7110_irq_ack(struct irq_data *d)
1228 +{
1229 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1230 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1231 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1232 + void __iomem *ic = sfp->base + irq_reg->ic_reg_base
1233 + + 4 * (gpio / 32);
1234 + u32 mask = BIT(gpio % 32);
1235 + unsigned long flags;
1236 + u32 value;
1237 +
1238 + raw_spin_lock_irqsave(&sfp->lock, flags);
1239 + value = readl_relaxed(ic) & ~mask;
1240 + writel_relaxed(value, ic);
1241 + writel_relaxed(value | mask, ic);
1242 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1243 +}
1244 +
1245 +static void jh7110_irq_mask(struct irq_data *d)
1246 +{
1247 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1248 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1249 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1250 + void __iomem *ie = sfp->base + irq_reg->ie_reg_base
1251 + + 4 * (gpio / 32);
1252 + u32 mask = BIT(gpio % 32);
1253 + unsigned long flags;
1254 + u32 value;
1255 +
1256 + raw_spin_lock_irqsave(&sfp->lock, flags);
1257 + value = readl_relaxed(ie) & ~mask;
1258 + writel_relaxed(value, ie);
1259 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1260 +
1261 + gpiochip_disable_irq(&sfp->gc, d->hwirq);
1262 +}
1263 +
1264 +static void jh7110_irq_mask_ack(struct irq_data *d)
1265 +{
1266 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1267 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1268 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1269 + void __iomem *ie = sfp->base + irq_reg->ie_reg_base
1270 + + 4 * (gpio / 32);
1271 + void __iomem *ic = sfp->base + irq_reg->ic_reg_base
1272 + + 4 * (gpio / 32);
1273 + u32 mask = BIT(gpio % 32);
1274 + unsigned long flags;
1275 + u32 value;
1276 +
1277 + raw_spin_lock_irqsave(&sfp->lock, flags);
1278 + value = readl_relaxed(ie) & ~mask;
1279 + writel_relaxed(value, ie);
1280 +
1281 + value = readl_relaxed(ic) & ~mask;
1282 + writel_relaxed(value, ic);
1283 + writel_relaxed(value | mask, ic);
1284 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1285 +}
1286 +
1287 +static void jh7110_irq_unmask(struct irq_data *d)
1288 +{
1289 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1290 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1291 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1292 + void __iomem *ie = sfp->base + irq_reg->ie_reg_base
1293 + + 4 * (gpio / 32);
1294 + u32 mask = BIT(gpio % 32);
1295 + unsigned long flags;
1296 + u32 value;
1297 +
1298 + gpiochip_enable_irq(&sfp->gc, d->hwirq);
1299 +
1300 + raw_spin_lock_irqsave(&sfp->lock, flags);
1301 + value = readl_relaxed(ie) | mask;
1302 + writel_relaxed(value, ie);
1303 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1304 +}
1305 +
1306 +static int jh7110_irq_set_type(struct irq_data *d, unsigned int trigger)
1307 +{
1308 + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
1309 + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
1310 + irq_hw_number_t gpio = irqd_to_hwirq(d);
1311 + void __iomem *base = sfp->base + 4 * (gpio / 32);
1312 + u32 mask = BIT(gpio % 32);
1313 + u32 irq_type, edge_both, polarity;
1314 + unsigned long flags;
1315 +
1316 + switch (trigger) {
1317 + case IRQ_TYPE_EDGE_RISING:
1318 + irq_type = mask; /* 1: edge triggered */
1319 + edge_both = 0; /* 0: single edge */
1320 + polarity = mask; /* 1: rising edge */
1321 + break;
1322 + case IRQ_TYPE_EDGE_FALLING:
1323 + irq_type = mask; /* 1: edge triggered */
1324 + edge_both = 0; /* 0: single edge */
1325 + polarity = 0; /* 0: falling edge */
1326 + break;
1327 + case IRQ_TYPE_EDGE_BOTH:
1328 + irq_type = mask; /* 1: edge triggered */
1329 + edge_both = mask; /* 1: both edges */
1330 + polarity = 0; /* 0: ignored */
1331 + break;
1332 + case IRQ_TYPE_LEVEL_HIGH:
1333 + irq_type = 0; /* 0: level triggered */
1334 + edge_both = 0; /* 0: ignored */
1335 + polarity = mask; /* 1: high level */
1336 + break;
1337 + case IRQ_TYPE_LEVEL_LOW:
1338 + irq_type = 0; /* 0: level triggered */
1339 + edge_both = 0; /* 0: ignored */
1340 + polarity = 0; /* 0: low level */
1341 + break;
1342 + default:
1343 + return -EINVAL;
1344 + }
1345 +
1346 + if (trigger & IRQ_TYPE_EDGE_BOTH)
1347 + irq_set_handler_locked(d, handle_edge_irq);
1348 + else
1349 + irq_set_handler_locked(d, handle_level_irq);
1350 +
1351 + raw_spin_lock_irqsave(&sfp->lock, flags);
1352 + irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask;
1353 + writel_relaxed(irq_type, base + irq_reg->is_reg_base);
1354 +
1355 + edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask;
1356 + writel_relaxed(edge_both, base + irq_reg->ibe_reg_base);
1357 +
1358 + polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask;
1359 + writel_relaxed(polarity, base + irq_reg->iev_reg_base);
1360 + raw_spin_unlock_irqrestore(&sfp->lock, flags);
1361 + return 0;
1362 +}
1363 +
1364 +static struct irq_chip jh7110_irq_chip = {
1365 + .irq_ack = jh7110_irq_ack,
1366 + .irq_mask = jh7110_irq_mask,
1367 + .irq_mask_ack = jh7110_irq_mask_ack,
1368 + .irq_unmask = jh7110_irq_unmask,
1369 + .irq_set_type = jh7110_irq_set_type,
1370 + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
1371 + GPIOCHIP_IRQ_RESOURCE_HELPERS,
1372 +};
1373 +
1374 +static void jh7110_disable_clock(void *data)
1375 +{
1376 + clk_disable_unprepare(data);
1377 +}
1378 +
1379 +int jh7110_pinctrl_probe(struct platform_device *pdev)
1380 +{
1381 + struct device *dev = &pdev->dev;
1382 + const struct jh7110_pinctrl_soc_info *info;
1383 + struct jh7110_pinctrl *sfp;
1384 + struct pinctrl_desc *jh7110_pinctrl_desc;
1385 + struct reset_control *rst;
1386 + struct clk *clk;
1387 + int ret;
1388 +
1389 + info = of_device_get_match_data(&pdev->dev);
1390 + if (!info)
1391 + return -ENODEV;
1392 +
1393 + if (!info->pins || !info->npins) {
1394 + dev_err(dev, "wrong pinctrl info\n");
1395 + return -EINVAL;
1396 + }
1397 +
1398 + sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
1399 + if (!sfp)
1400 + return -ENOMEM;
1401 +
1402 + sfp->base = devm_platform_ioremap_resource(pdev, 0);
1403 + if (IS_ERR(sfp->base))
1404 + return PTR_ERR(sfp->base);
1405 +
1406 + clk = devm_clk_get_optional(dev, NULL);
1407 + if (IS_ERR(clk))
1408 + return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
1409 +
1410 + rst = devm_reset_control_get_exclusive(dev, NULL);
1411 + if (IS_ERR(rst))
1412 + return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
1413 +
1414 + /*
1415 + * we don't want to assert reset and risk undoing pin muxing for the
1416 + * early boot serial console, but let's make sure the reset line is
1417 + * deasserted in case someone runs a really minimal bootloader.
1418 + */
1419 + ret = reset_control_deassert(rst);
1420 + if (ret)
1421 + return dev_err_probe(dev, ret, "could not deassert reset\n");
1422 +
1423 + if (clk) {
1424 + ret = clk_prepare_enable(clk);
1425 + if (ret)
1426 + return dev_err_probe(dev, ret, "could not enable clock\n");
1427 +
1428 + ret = devm_add_action_or_reset(dev, jh7110_disable_clock, clk);
1429 + if (ret)
1430 + return ret;
1431 + }
1432 +
1433 + jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev,
1434 + sizeof(*jh7110_pinctrl_desc),
1435 + GFP_KERNEL);
1436 + if (!jh7110_pinctrl_desc)
1437 + return -ENOMEM;
1438 +
1439 + jh7110_pinctrl_desc->name = dev_name(dev);
1440 + jh7110_pinctrl_desc->pins = info->pins;
1441 + jh7110_pinctrl_desc->npins = info->npins;
1442 + jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops;
1443 + jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops;
1444 + jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops;
1445 + jh7110_pinctrl_desc->owner = THIS_MODULE;
1446 +
1447 + sfp->info = info;
1448 + sfp->dev = dev;
1449 + platform_set_drvdata(pdev, sfp);
1450 + sfp->gc.parent = dev;
1451 + raw_spin_lock_init(&sfp->lock);
1452 + mutex_init(&sfp->mutex);
1453 +
1454 + ret = devm_pinctrl_register_and_init(dev,
1455 + jh7110_pinctrl_desc,
1456 + sfp, &sfp->pctl);
1457 + if (ret)
1458 + return dev_err_probe(dev, ret,
1459 + "could not register pinctrl driver\n");
1460 +
1461 + sfp->gc.label = dev_name(dev);
1462 + sfp->gc.owner = THIS_MODULE;
1463 + sfp->gc.request = jh7110_gpio_request;
1464 + sfp->gc.free = jh7110_gpio_free;
1465 + sfp->gc.get_direction = jh7110_gpio_get_direction;
1466 + sfp->gc.direction_input = jh7110_gpio_direction_input;
1467 + sfp->gc.direction_output = jh7110_gpio_direction_output;
1468 + sfp->gc.get = jh7110_gpio_get;
1469 + sfp->gc.set = jh7110_gpio_set;
1470 + sfp->gc.set_config = jh7110_gpio_set_config;
1471 + sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;
1472 + sfp->gc.base = info->gc_base;
1473 + sfp->gc.ngpio = info->ngpios;
1474 +
1475 + jh7110_irq_chip.name = sfp->gc.label;
1476 + gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip);
1477 + sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler;
1478 + sfp->gc.irq.num_parents = 1;
1479 + sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
1480 + sizeof(*sfp->gc.irq.parents),
1481 + GFP_KERNEL);
1482 + if (!sfp->gc.irq.parents)
1483 + return -ENOMEM;
1484 + sfp->gc.irq.default_type = IRQ_TYPE_NONE;
1485 + sfp->gc.irq.handler = handle_bad_irq;
1486 + sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw;
1487 +
1488 + ret = platform_get_irq(pdev, 0);
1489 + if (ret < 0)
1490 + return ret;
1491 + sfp->gc.irq.parents[0] = ret;
1492 +
1493 + ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
1494 + if (ret)
1495 + return dev_err_probe(dev, ret, "could not register gpiochip\n");
1496 +
1497 + irq_domain_set_pm_device(sfp->gc.irq.domain, dev);
1498 +
1499 + dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio);
1500 +
1501 + return pinctrl_enable(sfp->pctl);
1502 +}
1503 +EXPORT_SYMBOL_GPL(jh7110_pinctrl_probe);
1504 +
1505 +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC");
1506 +MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1507 +MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
1508 +MODULE_LICENSE("GPL");
1509 --- /dev/null
1510 +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h
1511 @@ -0,0 +1,70 @@
1512 +/* SPDX-License-Identifier: GPL-2.0 */
1513 +/*
1514 + * Pinctrl / GPIO driver for StarFive JH7110 SoC
1515 + *
1516 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
1517 + */
1518 +
1519 +#ifndef __PINCTRL_STARFIVE_JH7110_H__
1520 +#define __PINCTRL_STARFIVE_JH7110_H__
1521 +
1522 +#include <linux/pinctrl/pinconf-generic.h>
1523 +#include <linux/pinctrl/pinmux.h>
1524 +
1525 +struct jh7110_pinctrl {
1526 + struct device *dev;
1527 + struct gpio_chip gc;
1528 + struct pinctrl_gpio_range gpios;
1529 + raw_spinlock_t lock;
1530 + void __iomem *base;
1531 + struct pinctrl_dev *pctl;
1532 + /* register read/write mutex */
1533 + struct mutex mutex;
1534 + const struct jh7110_pinctrl_soc_info *info;
1535 +};
1536 +
1537 +struct jh7110_gpio_irq_reg {
1538 + unsigned int is_reg_base;
1539 + unsigned int ic_reg_base;
1540 + unsigned int ibe_reg_base;
1541 + unsigned int iev_reg_base;
1542 + unsigned int ie_reg_base;
1543 + unsigned int ris_reg_base;
1544 + unsigned int mis_reg_base;
1545 +};
1546 +
1547 +struct jh7110_pinctrl_soc_info {
1548 + const struct pinctrl_pin_desc *pins;
1549 + unsigned int npins;
1550 + unsigned int ngpios;
1551 + unsigned int gc_base;
1552 +
1553 + /* gpio dout/doen/din/gpioinput register */
1554 + unsigned int dout_reg_base;
1555 + unsigned int dout_mask;
1556 + unsigned int doen_reg_base;
1557 + unsigned int doen_mask;
1558 + unsigned int gpi_reg_base;
1559 + unsigned int gpi_mask;
1560 + unsigned int gpioin_reg_base;
1561 +
1562 + const struct jh7110_gpio_irq_reg *irq_reg;
1563 +
1564 + /* generic pinmux */
1565 + int (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *sfp,
1566 + unsigned int pin,
1567 + unsigned int din, u32 dout,
1568 + u32 doen, u32 func);
1569 + /* gpio chip */
1570 + int (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *sfp,
1571 + unsigned int pin);
1572 + void (*jh7110_gpio_irq_handler)(struct irq_desc *desc);
1573 + int (*jh7110_gpio_init_hw)(struct gpio_chip *gc);
1574 +};
1575 +
1576 +void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
1577 + unsigned int din, u32 dout, u32 doen);
1578 +int jh7110_pinctrl_probe(struct platform_device *pdev);
1579 +struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc);
1580 +
1581 +#endif /* __PINCTRL_STARFIVE_JH7110_H__ */
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