target/linux/starfive/patches-6.1/0026-dt-bindings-pinctrl-Add-StarFive-JH7110-sys-pinctrl.patch

   1 From 28518a9637fee6b84464beff9d4308edc3efba72 Mon Sep 17 00:00:00 2001
   2 From: Jianlong Huang <jianlong.huang@starfivetech.com>
   3 Date: Thu, 9 Feb 2023 22:36:59 +0800
   4 Subject: [PATCH 026/122] dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl
   5
   6 Add pinctrl bindings for StarFive JH7110 SoC sys pinctrl controller.
   7
   8 Reviewed-by: Rob Herring <robh@kernel.org>
   9 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
  10 Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
  11 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
  12 Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
  13 ---
  14  .../pinctrl/starfive,jh7110-sys-pinctrl.yaml  | 142 ++++++++++++++++++
  15  MAINTAINERS                                   |   6 +-
  16  .../pinctrl/starfive,jh7110-pinctrl.h         | 115 ++++++++++++++
  17  3 files changed, 261 insertions(+), 2 deletions(-)
  18  create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
  19  create mode 100644 include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
  20
  21 --- /dev/null
  22 +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
  23 @@ -0,0 +1,142 @@
  24 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  25 +%YAML 1.2
  26 +---
  27 +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
  28 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  29 +
  30 +title: StarFive JH7110 SYS Pin Controller
  31 +
  32 +description: |
  33 +  Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
  34 +
  35 +  Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63
  36 +  can be multiplexed and have configurable bias, drive strength,
  37 +  schmitt trigger etc.
  38 +  Some peripherals have their I/O go through the 64 "GPIOs". This also
  39 +  includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
  40 +  All these peripherals are connected to all 64 GPIOs such that
  41 +  any GPIO can be set up to be controlled by any of the peripherals.
  42 +
  43 +maintainers:
  44 +  - Jianlong Huang <jianlong.huang@starfivetech.com>
  45 +
  46 +properties:
  47 +  compatible:
  48 +    const: starfive,jh7110-sys-pinctrl
  49 +
  50 +  reg:
  51 +    maxItems: 1
  52 +
  53 +  clocks:
  54 +    maxItems: 1
  55 +
  56 +  resets:
  57 +    maxItems: 1
  58 +
  59 +  interrupts:
  60 +    maxItems: 1
  61 +
  62 +  interrupt-controller: true
  63 +
  64 +  '#interrupt-cells':
  65 +    const: 2
  66 +
  67 +  gpio-controller: true
  68 +
  69 +  '#gpio-cells':
  70 +    const: 2
  71 +
  72 +patternProperties:
  73 +  '-[0-9]+$':
  74 +    type: object
  75 +    additionalProperties: false
  76 +    patternProperties:
  77 +      '-pins$':
  78 +        type: object
  79 +        description: |
  80 +          A pinctrl node should contain at least one subnode representing the
  81 +          pinctrl groups available on the machine. Each subnode will list the
  82 +          pins it needs, and how they should be configured, with regard to
  83 +          muxer configuration, bias, input enable/disable, input schmitt
  84 +          trigger enable/disable, slew-rate and drive strength.
  85 +        allOf:
  86 +          - $ref: /schemas/pinctrl/pincfg-node.yaml
  87 +          - $ref: /schemas/pinctrl/pinmux-node.yaml
  88 +        additionalProperties: false
  89 +
  90 +        properties:
  91 +          pinmux:
  92 +            description: |
  93 +              The list of GPIOs and their mux settings that properties in the
  94 +              node apply to. This should be set using the GPIOMUX or PINMUX
  95 +              macros.
  96 +
  97 +          bias-disable: true
  98 +
  99 +          bias-pull-up:
 100 +            type: boolean
 101 +
 102 +          bias-pull-down:
 103 +            type: boolean
 104 +
 105 +          drive-strength:
 106 +            enum: [ 2, 4, 8, 12 ]
 107 +
 108 +          input-enable: true
 109 +
 110 +          input-disable: true
 111 +
 112 +          input-schmitt-enable: true
 113 +
 114 +          input-schmitt-disable: true
 115 +
 116 +          slew-rate:
 117 +            maximum: 1
 118 +
 119 +required:
 120 +  - compatible
 121 +  - reg
 122 +  - clocks
 123 +  - interrupts
 124 +  - interrupt-controller
 125 +  - '#interrupt-cells'
 126 +  - gpio-controller
 127 +  - '#gpio-cells'
 128 +
 129 +additionalProperties: false
 130 +
 131 +examples:
 132 +  - |
 133 +    pinctrl@13040000 {
 134 +        compatible = "starfive,jh7110-sys-pinctrl";
 135 +        reg = <0x13040000 0x10000>;
 136 +        clocks = <&syscrg 112>;
 137 +        resets = <&syscrg 2>;
 138 +        interrupts = <86>;
 139 +        interrupt-controller;
 140 +        #interrupt-cells = <2>;
 141 +        gpio-controller;
 142 +        #gpio-cells = <2>;
 143 +
 144 +        uart0-0 {
 145 +            tx-pins {
 146 +                pinmux = <0xff140005>;
 147 +                bias-disable;
 148 +                drive-strength = <12>;
 149 +                input-disable;
 150 +                input-schmitt-disable;
 151 +                slew-rate = <0>;
 152 +            };
 153 +
 154 +            rx-pins {
 155 +                pinmux = <0x0E000406>;
 156 +                bias-pull-up;
 157 +                drive-strength = <2>;
 158 +                input-enable;
 159 +                input-schmitt-enable;
 160 +                slew-rate = <0>;
 161 +            };
 162 +        };
 163 +    };
 164 +
 165 +...
 166 --- a/MAINTAINERS
 167 +++ b/MAINTAINERS
 168 @@ -19665,13 +19665,15 @@ F:    Documentation/devicetree/bindings/clo
 169  F:     drivers/clk/starfive/clk-starfive-jh71*
 170  F:     include/dt-bindings/clock/starfive?jh71*.h
 171
 172 -STARFIVE JH7100 PINCTRL DRIVER
 173 +STARFIVE JH71X0 PINCTRL DRIVERS
 174  M:     Emil Renner Berthing <kernel@esmil.dk>
 175 +M:     Jianlong Huang <jianlong.huang@starfivetech.com>
 176  L:     linux-gpio@vger.kernel.org
 177  S:     Maintained
 178 -F:     Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
 179 +F:     Documentation/devicetree/bindings/pinctrl/starfive,jh71*.yaml
 180  F:     drivers/pinctrl/starfive/
 181  F:     include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
 182 +F:     include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
 183
 184  STARFIVE JH71X0 RESET CONTROLLER DRIVERS
 185  M:     Emil Renner Berthing <kernel@esmil.dk>
 186 --- /dev/null
 187 +++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
 188 @@ -0,0 +1,115 @@
 189 +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
 190 +/*
 191 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
 192 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
 193 + */
 194 +
 195 +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
 196 +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
 197 +
 198 +/* sys_iomux pins */
 199 +#define        PAD_GPIO0               0
 200 +#define        PAD_GPIO1               1
 201 +#define        PAD_GPIO2               2
 202 +#define        PAD_GPIO3               3
 203 +#define        PAD_GPIO4               4
 204 +#define        PAD_GPIO5               5
 205 +#define        PAD_GPIO6               6
 206 +#define        PAD_GPIO7               7
 207 +#define        PAD_GPIO8               8
 208 +#define        PAD_GPIO9               9
 209 +#define        PAD_GPIO10              10
 210 +#define        PAD_GPIO11              11
 211 +#define        PAD_GPIO12              12
 212 +#define        PAD_GPIO13              13
 213 +#define        PAD_GPIO14              14
 214 +#define        PAD_GPIO15              15
 215 +#define        PAD_GPIO16              16
 216 +#define        PAD_GPIO17              17
 217 +#define        PAD_GPIO18              18
 218 +#define        PAD_GPIO19              19
 219 +#define        PAD_GPIO20              20
 220 +#define        PAD_GPIO21              21
 221 +#define        PAD_GPIO22              22
 222 +#define        PAD_GPIO23              23
 223 +#define        PAD_GPIO24              24
 224 +#define        PAD_GPIO25              25
 225 +#define        PAD_GPIO26              26
 226 +#define        PAD_GPIO27              27
 227 +#define        PAD_GPIO28              28
 228 +#define        PAD_GPIO29              29
 229 +#define        PAD_GPIO30              30
 230 +#define        PAD_GPIO31              31
 231 +#define        PAD_GPIO32              32
 232 +#define        PAD_GPIO33              33
 233 +#define        PAD_GPIO34              34
 234 +#define        PAD_GPIO35              35
 235 +#define        PAD_GPIO36              36
 236 +#define        PAD_GPIO37              37
 237 +#define        PAD_GPIO38              38
 238 +#define        PAD_GPIO39              39
 239 +#define        PAD_GPIO40              40
 240 +#define        PAD_GPIO41              41
 241 +#define        PAD_GPIO42              42
 242 +#define        PAD_GPIO43              43
 243 +#define        PAD_GPIO44              44
 244 +#define        PAD_GPIO45              45
 245 +#define        PAD_GPIO46              46
 246 +#define        PAD_GPIO47              47
 247 +#define        PAD_GPIO48              48
 248 +#define        PAD_GPIO49              49
 249 +#define        PAD_GPIO50              50
 250 +#define        PAD_GPIO51              51
 251 +#define        PAD_GPIO52              52
 252 +#define        PAD_GPIO53              53
 253 +#define        PAD_GPIO54              54
 254 +#define        PAD_GPIO55              55
 255 +#define        PAD_GPIO56              56
 256 +#define        PAD_GPIO57              57
 257 +#define        PAD_GPIO58              58
 258 +#define        PAD_GPIO59              59
 259 +#define        PAD_GPIO60              60
 260 +#define        PAD_GPIO61              61
 261 +#define        PAD_GPIO62              62
 262 +#define        PAD_GPIO63              63
 263 +#define        PAD_SD0_CLK             64
 264 +#define        PAD_SD0_CMD             65
 265 +#define        PAD_SD0_DATA0           66
 266 +#define        PAD_SD0_DATA1           67
 267 +#define        PAD_SD0_DATA2           68
 268 +#define        PAD_SD0_DATA3           69
 269 +#define        PAD_SD0_DATA4           70
 270 +#define        PAD_SD0_DATA5           71
 271 +#define        PAD_SD0_DATA6           72
 272 +#define        PAD_SD0_DATA7           73
 273 +#define        PAD_SD0_STRB            74
 274 +#define        PAD_GMAC1_MDC           75
 275 +#define        PAD_GMAC1_MDIO          76
 276 +#define        PAD_GMAC1_RXD0          77
 277 +#define        PAD_GMAC1_RXD1          78
 278 +#define        PAD_GMAC1_RXD2          79
 279 +#define        PAD_GMAC1_RXD3          80
 280 +#define        PAD_GMAC1_RXDV          81
 281 +#define        PAD_GMAC1_RXC           82
 282 +#define        PAD_GMAC1_TXD0          83
 283 +#define        PAD_GMAC1_TXD1          84
 284 +#define        PAD_GMAC1_TXD2          85
 285 +#define        PAD_GMAC1_TXD3          86
 286 +#define        PAD_GMAC1_TXEN          87
 287 +#define        PAD_GMAC1_TXC           88
 288 +#define        PAD_QSPI_SCLK           89
 289 +#define        PAD_QSPI_CS0            90
 290 +#define        PAD_QSPI_DATA0          91
 291 +#define        PAD_QSPI_DATA1          92
 292 +#define        PAD_QSPI_DATA2          93
 293 +#define        PAD_QSPI_DATA3          94
 294 +
 295 +#define GPOUT_LOW              0
 296 +#define GPOUT_HIGH             1
 297 +
 298 +#define GPOEN_ENABLE           0
 299 +#define GPOEN_DISABLE          1
 300 +
 301 +#define GPI_NONE               255
 302 +
 303 +#endif