qualcommax: convert qca807x PHY to PHY package implementation
[openwrt/staging/robimarko.git] / target / linux / qualcommax / files / arch / arm64 / boot / dts / qcom / ipq8074-rax120v2.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 /dts-v1/;
4
5 #include "ipq8074.dtsi"
6 #include "ipq8074-ess.dtsi"
7 #include "ipq8074-hk-cpu.dtsi"
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11
12 / {
13 model = "Netgear RAX120v2";
14 compatible = "netgear,rax120v2", "qcom,ipq8074";
15
16 aliases {
17 serial0 = &blsp1_uart5;
18
19 led-running = &led_system_white;
20 led-upgrade = &led_system_white;
21 led-internet = &led_wan_white;
22 label-mac-device = &dp1;
23 };
24
25 chosen {
26 stdout-path = "serial0:115200n8";
27 bootargs-append = " ubi.mtd=rootfs root=/dev/ubiblock0_0";
28 };
29
30 keys {
31 compatible = "gpio-keys";
32
33 rfkill {
34 label = "rfkill";
35 gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
36 linux,code = <KEY_RFKILL>;
37 };
38
39 wps {
40 label = "wps";
41 gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_WPS_BUTTON>;
43 };
44
45 reset {
46 label = "reset";
47 gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_RESTART>;
49 };
50 };
51
52 led_spi {
53 compatible = "spi-gpio";
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 sck-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
58 mosi-gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
59
60 led_gpio: led_gpio@0 {
61 compatible = "fairchild,74hc595";
62 reg = <0>;
63 gpio-controller;
64 #gpio-cells = <2>;
65 registers-number = <2>;
66 enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
67 spi-max-frequency = <1000000>;
68 };
69 };
70
71 leds {
72 compatible = "gpio-leds";
73
74 led_system_white: system-white {
75 gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
76 color = <LED_COLOR_ID_WHITE>;
77 };
78
79 led_24g_white {
80 gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
81 color = <LED_COLOR_ID_WHITE>;
82 linux,default-trigger = "phy1radio";
83 };
84
85 led_5g_white {
86 gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
87 color = <LED_COLOR_ID_WHITE>;
88 linux,default-trigger = "phy0radio";
89 };
90
91 led_usb1_white {
92 gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
93 color = <LED_COLOR_ID_WHITE>;
94 };
95
96 led_usb2_white {
97 gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
98 color = <LED_COLOR_ID_WHITE>;
99 };
100
101 led_wan_white: wan-white {
102 gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
103 color = <LED_COLOR_ID_WHITE>;
104 };
105
106 led_aqr_green {
107 gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
108 color = <LED_COLOR_ID_GREEN>;
109 };
110
111 led_aqr_red {
112 gpios = <&led_gpio 10 GPIO_ACTIVE_LOW>;
113 color = <LED_COLOR_ID_RED>;
114 };
115
116 led_aqr_white {
117 gpios = <&led_gpio 11 GPIO_ACTIVE_LOW>;
118 color = <LED_COLOR_ID_WHITE>;
119 };
120
121 led_wps_white {
122 gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
123 color = <LED_COLOR_ID_WHITE>;
124 };
125 };
126 };
127
128 &tlmm {
129 mdio_pins: mdio-pins {
130 mdc {
131 pins = "gpio68";
132 function = "mdc";
133 drive-strength = <8>;
134 bias-pull-up;
135 };
136
137 mdio {
138 pins = "gpio69";
139 function = "mdio";
140 drive-strength = <8>;
141 bias-pull-up;
142 };
143 };
144 };
145
146 &mdio {
147 status = "okay";
148
149 pinctrl-0 = <&mdio_pins>;
150 pinctrl-names = "default";
151 reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
152
153 ethernet-phy-package@0 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 reg = <0>;
157
158 compatible = "qcom,qca8075-package";
159
160 qca8075_0: ethernet-phy@0 {
161 compatible = "ethernet-phy-ieee802.3-c22";
162 reg = <0>;
163 };
164
165 qca8075_1: ethernet-phy@1 {
166 compatible = "ethernet-phy-ieee802.3-c22";
167 reg = <1>;
168 };
169
170 qca8075_2: ethernet-phy@2 {
171 compatible = "ethernet-phy-ieee802.3-c22";
172 reg = <2>;
173 };
174
175 qca8075_3: ethernet-phy@3 {
176 compatible = "ethernet-phy-ieee802.3-c22";
177 reg = <3>;
178 };
179
180 qca8075_4: ethernet-phy@4 {
181 compatible = "ethernet-phy-ieee802.3-c22";
182 reg = <4>;
183 };
184 };
185
186 aqr111b0: ethernet-phy@7 {
187 compatible ="ethernet-phy-ieee802.3-c45";
188 reg = <7>;
189 reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
190 };
191 };
192
193 &switch {
194 status = "okay";
195
196 switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>; /* lan port bitmap */
197 switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
198 switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
199 switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
200
201 qcom,port_phyinfo {
202 port@1 {
203 port_id = <1>;
204 phy_address = <0>;
205 };
206 port@2 {
207 port_id = <2>;
208 phy_address = <1>;
209 };
210 port@3 {
211 port_id = <3>;
212 phy_address = <2>;
213 };
214 port@4 {
215 port_id = <4>;
216 phy_address = <3>;
217 };
218 port@5 {
219 port_id = <5>;
220 phy_address = <4>;
221 };
222 port@6 {
223 port_id = <6>;
224 phy_address = <7>;
225 compatible = "ethernet-phy-ieee802.3-c45";
226 ethernet-phy-ieee802.3-c45;
227 };
228 };
229 };
230
231 &edma {
232 status = "okay";
233 };
234
235 &dp1 {
236 status = "okay";
237 phy-handle = <&qca8075_0>;
238 label = "lan4";
239 nvmem-cells = <&macaddr_dp1>;
240 nvmem-cell-names = "mac-address";
241 };
242
243 &dp2 {
244 status = "okay";
245 phy-handle = <&qca8075_1>;
246 label = "lan3";
247 nvmem-cells = <&macaddr_dp2>;
248 nvmem-cell-names = "mac-address";
249 };
250
251 &dp3 {
252 status = "okay";
253 phy-handle = <&qca8075_2>;
254 label = "lan2";
255 nvmem-cells = <&macaddr_dp3>;
256 nvmem-cell-names = "mac-address";
257 };
258
259 &dp4 {
260 status = "okay";
261 phy-handle = <&qca8075_3>;
262 label = "lan1";
263 nvmem-cells = <&macaddr_dp4>;
264 nvmem-cell-names = "mac-address";
265 };
266
267 &dp5 {
268 status = "okay";
269 phy-handle = <&qca8075_4>;
270 label = "wan";
271 nvmem-cells = <&macaddr_dp5>;
272 nvmem-cell-names = "mac-address";
273 };
274
275 &dp6_syn {
276 status = "okay";
277 phy-handle = <&aqr111b0>;
278 label = "lan5";
279 nvmem-cells = <&macaddr_dp6_syn>;
280 nvmem-cell-names = "mac-address";
281 };
282
283 &blsp1_uart5 {
284 status = "okay";
285 };
286
287 &blsp1_i2c2 {
288 status = "okay";
289
290 g761@3e {
291 compatible = "gmt,g763";
292 reg = <0x3e>;
293 clocks =<&sleep_clk>;
294 fan_gear_mode = <0>;
295 fan_start = <1>;
296 pwm_polarity = <0>;
297 };
298 };
299
300 &qpic_bam {
301 status = "okay";
302 };
303
304 &qpic_nand {
305 status = "okay";
306
307 nand@0 {
308 reg = <0>;
309 nand-ecc-strength = <4>;
310 nand-ecc-step-size = <512>;
311 nand-bus-width = <8>;
312
313 partitions {
314 compatible = "fixed-partitions";
315 #address-cells = <1>;
316 #size-cells = <1>;
317
318 partition@0 {
319 label = "0:sbl1";
320 reg = <0x00 0x100000>;
321 read-only;
322 };
323
324 partition@100000 {
325 label = "0:mibib";
326 reg = <0x100000 0x100000>;
327 read-only;
328 };
329
330 partition@200000 {
331 label = "0:bootconfig";
332 reg = <0x200000 0x80000>;
333 read-only;
334 };
335
336 partition@280000 {
337 label = "0:bootconfig_1";
338 reg = <0x280000 0x80000>;
339 read-only;
340 };
341
342 partition@300000 {
343 label = "0:qsee";
344 reg = <0x300000 0x300000>;
345 read-only;
346 };
347
348 partition@600000 {
349 label = "0:qsee_1";
350 reg = <0x600000 0x300000>;
351 read-only;
352 };
353
354 partition@900000 {
355 label = "0:devcfg";
356 reg = <0x900000 0x80000>;
357 read-only;
358 };
359
360 partition@980000 {
361 label = "0:devcfg_1";
362 reg = <0x980000 0x80000>;
363 read-only;
364 };
365
366 partition@a00000 {
367 label = "0:apdp";
368 reg = <0xa00000 0x80000>;
369 read-only;
370 };
371
372 partition@a80000 {
373 label = "0:apdp_1";
374 reg = <0xa80000 0x80000>;
375 read-only;
376 };
377
378 partition@b00000 {
379 label = "0:rpm";
380 reg = <0xb00000 0x80000>;
381 read-only;
382 };
383
384 partition@b80000 {
385 label = "0:rpm_1";
386 reg = <0xb80000 0x80000>;
387 read-only;
388 };
389
390 partition@c00000 {
391 label = "0:cdt";
392 reg = <0xc00000 0x80000>;
393 read-only;
394 };
395
396 partition@c80000 {
397 label = "0:cdt_1";
398 reg = <0xc80000 0x80000>;
399 read-only;
400 };
401
402 partition@d00000 {
403 label = "0:appsblenv";
404 reg = <0xd00000 0x80000>;
405 };
406
407 partition@d80000 {
408 label = "0:appsbl";
409 reg = <0xd80000 0x100000>;
410 read-only;
411 };
412
413 partition@e80000 {
414 label = "0:appsbl_1";
415 reg = <0xe80000 0x100000>;
416 read-only;
417 };
418
419 partition@f80000 {
420 label = "0:art";
421 reg = <0xf80000 0x80000>;
422 read-only;
423 };
424
425 partition@1000000 {
426 label = "0:art.bak";
427 reg = <0x1000000 0x0080000>;
428 read-only;
429 };
430
431 partition@1080000 {
432 label = "config";
433 reg = <0x1080000 0x0100000>;
434 read-only;
435 };
436
437 partition@1180000 {
438 label = "boarddata1";
439 reg = <0x1180000 0x0100000>;
440 read-only;
441
442 nvmem-layout {
443 compatible = "fixed-layout";
444 #address-cells = <1>;
445 #size-cells = <1>;
446
447 macaddr_dp1: macaddr@0 {
448 reg = <0x0 0x6>;
449 };
450
451 macaddr_dp2: macaddr@1 {
452 reg = <0x6 0x6>;
453 };
454
455 macaddr_dp3: macaddr@2 {
456 reg = <0xc 0x6>;
457 };
458
459 macaddr_dp4: macaddr@3 {
460 reg = <0x12 0x6>;
461 };
462
463 macaddr_dp5: macaddr@4 {
464 reg = <0x18 0x6>;
465 };
466
467 macaddr_dp6_syn: macaddr@5 {
468 reg = <0x1e 0x6>;
469 };
470 };
471 };
472
473 partition@1280000 {
474 label = "boarddata2";
475 reg = <0x1280000 0x0100000>;
476 read-only;
477 };
478
479 partition@1380000 {
480 label = "pot";
481 reg = <0x1380000 0x0100000>;
482 read-only;
483 };
484
485 partition@1480000 {
486 label = "dnidata";
487 reg = <0x1480000 0x0500000>;
488 read-only;
489 };
490
491 partition@1980000 {
492 label = "kernel";
493 reg = <0x1980000 0x1d00000>;
494 };
495
496 partition@7e00000 {
497 label = "ethphyfw";
498 reg = <0x7e00000 0x80000>;
499 };
500
501 partition@e8800000 {
502 label = "rootfs";
503 reg = <0xe880000 0x11780000>;
504 };
505 };
506 };
507 };
508
509 &qusb_phy_0 {
510 status = "okay";
511 };
512
513 &qusb_phy_1 {
514 status = "okay";
515 };
516
517 &ssphy_0 {
518 status = "okay";
519 };
520
521 &ssphy_1 {
522 status = "okay";
523 };
524
525 &usb_0 {
526 status = "okay";
527 };
528
529 &usb_1 {
530 status = "okay";
531 };
532
533 &wifi{
534 status = "okay";
535
536 qcom,ath11k-calibration-variant = "Netgear-RAX120v2";
537 };
538
539 &cryptobam {
540 status = "okay";
541 };
542
543 &crypto {
544 status = "okay";
545 };
546
547 &prng {
548 status = "okay";
549 };