mediatek: convert to nvmem-layout
[openwrt/staging/hauke.git] / target / linux / mediatek / dts / mt7981b-zyxel-nwa50ax-pro.dts
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /dts-v1/;
3
4 #include "mt7981.dtsi"
5
6 / {
7 model = "ZyXEL NWA50AX Pro";
8 compatible = "zyxel,nwa50ax-pro", "mediatek,mt7981";
9
10 aliases {
11 led-boot = &led_green;
12 led-failsafe = &led_red;
13 led-running = &led_green;
14 led-upgrade = &led_red;
15 serial0 = &uart0;
16 label-mac-device = &gmac1;
17 };
18
19 chosen {
20 stdout-path = "serial0:115200n8";
21 };
22
23 gpio-keys {
24 compatible = "gpio-keys";
25
26 reset {
27 label = "reset";
28 linux,code = <KEY_RESTART>;
29 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
30 };
31 };
32
33 leds {
34 compatible = "gpio-leds";
35
36 led_green: led@0 {
37 label = "green:system";
38 gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
39 };
40
41 led@1 {
42 label = "blue:system";
43 gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
44 };
45
46 led_red: led@2 {
47 label = "red:system";
48 gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
49 };
50 };
51 };
52
53 &uart0 {
54 status = "okay";
55 };
56
57 &watchdog {
58 status = "okay";
59 };
60
61 &eth {
62 pinctrl-names = "default";
63 pinctrl-0 = <&mdio_pins>;
64
65 status = "okay";
66
67 gmac1: mac@1 {
68 compatible = "mediatek,eth-mac";
69 reg = <1>;
70 phy-mode = "2500base-x";
71
72 phy-handle = <&phy0>;
73
74 nvmem-cells = <&macaddr_mrd_1fff8>;
75 nvmem-cell-names = "mac-address";
76 };
77 };
78
79 &mdio_bus {
80 reset-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
81 reset-delay-us = <1500000>;
82 reset-post-delay-us = <1000000>;
83
84 phy0: ethernet-phy@5 {
85 reg = <5>;
86 compatible = "ethernet-phy-ieee802.3-c45";
87
88 /* LED0: Amber ; LED1: nc ; LED2: nc ; LED3: Green */
89 mxl,led-config = <0x3b0 0x0 0x0 0x3c0>;
90 };
91 };
92
93 &spi0 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&spi0_flash_pins>;
96 status = "okay";
97
98 spi_nand: flash@0 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "spi-nand";
102 reg = <0>;
103 spi-max-frequency = <52000000>;
104
105 spi-cal-enable;
106 spi-cal-mode = "read-data";
107 spi-cal-datalen = <7>;
108 spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
109 spi-cal-addrlen = <5>;
110 spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
111
112 spi-tx-bus-width = <4>;
113 spi-rx-bus-width = <4>;
114 mediatek,nmbm;
115 mediatek,bmt-max-ratio = <1>;
116 mediatek,bmt-max-reserved-blocks = <64>;
117
118 partitions {
119 compatible = "fixed-partitions";
120 #address-cells = <1>;
121 #size-cells = <1>;
122
123 partition@0 {
124 label = "BL2";
125 reg = <0x00000 0x0100000>;
126 read-only;
127 };
128
129 partition@100000 {
130 label = "u-boot-env";
131 reg = <0x0100000 0x0080000>;
132 };
133
134 factory: partition@180000 {
135 label = "Factory";
136 reg = <0x180000 0x0200000>;
137 read-only;
138
139 nvmem-layout {
140 compatible = "fixed-layout";
141 #address-cells = <1>;
142 #size-cells = <1>;
143
144 macaddr: macaddr@a {
145 reg = <0xa 0x6>;
146 };
147 };
148 };
149
150 partition@380000 {
151 label = "FIP";
152 reg = <0x380000 0x0200000>;
153 read-only;
154 };
155
156 partition@580000 {
157 label = "ubi";
158 reg = <0x580000 0x3200000>;
159 };
160
161 partition@3780000 {
162 label = "ubi_1";
163 reg = <0x3780000 0x3200000>;
164 read-only;
165 };
166
167 partition@6980000 {
168 label = "rootfs-data";
169 reg = <0x6980000 0x3c00000>;
170 read-only;
171 };
172
173 partition@a580000 {
174 label = "logs";
175 reg = <0xa580000 0x3a80000>;
176 read-only;
177 };
178
179 partition@e000000 {
180 label = "myzyxel";
181 reg = <0xe000000 0xf00000>;
182 read-only;
183 };
184
185 partition@ef00000 {
186 label = "bootconfig";
187 reg = <0xef00000 0x80000>;
188 };
189
190 partition@ef80000 {
191 label = "mrd";
192 reg = <0xef80000 0x80000>;
193 read-only;
194
195 nvmem-layout {
196 compatible = "fixed-layout";
197 #address-cells = <1>;
198 #size-cells = <1>;
199
200 macaddr_mrd_1fff8: macaddr@1fff8 {
201 reg = <0x1fff8 0x6>;
202 };
203 };
204 };
205 };
206 };
207 };
208
209 &pio {
210 spi0_flash_pins: spi0-pins {
211 mux {
212 function = "spi";
213 groups = "spi0", "spi0_wp_hold";
214 };
215 };
216
217 pwm_pins: pwm0-pins {
218 mux {
219 function = "pwm";
220 groups = "pwm0_1";
221 };
222 };
223 };
224
225 &wifi {
226 status = "okay";
227
228 mediatek,mtd-eeprom = <&factory 0x0>;
229 };