target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts

   1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 #include "mt7622.dtsi"
   8 #include "mt6380.dtsi"
   9
  10 / {
  11         model = "TOTOLINK A8000RU";
  12         compatible = "totolink,a8000ru", "mediatek,mt7622";
  13
  14         aliases {
  15                 label-mac-device = &gmac0;
  16                 led-boot = &led_status;
  17                 led-failsafe = &led_status;
  18                 led-running = &led_status;
  19                 led-upgrade = &led_status;
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 reset {
  44                         label = "reset";
  45                         linux,code = <KEY_RESTART>;
  46                         gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  47                 };
  48
  49                 wps {
  50                         label = "wps";
  51                         linux,code = <KEY_WPS_BUTTON>;
  52                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  53                 };
  54         };
  55
  56         gpio-leds {
  57                 compatible = "gpio-leds";
  58
  59                 led_status: status_red {
  60                         label = "red:status";
  61                         gpios = <&pio 81 GPIO_ACTIVE_LOW>;
  62                         default-state = "on";
  63                 };
  64         };
  65
  66         reg_1p8v: regulator-1p8v {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "fixed-1.8V";
  69                 regulator-min-microvolt = <1800000>;
  70                 regulator-max-microvolt = <1800000>;
  71                 regulator-always-on;
  72         };
  73
  74         reg_3p3v: regulator-3p3v {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "fixed-3.3V";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 regulator-boot-on;
  80                 regulator-always-on;
  81         };
  82
  83         reg_5v: regulator-5v {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "fixed-5V";
  86                 regulator-min-microvolt = <5000000>;
  87                 regulator-max-microvolt = <5000000>;
  88                 regulator-boot-on;
  89                 regulator-always-on;
  90         };
  91
  92         rtkgsw: rtkgsw@0 {
  93                 compatible = "mediatek,rtk-gsw";
  94                 mediatek,ethsys = <&ethsys>;
  95                 mediatek,mdio = <&mdio>;
  96                 mediatek,reset-pin = <&pio 54 0>;
  97                 status = "okay";
  98         };
  99 };
 100
 101 &pcie0 {
 102         pinctrl-names = "default";
 103         pinctrl-0 = <&pcie0_pins>;
 104         status = "okay";
 105 };
 106
 107 &slot0 {
 108         mt7615@0,0 {
 109                 reg = <0x0000 0 0 0 0>;
 110                 mediatek,mtd-eeprom = <&factory 0x5000>;
 111                 ieee80211-freq-limit = <5490000 6000000>;
 112         };
 113 };
 114
 115 &pcie1 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pcie1_pins>;
 118         status = "okay";
 119 };
 120
 121 &slot1 {
 122         mt7615@0,0 {
 123                 reg = <0x0000 0 0 0 0>;
 124                 mediatek,mtd-eeprom = <&factory 0x10000>;
 125                 ieee80211-freq-limit = <5000000 5490000>;
 126         };
 127 };
 128
 129 &pio {
 130         eth_pins: eth-pins {
 131                 mux {
 132                         function = "eth";
 133                         groups = "mdc_mdio", "rgmii_via_gmac2";
 134                 };
 135         };
 136
 137         pcie0_pins: pcie0-pins {
 138                 mux {
 139                         function = "pcie";
 140                         groups = "pcie0_pad_perst",
 141                                  "pcie0_1_waken",
 142                                  "pcie0_1_clkreq";
 143                 };
 144         };
 145
 146         pcie1_pins: pcie1-pins {
 147                 mux {
 148                         function = "pcie";
 149                         groups = "pcie1_pad_perst",
 150                                  "pcie1_0_waken",
 151                                  "pcie1_0_clkreq";
 152                 };
 153         };
 154
 155         pmic_bus_pins: pmic-bus-pins {
 156                 mux {
 157                         function = "pmic";
 158                         groups = "pmic_bus";
 159                 };
 160         };
 161
 162         /* serial NAND is shared pin with SPI-NOR */
 163         serial_nand_pins: serial-nand-pins {
 164                 mux {
 165                         function = "flash";
 166                         groups = "snfi";
 167                 };
 168         };
 169
 170         uart0_pins: uart0-pins {
 171                 mux {
 172                         function = "uart";
 173                         groups = "uart0_0_tx_rx" ;
 174                 };
 175         };
 176
 177         watchdog_pins: watchdog-pins {
 178                 mux {
 179                         function = "watchdog";
 180                         groups = "watchdog";
 181                 };
 182         };
 183
 184         epa_elna_pins: epa-elna-pins {
 185                 mux {
 186                         function = "antsel";
 187                         groups = "antsel0", "antsel1", "antsel2", "antsel3",
 188                                 "antsel4", "antsel5", "antsel6", "antsel7",
 189                                 "antsel8", "antsel9", "antsel12", "antsel13",
 190                                 "antsel14", "antsel15", "antsel16", "antsel17";
 191                 };
 192         };
 193 };
 194
 195 &eth {
 196         status = "okay";
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&eth_pins>;
 199
 200         gmac0: mac@0 {
 201                 compatible = "mediatek,eth-mac";
 202                 reg = <0>;
 203                 nvmem-cells = <&macaddr_factory_2a>;
 204                 nvmem-cell-names = "mac-address";
 205                 phy-connection-type = "2500base-x";
 206                 fixed-link {
 207                         speed = <2500>;
 208                         full-duplex;
 209                         pause;
 210                 };
 211         };
 212
 213         gmac1: mac@1 {
 214                 compatible = "mediatek,eth-mac";
 215                 reg = <1>;
 216                 phy-mode = "rgmii";
 217                 nvmem-cells = <&macaddr_factory_24>;
 218                 nvmem-cell-names = "mac-address";
 219                 fixed-link {
 220                         speed = <1000>;
 221                         full-duplex;
 222                         pause;
 223                 };
 224         };
 225
 226         mdio: mdio-bus {
 227                 #address-cells = <1>;
 228                 #size-cells = <0>;
 229         };
 230 };
 231
 232 &pwrap {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pmic_bus_pins>;
 235         status = "okay";
 236 };
 237
 238 &bch {
 239         status = "okay";
 240 };
 241
 242 &snfi {
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&serial_nand_pins>;
 245         status = "okay";
 246         flash@0 {
 247                 compatible = "spi-nand";
 248                 reg = <0>;
 249                 spi-tx-bus-width = <4>;
 250                 spi-rx-bus-width = <4>;
 251                 nand-ecc-engine = <&snfi>;
 252                 mediatek,bmt-v2;
 253
 254                 partitions {
 255                         compatible = "fixed-partitions";
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258
 259                         partition@0 {
 260                                 label = "Preloader";
 261                                 reg = <0x0 0x80000>;
 262                                 read-only;
 263                         };
 264
 265                         partition@80000 {
 266                                 label = "ATF";
 267                                 reg = <0x80000 0x40000>;
 268                                 read-only;
 269                         };
 270
 271                         partition@c0000 {
 272                                 label = "u-boot";
 273                                 reg = <0xc0000 0x80000>;
 274                                 read-only;
 275                         };
 276
 277                         partition@140000 {
 278                                 label = "u-boot-env";
 279                                 reg = <0x140000 0x80000>;
 280                                 read-only;
 281                         };
 282
 283                         factory: partition@1c0000 {
 284                                 label = "factory";
 285                                 reg = <0x1c0000 0x40000>;
 286                                 read-only;
 287
 288                                 nvmem-layout {
 289                                         compatible = "fixed-layout";
 290                                         #address-cells = <1>;
 291                                         #size-cells = <1>;
 292
 293                                         macaddr_factory_24: macaddr@24 {
 294                                                 reg = <0x24 0x6>;
 295                                         };
 296
 297                                         macaddr_factory_2a: macaddr@2a {
 298                                                 reg = <0x2a 0x6>;
 299                                         };
 300                                 };
 301                         };
 302
 303                         partition@200000 {
 304                                 label = "ubi";
 305                                 reg = <0x200000 0x6400000>;
 306                         };
 307
 308                         partition@6600000 {
 309                                 label = "User_data";
 310                                 reg = <0x6600000 0x100000>;
 311                         };
 312
 313                         /* size of this partition varies due to BMT & bad blocks. */
 314                         partition@6700000 {
 315                                 label = "reserved";
 316                                 reg = <0x6700000 0>;
 317                         };
 318                 };
 319         };
 320 };
 321
 322 &ssusb {
 323         vusb33-supply = <&reg_3p3v>;
 324         vbus-supply = <&reg_5v>;
 325         status = "okay";
 326 };
 327
 328 &u3phy {
 329         status = "okay";
 330 };
 331
 332 &uart0 {
 333         pinctrl-names = "default";
 334         pinctrl-0 = <&uart0_pins>;
 335         status = "okay";
 336 };
 337
 338 &watchdog {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&watchdog_pins>;
 341         status = "okay";
 342 };
 343
 344 &wmac {
 345         pinctrl-names = "default";
 346         pinctrl-0 = <&epa_elna_pins>;
 347         mediatek,mtd-eeprom = <&factory 0x0>;
 348         status = "okay";
 349 };