ipq806x: switch default to 6.6
[openwrt/staging/stintel.git] / target / linux / ipq806x / files-6.1 / arch / arm / boot / dts / qcom-ipq8064-wpq864.dts
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Christian Mehlis <christian@m3hlis.de>
4 * Copyright (C) 2018 Mathias Kresin <dev@kresin.me>
5 * All rights reserved.
6 */
7
8 #include "qcom-ipq8064-v1.0.dtsi"
9
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/soc/qcom,tcsr.h>
13
14 / {
15 compatible = "compex,wpq864", "qcom,ipq8064";
16 model = "Compex WPQ864";
17
18 aliases {
19 mdio-gpio0 = &mdio0;
20 ethernet0 = &gmac1;
21 ethernet1 = &gmac0;
22
23 led-boot = &led_pass;
24 led-failsafe = &led_fail;
25 led-running = &led_pass;
26 led-upgrade = &led_pass;
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 pinctrl-0 = <&led_pins>;
33 pinctrl-names = "default";
34
35 rss4 {
36 label = "green:rss4";
37 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
38 };
39
40 rss3 {
41 label = "green:rss3";
42 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
43 default-state = "keep";
44 };
45
46 rss2 {
47 label = "orange:rss2";
48 gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
49 };
50
51 rss1 {
52 label = "red:rss1";
53 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
54 };
55
56 led_pass: pass {
57 label = "green:pass";
58 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
59 };
60
61 led_fail: fail {
62 label = "green:fail";
63 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
64 };
65
66 usb {
67 function = LED_FUNCTION_USB;
68 color = <LED_COLOR_ID_GREEN>;
69 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
70 };
71
72 usb-pcie {
73 label = "green:usb-pcie";
74 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
75 };
76 };
77
78 keys {
79 compatible = "gpio-keys";
80
81 pinctrl-0 = <&button_pins>;
82 pinctrl-names = "default";
83
84 reset {
85 label = "reset";
86 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
87 linux,code = <KEY_RESTART>;
88 debounce-interval = <60>;
89 wakeup-source;
90 };
91 };
92
93 beeper {
94 compatible = "gpio-beeper";
95
96 pinctrl-0 = <&beeper_pins>;
97 pinctrl-names = "default";
98
99 gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
100 };
101 };
102
103 &rpm {
104 pinctrl-0 = <&rpm_pins>;
105 pinctrl-names = "default";
106 };
107
108 &nand {
109 status = "okay";
110
111 pinctrl-0 = <&nand_pins>;
112 pinctrl-names = "default";
113
114 mt29f2g08abbeah4@0 {
115 compatible = "qcom,nandcs";
116
117 reg = <0>;
118
119 nand-ecc-strength = <4>;
120 nand-bus-width = <8>;
121 nand-ecc-step-size = <512>;
122
123 nand-is-boot-medium;
124 qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
125
126 partitions {
127 compatible = "fixed-partitions";
128 #address-cells = <1>;
129 #size-cells = <1>;
130
131 partition@0 {
132 label = "0:SBL1";
133 reg = <0x0000000 0x0040000>;
134 read-only;
135 };
136
137 partition@40000 {
138 label = "0:MIBIB";
139 reg = <0x0040000 0x0140000>;
140 read-only;
141 };
142
143 partition@180000 {
144 label = "0:SBL2";
145 reg = <0x0180000 0x0140000>;
146 read-only;
147 };
148
149 partition@2c0000 {
150 label = "0:SBL3";
151 reg = <0x02c0000 0x0280000>;
152 read-only;
153 };
154
155 partition@540000 {
156 label = "0:DDRCONFIG";
157 reg = <0x0540000 0x0120000>;
158 read-only;
159 };
160
161 partition@660000 {
162 label = "0:SSD";
163 reg = <0x0660000 0x0120000>;
164 read-only;
165 };
166
167 partition@780000 {
168 label = "0:TZ";
169 reg = <0x0780000 0x0280000>;
170 read-only;
171 };
172
173 partition@a00000 {
174 label = "0:RPM";
175 reg = <0x0a00000 0x0280000>;
176 read-only;
177 };
178
179 partition@c80000 {
180 label = "0:APPSBL";
181 reg = <0x0c80000 0x0500000>;
182 read-only;
183 };
184
185 partition@1180000 {
186 label = "0:APPSBLENV";
187 reg = <0x1180000 0x0080000>;
188 };
189
190 partition@1200000 {
191 label = "0:ART";
192 reg = <0x1200000 0x0140000>;
193 };
194
195 partition@1340000 {
196 label = "ubi";
197 reg = <0x1340000 0x4000000>;
198 };
199
200 partition@5340000 {
201 label = "0:BOOTCONFIG";
202 reg = <0x5340000 0x0060000>;
203 };
204
205 partition@53a0000 {
206 label = "0:SBL2_1";
207 reg = <0x53a0000 0x0140000>;
208 read-only;
209 };
210
211 partition@54e0000 {
212 label = "0:SBL3_1";
213 reg = <0x54e0000 0x0280000>;
214 read-only;
215 };
216
217 partition@5760000 {
218 label = "0:DDRCONFIG_1";
219 reg = <0x5760000 0x0120000>;
220 read-only;
221 };
222
223 partition@5880000 {
224 label = "0:SSD_1";
225 reg = <0x5880000 0x0120000>;
226 read-only;
227 };
228
229 partition@59a0000 {
230 label = "0:TZ_1";
231 reg = <0x59a0000 0x0280000>;
232 read-only;
233 };
234
235 partition@5c20000 {
236 label = "0:RPM_1";
237 reg = <0x5c20000 0x0280000>;
238 read-only;
239 };
240
241 partition@5ea0000 {
242 label = "0:BOOTCONFIG1";
243 reg = <0x5ea0000 0x0060000>;
244 };
245
246 partition@5f00000 {
247 label = "0:APPSBL_1";
248 reg = <0x5f00000 0x0500000>;
249 read-only;
250 };
251
252 partition@6400000 {
253 label = "ubi_1";
254 reg = <0x6400000 0x4000000>;
255 };
256
257 partition@a400000 {
258 label = "unused";
259 reg = <0xa400000 0x5c00000>;
260 };
261 };
262 };
263 };
264
265 &adm_dma {
266 status = "okay";
267 };
268
269 &mdio0 {
270 status = "okay";
271
272 pinctrl-0 = <&mdio0_pins>;
273 pinctrl-names = "default";
274
275 switch@10 {
276 compatible = "qca,qca8337";
277 #address-cells = <1>;
278 #size-cells = <0>;
279 reg = <0x10>;
280
281 ports {
282 #address-cells = <1>;
283 #size-cells = <0>;
284
285 port@0 {
286 reg = <0>;
287 label = "cpu";
288 ethernet = <&gmac1>;
289 phy-mode = "rgmii";
290 tx-internal-delay-ps = <1000>;
291 rx-internal-delay-ps = <1000>;
292
293 fixed-link {
294 speed = <1000>;
295 full-duplex;
296 };
297 };
298
299 port@1 {
300 reg = <1>;
301 label = "lan1";
302 phy-mode = "internal";
303 phy-handle = <&phy_port1>;
304 };
305
306 port@2 {
307 reg = <2>;
308 label = "lan2";
309 phy-mode = "internal";
310 phy-handle = <&phy_port2>;
311 };
312
313 port@3 {
314 reg = <3>;
315 label = "lan3";
316 phy-mode = "internal";
317 phy-handle = <&phy_port3>;
318 };
319
320 port@4 {
321 reg = <4>;
322 label = "lan4";
323 phy-mode = "internal";
324 phy-handle = <&phy_port4>;
325 };
326
327 port@5 {
328 reg = <5>;
329 label = "wan";
330 phy-mode = "internal";
331 phy-handle = <&phy_port5>;
332 };
333
334 port@6 {
335 reg = <6>;
336 label = "cpu";
337 ethernet = <&gmac2>;
338 phy-mode = "sgmii";
339 qca,sgmii-enable-pll;
340
341 fixed-link {
342 speed = <1000>;
343 full-duplex;
344 };
345 };
346 };
347
348 mdio {
349 #address-cells = <1>;
350 #size-cells = <0>;
351
352 phy_port1: phy@0 {
353 reg = <0>;
354 };
355
356 phy_port2: phy@1 {
357 reg = <1>;
358 };
359
360 phy_port3: phy@2 {
361 reg = <2>;
362 };
363
364 phy_port4: phy@3 {
365 reg = <3>;
366 };
367
368 phy_port5: phy@4 {
369 reg = <4>;
370 };
371 };
372 };
373 };
374
375 &gmac1 {
376 status = "okay";
377
378 pinctrl-0 = <&rgmii2_pins>;
379 pinctrl-names = "default";
380
381 phy-mode = "rgmii";
382 qcom,id = <1>;
383
384 fixed-link {
385 speed = <1000>;
386 full-duplex;
387 };
388 };
389
390 &gmac2 {
391 status = "okay";
392
393 phy-mode = "sgmii";
394 qcom,id = <2>;
395
396 fixed-link {
397 speed = <1000>;
398 full-duplex;
399 };
400 };
401
402 &gsbi4_serial {
403 pinctrl-0 = <&uart0_pins>;
404 pinctrl-names = "default";
405 };
406
407 &flash {
408 compatible = "jedec,spi-nor";
409 };
410
411 &sata_phy {
412 status = "disabled";
413 };
414
415 &sata {
416 status = "disabled";
417 };
418
419 &hs_phy_0 {
420 status = "okay";
421 };
422
423 &ss_phy_0 {
424 status = "okay";
425
426 rx_eq = <2>;
427 tx_deamp_3_5db = <32>;
428 mpll = <160>;
429 };
430
431 &usb3_0 {
432 status = "okay";
433 };
434
435 &hs_phy_1 {
436 status = "okay";
437 };
438
439 &ss_phy_1 {
440 status = "okay";
441
442 rx_eq = <2>;
443 tx_deamp_3_5db = <32>;
444 mpll = <160>;
445 };
446
447 &usb3_1 {
448 status = "okay";
449 };
450
451 &pcie0 {
452 status = "okay";
453
454 /delete-property/ pinctrl-0;
455 /delete-property/ pinctrl-names;
456 /delete-property/ perst-gpios;
457 };
458
459 &pcie1 {
460 status = "okay";
461 };
462
463 &pcie2 {
464 status = "okay";
465
466 /delete-property/ pinctrl-0;
467 /delete-property/ pinctrl-names;
468 /delete-property/ perst-gpios;
469 };
470
471 &qcom_pinmux {
472 pinctrl-names = "default";
473 pinctrl-0 = <&state_default>;
474
475 state_default: pinctrl0 {
476 pcie0_pcie2_perst {
477 pins = "gpio3";
478 function = "gpio";
479 drive-strength = <2>;
480 bias-disable;
481 output-high;
482 };
483 };
484
485 led_pins: led_pins {
486 mux {
487 pins = "gpio7", "gpio8", "gpio9", "gpio22",
488 "gpio23", "gpio24", "gpio25", "gpio53";
489 function = "gpio";
490 drive-strength = <2>;
491 bias-pull-up;
492 };
493 };
494
495 button_pins: button_pins {
496 mux {
497 pins = "gpio54";
498 function = "gpio";
499 drive-strength = <2>;
500 bias-pull-up;
501 };
502 };
503
504 beeper_pins: beeper_pins {
505 mux {
506 pins = "gpio55";
507 function = "gpio";
508 drive-strength = <2>;
509 bias-pull-up;
510 };
511 };
512
513 rpm_pins: rpm_pins {
514 mux {
515 pins = "gpio12", "gpio13";
516 function = "gsbi4";
517 drive-strength = <10>;
518 bias-disable;
519 };
520 };
521
522 uart0_pins: uart0_pins {
523 mux {
524 pins = "gpio10", "gpio11";
525 function = "gsbi4";
526 drive-strength = <10>;
527 bias-disable;
528 };
529 };
530
531 spi_pins: spi_pins {
532 mux {
533 pins = "gpio18", "gpio19";
534 function = "gsbi5";
535 drive-strength = <10>;
536 bias-pull-down;
537 };
538
539 clk {
540 pins = "gpio21";
541 function = "gsbi5";
542 drive-strength = <12>;
543 bias-pull-down;
544 };
545
546 cs {
547 pins = "gpio20";
548 function = "gpio";
549 drive-strength = <10>;
550 bias-pull-up;
551 };
552 };
553 };
554
555 &tcsr {
556 qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
557 };