dcbe95c526ba662b6e448f20d6e9c3f00b032bc3
[openwrt/staging/chunkeey.git] / target / linux / ipq40xx / files / arch / arm / boot / dts / qcom-ipq4019-rtl30vw.dts
1 // SPDX-License-Identifier: ISC
2 // Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2019, Cezary Jackiewicz <cezary@eko.one.pl>.
4 // Copyright (c) 2020, Pawel Dembicki <paweldembicki@gmail.com>.
5
6 #include "qcom-ipq4019.dtsi"
7 #include <dt-bindings/soc/qcom,tcsr.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10
11 / {
12 model = "Cell C RTL30VW";
13 compatible = "cellc,rtl30vw";
14
15 aliases {
16 led-boot = &led_power_blue;
17 led-failsafe = &led_power_red;
18 led-running = &led_power_blue;
19 led-upgrade = &led_power_red;
20 };
21
22 chosen {
23 bootargs-append = "ubi.mtd=ubifs root=/dev/ubiblock0_0 rootfstype=squashfs ro";
24 };
25
26 led_spi {
27 compatible = "spi-gpio";
28 #address-cells = <1>;
29 #size-cells = <0>;
30 num-chipselects = <1>;
31
32 mosi-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
33 cs-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
34 sck-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
35
36 led_gpio: led_gpio@0 {
37 compatible = "fairchild,74hc595";
38 reg = <0>;
39 gpio-controller;
40 #gpio-cells = <2>;
41 registers-number = <2>;
42 spi-max-frequency = <1000000>;
43 };
44 };
45
46 leds {
47 compatible = "gpio-leds";
48
49 led_power_blue: power_blue {
50 gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
51 label = "blue:power";
52 default-state = "on";
53 };
54
55 led_power_red: power_red {
56 gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
57 label = "red:power";
58 };
59
60 tp28 {
61 gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
62 label = "ext:tp28";
63 default-state = "keep";
64 };
65
66 tp27 {
67 gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
68 label = "ext:tp27";
69 default-state = "keep";
70 };
71
72 wlan2g {
73 gpios = <&led_gpio 8 GPIO_ACTIVE_HIGH>;
74 label = "blue:wlan2g";
75 linux,default-trigger = "phy0tpt";
76 };
77
78 wlan5g {
79 gpios = <&led_gpio 9 GPIO_ACTIVE_HIGH>;
80 label = "blue:wlan5g";
81 linux,default-trigger = "phy1tpt";
82 };
83
84 wps {
85 gpios = <&led_gpio 10 GPIO_ACTIVE_HIGH>;
86 label = "blue:wps";
87 };
88
89 voip {
90 gpios = <&led_gpio 11 GPIO_ACTIVE_HIGH>;
91 label = "blue:voip";
92 };
93
94 s1 {
95 gpios = <&led_gpio 12 GPIO_ACTIVE_HIGH>;
96 label = "blue:s1";
97 };
98
99 s2 {
100 gpios = <&led_gpio 13 GPIO_ACTIVE_HIGH>;
101 label = "blue:s2";
102 };
103
104 s3 {
105 gpios = <&led_gpio 14 GPIO_ACTIVE_HIGH>;
106 label = "blue:s3";
107 };
108
109 s4 {
110 gpios = <&led_gpio 15 GPIO_ACTIVE_HIGH>;
111 label = "blue:s4";
112 };
113
114 signal {
115 gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
116 label = "red:signal";
117 };
118 };
119
120 keys {
121 compatible = "gpio-keys";
122
123 wps {
124 label = "wps";
125 linux,code = <KEY_WPS_BUTTON>;
126 gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
127 };
128
129 reset {
130 label = "reset";
131 linux,code = <KEY_RESTART>;
132 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
133 };
134 };
135
136 soc {
137 rng@22000 {
138 status = "okay";
139 };
140
141 mdio@90000 {
142 status = "okay";
143 };
144
145 ess-psgmii@98000 {
146 status = "okay";
147 };
148
149 tcsr@1949000 {
150 compatible = "qcom,tcsr";
151 reg = <0x1949000 0x100>;
152 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
153 };
154
155 tcsr@194b000 {
156 /* select hostmode */
157 compatible = "qcom,tcsr";
158 reg = <0x194b000 0x100>;
159 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
160 status = "okay";
161 };
162
163 ess_tcsr@1953000 {
164 compatible = "qcom,tcsr";
165 reg = <0x1953000 0x1000>;
166 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
167 };
168
169 tcsr@1957000 {
170 compatible = "qcom,tcsr";
171 reg = <0x1957000 0x100>;
172 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
173 };
174
175 usb2@60f8800 {
176 status = "okay";
177 };
178
179 usb3@8af8800 {
180 status = "okay";
181 };
182
183 crypto@8e3a000 {
184 status = "okay";
185 };
186
187 watchdog@b017000 {
188 status = "okay";
189 };
190
191 ess-switch@c000000 {
192 status = "okay";
193 };
194
195 edma@c080000 {
196 status = "okay";
197 };
198 };
199 };
200
201 &blsp_dma {
202 status = "okay";
203 };
204
205 &blsp1_spi1 {
206 pinctrl-0 = <&spi_0_pins>;
207 pinctrl-names = "default";
208 status = "okay";
209 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
210
211 flash@0 {
212 /*"n25q128a11" is required for proper nand recognition in u-boot. */
213 compatible = "jedec,spi-nor", "n25q128a11";
214 #address-cells = <1>;
215 #size-cells = <1>;
216 reg = <0>;
217 spi-max-frequency = <24000000>;
218
219 partitions {
220 compatible = "fixed-partitions";
221 #address-cells = <1>;
222 #size-cells = <1>;
223
224 partition@0 {
225 label = "0:SBL1";
226 reg = <0x0 0x40000>;
227 read-only;
228 };
229
230 partition@40000 {
231 label = "0:MIBIB";
232 reg = <0x40000 0x20000>;
233 read-only;
234 };
235
236 partition@60000 {
237 label = "0:QSEE";
238 reg = <0x60000 0x60000>;
239 read-only;
240 };
241
242 partition@c0000 {
243 label = "0:CDT";
244 reg = <0xc0000 0x10000>;
245 read-only;
246 };
247
248 partition@d0000 {
249 label = "0:DDRPARAMS";
250 reg = <0xd0000 0x10000>;
251 read-only;
252 };
253
254 partition@e0000 {
255 label = "0:APPSBLENV";
256 reg = <0xe0000 0x10000>;
257 read-only;
258 };
259
260 partition@f0000 {
261 label = "0:APPSBL";
262 reg = <0xf0000 0x80000>;
263 read-only;
264 };
265
266 partition@170000 {
267 label = "0:ART";
268 reg = <0x170000 0x10000>;
269 read-only;
270 compatible = "nvmem-cells";
271 #address-cells = <1>;
272 #size-cells = <1>;
273
274 precal_art_1000: precal@1000 {
275 reg = <0x1000 0x2f20>;
276 };
277
278 precal_art_5000: precal@5000 {
279 reg = <0x5000 0x2f20>;
280 };
281 };
282
283 partition@180000 {
284 label = "0:BOOTCONFIG";
285 reg = <0x180000 0x10000>;
286 read-only;
287 };
288 };
289 };
290
291 flash@1 {
292 /*
293 * Factory U-boot looks in 0:BOOTCONFIG partition for active
294 * partitions settings and mangle partition config. So kernel
295 * /kernel_1 and rootfs/rootfs_1 pairs can be swaped.
296 * It isn't a problem but we never can be sure where OFW put
297 * factory images. "spinand,mt29f" value is required for proper
298 * nand recognition in u-boot.
299 */
300 compatible = "spi-nand","spinand,mt29f";
301 #address-cells = <1>;
302 #size-cells = <0>;
303 reg = <1>;
304 spi-max-frequency = <24000000>;
305
306 partitions {
307 compatible = "fixed-partitions";
308 #address-cells = <1>;
309 #size-cells = <1>;
310
311 partition@0 {
312 label = "kernel";
313 reg = <0x0 0x400000>;
314 };
315
316 partition@400000 {
317 label = "rootfs";
318 reg = <0x400000 0x2000000>;
319 };
320
321 partition@2400000 {
322 label = "kernel_1";
323 reg = <0x2400000 0x400000>;
324 };
325
326 partition@2800000 {
327 label = "rootfs_1";
328 reg = <0x2800000 0x2000000>;
329 };
330
331 partition@4800000 {
332 label = "ubifs";
333 reg = <0x4800000 0x3800000>;
334 };
335 };
336 };
337 };
338
339 &blsp1_uart1 {
340 pinctrl-0 = <&serial_pins>;
341 pinctrl-names = "default";
342 status = "okay";
343 };
344
345 &cryptobam {
346 status = "okay";
347 };
348
349 &tlmm {
350 serial_pins: serial_pinmux {
351 mux {
352 pins = "gpio60", "gpio61";
353 function = "blsp_uart0";
354 bias-disable;
355 };
356 };
357
358 spi_0_pins: spi_0_pinmux {
359 pinmux {
360 function = "blsp_spi0";
361 pins = "gpio55", "gpio56", "gpio57";
362 drive-strength = <12>;
363 bias-disable;
364 };
365
366 pinmux_cs {
367 function = "gpio";
368 pins = "gpio54", "gpio59";
369 drive-strength = <2>;
370 bias-disable;
371 output-high;
372 };
373 };
374 };
375
376 &usb2_hs_phy {
377 status = "okay";
378 };
379
380 &usb3_ss_phy {
381 status = "okay";
382 };
383
384 &usb3_hs_phy {
385 status = "okay";
386 };
387
388 &wifi0 {
389 status = "okay";
390 nvmem-cell-names = "pre-calibration";
391 nvmem-cells = <&precal_art_1000>;
392 qcom,ath10k-calibration-variant = "cellc,rtl30vw";
393 };
394
395 &wifi1 {
396 status = "okay";
397 nvmem-cell-names = "pre-calibration";
398 nvmem-cells = <&precal_art_5000>;
399 qcom,ath10k-calibration-variant = "cellc,rtl30vw";
400 };