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generic: 6.6: refresh pending patches
[openwrt/staging/981213.git] / target / linux / generic / pending-6.6 / 750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
1 From patchwork Tue Feb 6 19:47:51 2024
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 X-Patchwork-Submitter: Eric Woudstra <ericwouds@gmail.com>
6 X-Patchwork-Id: 13547762
7 X-Patchwork-Delegate: kuba@kernel.org
8 From: Eric Woudstra <ericwouds@gmail.com>
9 To: "David S. Miller" <davem@davemloft.net>,
10 Eric Dumazet <edumazet@google.com>,
11 Jakub Kicinski <kuba@kernel.org>,
12 Paolo Abeni <pabeni@redhat.com>,
13 Rob Herring <robh+dt@kernel.org>,
14 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
15 Conor Dooley <conor+dt@kernel.org>,
16 Andrew Lunn <andrew@lunn.ch>,
17 Heiner Kallweit <hkallweit1@gmail.com>,
18 Russell King <linux@armlinux.org.uk>,
19 Matthias Brugger <matthias.bgg@gmail.com>,
20 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
21 "Frank Wunderlich" <frank-w@public-files.de>,
22 Daniel Golle <daniel@makrotopia.org>,
23 Lucien Jheng <lucien.jheng@airoha.com>,
24 Zhi-Jun You <hujy652@protonmail.com>
25 Cc: netdev@vger.kernel.org,
26 devicetree@vger.kernel.org,
27 Eric Woudstra <ericwouds@gmail.com>
28 Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H
29 PHY driver
30 Date: Tue, 6 Feb 2024 20:47:51 +0100
31 Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com>
32 X-Mailer: git-send-email 2.42.1
33 In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com>
34 References: <20240206194751.1901802-1-ericwouds@gmail.com>
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41 X-Patchwork-Delegate: kuba@kernel.org
42
43 * Source originated from airoha's en8811h v1.2.1 driver
44 * Moved air_en8811h.h to air_en8811h.c
45 * Removed air_pbus_reg_write() as it writes to another device on mdio-bus
46 * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/
47 * Added .get_rate_matching()
48 * Use generic phy_read/write() and phy_read/write_mmd()
49 * Edited .get_features() to use generic C45 functions
50 * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45
51 * Use led handling functions from mediatek-ge-soc.c
52 * Simplified led handling by storing led rules
53 * Cleanup macro definitions
54 * Cleanup code to pass checkpatch.pl
55 * General code cleanup
56
57 Changes from original RFC patch:
58
59 * Use the correct order in Kconfig and Makefile
60 * Change some register naming to correspond with datasheet
61 * Use phy_driver .read_page() and .write_page()
62 * Use module_phy_driver()
63 * Use get_unaligned_le16() instead of macro
64 * In .config_aneg() and .read_status() use genphy_xxx() C22
65 * Use another vendor register to read real speed
66 * Load firmware only once and store firmware version
67 * Apply 2.5G LPA work-around (firmware before 24011202)
68 * Read 2.5G LPA from vendor register (firmware 24011202 and later)
69
70 Changes to be committed:
71 modified: drivers/net/phy/Kconfig
72 modified: drivers/net/phy/Makefile
73 new file: drivers/net/phy/air_en8811h.c
74
75 Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
76 ---
77 drivers/net/phy/Kconfig | 5 +
78 drivers/net/phy/Makefile | 1 +
79 drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++
80 3 files changed, 1012 insertions(+)
81 create mode 100644 drivers/net/phy/air_en8811h.c
82
83 --- a/drivers/net/phy/Kconfig
84 +++ b/drivers/net/phy/Kconfig
85 @@ -68,6 +68,11 @@ config SFP
86
87 comment "MII PHY device drivers"
88
89 +config AIR_EN8811H_PHY
90 + tristate "Airoha EN8811H 2.5 Gigabit PHY"
91 + help
92 + Currently supports the Airoha EN8811H PHY.
93 +
94 config AMD_PHY
95 tristate "AMD and Altima PHYs"
96 help
97 --- a/drivers/net/phy/Makefile
98 +++ b/drivers/net/phy/Makefile
99 @@ -34,6 +34,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
100
101 obj-$(CONFIG_ADIN_PHY) += adin.o
102 obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
103 +obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
104 obj-$(CONFIG_AMD_PHY) += amd.o
105 obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
106 obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
107 --- /dev/null
108 +++ b/drivers/net/phy/air_en8811h.c
109 @@ -0,0 +1,1006 @@
110 +// SPDX-License-Identifier: GPL-2.0+
111 +/*
112 + * Driver for Airoha Ethernet PHYs
113 + *
114 + * Currently supporting the EN8811H.
115 + *
116 + * Limitations of the EN8811H:
117 + * - Only full duplex supported
118 + * - Forced speed (AN off) is not supported by hardware (100Mbps)
119 + *
120 + * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
121 + *
122 + * Copyright (C) 2023 Airoha Technology Corp.
123 + */
124 +
125 +#include <linux/phy.h>
126 +#include <linux/firmware.h>
127 +#include <linux/property.h>
128 +#include <asm/unaligned.h>
129 +
130 +#define EN8811H_PHY_ID 0x03a2a411
131 +
132 +#define EN8811H_MD32_DM "airoha/EthMD32.dm.bin"
133 +#define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin"
134 +
135 +#define AIR_FW_ADDR_DM 0x00000000
136 +#define AIR_FW_ADDR_DSP 0x00100000
137 +
138 +/* u32 (DWORD) component macros */
139 +#define LOWORD(d) ((u16)(u32)(d))
140 +#define HIWORD(d) ((u16)(((u32)(d)) >> 16))
141 +
142 +/* MII Registers */
143 +#define AIR_AUX_CTRL_STATUS 0x1d
144 +#define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2)
145 +#define AIR_AUX_CTRL_STATUS_SPEED_100 0x4
146 +#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
147 +#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
148 +
149 +#define AIR_EXT_PAGE_ACCESS 0x1f
150 +#define AIR_PHY_PAGE_STANDARD 0x0000
151 +#define AIR_PHY_PAGE_EXTENDED_4 0x0004
152 +
153 +/* MII Registers Page 4*/
154 +#define AIR_PBUS_MODE 0x10
155 +#define AIR_PBUS_MODE_ADDR_FIXED 0x0000
156 +#define AIR_PBUS_MODE_ADDR_INCR BIT(15)
157 +#define AIR_PBUS_WR_ADDR_HIGH 0x11
158 +#define AIR_PBUS_WR_ADDR_LOW 0x12
159 +#define AIR_PBUS_WR_DATA_HIGH 0x13
160 +#define AIR_PBUS_WR_DATA_LOW 0x14
161 +#define AIR_PBUS_RD_ADDR_HIGH 0x15
162 +#define AIR_PBUS_RD_ADDR_LOW 0x16
163 +#define AIR_PBUS_RD_DATA_HIGH 0x17
164 +#define AIR_PBUS_RD_DATA_LOW 0x18
165 +
166 +/* Registers on MDIO_MMD_VEND1 */
167 +#define EN8811H_PHY_FW_STATUS 0x8009
168 +#define EN8811H_PHY_READY 0x02
169 +
170 +#define AIR_PHY_HOST_CMD_1 0x800c
171 +#define AIR_PHY_HOST_CMD_1_MODE1 0x0
172 +#define AIR_PHY_HOST_CMD_2 0x800d
173 +#define AIR_PHY_HOST_CMD_2_MODE1 0x0
174 +#define AIR_PHY_HOST_CMD_3 0x800e
175 +#define AIR_PHY_HOST_CMD_3_MODE1 0x1101
176 +#define AIR_PHY_HOST_CMD_3_DOCMD 0x1100
177 +#define AIR_PHY_HOST_CMD_4 0x800f
178 +#define AIR_PHY_HOST_CMD_4_MODE1 0x0002
179 +#define AIR_PHY_HOST_CMD_4_INTCLR 0x00e4
180 +
181 +/* Registers on MDIO_MMD_VEND2 */
182 +#define AIR_PHY_LED_BCR 0x021
183 +#define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0)
184 +#define AIR_PHY_LED_BCR_TIME_TEST BIT(2)
185 +#define AIR_PHY_LED_BCR_CLK_EN BIT(3)
186 +#define AIR_PHY_LED_BCR_EXT_CTRL BIT(15)
187 +
188 +#define AIR_PHY_LED_DUR_ON 0x022
189 +
190 +#define AIR_PHY_LED_DUR_BLINK 0x023
191 +
192 +#define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2))
193 +#define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8))
194 +#define AIR_PHY_LED_ON_LINK1000 BIT(0)
195 +#define AIR_PHY_LED_ON_LINK100 BIT(1)
196 +#define AIR_PHY_LED_ON_LINK10 BIT(2)
197 +#define AIR_PHY_LED_ON_LINKDOWN BIT(3)
198 +#define AIR_PHY_LED_ON_FDX BIT(4) /* Full duplex */
199 +#define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */
200 +#define AIR_PHY_LED_ON_FORCE_ON BIT(6)
201 +#define AIR_PHY_LED_ON_LINK2500 BIT(8)
202 +#define AIR_PHY_LED_ON_POLARITY BIT(14)
203 +#define AIR_PHY_LED_ON_ENABLE BIT(15)
204 +
205 +#define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2))
206 +#define AIR_PHY_LED_BLINK_1000TX BIT(0)
207 +#define AIR_PHY_LED_BLINK_1000RX BIT(1)
208 +#define AIR_PHY_LED_BLINK_100TX BIT(2)
209 +#define AIR_PHY_LED_BLINK_100RX BIT(3)
210 +#define AIR_PHY_LED_BLINK_10TX BIT(4)
211 +#define AIR_PHY_LED_BLINK_10RX BIT(5)
212 +#define AIR_PHY_LED_BLINK_COLLISION BIT(6)
213 +#define AIR_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
214 +#define AIR_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
215 +#define AIR_PHY_LED_BLINK_FORCE_BLINK BIT(9)
216 +#define AIR_PHY_LED_BLINK_2500TX BIT(10)
217 +#define AIR_PHY_LED_BLINK_2500RX BIT(11)
218 +
219 +/* Registers on BUCKPBUS */
220 +#define EN8811H_2P5G_LPA 0x3b30
221 +#define EN8811H_2P5G_LPA_2P5G BIT(0)
222 +
223 +#define EN8811H_FW_VERSION 0x3b3c
224 +
225 +#define EN8811H_POLARITY 0xca0f8
226 +#define EN8811H_POLARITY_TX_NORMAL BIT(0)
227 +#define EN8811H_POLARITY_RX_REVERSE BIT(1)
228 +
229 +#define EN8811H_GPIO_OUTPUT 0xcf8b8
230 +#define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5))
231 +
232 +#define EN8811H_FW_CTRL_1 0x0f0018
233 +#define EN8811H_FW_CTRL_1_START 0x0
234 +#define EN8811H_FW_CTRL_1_FINISH 0x1
235 +#define EN8811H_FW_CTRL_2 0x800000
236 +#define EN8811H_FW_CTRL_2_LOADING BIT(11)
237 +
238 +#define EN8811H_LED_COUNT 3
239 +
240 +/* GPIO5 <-> BASE_T_LED0
241 + * GPIO4 <-> BASE_T_LED1
242 + * GPIO3 <-> BASE_T_LED2
243 + *
244 + * Default setup suitable for 2 leds connected:
245 + * 100M link up triggers led0, only led0 blinking on traffic
246 + * 1000M link up triggers led1, only led1 blinking on traffic
247 + * 2500M link up triggers led0 and led1, both blinking on traffic
248 + * Also suitable for 1 led connected:
249 + * any link up triggers led2
250 + */
251 +#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \
252 + BIT(TRIGGER_NETDEV_LINK_100) | \
253 + BIT(TRIGGER_NETDEV_RX) | \
254 + BIT(TRIGGER_NETDEV_TX))
255 +#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
256 + BIT(TRIGGER_NETDEV_LINK_1000) | \
257 + BIT(TRIGGER_NETDEV_RX) | \
258 + BIT(TRIGGER_NETDEV_TX))
259 +#define AIR_DEFAULT_TRIGGER_LED2 BIT(TRIGGER_NETDEV_LINK)
260 +
261 +struct led {
262 + unsigned long rules;
263 + unsigned long state;
264 +};
265 +
266 +struct en8811h_priv {
267 + u32 firmware_version;
268 + struct led led[EN8811H_LED_COUNT];
269 +};
270 +
271 +enum {
272 + AIR_PHY_LED_STATE_FORCE_ON,
273 + AIR_PHY_LED_STATE_FORCE_BLINK,
274 +};
275 +
276 +enum {
277 + AIR_PHY_LED_DUR_BLINK_32M,
278 + AIR_PHY_LED_DUR_BLINK_64M,
279 + AIR_PHY_LED_DUR_BLINK_128M,
280 + AIR_PHY_LED_DUR_BLINK_256M,
281 + AIR_PHY_LED_DUR_BLINK_512M,
282 + AIR_PHY_LED_DUR_BLINK_1024M,
283 +};
284 +
285 +enum {
286 + AIR_LED_DISABLE,
287 + AIR_LED_ENABLE,
288 +};
289 +
290 +enum {
291 + AIR_ACTIVE_LOW,
292 + AIR_ACTIVE_HIGH,
293 +};
294 +
295 +enum {
296 + AIR_LED_MODE_DISABLE,
297 + AIR_LED_MODE_USER_DEFINE,
298 +};
299 +
300 +#define AIR_PHY_LED_DUR_UNIT 1024
301 +#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M)
302 +
303 +static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
304 + BIT(TRIGGER_NETDEV_LINK) |
305 + BIT(TRIGGER_NETDEV_LINK_10) |
306 + BIT(TRIGGER_NETDEV_LINK_100) |
307 + BIT(TRIGGER_NETDEV_LINK_1000) |
308 + BIT(TRIGGER_NETDEV_LINK_2500) |
309 + BIT(TRIGGER_NETDEV_RX) |
310 + BIT(TRIGGER_NETDEV_TX));
311 +
312 +static int air_phy_read_page(struct phy_device *phydev)
313 +{
314 + return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
315 +}
316 +
317 +static int air_phy_write_page(struct phy_device *phydev, int page)
318 +{
319 + return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
320 +}
321 +
322 +static int __air_buckpbus_reg_write(struct phy_device *phydev,
323 + u32 pbus_address, u32 pbus_data)
324 +{
325 + int ret;
326 +
327 + ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
328 + if (ret < 0)
329 + return ret;
330 +
331 + ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address));
332 + if (ret < 0)
333 + return ret;
334 +
335 + ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(pbus_address));
336 + if (ret < 0)
337 + return ret;
338 +
339 + ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data));
340 + if (ret < 0)
341 + return ret;
342 +
343 + ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, LOWORD(pbus_data));
344 + if (ret < 0)
345 + return ret;
346 +
347 + return 0;
348 +}
349 +
350 +static int air_buckpbus_reg_write(struct phy_device *phydev,
351 + u32 pbus_address, u32 pbus_data)
352 +{
353 + int ret, saved_page;
354 +
355 + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
356 +
357 + ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data);
358 + if (ret < 0)
359 + phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
360 + pbus_address, ret);
361 +
362 + return phy_restore_page(phydev, saved_page, ret);
363 +;
364 +}
365 +
366 +static int __air_buckpbus_reg_read(struct phy_device *phydev,
367 + u32 pbus_address, u32 *pbus_data)
368 +{
369 + int pbus_data_low, pbus_data_high;
370 + int ret;
371 +
372 + ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
373 + if (ret < 0)
374 + return ret;
375 +
376 + ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address));
377 + if (ret < 0)
378 + return ret;
379 +
380 + ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW, LOWORD(pbus_address));
381 + if (ret < 0)
382 + return ret;
383 +
384 + pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH);
385 + if (pbus_data_high < 0)
386 + return ret;
387 +
388 + pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW);
389 + if (pbus_data_low < 0)
390 + return ret;
391 +
392 + *pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16);
393 + return 0;
394 +}
395 +
396 +static int air_buckpbus_reg_read(struct phy_device *phydev,
397 + u32 pbus_address, u32 *pbus_data)
398 +{
399 + int ret, saved_page;
400 +
401 + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
402 +
403 + ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
404 + if (ret < 0)
405 + phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
406 + pbus_address, ret);
407 +
408 + return phy_restore_page(phydev, saved_page, ret);
409 +}
410 +
411 +static int __air_write_buf(struct phy_device *phydev, u32 address,
412 + const struct firmware *fw)
413 +{
414 + unsigned int offset;
415 + int ret;
416 + u16 val;
417 +
418 + ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR);
419 + if (ret < 0)
420 + return ret;
421 +
422 + ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address));
423 + if (ret < 0)
424 + return ret;
425 +
426 + ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(address));
427 + if (ret < 0)
428 + return ret;
429 +
430 + for (offset = 0; offset < fw->size; offset += 4) {
431 + val = get_unaligned_le16(&fw->data[offset + 2]);
432 + ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val);
433 + if (ret < 0)
434 + return ret;
435 +
436 + val = get_unaligned_le16(&fw->data[offset]);
437 + ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val);
438 + if (ret < 0)
439 + return ret;
440 + }
441 +
442 + return 0;
443 +}
444 +
445 +static int air_write_buf(struct phy_device *phydev, u32 address,
446 + const struct firmware *fw)
447 +{
448 + int ret, saved_page;
449 +
450 + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
451 +
452 + ret = __air_write_buf(phydev, address, fw);
453 + if (ret < 0)
454 + phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
455 + address, ret);
456 +
457 + return phy_restore_page(phydev, saved_page, ret);
458 +}
459 +
460 +static int en8811h_load_firmware(struct phy_device *phydev)
461 +{
462 + struct device *dev = &phydev->mdio.dev;
463 + const struct firmware *fw1, *fw2;
464 + u32 pbus_value;
465 + int ret;
466 +
467 + ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
468 + if (ret < 0)
469 + return ret;
470 +
471 + ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
472 + if (ret < 0)
473 + goto en8811h_load_firmware_rel1;
474 +
475 + ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
476 + EN8811H_FW_CTRL_1_START);
477 + if (ret < 0)
478 + goto en8811h_load_firmware_out;
479 +
480 + ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
481 + if (ret < 0)
482 + goto en8811h_load_firmware_out;
483 + pbus_value |= EN8811H_FW_CTRL_2_LOADING;
484 + ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
485 + if (ret < 0)
486 + goto en8811h_load_firmware_out;
487 +
488 + ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1);
489 + if (ret < 0)
490 + goto en8811h_load_firmware_out;
491 +
492 + ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
493 + if (ret < 0)
494 + goto en8811h_load_firmware_out;
495 +
496 + ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
497 + if (ret < 0)
498 + goto en8811h_load_firmware_out;
499 + pbus_value &= ~EN8811H_FW_CTRL_2_LOADING;
500 + ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
501 + if (ret < 0)
502 + goto en8811h_load_firmware_out;
503 +
504 + ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
505 + EN8811H_FW_CTRL_1_FINISH);
506 + if (ret < 0)
507 + goto en8811h_load_firmware_out;
508 +
509 + ret = 0;
510 +
511 +en8811h_load_firmware_out:
512 + release_firmware(fw2);
513 +
514 +en8811h_load_firmware_rel1:
515 + release_firmware(fw1);
516 +
517 + if (ret < 0)
518 + phydev_err(phydev, "Load firmware failed: %d\n", ret);
519 +
520 + return ret;
521 +}
522 +
523 +static int en8811h_restart_host(struct phy_device *phydev)
524 +{
525 + int ret;
526 +
527 + ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
528 + EN8811H_FW_CTRL_1_START);
529 + if (ret < 0)
530 + return ret;
531 +
532 + return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
533 + EN8811H_FW_CTRL_1_FINISH);
534 +}
535 +
536 +static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
537 +{
538 + struct en8811h_priv *priv = phydev->priv;
539 + bool changed;
540 +
541 + if (index >= EN8811H_LED_COUNT)
542 + return -EINVAL;
543 +
544 + if (on)
545 + changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
546 + &priv->led[index].state);
547 + else
548 + changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
549 + &priv->led[index].state);
550 +
551 + changed |= (priv->led[index].rules != 0);
552 +
553 + if (changed)
554 + return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
555 + AIR_PHY_LED_ON(index),
556 + AIR_PHY_LED_ON_MASK,
557 + on ? AIR_PHY_LED_ON_FORCE_ON : 0);
558 +
559 + return 0;
560 +}
561 +
562 +static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
563 + bool blinking)
564 +{
565 + struct en8811h_priv *priv = phydev->priv;
566 + bool changed;
567 +
568 + if (index >= EN8811H_LED_COUNT)
569 + return -EINVAL;
570 +
571 + if (blinking)
572 + changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
573 + &priv->led[index].state);
574 + else
575 + changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
576 + &priv->led[index].state);
577 +
578 + changed |= (priv->led[index].rules != 0);
579 +
580 + if (changed)
581 + return phy_write_mmd(phydev, MDIO_MMD_VEND2,
582 + AIR_PHY_LED_BLINK(index),
583 + blinking ?
584 + AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
585 + else
586 + return 0;
587 +}
588 +
589 +static int air_led_blink_set(struct phy_device *phydev, u8 index,
590 + unsigned long *delay_on,
591 + unsigned long *delay_off)
592 +{
593 + struct en8811h_priv *priv = phydev->priv;
594 + bool blinking = false;
595 + int err;
596 +
597 + if (index >= EN8811H_LED_COUNT)
598 + return -EINVAL;
599 +
600 + if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
601 + blinking = true;
602 + *delay_on = 50;
603 + *delay_off = 50;
604 + }
605 +
606 + err = air_hw_led_blink_set(phydev, index, blinking);
607 + if (err)
608 + return err;
609 +
610 + /* led-blink set, so switch led-on off */
611 + err = air_hw_led_on_set(phydev, index, false);
612 + if (err)
613 + return err;
614 +
615 + /* hw-control is off*/
616 + if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
617 + priv->led[index].rules = 0;
618 +
619 + return 0;
620 +}
621 +
622 +static int air_led_brightness_set(struct phy_device *phydev, u8 index,
623 + enum led_brightness value)
624 +{
625 + struct en8811h_priv *priv = phydev->priv;
626 + int err;
627 +
628 + if (index >= EN8811H_LED_COUNT)
629 + return -EINVAL;
630 +
631 + /* led-on set, so switch led-blink off */
632 + err = air_hw_led_blink_set(phydev, index, false);
633 + if (err)
634 + return err;
635 +
636 + err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
637 + if (err)
638 + return err;
639 +
640 + /* hw-control is off */
641 + if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
642 + priv->led[index].rules = 0;
643 +
644 + return 0;
645 +}
646 +
647 +static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
648 + unsigned long *rules)
649 +{
650 + struct en8811h_priv *priv = phydev->priv;
651 +
652 + if (index >= EN8811H_LED_COUNT)
653 + return -EINVAL;
654 +
655 + *rules = priv->led[index].rules;
656 +
657 + return 0;
658 +};
659 +
660 +static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
661 + unsigned long rules)
662 +{
663 + struct en8811h_priv *priv = phydev->priv;
664 + u16 on = 0, blink = 0;
665 + int ret;
666 +
667 + priv->led[index].rules = rules;
668 +
669 + if (index >= EN8811H_LED_COUNT)
670 + return -EINVAL;
671 +
672 + if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) {
673 + on |= AIR_PHY_LED_ON_LINK10;
674 + if (rules & BIT(TRIGGER_NETDEV_RX))
675 + blink |= AIR_PHY_LED_BLINK_10RX;
676 + if (rules & BIT(TRIGGER_NETDEV_TX))
677 + blink |= AIR_PHY_LED_BLINK_10TX;
678 + }
679 +
680 + if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) {
681 + on |= AIR_PHY_LED_ON_LINK100;
682 + if (rules & BIT(TRIGGER_NETDEV_RX))
683 + blink |= AIR_PHY_LED_BLINK_100RX;
684 + if (rules & BIT(TRIGGER_NETDEV_TX))
685 + blink |= AIR_PHY_LED_BLINK_100TX;
686 + }
687 +
688 + if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) {
689 + on |= AIR_PHY_LED_ON_LINK1000;
690 + if (rules & BIT(TRIGGER_NETDEV_RX))
691 + blink |= AIR_PHY_LED_BLINK_1000RX;
692 + if (rules & BIT(TRIGGER_NETDEV_TX))
693 + blink |= AIR_PHY_LED_BLINK_1000TX;
694 + }
695 +
696 + if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) {
697 + on |= AIR_PHY_LED_ON_LINK2500;
698 + if (rules & BIT(TRIGGER_NETDEV_RX))
699 + blink |= AIR_PHY_LED_BLINK_2500RX;
700 + if (rules & BIT(TRIGGER_NETDEV_TX))
701 + blink |= AIR_PHY_LED_BLINK_2500TX;
702 + }
703 +
704 + if (on == 0) {
705 + if (rules & BIT(TRIGGER_NETDEV_RX)) {
706 + blink |= AIR_PHY_LED_BLINK_10RX |
707 + AIR_PHY_LED_BLINK_100RX |
708 + AIR_PHY_LED_BLINK_1000RX |
709 + AIR_PHY_LED_BLINK_2500RX;
710 + }
711 + if (rules & BIT(TRIGGER_NETDEV_TX)) {
712 + blink |= AIR_PHY_LED_BLINK_10TX |
713 + AIR_PHY_LED_BLINK_100TX |
714 + AIR_PHY_LED_BLINK_1000TX |
715 + AIR_PHY_LED_BLINK_2500TX;
716 + }
717 + }
718 +
719 + if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
720 + on |= AIR_PHY_LED_ON_FDX;
721 +
722 + if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
723 + on |= AIR_PHY_LED_ON_HDX;
724 +
725 + if (blink || on) {
726 + /* switch hw-control on, so led-on and led-blink are off */
727 + clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state);
728 + clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state);
729 + } else {
730 + priv->led[index].rules = 0;
731 + }
732 +
733 + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
734 + AIR_PHY_LED_ON_MASK, on);
735 +
736 + if (ret < 0)
737 + return ret;
738 +
739 + return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
740 + blink);
741 +};
742 +
743 +static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
744 +{
745 + int cl45_data;
746 + int err;
747 +
748 + if (index >= EN8811H_LED_COUNT)
749 + return -EINVAL;
750 +
751 + cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index));
752 + if (cl45_data < 0)
753 + return cl45_data;
754 +
755 + if (state == AIR_LED_ENABLE)
756 + cl45_data |= AIR_PHY_LED_ON_ENABLE;
757 + else
758 + cl45_data &= ~AIR_PHY_LED_ON_ENABLE;
759 +
760 + if (pol == AIR_ACTIVE_HIGH)
761 + cl45_data |= AIR_PHY_LED_ON_POLARITY;
762 + else
763 + cl45_data &= ~AIR_PHY_LED_ON_POLARITY;
764 +
765 + err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
766 + cl45_data);
767 + if (err < 0)
768 + return err;
769 +
770 + return 0;
771 +}
772 +
773 +static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
774 +{
775 + struct en8811h_priv *priv = phydev->priv;
776 + int cl45_data = dur;
777 + int ret, i;
778 +
779 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
780 + cl45_data);
781 + if (ret < 0)
782 + return ret;
783 +
784 + cl45_data >>= 1;
785 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
786 + cl45_data);
787 + if (ret < 0)
788 + return ret;
789 +
790 + cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR);
791 + if (cl45_data < 0)
792 + return cl45_data;
793 +
794 + switch (mode) {
795 + case AIR_LED_MODE_DISABLE:
796 + cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL;
797 + cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK;
798 + break;
799 + case AIR_LED_MODE_USER_DEFINE:
800 + cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL;
801 + cl45_data |= AIR_PHY_LED_BCR_CLK_EN;
802 + break;
803 + default:
804 + phydev_err(phydev, "LED mode %d is not supported\n", mode);
805 + return -EINVAL;
806 + }
807 +
808 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data);
809 + if (ret < 0)
810 + return ret;
811 +
812 + for (i = 0; i < num; ++i) {
813 + ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
814 + if (ret < 0) {
815 + phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
816 + return ret;
817 + }
818 + air_led_hw_control_set(phydev, i, priv->led[i].rules);
819 + }
820 +
821 + return 0;
822 +}
823 +
824 +static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
825 + unsigned long rules)
826 +{
827 + if (index >= EN8811H_LED_COUNT)
828 + return -EINVAL;
829 +
830 + /* All combinations of the supported triggers are allowed */
831 + if (rules & ~en8811h_led_trig)
832 + return -EOPNOTSUPP;
833 +
834 + return 0;
835 +};
836 +
837 +static int en8811h_probe(struct phy_device *phydev)
838 +{
839 + struct en8811h_priv *priv;
840 +
841 + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
842 + GFP_KERNEL);
843 + if (!priv)
844 + return -ENOMEM;
845 +
846 + priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
847 + priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
848 + priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
849 +
850 + phydev->priv = priv;
851 +
852 + /* MDIO_DEVS1/2 empty, so set mmds_present bits here */
853 + phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
854 +
855 + return 0;
856 +}
857 +
858 +static int en8811h_config_init(struct phy_device *phydev)
859 +{
860 + struct en8811h_priv *priv = phydev->priv;
861 + struct device *dev = &phydev->mdio.dev;
862 + int ret, pollret, reg_value;
863 + u32 pbus_value;
864 +
865 + if (!priv->firmware_version)
866 + ret = en8811h_load_firmware(phydev);
867 + else
868 + ret = en8811h_restart_host(phydev);
869 + if (ret < 0)
870 + return ret;
871 +
872 + /* Because of mdio-lock, may have to wait for multiple loads */
873 + pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
874 + EN8811H_PHY_FW_STATUS, reg_value,
875 + reg_value == EN8811H_PHY_READY,
876 + 20000, 7500000, true);
877 +
878 + ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value);
879 + if (ret < 0)
880 + return ret;
881 +
882 + if (pollret || !pbus_value) {
883 + phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value);
884 + return -ENODEV;
885 + }
886 +
887 + if (!priv->firmware_version) {
888 + phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value);
889 + priv->firmware_version = pbus_value;
890 + }
891 +
892 + /* Select mode 1, the only mode supported */
893 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1,
894 + AIR_PHY_HOST_CMD_1_MODE1);
895 + if (ret < 0)
896 + return ret;
897 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2,
898 + AIR_PHY_HOST_CMD_2_MODE1);
899 + if (ret < 0)
900 + return ret;
901 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
902 + AIR_PHY_HOST_CMD_3_MODE1);
903 + if (ret < 0)
904 + return ret;
905 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
906 + AIR_PHY_HOST_CMD_4_MODE1);
907 + if (ret < 0)
908 + return ret;
909 +
910 + /* Serdes polarity */
911 + ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value);
912 + if (ret < 0)
913 + return ret;
914 + if (device_property_read_bool(dev, "airoha,pnswap-rx"))
915 + pbus_value |= EN8811H_POLARITY_RX_REVERSE;
916 + else
917 + pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
918 + if (device_property_read_bool(dev, "airoha,pnswap-tx"))
919 + pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
920 + else
921 + pbus_value |= EN8811H_POLARITY_TX_NORMAL;
922 + ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value);
923 + if (ret < 0)
924 + return ret;
925 +
926 + ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
927 + AIR_LED_MODE_USER_DEFINE);
928 + if (ret < 0) {
929 + phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
930 + return ret;
931 + }
932 +
933 + ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value);
934 + if (ret < 0)
935 + return ret;
936 + pbus_value |= EN8811H_GPIO_OUTPUT_345;
937 + ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value);
938 + if (ret < 0)
939 + return ret;
940 +
941 + return 0;
942 +}
943 +
944 +static int en8811h_get_features(struct phy_device *phydev)
945 +{
946 + linkmode_set_bit_array(phy_basic_ports_array,
947 + ARRAY_SIZE(phy_basic_ports_array),
948 + phydev->supported);
949 +
950 + return genphy_c45_pma_read_abilities(phydev);
951 +}
952 +
953 +static int en8811h_get_rate_matching(struct phy_device *phydev,
954 + phy_interface_t iface)
955 +{
956 + return RATE_MATCH_PAUSE;
957 +}
958 +
959 +static int en8811h_config_aneg(struct phy_device *phydev)
960 +{
961 + bool changed = false;
962 + int err, val;
963 +
964 + val = 0;
965 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
966 + phydev->advertising))
967 + val |= MDIO_AN_10GBT_CTRL_ADV2_5G;
968 + err = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
969 + MDIO_AN_10GBT_CTRL_ADV2_5G, val);
970 + if (err < 0)
971 + return err;
972 + if (err > 0)
973 + changed = true;
974 +
975 + return __genphy_config_aneg(phydev, changed);
976 +}
977 +
978 +static int en8811h_read_status(struct phy_device *phydev)
979 +{
980 + struct en8811h_priv *priv = phydev->priv;
981 + u32 pbus_value;
982 + int ret, val;
983 +
984 + ret = genphy_update_link(phydev);
985 + if (ret)
986 + return ret;
987 +
988 + phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
989 + phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
990 + phydev->speed = SPEED_UNKNOWN;
991 + phydev->duplex = DUPLEX_UNKNOWN;
992 + phydev->pause = 0;
993 + phydev->asym_pause = 0;
994 +
995 + ret = genphy_read_master_slave(phydev);
996 + if (ret < 0)
997 + return ret;
998 +
999 + ret = genphy_read_lpa(phydev);
1000 + if (ret < 0)
1001 + return ret;
1002 +
1003 + /* Get link partner 2.5GBASE-T ability from vendor register */
1004 + ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
1005 + if (ret < 0)
1006 + return ret;
1007 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1008 + phydev->lp_advertising,
1009 + pbus_value & EN8811H_2P5G_LPA_2P5G);
1010 +
1011 + if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1012 + phy_resolve_aneg_pause(phydev);
1013 +
1014 + if (!phydev->link)
1015 + return 0;
1016 +
1017 + /* Get real speed from vendor register */
1018 + val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
1019 + if (val < 0)
1020 + return val;
1021 + switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
1022 + case AIR_AUX_CTRL_STATUS_SPEED_2500:
1023 + phydev->speed = SPEED_2500;
1024 + break;
1025 + case AIR_AUX_CTRL_STATUS_SPEED_1000:
1026 + phydev->speed = SPEED_1000;
1027 + break;
1028 + case AIR_AUX_CTRL_STATUS_SPEED_100:
1029 + phydev->speed = SPEED_100;
1030 + break;
1031 + }
1032 +
1033 + /* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set.
1034 + * Firmware before version 24011202 has no vendor register 2P5G_LPA.
1035 + * Assume link partner advertised it if connected at 2500Mbps.
1036 + */
1037 + if (priv->firmware_version < 0x24011202) {
1038 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1039 + phydev->lp_advertising,
1040 + phydev->speed == SPEED_2500);
1041 + }
1042 +
1043 + /* Only supports full duplex */
1044 + phydev->duplex = DUPLEX_FULL;
1045 +
1046 + return 0;
1047 +}
1048 +
1049 +static int en8811h_clear_intr(struct phy_device *phydev)
1050 +{
1051 + int ret;
1052 +
1053 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
1054 + AIR_PHY_HOST_CMD_3_DOCMD);
1055 + if (ret < 0)
1056 + return ret;
1057 +
1058 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
1059 + AIR_PHY_HOST_CMD_4_INTCLR);
1060 + if (ret < 0)
1061 + return ret;
1062 +
1063 + return 0;
1064 +}
1065 +
1066 +static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
1067 +{
1068 + int ret;
1069 +
1070 + ret = en8811h_clear_intr(phydev);
1071 + if (ret < 0) {
1072 + phy_error(phydev);
1073 + return IRQ_NONE;
1074 + }
1075 +
1076 + phy_trigger_machine(phydev);
1077 +
1078 + return IRQ_HANDLED;
1079 +}
1080 +
1081 +static struct phy_driver en8811h_driver[] = {
1082 +{
1083 + PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
1084 + .name = "Airoha EN8811H",
1085 + .probe = en8811h_probe,
1086 + .get_features = en8811h_get_features,
1087 + .config_init = en8811h_config_init,
1088 + .get_rate_matching = en8811h_get_rate_matching,
1089 + .config_aneg = en8811h_config_aneg,
1090 + .read_status = en8811h_read_status,
1091 + .config_intr = en8811h_clear_intr,
1092 + .handle_interrupt = en8811h_handle_interrupt,
1093 + .led_hw_is_supported = en8811h_led_hw_is_supported,
1094 + .read_page = air_phy_read_page,
1095 + .write_page = air_phy_write_page,
1096 + .led_blink_set = air_led_blink_set,
1097 + .led_brightness_set = air_led_brightness_set,
1098 + .led_hw_control_set = air_led_hw_control_set,
1099 + .led_hw_control_get = air_led_hw_control_get,
1100 +} };
1101 +
1102 +module_phy_driver(en8811h_driver);
1103 +
1104 +static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
1105 + { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
1106 + { }
1107 +};
1108 +MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
1109 +MODULE_FIRMWARE(EN8811H_MD32_DM);
1110 +MODULE_FIRMWARE(EN8811H_MD32_DSP);
1111 +
1112 +MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
1113 +MODULE_AUTHOR("Airoha");
1114 +MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
1115 +MODULE_LICENSE("GPL");
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