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generic: 6.6: fix copy & refresh
[openwrt/staging/981213.git] / target / linux / generic / pending-6.6 / 737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
1 From d5e337e7aecc2e1cc9e96768062610adb95f8f72 Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Tue, 12 Dec 2023 03:51:14 +0000
4 Subject: [PATCH] net: ethernet: mtk_eth_soc: add paths and SerDes modes for
5 MT7988
6
7 MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
8 connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
9 2500Base-X, 1000Base-X and Cisco SGMII interface modes.
10
11 Implement support for configuring for the new paths to SerDes interfaces
12 and the internal 2.5G PHY.
13
14 Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and
15 setup the new PHYA on MT7988 to access the also still existing old
16 LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface
17 modes.
18
19 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
20 ---
21 drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 +++++++-
22 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 292 +++++++++++++++++--
23 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 107 ++++++-
24 3 files changed, 470 insertions(+), 51 deletions(-)
25
26 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
27 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
28 @@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
29 return "gmac2_rgmii";
30 case MTK_ETH_PATH_GMAC2_SGMII:
31 return "gmac2_sgmii";
32 + case MTK_ETH_PATH_GMAC2_2P5GPHY:
33 + return "gmac2_2p5gphy";
34 case MTK_ETH_PATH_GMAC2_GEPHY:
35 return "gmac2_gephy";
36 + case MTK_ETH_PATH_GMAC3_SGMII:
37 + return "gmac3_sgmii";
38 case MTK_ETH_PATH_GDM1_ESW:
39 return "gdm1_esw";
40 + case MTK_ETH_PATH_GMAC1_USXGMII:
41 + return "gmac1_usxgmii";
42 + case MTK_ETH_PATH_GMAC2_USXGMII:
43 + return "gmac2_usxgmii";
44 + case MTK_ETH_PATH_GMAC3_USXGMII:
45 + return "gmac3_usxgmii";
46 default:
47 return "unknown path";
48 }
49 @@ -127,6 +137,27 @@ static int set_mux_u3_gmac2_to_qphy(stru
50 return 0;
51 }
52
53 +static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
54 +{
55 + int ret;
56 +
57 + if (path == MTK_ETH_PATH_GMAC2_2P5GPHY) {
58 + ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0, SYSCFG0_SGMII_GMAC2_V2);
59 + if (ret)
60 + return ret;
61 +
62 + /* Setup mux to 2p5g PHY */
63 + ret = regmap_clear_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, MUX_G2_USXGMII_SEL);
64 + if (ret)
65 + return ret;
66 +
67 + dev_dbg(eth->dev, "path %s in %s updated\n",
68 + mtk_eth_path_name(path), __func__);
69 + }
70 +
71 + return 0;
72 +}
73 +
74 static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
75 {
76 unsigned int val = 0;
77 @@ -165,7 +196,48 @@ static int set_mux_gmac1_gmac2_to_sgmii_
78 return 0;
79 }
80
81 -static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
82 +static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
83 +{
84 + unsigned int val = 0;
85 + bool updated = true;
86 + int mac_id = 0;
87 +
88 + /* Disable SYSCFG1 SGMII */
89 + regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
90 +
91 + switch (path) {
92 + case MTK_ETH_PATH_GMAC1_USXGMII:
93 + val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
94 + mac_id = MTK_GMAC1_ID;
95 + break;
96 + case MTK_ETH_PATH_GMAC2_USXGMII:
97 + val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
98 + mac_id = MTK_GMAC2_ID;
99 + break;
100 + case MTK_ETH_PATH_GMAC3_USXGMII:
101 + val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
102 + mac_id = MTK_GMAC3_ID;
103 + break;
104 + default:
105 + updated = false;
106 + };
107 +
108 + if (updated) {
109 + regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
110 + SYSCFG0_SGMII_MASK, val);
111 +
112 + if (mac_id == MTK_GMAC2_ID)
113 + regmap_set_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX,
114 + MUX_G2_USXGMII_SEL);
115 + }
116 +
117 + dev_dbg(eth->dev, "path %s in %s updated = %d\n",
118 + mtk_eth_path_name(path), __func__, updated);
119 +
120 + return 0;
121 +}
122 +
123 +static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
124 {
125 unsigned int val = 0;
126 bool updated = true;
127 @@ -182,6 +254,9 @@ static int set_mux_gmac12_to_gephy_sgmii
128 case MTK_ETH_PATH_GMAC2_SGMII:
129 val |= SYSCFG0_SGMII_GMAC2_V2;
130 break;
131 + case MTK_ETH_PATH_GMAC3_SGMII:
132 + val |= SYSCFG0_SGMII_GMAC3_V2;
133 + break;
134 default:
135 updated = false;
136 }
137 @@ -210,13 +285,25 @@ static const struct mtk_eth_muxc mtk_eth
138 .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
139 .set_path = set_mux_u3_gmac2_to_qphy,
140 }, {
141 + .name = "mux_gmac2_to_2p5gphy",
142 + .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
143 + .set_path = set_mux_gmac2_to_2p5gphy,
144 + }, {
145 .name = "mux_gmac1_gmac2_to_sgmii_rgmii",
146 .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
147 .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii,
148 }, {
149 .name = "mux_gmac12_to_gephy_sgmii",
150 .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
151 - .set_path = set_mux_gmac12_to_gephy_sgmii,
152 + .set_path = set_mux_gmac123_to_gephy_sgmii,
153 + }, {
154 + .name = "mux_gmac123_to_gephy_sgmii",
155 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
156 + .set_path = set_mux_gmac123_to_gephy_sgmii,
157 + }, {
158 + .name = "mux_gmac123_to_usxgmii",
159 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
160 + .set_path = set_mux_gmac123_to_usxgmii,
161 },
162 };
163
164 @@ -249,12 +336,39 @@ out:
165 return err;
166 }
167
168 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
169 +{
170 + u64 path;
171 +
172 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII :
173 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII :
174 + MTK_ETH_PATH_GMAC3_USXGMII;
175 +
176 + /* Setup proper MUXes along the path */
177 + return mtk_eth_mux_setup(eth, path);
178 +}
179 +
180 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
181 {
182 u64 path;
183
184 - path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
185 - MTK_ETH_PATH_GMAC2_SGMII;
186 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
187 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
188 + MTK_ETH_PATH_GMAC3_SGMII;
189 +
190 + /* Setup proper MUXes along the path */
191 + return mtk_eth_mux_setup(eth, path);
192 +}
193 +
194 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
195 +{
196 + u64 path = 0;
197 +
198 + if (mac_id == MTK_GMAC2_ID)
199 + path = MTK_ETH_PATH_GMAC2_2P5GPHY;
200 +
201 + if (!path)
202 + return -EINVAL;
203
204 /* Setup proper MUXes along the path */
205 return mtk_eth_mux_setup(eth, path);
206 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
207 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
208 @@ -22,6 +22,8 @@
209 #include <linux/pinctrl/devinfo.h>
210 #include <linux/phylink.h>
211 #include <linux/pcs/pcs-mtk-lynxi.h>
212 +#include <linux/pcs/pcs-mtk-usxgmii.h>
213 +#include <linux/phy/phy.h>
214 #include <linux/jhash.h>
215 #include <linux/bitfield.h>
216 #include <net/dsa.h>
217 @@ -261,12 +263,8 @@ static const char * const mtk_clks_sourc
218 "ethwarp_wocpu2",
219 "ethwarp_wocpu1",
220 "ethwarp_wocpu0",
221 - "top_usxgmii0_sel",
222 - "top_usxgmii1_sel",
223 "top_sgm0_sel",
224 "top_sgm1_sel",
225 - "top_xfi_phy0_xtal_sel",
226 - "top_xfi_phy1_xtal_sel",
227 "top_eth_gmii_sel",
228 "top_eth_refck_50m_sel",
229 "top_eth_sys_200m_sel",
230 @@ -509,6 +507,30 @@ static void mtk_setup_bridge_switch(stru
231 MTK_GSW_CFG);
232 }
233
234 +static bool mtk_check_gmac23_idle(struct mtk_mac *mac)
235 +{
236 + u32 mac_fsm, gdm_fsm;
237 +
238 + mac_fsm = mtk_r32(mac->hw, MTK_MAC_FSM(mac->id));
239 +
240 + switch (mac->id) {
241 + case MTK_GMAC2_ID:
242 + gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM2_FSM);
243 + break;
244 + case MTK_GMAC3_ID:
245 + gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM3_FSM);
246 + break;
247 + default:
248 + return true;
249 + };
250 +
251 + if ((mac_fsm & 0xFFFF0000) == 0x01010000 &&
252 + (gdm_fsm & 0xFFFF0000) == 0x00000000)
253 + return true;
254 +
255 + return false;
256 +}
257 +
258 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
259 phy_interface_t interface)
260 {
261 @@ -517,6 +539,21 @@ static struct phylink_pcs *mtk_mac_selec
262 struct mtk_eth *eth = mac->hw;
263 unsigned int sid;
264
265 + if (mtk_is_netsys_v3_or_greater(eth)) {
266 + switch (interface) {
267 + case PHY_INTERFACE_MODE_1000BASEX:
268 + case PHY_INTERFACE_MODE_2500BASEX:
269 + case PHY_INTERFACE_MODE_SGMII:
270 + return mac->sgmii_pcs;
271 + case PHY_INTERFACE_MODE_5GBASER:
272 + case PHY_INTERFACE_MODE_10GBASER:
273 + case PHY_INTERFACE_MODE_USXGMII:
274 + return mac->usxgmii_pcs;
275 + default:
276 + return NULL;
277 + }
278 + }
279 +
280 if (interface == PHY_INTERFACE_MODE_SGMII ||
281 phy_interface_mode_is_8023z(interface)) {
282 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
283 @@ -568,7 +605,22 @@ static void mtk_mac_config(struct phylin
284 goto init_err;
285 }
286 break;
287 + case PHY_INTERFACE_MODE_USXGMII:
288 + case PHY_INTERFACE_MODE_10GBASER:
289 + case PHY_INTERFACE_MODE_5GBASER:
290 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
291 + err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
292 + if (err)
293 + goto init_err;
294 + }
295 + break;
296 case PHY_INTERFACE_MODE_INTERNAL:
297 + if (mac->id == MTK_GMAC2_ID &&
298 + MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
299 + err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
300 + if (err)
301 + goto init_err;
302 + }
303 break;
304 default:
305 goto err_phy;
306 @@ -615,8 +667,6 @@ static void mtk_mac_config(struct phylin
307 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
308 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
309 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
310 -
311 - mac->interface = state->interface;
312 }
313
314 /* SGMII */
315 @@ -633,21 +683,40 @@ static void mtk_mac_config(struct phylin
316
317 /* Save the syscfg0 value for mac_finish */
318 mac->syscfg0 = val;
319 - } else if (phylink_autoneg_inband(mode)) {
320 + } else if (state->interface != PHY_INTERFACE_MODE_USXGMII &&
321 + state->interface != PHY_INTERFACE_MODE_10GBASER &&
322 + state->interface != PHY_INTERFACE_MODE_5GBASER &&
323 + phylink_autoneg_inband(mode)) {
324 dev_err(eth->dev,
325 - "In-band mode not supported in non SGMII mode!\n");
326 + "In-band mode not supported in non-SerDes modes!\n");
327 return;
328 }
329
330 /* Setup gmac */
331 - if (mtk_is_netsys_v3_or_greater(eth) &&
332 - mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
333 - mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
334 - mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
335 + if (mtk_is_netsys_v3_or_greater(eth)) {
336 + if (mtk_interface_mode_is_xgmii(state->interface)) {
337 + mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
338 + mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
339 +
340 + if (mac->id == MTK_GMAC1_ID)
341 + mtk_setup_bridge_switch(eth);
342 + } else {
343 + mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id));
344
345 - mtk_setup_bridge_switch(eth);
346 + /* FIXME: In current hardware design, we have to reset FE
347 + * when swtiching XGDM to GDM. Therefore, here trigger an SER
348 + * to let GDM go back to the initial state.
349 + */
350 + if ((mtk_interface_mode_is_xgmii(mac->interface) ||
351 + mac->interface == PHY_INTERFACE_MODE_NA) &&
352 + !mtk_check_gmac23_idle(mac) &&
353 + !test_bit(MTK_RESETTING, &eth->state))
354 + schedule_work(&eth->pending_work);
355 + }
356 }
357
358 + mac->interface = state->interface;
359 +
360 return;
361
362 err_phy:
363 @@ -660,6 +729,18 @@ init_err:
364 mac->id, phy_modes(state->interface), err);
365 }
366
367 +static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
368 + phy_interface_t interface)
369 +{
370 + struct mtk_mac *mac = container_of(config, struct mtk_mac,
371 + phylink_config);
372 +
373 + if (mac->pextp && mac->interface != interface)
374 + phy_reset(mac->pextp);
375 +
376 + return 0;
377 +}
378 +
379 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
380 phy_interface_t interface)
381 {
382 @@ -668,6 +749,10 @@ static int mtk_mac_finish(struct phylink
383 struct mtk_eth *eth = mac->hw;
384 u32 mcr_cur, mcr_new;
385
386 + /* Setup PMA/PMD */
387 + if (mac->pextp)
388 + phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
389 +
390 /* Enable SGMII */
391 if (interface == PHY_INTERFACE_MODE_SGMII ||
392 phy_interface_mode_is_8023z(interface))
393 @@ -692,10 +777,14 @@ static void mtk_mac_link_down(struct phy
394 {
395 struct mtk_mac *mac = container_of(config, struct mtk_mac,
396 phylink_config);
397 - u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
398
399 - mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK);
400 - mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
401 + if (!mtk_interface_mode_is_xgmii(interface)) {
402 + mtk_m32(mac->hw, MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK, 0, MTK_MAC_MCR(mac->id));
403 + if (mtk_is_netsys_v3_or_greater(mac->hw))
404 + mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id));
405 + } else if (mtk_is_netsys_v3_or_greater(mac->hw) && mac->id != MTK_GMAC1_ID) {
406 + mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id));
407 + }
408 }
409
410 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
411 @@ -767,13 +856,11 @@ static void mtk_set_queue_speed(struct m
412 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
413 }
414
415 -static void mtk_mac_link_up(struct phylink_config *config,
416 - struct phy_device *phy,
417 - unsigned int mode, phy_interface_t interface,
418 - int speed, int duplex, bool tx_pause, bool rx_pause)
419 +static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
420 + struct phy_device *phy,
421 + unsigned int mode, phy_interface_t interface,
422 + int speed, int duplex, bool tx_pause, bool rx_pause)
423 {
424 - struct mtk_mac *mac = container_of(config, struct mtk_mac,
425 - phylink_config);
426 u32 mcr;
427
428 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
429 @@ -807,9 +894,63 @@ static void mtk_mac_link_up(struct phyli
430 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
431 }
432
433 +static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
434 + struct phy_device *phy,
435 + unsigned int mode, phy_interface_t interface,
436 + int speed, int duplex, bool tx_pause, bool rx_pause)
437 +{
438 + u32 mcr, force_link = 0;
439 +
440 + if (mac->id == MTK_GMAC1_ID)
441 + return;
442 +
443 + /* Eliminate the interference(before link-up) caused by PHY noise */
444 + mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id));
445 + mdelay(20);
446 + mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id));
447 +
448 + if (mac->interface == PHY_INTERFACE_MODE_INTERNAL || mac->id == MTK_GMAC3_ID)
449 + force_link = MTK_XGMAC_FORCE_LINK(mac->id);
450 +
451 + mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), force_link, MTK_XGMAC_STS(mac->id));
452 +
453 + mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
454 + mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE);
455 + /* Configure pause modes -
456 + * phylink will avoid these for half duplex
457 + */
458 + if (tx_pause)
459 + mcr |= XMAC_MCR_FORCE_TX_FC;
460 + if (rx_pause)
461 + mcr |= XMAC_MCR_FORCE_RX_FC;
462 +
463 + mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
464 +}
465 +
466 +static void mtk_mac_link_up(struct phylink_config *config,
467 + struct phy_device *phy,
468 + unsigned int mode, phy_interface_t interface,
469 + int speed, int duplex, bool tx_pause, bool rx_pause)
470 +{
471 + struct mtk_mac *mac = container_of(config, struct mtk_mac,
472 + phylink_config);
473 +
474 + if (mtk_is_netsys_v3_or_greater(mac->hw) && mtk_interface_mode_is_xgmii(interface))
475 + mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
476 + tx_pause, rx_pause);
477 + else
478 + mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
479 + tx_pause, rx_pause);
480 +
481 + /* Repeat pextp setup to tune link */
482 + if (mac->pextp)
483 + phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
484 +}
485 +
486 static const struct phylink_mac_ops mtk_phylink_ops = {
487 .mac_select_pcs = mtk_mac_select_pcs,
488 .mac_config = mtk_mac_config,
489 + .mac_prepare = mtk_mac_prepare,
490 .mac_finish = mtk_mac_finish,
491 .mac_link_down = mtk_mac_link_down,
492 .mac_link_up = mtk_mac_link_up,
493 @@ -3390,6 +3531,9 @@ static int mtk_open(struct net_device *d
494 struct mtk_eth *eth = mac->hw;
495 int i, err;
496
497 + if (mac->pextp)
498 + phy_power_on(mac->pextp);
499 +
500 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
501 if (err) {
502 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
503 @@ -3519,6 +3663,9 @@ static int mtk_stop(struct net_device *d
504 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
505 mtk_ppe_stop(eth->ppe[i]);
506
507 + if (mac->pextp)
508 + phy_power_off(mac->pextp);
509 +
510 return 0;
511 }
512
513 @@ -4516,6 +4663,7 @@ static const struct net_device_ops mtk_n
514 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
515 {
516 const __be32 *_id = of_get_property(np, "reg", NULL);
517 + struct device_node *pcs_np;
518 phy_interface_t phy_mode;
519 struct phylink *phylink;
520 struct mtk_mac *mac;
521 @@ -4552,16 +4700,41 @@ static int mtk_add_mac(struct mtk_eth *e
522 mac->id = id;
523 mac->hw = eth;
524 mac->of_node = np;
525 + pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 0);
526 + if (pcs_np) {
527 + mac->sgmii_pcs = mtk_pcs_lynxi_get(eth->dev, pcs_np);
528 + if (IS_ERR(mac->sgmii_pcs)) {
529 + if (PTR_ERR(mac->sgmii_pcs) == -EPROBE_DEFER)
530 + return -EPROBE_DEFER;
531
532 - err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
533 - if (err == -EPROBE_DEFER)
534 - return err;
535 + dev_err(eth->dev, "cannot select SGMII PCS, error %ld\n",
536 + PTR_ERR(mac->sgmii_pcs));
537 + return PTR_ERR(mac->sgmii_pcs);
538 + }
539 + }
540
541 - if (err) {
542 - /* If the mac address is invalid, use random mac address */
543 - eth_hw_addr_random(eth->netdev[id]);
544 - dev_err(eth->dev, "generated random MAC address %pM\n",
545 - eth->netdev[id]->dev_addr);
546 + pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 1);
547 + if (pcs_np) {
548 + mac->usxgmii_pcs = mtk_usxgmii_pcs_get(eth->dev, pcs_np);
549 + if (IS_ERR(mac->usxgmii_pcs)) {
550 + if (PTR_ERR(mac->usxgmii_pcs) == -EPROBE_DEFER)
551 + return -EPROBE_DEFER;
552 +
553 + dev_err(eth->dev, "cannot select USXGMII PCS, error %ld\n",
554 + PTR_ERR(mac->usxgmii_pcs));
555 + return PTR_ERR(mac->usxgmii_pcs);
556 + }
557 + }
558 +
559 + if (mtk_is_netsys_v3_or_greater(eth) && (mac->sgmii_pcs || mac->usxgmii_pcs)) {
560 + mac->pextp = devm_of_phy_get(eth->dev, mac->of_node, NULL);
561 + if (IS_ERR(mac->pextp)) {
562 + if (PTR_ERR(mac->pextp) != -EPROBE_DEFER)
563 + dev_err(eth->dev, "cannot get PHY, error %ld\n",
564 + PTR_ERR(mac->pextp));
565 +
566 + return PTR_ERR(mac->pextp);
567 + }
568 }
569
570 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
571 @@ -4644,8 +4817,21 @@ static int mtk_add_mac(struct mtk_eth *e
572 phy_interface_zero(mac->phylink_config.supported_interfaces);
573 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
574 mac->phylink_config.supported_interfaces);
575 + } else if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
576 + mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
577 + __set_bit(PHY_INTERFACE_MODE_5GBASER,
578 + mac->phylink_config.supported_interfaces);
579 + __set_bit(PHY_INTERFACE_MODE_10GBASER,
580 + mac->phylink_config.supported_interfaces);
581 + __set_bit(PHY_INTERFACE_MODE_USXGMII,
582 + mac->phylink_config.supported_interfaces);
583 }
584
585 + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) &&
586 + id == MTK_GMAC2_ID)
587 + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
588 + mac->phylink_config.supported_interfaces);
589 +
590 phylink = phylink_create(&mac->phylink_config,
591 of_fwnode_handle(mac->of_node),
592 phy_mode, &mtk_phylink_ops);
593 @@ -4696,6 +4882,26 @@ free_netdev:
594 return err;
595 }
596
597 +static int mtk_mac_assign_address(struct mtk_eth *eth, int i, bool test_defer_only)
598 +{
599 + int err = of_get_ethdev_address(eth->mac[i]->of_node, eth->netdev[i]);
600 +
601 + if (err == -EPROBE_DEFER)
602 + return err;
603 +
604 + if (test_defer_only)
605 + return 0;
606 +
607 + if (err) {
608 + /* If the mac address is invalid, use random mac address */
609 + eth_hw_addr_random(eth->netdev[i]);
610 + dev_err(eth->dev, "generated random MAC address %pM\n",
611 + eth->netdev[i]);
612 + }
613 +
614 + return 0;
615 +}
616 +
617 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
618 {
619 struct net_device *dev, *tmp;
620 @@ -4842,7 +5048,8 @@ static int mtk_probe(struct platform_dev
621 regmap_write(cci, 0, 3);
622 }
623
624 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
625 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII) &&
626 + !mtk_is_netsys_v3_or_greater(eth)) {
627 err = mtk_sgmii_init(eth);
628
629 if (err)
630 @@ -4953,6 +5160,24 @@ static int mtk_probe(struct platform_dev
631 }
632 }
633
634 + for (i = 0; i < MTK_MAX_DEVS; i++) {
635 + if (!eth->netdev[i])
636 + continue;
637 +
638 + err = mtk_mac_assign_address(eth, i, true);
639 + if (err)
640 + goto err_deinit_hw;
641 + }
642 +
643 + for (i = 0; i < MTK_MAX_DEVS; i++) {
644 + if (!eth->netdev[i])
645 + continue;
646 +
647 + err = mtk_mac_assign_address(eth, i, false);
648 + if (err)
649 + goto err_deinit_hw;
650 + }
651 +
652 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
653 err = devm_request_irq(eth->dev, eth->irq[0],
654 mtk_handle_irq, 0,
655 @@ -5055,6 +5280,11 @@ static int mtk_remove(struct platform_de
656 mtk_stop(eth->netdev[i]);
657 mac = netdev_priv(eth->netdev[i]);
658 phylink_disconnect_phy(mac->phylink);
659 + if (mac->sgmii_pcs)
660 + mtk_pcs_lynxi_put(mac->sgmii_pcs);
661 +
662 + if (mac->usxgmii_pcs)
663 + mtk_usxgmii_pcs_put(mac->usxgmii_pcs);
664 }
665
666 mtk_wed_exit();
667 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
668 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
669 @@ -15,6 +15,7 @@
670 #include <linux/u64_stats_sync.h>
671 #include <linux/refcount.h>
672 #include <linux/phylink.h>
673 +#include <linux/reset.h>
674 #include <linux/rhashtable.h>
675 #include <linux/dim.h>
676 #include <linux/bitfield.h>
677 @@ -502,6 +503,21 @@
678 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
679 #define INTF_MODE_RGMII_10_100 0
680
681 +/* XFI Mac control registers */
682 +#define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000))
683 +#define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x))
684 +#define XMAC_MCR_TRX_DISABLE 0xf
685 +#define XMAC_MCR_FORCE_TX_FC BIT(5)
686 +#define XMAC_MCR_FORCE_RX_FC BIT(4)
687 +
688 +/* XFI Mac logic reset registers */
689 +#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
690 +#define XMAC_LOGIC_RST BIT(0)
691 +
692 +/* XFI Mac count global control */
693 +#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
694 +#define XMAC_GLB_CNTCLR BIT(0)
695 +
696 /* GPIO port control registers for GMAC 2*/
697 #define GPIO_OD33_CTRL8 0x4c0
698 #define GPIO_BIAS_CTRL 0xed0
699 @@ -527,6 +543,7 @@
700 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
701 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
702 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
703 +#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)
704
705
706 /* ethernet subsystem clock register */
707 @@ -565,6 +582,11 @@
708 #define GEPHY_MAC_SEL BIT(1)
709
710 /* Top misc registers */
711 +#define TOP_MISC_NETSYS_PCS_MUX 0x84
712 +#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
713 +#define MUX_G2_USXGMII_SEL BIT(1)
714 +#define MUX_HSGMII1_G1_SEL BIT(0)
715 +
716 #define USB_PHY_SWITCH_REG 0x218
717 #define QPHY_SEL_MASK GENMASK(1, 0)
718 #define SGMII_QPHY_SEL 0x2
719 @@ -589,6 +611,8 @@
720 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
721 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
722
723 +/* Debug Purpose Register */
724 +#define MTK_PSE_FQFC_CFG 0x100
725 #define MTK_FE_CDM1_FSM 0x220
726 #define MTK_FE_CDM2_FSM 0x224
727 #define MTK_FE_CDM3_FSM 0x238
728 @@ -597,6 +621,11 @@
729 #define MTK_FE_CDM6_FSM 0x328
730 #define MTK_FE_GDM1_FSM 0x228
731 #define MTK_FE_GDM2_FSM 0x22C
732 +#define MTK_FE_GDM3_FSM 0x23C
733 +#define MTK_FE_PSE_FREE 0x240
734 +#define MTK_FE_DROP_FQ 0x244
735 +#define MTK_FE_DROP_FC 0x248
736 +#define MTK_FE_DROP_PPE 0x24C
737
738 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
739
740 @@ -721,12 +750,8 @@ enum mtk_clks_map {
741 MTK_CLK_ETHWARP_WOCPU2,
742 MTK_CLK_ETHWARP_WOCPU1,
743 MTK_CLK_ETHWARP_WOCPU0,
744 - MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
745 - MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
746 MTK_CLK_TOP_SGM_0_SEL,
747 MTK_CLK_TOP_SGM_1_SEL,
748 - MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
749 - MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
750 MTK_CLK_TOP_ETH_GMII_SEL,
751 MTK_CLK_TOP_ETH_REFCK_50M_SEL,
752 MTK_CLK_TOP_ETH_SYS_200M_SEL,
753 @@ -797,19 +822,9 @@ enum mtk_clks_map {
754 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
755 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
756 BIT_ULL(MTK_CLK_CRYPTO) | \
757 - BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
758 - BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
759 - BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
760 - BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
761 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
762 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
763 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
764 - BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
765 - BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
766 - BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
767 - BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
768 - BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
769 - BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
770 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
771 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
772 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
773 @@ -943,6 +958,8 @@ enum mkt_eth_capabilities {
774 MTK_RGMII_BIT = 0,
775 MTK_TRGMII_BIT,
776 MTK_SGMII_BIT,
777 + MTK_USXGMII_BIT,
778 + MTK_2P5GPHY_BIT,
779 MTK_ESW_BIT,
780 MTK_GEPHY_BIT,
781 MTK_MUX_BIT,
782 @@ -963,8 +980,11 @@ enum mkt_eth_capabilities {
783 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
784 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
785 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
786 + MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
787 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
788 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
789 + MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
790 + MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,
791
792 /* PATH BITS */
793 MTK_ETH_PATH_GMAC1_RGMII_BIT,
794 @@ -972,14 +992,21 @@ enum mkt_eth_capabilities {
795 MTK_ETH_PATH_GMAC1_SGMII_BIT,
796 MTK_ETH_PATH_GMAC2_RGMII_BIT,
797 MTK_ETH_PATH_GMAC2_SGMII_BIT,
798 + MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
799 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
800 + MTK_ETH_PATH_GMAC3_SGMII_BIT,
801 MTK_ETH_PATH_GDM1_ESW_BIT,
802 + MTK_ETH_PATH_GMAC1_USXGMII_BIT,
803 + MTK_ETH_PATH_GMAC2_USXGMII_BIT,
804 + MTK_ETH_PATH_GMAC3_USXGMII_BIT,
805 };
806
807 /* Supported hardware group on SoCs */
808 #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
809 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
810 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
811 +#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
812 +#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
813 #define MTK_ESW BIT_ULL(MTK_ESW_BIT)
814 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
815 #define MTK_MUX BIT_ULL(MTK_MUX_BIT)
816 @@ -1002,10 +1029,16 @@ enum mkt_eth_capabilities {
817 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
818 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
819 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
820 +#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
821 + BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
822 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
823 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
824 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
825 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
826 +#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \
827 + BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
828 +#define MTK_ETH_MUX_GMAC123_TO_USXGMII \
829 + BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)
830
831 /* Supported path present on SoCs */
832 #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
833 @@ -1013,8 +1046,13 @@ enum mkt_eth_capabilities {
834 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
835 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
836 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
837 +#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
838 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
839 +#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
840 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
841 +#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
842 +#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
843 +#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)
844
845 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
846 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
847 @@ -1022,7 +1060,12 @@ enum mkt_eth_capabilities {
848 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
849 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
850 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
851 +#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
852 +#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
853 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
854 +#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
855 +#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
856 +#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
857
858 /* MUXes present on SoCs */
859 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
860 @@ -1041,10 +1084,20 @@ enum mkt_eth_capabilities {
861 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
862 MTK_SHARED_SGMII)
863
864 +/* 2: GMAC2 -> XGMII */
865 +#define MTK_MUX_GMAC2_TO_2P5GPHY \
866 + (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
867 +
868 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
869 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
870 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
871
872 +#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \
873 + (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
874 +
875 +#define MTK_MUX_GMAC123_TO_USXGMII \
876 + (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
877 +
878 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
879
880 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
881 @@ -1076,8 +1129,12 @@ enum mkt_eth_capabilities {
882 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
883 MTK_RSTCTRL_PPE1 | MTK_SRAM)
884
885 -#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
886 - MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
887 +#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
888 + MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
889 + MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \
890 + MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
891 + MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
892 + MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
893
894 struct mtk_tx_dma_desc_info {
895 dma_addr_t addr;
896 @@ -1314,6 +1371,9 @@ struct mtk_mac {
897 struct device_node *of_node;
898 struct phylink *phylink;
899 struct phylink_config phylink_config;
900 + struct phylink_pcs *sgmii_pcs;
901 + struct phylink_pcs *usxgmii_pcs;
902 + struct phy *pextp;
903 struct mtk_eth *hw;
904 struct mtk_hw_stats *hw_stats;
905 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
906 @@ -1437,6 +1497,19 @@ static inline u32 mtk_get_ib2_multicast_
907 return MTK_FOE_IB2_MULTICAST;
908 }
909
910 +static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
911 +{
912 + switch (interface) {
913 + case PHY_INTERFACE_MODE_INTERNAL:
914 + case PHY_INTERFACE_MODE_USXGMII:
915 + case PHY_INTERFACE_MODE_10GBASER:
916 + case PHY_INTERFACE_MODE_5GBASER:
917 + return true;
918 + default:
919 + return false;
920 + }
921 +}
922 +
923 /* read the hardware status register */
924 void mtk_stats_update_mac(struct mtk_mac *mac);
925
926 @@ -1445,8 +1518,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
927 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
928
929 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
930 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
931 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
932 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
933 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);
934
935 int mtk_eth_offload_init(struct mtk_eth *eth);
936 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
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