target/linux/generic/backport-5.15/850-v5.17-0004-PCI-aardvark-Clear-all-MSIs-at-setup.patch

   1 From 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Tue, 30 Nov 2021 18:29:06 +0100
   4 Subject: [PATCH] PCI: aardvark: Clear all MSIs at setup
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
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   8
   9 We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).
  10
  11 Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs,
  12 to ensure that we don't start receiving spurious interrupts.
  13
  14 Use this new mask in advk_pcie_handle_msi();
  15
  16 Link: https://lore.kernel.org/r/20211130172913.9727-5-kabel@kernel.org
  17 Signed-off-by: Pali Rohár <pali@kernel.org>
  18 Signed-off-by: Marek Behún <kabel@kernel.org>
  19 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  20 ---
  21  drivers/pci/controller/pci-aardvark.c | 6 ++++--
  22  1 file changed, 4 insertions(+), 2 deletions(-)
  23
  24 --- a/drivers/pci/controller/pci-aardvark.c
  25 +++ b/drivers/pci/controller/pci-aardvark.c
  26 @@ -115,6 +115,7 @@
  27  #define PCIE_MSI_ADDR_HIGH_REG                 (CONTROL_BASE_ADDR + 0x54)
  28  #define PCIE_MSI_STATUS_REG                    (CONTROL_BASE_ADDR + 0x58)
  29  #define PCIE_MSI_MASK_REG                      (CONTROL_BASE_ADDR + 0x5C)
  30 +#define     PCIE_MSI_ALL_MASK                  GENMASK(31, 0)
  31  #define PCIE_MSI_PAYLOAD_REG                   (CONTROL_BASE_ADDR + 0x9C)
  32  #define     PCIE_MSI_DATA_MASK                 GENMASK(15, 0)
  33
  34 @@ -570,6 +571,7 @@ static void advk_pcie_setup_hw(struct ad
  35         advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  36
  37         /* Clear all interrupts */
  38 +       advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
  39         advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
  40         advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
  41         advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
  42 @@ -582,7 +584,7 @@ static void advk_pcie_setup_hw(struct ad
  43         advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
  44
  45         /* Unmask all MSIs */
  46 -       advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
  47 +       advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
  48
  49         /* Enable summary interrupt for GIC SPI source */
  50         reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
  51 @@ -1389,7 +1391,7 @@ static void advk_pcie_handle_msi(struct
  52
  53         msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
  54         msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
  55 -       msi_status = msi_val & ~msi_mask;
  56 +       msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
  57
  58         for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
  59                 if (!(BIT(msi_idx) & msi_status))