target/linux/bcm53xx/patches-5.10/040-v5.16-ARM-dts-BCM5301X-Fix-I2C-controller-interrupt.patch

   1 From beda1bbdb19baa8319ed81fa370fe0c5b91d05df Mon Sep 17 00:00:00 2001
   2 From: Florian Fainelli <f.fainelli@gmail.com>
   3 Date: Tue, 26 Oct 2021 11:36:22 -0700
   4 Subject: [PATCH] ARM: dts: BCM5301X: Fix I2C controller interrupt
   5
   6 The I2C interrupt controller line is off by 32 because the datasheet
   7 describes interrupt inputs into the GIC which are for Shared Peripheral
   8 Interrupts and are starting at offset 32. The ARM GIC binding expects
   9 the SPI interrupts to be numbered from 0 relative to the SPI base.
  10
  11 Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT")
  12 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  13 ---
  14  arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
  15  1 file changed, 1 insertion(+), 1 deletion(-)
  16
  17 diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
  18 index f92089290ccd..ec5de636796e 100644
  19 --- a/arch/arm/boot/dts/bcm5301x.dtsi
  20 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
  21 @@ -408,7 +408,7 @@ uart2: serial@18008000 {
  22         i2c0: i2c@18009000 {
  23                 compatible = "brcm,iproc-i2c";
  24                 reg = <0x18009000 0x50>;
  25 -               interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
  26 +               interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29                 clock-frequency = <100000>;
  30 --
  31 2.25.1
  32