target/linux/bcm27xx/patches-5.15/950-0074-Add-SMI-driver.patch

   1 From c7a3892d84af30b95f30d14a1140ddbcf738abf7 Mon Sep 17 00:00:00 2001
   2 From: Luke Wren <wren6991@gmail.com>
   3 Date: Sat, 5 Sep 2015 01:14:45 +0100
   4 Subject: [PATCH] Add SMI driver
   5
   6 Signed-off-by: Luke Wren <wren6991@gmail.com>
   7
   8 MISC: bcm2835: smi: use clock manager and fix reload issues
   9
  10 Use clock manager instead of self-made clockmanager.
  11
  12 Also fix some error paths that showd up during development
  13 (especially missing release of dma resources on rmmod)
  14
  15 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  16
  17 bcm2835_smi: re-add dereference to fix DMA transfers
  18 ---
  19  .../bindings/misc/brcm,bcm2835-smi-dev.txt    |  17 +
  20  .../bindings/misc/brcm,bcm2835-smi.txt        |  48 +
  21  drivers/char/broadcom/Kconfig                 |   9 +
  22  drivers/char/broadcom/Makefile                |   1 +
  23  drivers/char/broadcom/bcm2835_smi_dev.c       | 402 ++++++++
  24  drivers/misc/Kconfig                          |   8 +
  25  drivers/misc/Makefile                         |   1 +
  26  drivers/misc/bcm2835_smi.c                    | 955 ++++++++++++++++++
  27  include/linux/broadcom/bcm2835_smi.h          | 391 +++++++
  28  9 files changed, 1832 insertions(+)
  29  create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  30  create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
  31  create mode 100644 drivers/char/broadcom/bcm2835_smi_dev.c
  32  create mode 100644 drivers/misc/bcm2835_smi.c
  33  create mode 100644 include/linux/broadcom/bcm2835_smi.h
  34
  35 --- /dev/null
  36 +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  37 @@ -0,0 +1,17 @@
  38 +* Broadcom BCM2835 SMI character device driver.
  39 +
  40 +SMI or secondary memory interface is a peripheral specific to certain Broadcom
  41 +SOCs, and is helpful for talking to things like parallel-interface displays
  42 +and NAND flashes (in fact, most things with a parallel register interface).
  43 +
  44 +This driver adds a character device which provides a user-space interface to
  45 +an instance of the SMI driver.
  46 +
  47 +Required properties:
  48 +- compatible: "brcm,bcm2835-smi-dev"
  49 +- smi_handle: a phandle to the smi node.
  50 +
  51 +Optional properties:
  52 +- None.
  53 +
  54 +
  55 --- /dev/null
  56 +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
  57 @@ -0,0 +1,48 @@
  58 +* Broadcom BCM2835 SMI driver.
  59 +
  60 +SMI or secondary memory interface is a peripheral specific to certain Broadcom
  61 +SOCs, and is helpful for talking to things like parallel-interface displays
  62 +and NAND flashes (in fact, most things with a parallel register interface).
  63 +
  64 +Required properties:
  65 +- compatible: "brcm,bcm2835-smi"
  66 +- reg: Should contain location and length of SMI registers and SMI clkman regs
  67 +- interrupts: *the* SMI interrupt.
  68 +- pinctrl-names: should be "default".
  69 +- pinctrl-0: the phandle of the gpio pin node.
  70 +- brcm,smi-clock-source: the clock source for clkman
  71 +- brcm,smi-clock-divisor: the integer clock divisor for clkman
  72 +- dmas: the dma controller phandle and the DREQ number (4 on a 2835)
  73 +- dma-names: the name used by the driver to request its channel.
  74 +  Should be "rx-tx".
  75 +
  76 +Optional properties:
  77 +- None.
  78 +
  79 +Examples:
  80 +
  81 +8 data pin configuration:
  82 +
  83 +smi: smi@7e600000 {
  84 +       compatible = "brcm,bcm2835-smi";
  85 +       reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>;
  86 +       interrupts = <2 16>;
  87 +       pinctrl-names = "default";
  88 +       pinctrl-0 = <&smi_pins>;
  89 +       brcm,smi-clock-source = <6>;
  90 +       brcm,smi-clock-divisor = <4>;
  91 +       dmas = <&dma 4>;
  92 +       dma-names = "rx-tx";
  93 +
  94 +       status = "okay";
  95 +};
  96 +
  97 +smi_pins: smi_pins {
  98 +       brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  99 +       /* Alt 1: SMI */
 100 +       brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>;
 101 +       /* /CS, /WE and /OE are pulled high, as they are
 102 +          generally active low signals */
 103 +       brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>;
 104 +};
 105 +
 106 --- a/drivers/char/broadcom/Kconfig
 107 +++ b/drivers/char/broadcom/Kconfig
 108 @@ -24,3 +24,12 @@ config BCM2835_DEVGPIOMEM
 109                 Provides users with root-free access to the GPIO registers
 110                 on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO
 111                 register page to the user's pointer.
 112 +
 113 +config BCM2835_SMI_DEV
 114 +       tristate "Character device driver for BCM2835 Secondary Memory Interface"
 115 +       depends on BCM2835_SMI
 116 +       default m
 117 +       help
 118 +               This driver provides a character device interface (ioctl + read/write) to
 119 +               Broadcom's Secondary Memory interface. The low-level functionality is provided
 120 +               by the SMI driver itself.
 121 --- a/drivers/char/broadcom/Makefile
 122 +++ b/drivers/char/broadcom/Makefile
 123 @@ -1,2 +1,3 @@
 124  obj-$(CONFIG_BCM2708_VCMEM)    += vc_mem.o
 125  obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o
 126 +obj-$(CONFIG_BCM2835_SMI_DEV)  += bcm2835_smi_dev.o
 127 --- /dev/null
 128 +++ b/drivers/char/broadcom/bcm2835_smi_dev.c
 129 @@ -0,0 +1,402 @@
 130 +/**
 131 + * Character device driver for Broadcom Secondary Memory Interface
 132 + *
 133 + * Written by Luke Wren <luke@raspberrypi.org>
 134 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
 135 + *
 136 + * Redistribution and use in source and binary forms, with or without
 137 + * modification, are permitted provided that the following conditions
 138 + * are met:
 139 + * 1. Redistributions of source code must retain the above copyright
 140 + *    notice, this list of conditions, and the following disclaimer,
 141 + *    without modification.
 142 + * 2. Redistributions in binary form must reproduce the above copyright
 143 + *    notice, this list of conditions and the following disclaimer in the
 144 + *    documentation and/or other materials provided with the distribution.
 145 + * 3. The names of the above-listed copyright holders may not be used
 146 + *    to endorse or promote products derived from this software without
 147 + *    specific prior written permission.
 148 + *
 149 + * ALTERNATIVELY, this software may be distributed under the terms of the
 150 + * GNU General Public License ("GPL") version 2, as published by the Free
 151 + * Software Foundation.
 152 + *
 153 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 154 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 155 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 156 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 157 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 158 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 159 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 160 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 161 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 162 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 163 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 164 + */
 165 +
 166 +#include <linux/kernel.h>
 167 +#include <linux/module.h>
 168 +#include <linux/of.h>
 169 +#include <linux/platform_device.h>
 170 +#include <linux/slab.h>
 171 +#include <linux/mm.h>
 172 +#include <linux/pagemap.h>
 173 +#include <linux/fs.h>
 174 +#include <linux/cdev.h>
 175 +#include <linux/fs.h>
 176 +
 177 +#include <linux/broadcom/bcm2835_smi.h>
 178 +
 179 +#define DEVICE_NAME "bcm2835-smi-dev"
 180 +#define DRIVER_NAME "smi-dev-bcm2835"
 181 +#define DEVICE_MINOR 0
 182 +
 183 +static struct cdev bcm2835_smi_cdev;
 184 +static dev_t bcm2835_smi_devid;
 185 +static struct class *bcm2835_smi_class;
 186 +static struct device *bcm2835_smi_dev;
 187 +
 188 +struct bcm2835_smi_dev_instance {
 189 +       struct device *dev;
 190 +};
 191 +
 192 +static struct bcm2835_smi_instance *smi_inst;
 193 +static struct bcm2835_smi_dev_instance *inst;
 194 +
 195 +static const char *const ioctl_names[] = {
 196 +       "READ_SETTINGS",
 197 +       "WRITE_SETTINGS",
 198 +       "ADDRESS"
 199 +};
 200 +
 201 +/****************************************************************************
 202 +*
 203 +*   SMI chardev file ops
 204 +*
 205 +***************************************************************************/
 206 +static long
 207 +bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 208 +{
 209 +       long ret = 0;
 210 +
 211 +       dev_info(inst->dev, "serving ioctl...");
 212 +
 213 +       switch (cmd) {
 214 +       case BCM2835_SMI_IOC_GET_SETTINGS:{
 215 +               struct smi_settings *settings;
 216 +
 217 +               dev_info(inst->dev, "Reading SMI settings to user.");
 218 +               settings = bcm2835_smi_get_settings_from_regs(smi_inst);
 219 +               if (copy_to_user((void *)arg, settings,
 220 +                                sizeof(struct smi_settings)))
 221 +                       dev_err(inst->dev, "settings copy failed.");
 222 +               break;
 223 +       }
 224 +       case BCM2835_SMI_IOC_WRITE_SETTINGS:{
 225 +               struct smi_settings *settings;
 226 +
 227 +               dev_info(inst->dev, "Setting user's SMI settings.");
 228 +               settings = bcm2835_smi_get_settings_from_regs(smi_inst);
 229 +               if (copy_from_user(settings, (void *)arg,
 230 +                                  sizeof(struct smi_settings)))
 231 +                       dev_err(inst->dev, "settings copy failed.");
 232 +               else
 233 +                       bcm2835_smi_set_regs_from_settings(smi_inst);
 234 +               break;
 235 +       }
 236 +       case BCM2835_SMI_IOC_ADDRESS:
 237 +               dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg);
 238 +               bcm2835_smi_set_address(smi_inst, arg);
 239 +               break;
 240 +       default:
 241 +               dev_err(inst->dev, "invalid ioctl cmd: %d", cmd);
 242 +               ret = -ENOTTY;
 243 +               break;
 244 +       }
 245 +
 246 +       return ret;
 247 +}
 248 +
 249 +static int bcm2835_smi_open(struct inode *inode, struct file *file)
 250 +{
 251 +       int dev = iminor(inode);
 252 +
 253 +       dev_dbg(inst->dev, "SMI device opened.");
 254 +
 255 +       if (dev != DEVICE_MINOR) {
 256 +               dev_err(inst->dev,
 257 +                       "bcm2835_smi_release: Unknown minor device: %d",
 258 +                       dev);
 259 +               return -ENXIO;
 260 +       }
 261 +
 262 +       return 0;
 263 +}
 264 +
 265 +static int bcm2835_smi_release(struct inode *inode, struct file *file)
 266 +{
 267 +       int dev = iminor(inode);
 268 +
 269 +       if (dev != DEVICE_MINOR) {
 270 +               dev_err(inst->dev,
 271 +                       "bcm2835_smi_release: Unknown minor device %d", dev);
 272 +               return -ENXIO;
 273 +       }
 274 +
 275 +       return 0;
 276 +}
 277 +
 278 +static ssize_t dma_bounce_user(
 279 +       enum dma_transfer_direction dma_dir,
 280 +       char __user *user_ptr,
 281 +       size_t count,
 282 +       struct bcm2835_smi_bounce_info *bounce)
 283 +{
 284 +       int chunk_size;
 285 +       int chunk_no = 0;
 286 +       int count_left = count;
 287 +
 288 +       while (count_left) {
 289 +               int rv;
 290 +               void *buf;
 291 +
 292 +               /* Wait for current chunk to complete: */
 293 +               if (down_timeout(&bounce->callback_sem,
 294 +                       msecs_to_jiffies(1000))) {
 295 +                       dev_err(inst->dev, "DMA bounce timed out");
 296 +                       count -= (count_left);
 297 +                       break;
 298 +               }
 299 +
 300 +               if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1)
 301 +                       dev_err(inst->dev, "WARNING: Ring buffer overflow");
 302 +               chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
 303 +                       DMA_BOUNCE_BUFFER_SIZE : count_left;
 304 +               buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
 305 +               if (dma_dir == DMA_DEV_TO_MEM)
 306 +                       rv = copy_to_user(user_ptr, buf, chunk_size);
 307 +               else
 308 +                       rv = copy_from_user(buf, user_ptr, chunk_size);
 309 +               if (rv)
 310 +                       dev_err(inst->dev, "copy_*_user() failed!: %d", rv);
 311 +               user_ptr += chunk_size;
 312 +               count_left -= chunk_size;
 313 +               chunk_no++;
 314 +       }
 315 +       return count;
 316 +}
 317 +
 318 +static ssize_t
 319 +bcm2835_read_file(struct file *f, char __user *user_ptr,
 320 +                 size_t count, loff_t *offs)
 321 +{
 322 +       int odd_bytes;
 323 +
 324 +       dev_dbg(inst->dev, "User reading %zu bytes from SMI.", count);
 325 +       /* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */
 326 +       if (count > DMA_THRESHOLD_BYTES)
 327 +               odd_bytes = count & 0x3;
 328 +       else
 329 +               odd_bytes = count;
 330 +       count -= odd_bytes;
 331 +       if (count) {
 332 +               struct bcm2835_smi_bounce_info *bounce;
 333 +
 334 +               count = bcm2835_smi_user_dma(smi_inst,
 335 +                       DMA_DEV_TO_MEM, user_ptr, count,
 336 +                       &bounce);
 337 +               if (count)
 338 +                       count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr,
 339 +                               count, bounce);
 340 +       }
 341 +       if (odd_bytes) {
 342 +               /* Read from FIFO directly if not using DMA */
 343 +               uint8_t buf[DMA_THRESHOLD_BYTES];
 344 +
 345 +               bcm2835_smi_read_buf(smi_inst, buf, odd_bytes);
 346 +               if (copy_to_user(user_ptr, buf, odd_bytes))
 347 +                       dev_err(inst->dev, "copy_to_user() failed.");
 348 +               count += odd_bytes;
 349 +
 350 +       }
 351 +       return count;
 352 +}
 353 +
 354 +static ssize_t
 355 +bcm2835_write_file(struct file *f, const char __user *user_ptr,
 356 +                  size_t count, loff_t *offs)
 357 +{
 358 +       int odd_bytes;
 359 +
 360 +       dev_dbg(inst->dev, "User writing %zu bytes to SMI.", count);
 361 +       if (count > DMA_THRESHOLD_BYTES)
 362 +               odd_bytes = count & 0x3;
 363 +       else
 364 +               odd_bytes = count;
 365 +       count -= odd_bytes;
 366 +       if (count) {
 367 +               struct bcm2835_smi_bounce_info *bounce;
 368 +
 369 +               count = bcm2835_smi_user_dma(smi_inst,
 370 +                       DMA_MEM_TO_DEV, (char __user *)user_ptr, count,
 371 +                       &bounce);
 372 +               if (count)
 373 +                       count = dma_bounce_user(DMA_MEM_TO_DEV,
 374 +                               (char __user *)user_ptr,
 375 +                               count, bounce);
 376 +       }
 377 +       if (odd_bytes) {
 378 +               uint8_t buf[DMA_THRESHOLD_BYTES];
 379 +
 380 +               if (copy_from_user(buf, user_ptr, odd_bytes))
 381 +                       dev_err(inst->dev, "copy_from_user() failed.");
 382 +               else
 383 +                       bcm2835_smi_write_buf(smi_inst, buf, odd_bytes);
 384 +               count += odd_bytes;
 385 +       }
 386 +       return count;
 387 +}
 388 +
 389 +static const struct file_operations
 390 +bcm2835_smi_fops = {
 391 +       .owner = THIS_MODULE,
 392 +       .unlocked_ioctl = bcm2835_smi_ioctl,
 393 +       .open = bcm2835_smi_open,
 394 +       .release = bcm2835_smi_release,
 395 +       .read = bcm2835_read_file,
 396 +       .write = bcm2835_write_file,
 397 +};
 398 +
 399 +
 400 +/****************************************************************************
 401 +*
 402 +*   bcm2835_smi_probe - called when the driver is loaded.
 403 +*
 404 +***************************************************************************/
 405 +
 406 +static int bcm2835_smi_dev_probe(struct platform_device *pdev)
 407 +{
 408 +       int err;
 409 +       void *ptr_err;
 410 +       struct device *dev = &pdev->dev;
 411 +       struct device_node *node = dev->of_node, *smi_node;
 412 +
 413 +       if (!node) {
 414 +               dev_err(dev, "No device tree node supplied!");
 415 +               return -EINVAL;
 416 +       }
 417 +
 418 +       smi_node = of_parse_phandle(node, "smi_handle", 0);
 419 +
 420 +       if (!smi_node) {
 421 +               dev_err(dev, "No such property: smi_handle");
 422 +               return -ENXIO;
 423 +       }
 424 +
 425 +       smi_inst = bcm2835_smi_get(smi_node);
 426 +
 427 +       if (!smi_inst)
 428 +               return -EPROBE_DEFER;
 429 +
 430 +       /* Allocate buffers and instance data */
 431 +
 432 +       inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
 433 +
 434 +       if (!inst)
 435 +               return -ENOMEM;
 436 +
 437 +       inst->dev = dev;
 438 +
 439 +       /* Create character device entries */
 440 +
 441 +       err = alloc_chrdev_region(&bcm2835_smi_devid,
 442 +                                 DEVICE_MINOR, 1, DEVICE_NAME);
 443 +       if (err != 0) {
 444 +               dev_err(inst->dev, "unable to allocate device number");
 445 +               return -ENOMEM;
 446 +       }
 447 +       cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops);
 448 +       bcm2835_smi_cdev.owner = THIS_MODULE;
 449 +       err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1);
 450 +       if (err != 0) {
 451 +               dev_err(inst->dev, "unable to register device");
 452 +               err = -ENOMEM;
 453 +               goto failed_cdev_add;
 454 +       }
 455 +
 456 +       /* Create sysfs entries */
 457 +
 458 +       bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME);
 459 +       ptr_err = bcm2835_smi_class;
 460 +       if (IS_ERR(ptr_err))
 461 +               goto failed_class_create;
 462 +
 463 +       bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL,
 464 +                                       bcm2835_smi_devid, NULL,
 465 +                                       "smi");
 466 +       ptr_err = bcm2835_smi_dev;
 467 +       if (IS_ERR(ptr_err))
 468 +               goto failed_device_create;
 469 +
 470 +       dev_info(inst->dev, "initialised");
 471 +
 472 +       return 0;
 473 +
 474 +failed_device_create:
 475 +       class_destroy(bcm2835_smi_class);
 476 +failed_class_create:
 477 +       cdev_del(&bcm2835_smi_cdev);
 478 +       err = PTR_ERR(ptr_err);
 479 +failed_cdev_add:
 480 +       unregister_chrdev_region(bcm2835_smi_devid, 1);
 481 +       dev_err(dev, "could not load bcm2835_smi_dev");
 482 +       return err;
 483 +}
 484 +
 485 +/****************************************************************************
 486 +*
 487 +*   bcm2835_smi_remove - called when the driver is unloaded.
 488 +*
 489 +***************************************************************************/
 490 +
 491 +static int bcm2835_smi_dev_remove(struct platform_device *pdev)
 492 +{
 493 +       device_destroy(bcm2835_smi_class, bcm2835_smi_devid);
 494 +       class_destroy(bcm2835_smi_class);
 495 +       cdev_del(&bcm2835_smi_cdev);
 496 +       unregister_chrdev_region(bcm2835_smi_devid, 1);
 497 +
 498 +       dev_info(inst->dev, "SMI character dev removed - OK");
 499 +       return 0;
 500 +}
 501 +
 502 +/****************************************************************************
 503 +*
 504 +*   Register the driver with device tree
 505 +*
 506 +***************************************************************************/
 507 +
 508 +static const struct of_device_id bcm2835_smi_dev_of_match[] = {
 509 +       {.compatible = "brcm,bcm2835-smi-dev",},
 510 +       { /* sentinel */ },
 511 +};
 512 +
 513 +MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match);
 514 +
 515 +static struct platform_driver bcm2835_smi_dev_driver = {
 516 +       .probe = bcm2835_smi_dev_probe,
 517 +       .remove = bcm2835_smi_dev_remove,
 518 +       .driver = {
 519 +                  .name = DRIVER_NAME,
 520 +                  .owner = THIS_MODULE,
 521 +                  .of_match_table = bcm2835_smi_dev_of_match,
 522 +                  },
 523 +};
 524 +
 525 +module_platform_driver(bcm2835_smi_dev_driver);
 526 +
 527 +MODULE_ALIAS("platform:smi-dev-bcm2835");
 528 +MODULE_LICENSE("GPL");
 529 +MODULE_DESCRIPTION(
 530 +       "Character device driver for BCM2835's secondary memory interface");
 531 +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
 532 --- a/drivers/misc/Kconfig
 533 +++ b/drivers/misc/Kconfig
 534 @@ -9,6 +9,14 @@ config SENSORS_LIS3LV02D
 535         tristate
 536         depends on INPUT
 537
 538 +config BCM2835_SMI
 539 +       tristate "Broadcom 283x Secondary Memory Interface driver"
 540 +       depends on ARCH_BCM2835
 541 +       default m
 542 +       help
 543 +               Driver for enabling and using Broadcom's Secondary/Slow Memory Interface.
 544 +               Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h
 545 +
 546  config AD525X_DPOT
 547         tristate "Analog Devices Digital Potentiometers"
 548         depends on (I2C || SPI) && SYSFS
 549 --- a/drivers/misc/Makefile
 550 +++ b/drivers/misc/Makefile
 551 @@ -9,6 +9,7 @@ obj-$(CONFIG_AD525X_DPOT)       += ad525x_dpot
 552  obj-$(CONFIG_AD525X_DPOT_I2C)  += ad525x_dpot-i2c.o
 553  obj-$(CONFIG_AD525X_DPOT_SPI)  += ad525x_dpot-spi.o
 554  obj-$(CONFIG_ATMEL_SSC)                += atmel-ssc.o
 555 +obj-$(CONFIG_BCM2835_SMI)      += bcm2835_smi.o
 556  obj-$(CONFIG_DUMMY_IRQ)                += dummy-irq.o
 557  obj-$(CONFIG_ICS932S401)       += ics932s401.o
 558  obj-$(CONFIG_LKDTM)            += lkdtm/
 559 --- /dev/null
 560 +++ b/drivers/misc/bcm2835_smi.c
 561 @@ -0,0 +1,955 @@
 562 +/**
 563 + * Broadcom Secondary Memory Interface driver
 564 + *
 565 + * Written by Luke Wren <luke@raspberrypi.org>
 566 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
 567 + *
 568 + * Redistribution and use in source and binary forms, with or without
 569 + * modification, are permitted provided that the following conditions
 570 + * are met:
 571 + * 1. Redistributions of source code must retain the above copyright
 572 + *    notice, this list of conditions, and the following disclaimer,
 573 + *    without modification.
 574 + * 2. Redistributions in binary form must reproduce the above copyright
 575 + *    notice, this list of conditions and the following disclaimer in the
 576 + *    documentation and/or other materials provided with the distribution.
 577 + * 3. The names of the above-listed copyright holders may not be used
 578 + *    to endorse or promote products derived from this software without
 579 + *    specific prior written permission.
 580 + *
 581 + * ALTERNATIVELY, this software may be distributed under the terms of the
 582 + * GNU General Public License ("GPL") version 2, as published by the Free
 583 + * Software Foundation.
 584 + *
 585 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 586 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 587 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 588 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 589 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 590 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 591 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 592 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 593 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 594 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 595 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 596 + */
 597 +
 598 +#include <linux/clk.h>
 599 +#include <linux/kernel.h>
 600 +#include <linux/module.h>
 601 +#include <linux/of.h>
 602 +#include <linux/platform_device.h>
 603 +#include <linux/of_address.h>
 604 +#include <linux/of_platform.h>
 605 +#include <linux/mm.h>
 606 +#include <linux/slab.h>
 607 +#include <linux/pagemap.h>
 608 +#include <linux/dma-mapping.h>
 609 +#include <linux/dmaengine.h>
 610 +#include <linux/semaphore.h>
 611 +#include <linux/spinlock.h>
 612 +#include <linux/io.h>
 613 +
 614 +#define BCM2835_SMI_IMPLEMENTATION
 615 +#include <linux/broadcom/bcm2835_smi.h>
 616 +
 617 +#define DRIVER_NAME "smi-bcm2835"
 618 +
 619 +#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE)
 620 +
 621 +#define DMA_WRITE_TO_MEM true
 622 +#define DMA_READ_FROM_MEM false
 623 +
 624 +struct bcm2835_smi_instance {
 625 +       struct device *dev;
 626 +       struct smi_settings settings;
 627 +       __iomem void *smi_regs_ptr;
 628 +       dma_addr_t smi_regs_busaddr;
 629 +
 630 +       struct dma_chan *dma_chan;
 631 +       struct dma_slave_config dma_config;
 632 +
 633 +       struct bcm2835_smi_bounce_info bounce;
 634 +
 635 +       struct scatterlist buffer_sgl;
 636 +
 637 +       struct clk *clk;
 638 +
 639 +       /* Sometimes we are called into in an atomic context (e.g. by
 640 +          JFFS2 + MTD) so we can't use a mutex */
 641 +       spinlock_t transaction_lock;
 642 +};
 643 +
 644 +/****************************************************************************
 645 +*
 646 +*   SMI peripheral setup
 647 +*
 648 +***************************************************************************/
 649 +
 650 +static inline void write_smi_reg(struct bcm2835_smi_instance *inst,
 651 +       u32 val, unsigned reg)
 652 +{
 653 +       writel(val, inst->smi_regs_ptr + reg);
 654 +}
 655 +
 656 +static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg)
 657 +{
 658 +       return readl(inst->smi_regs_ptr + reg);
 659 +}
 660 +
 661 +/* Token-paste macro for e.g SMIDSR_RSTROBE ->  value of SMIDSR_RSTROBE_MASK */
 662 +#define _CONCAT(x, y) x##y
 663 +#define CONCAT(x, y) _CONCAT(x, y)
 664 +
 665 +#define SET_BIT_FIELD(dest, field, bits) ((dest) = \
 666 +       ((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \
 667 +        CONCAT(field, _MASK)))
 668 +#define GET_BIT_FIELD(src, field) (((src) & \
 669 +       CONCAT(field, _MASK)) >> CONCAT(field, _OFFS))
 670 +
 671 +static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst,
 672 +       const char *label)
 673 +{
 674 +       dev_err(inst->dev, "SMI context dump: %s", label);
 675 +       dev_err(inst->dev, "SMICS:  0x%08x", read_smi_reg(inst, SMICS));
 676 +       dev_err(inst->dev, "SMIL:   0x%08x", read_smi_reg(inst, SMIL));
 677 +       dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0));
 678 +       dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0));
 679 +       dev_err(inst->dev, "SMIDC:  0x%08x", read_smi_reg(inst, SMIDC));
 680 +       dev_err(inst->dev, "SMIFD:  0x%08x", read_smi_reg(inst, SMIFD));
 681 +       dev_err(inst->dev, " ");
 682 +}
 683 +
 684 +static inline void smi_dump_context(struct bcm2835_smi_instance *inst)
 685 +{
 686 +       smi_dump_context_labelled(inst, "");
 687 +}
 688 +
 689 +static void smi_get_default_settings(struct bcm2835_smi_instance *inst)
 690 +{
 691 +       struct smi_settings *settings = &inst->settings;
 692 +
 693 +       settings->data_width = SMI_WIDTH_16BIT;
 694 +       settings->pack_data = true;
 695 +
 696 +       settings->read_setup_time = 1;
 697 +       settings->read_hold_time = 1;
 698 +       settings->read_pace_time = 1;
 699 +       settings->read_strobe_time = 3;
 700 +
 701 +       settings->write_setup_time = settings->read_setup_time;
 702 +       settings->write_hold_time = settings->read_hold_time;
 703 +       settings->write_pace_time = settings->read_pace_time;
 704 +       settings->write_strobe_time = settings->read_strobe_time;
 705 +
 706 +       settings->dma_enable = true;
 707 +       settings->dma_passthrough_enable = false;
 708 +       settings->dma_read_thresh = 0x01;
 709 +       settings->dma_write_thresh = 0x3f;
 710 +       settings->dma_panic_read_thresh = 0x20;
 711 +       settings->dma_panic_write_thresh = 0x20;
 712 +}
 713 +
 714 +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst)
 715 +{
 716 +       struct smi_settings *settings = &inst->settings;
 717 +       int smidsr_temp = 0, smidsw_temp = 0, smics_temp,
 718 +           smidcs_temp, smidc_temp = 0;
 719 +
 720 +       spin_lock(&inst->transaction_lock);
 721 +
 722 +       /* temporarily disable the peripheral: */
 723 +       smics_temp = read_smi_reg(inst, SMICS);
 724 +       write_smi_reg(inst, 0, SMICS);
 725 +       smidcs_temp = read_smi_reg(inst, SMIDCS);
 726 +       write_smi_reg(inst, 0, SMIDCS);
 727 +
 728 +       if (settings->pack_data)
 729 +               smics_temp |= SMICS_PXLDAT;
 730 +       else
 731 +               smics_temp &= ~SMICS_PXLDAT;
 732 +
 733 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width);
 734 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time);
 735 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time);
 736 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time);
 737 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time);
 738 +       write_smi_reg(inst, smidsr_temp, SMIDSR0);
 739 +
 740 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width);
 741 +       if (settings->data_width == SMI_WIDTH_8BIT)
 742 +               smidsw_temp |= SMIDSW_WSWAP;
 743 +       else
 744 +               smidsw_temp &= ~SMIDSW_WSWAP;
 745 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time);
 746 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time);
 747 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time);
 748 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE,
 749 +                       settings->write_strobe_time);
 750 +       write_smi_reg(inst, smidsw_temp, SMIDSW0);
 751 +
 752 +       SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh);
 753 +       SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh);
 754 +       SET_BIT_FIELD(smidc_temp, SMIDC_PANICR,
 755 +                     settings->dma_panic_read_thresh);
 756 +       SET_BIT_FIELD(smidc_temp, SMIDC_PANICW,
 757 +                     settings->dma_panic_write_thresh);
 758 +       if (settings->dma_passthrough_enable) {
 759 +               smidc_temp |= SMIDC_DMAP;
 760 +               smidsr_temp |= SMIDSR_RDREQ;
 761 +               write_smi_reg(inst, smidsr_temp, SMIDSR0);
 762 +               smidsw_temp |= SMIDSW_WDREQ;
 763 +               write_smi_reg(inst, smidsw_temp, SMIDSW0);
 764 +       } else
 765 +               smidc_temp &= ~SMIDC_DMAP;
 766 +       if (settings->dma_enable)
 767 +               smidc_temp |= SMIDC_DMAEN;
 768 +       else
 769 +               smidc_temp &= ~SMIDC_DMAEN;
 770 +
 771 +       write_smi_reg(inst, smidc_temp, SMIDC);
 772 +
 773 +       /* re-enable (if was previously enabled) */
 774 +       write_smi_reg(inst, smics_temp, SMICS);
 775 +       write_smi_reg(inst, smidcs_temp, SMIDCS);
 776 +
 777 +       spin_unlock(&inst->transaction_lock);
 778 +}
 779 +EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings);
 780 +
 781 +struct smi_settings *bcm2835_smi_get_settings_from_regs
 782 +       (struct bcm2835_smi_instance *inst)
 783 +{
 784 +       struct smi_settings *settings = &inst->settings;
 785 +       int smidsr, smidsw, smidc;
 786 +
 787 +       spin_lock(&inst->transaction_lock);
 788 +
 789 +       smidsr = read_smi_reg(inst, SMIDSR0);
 790 +       smidsw = read_smi_reg(inst, SMIDSW0);
 791 +       smidc = read_smi_reg(inst, SMIDC);
 792 +
 793 +       settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ?
 794 +           true : false;
 795 +
 796 +       settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH);
 797 +       settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP);
 798 +       settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD);
 799 +       settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE);
 800 +       settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE);
 801 +
 802 +       settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP);
 803 +       settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD);
 804 +       settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE);
 805 +       settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE);
 806 +
 807 +       settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR);
 808 +       settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW);
 809 +       settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR);
 810 +       settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW);
 811 +       settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false;
 812 +       settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false;
 813 +
 814 +       spin_unlock(&inst->transaction_lock);
 815 +
 816 +       return settings;
 817 +}
 818 +EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs);
 819 +
 820 +static inline void smi_set_address(struct bcm2835_smi_instance *inst,
 821 +       unsigned int address)
 822 +{
 823 +       int smia_temp = 0, smida_temp = 0;
 824 +
 825 +       SET_BIT_FIELD(smia_temp, SMIA_ADDR, address);
 826 +       SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address);
 827 +
 828 +       /* Write to both address registers - user doesn't care whether we're
 829 +          doing programmed or direct transfers. */
 830 +       write_smi_reg(inst, smia_temp, SMIA);
 831 +       write_smi_reg(inst, smida_temp, SMIDA);
 832 +}
 833 +
 834 +static void smi_setup_regs(struct bcm2835_smi_instance *inst)
 835 +{
 836 +
 837 +       dev_dbg(inst->dev, "Initialising SMI registers...");
 838 +       /* Disable the peripheral if already enabled */
 839 +       write_smi_reg(inst, 0, SMICS);
 840 +       write_smi_reg(inst, 0, SMIDCS);
 841 +
 842 +       smi_get_default_settings(inst);
 843 +       bcm2835_smi_set_regs_from_settings(inst);
 844 +       smi_set_address(inst, 0);
 845 +
 846 +       write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS);
 847 +       write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE,
 848 +               SMIDCS);
 849 +}
 850 +
 851 +/****************************************************************************
 852 +*
 853 +*   Low-level SMI access functions
 854 +*   Other modules should use the exported higher-level functions e.g.
 855 +*   bcm2835_smi_write_buf() unless they have a good reason to use these
 856 +*
 857 +***************************************************************************/
 858 +
 859 +static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst)
 860 +{
 861 +       int timeout = 0;
 862 +
 863 +       write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS);
 864 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS);
 865 +       /* Make sure things happen in the right order...*/
 866 +       mb();
 867 +       while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
 868 +               ++timeout < 10000)
 869 +               ;
 870 +       if (timeout < 10000)
 871 +               return read_smi_reg(inst, SMIDD);
 872 +
 873 +       dev_err(inst->dev,
 874 +               "SMI direct read timed out (is the clock set up correctly?)");
 875 +       return 0;
 876 +}
 877 +
 878 +static inline void smi_write_single_word(struct bcm2835_smi_instance *inst,
 879 +       uint32_t data)
 880 +{
 881 +       int timeout = 0;
 882 +
 883 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS);
 884 +       write_smi_reg(inst, data, SMIDD);
 885 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START,
 886 +               SMIDCS);
 887 +
 888 +       while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
 889 +               ++timeout < 10000)
 890 +               ;
 891 +       if (timeout >= 10000)
 892 +               dev_err(inst->dev,
 893 +               "SMI direct write timed out (is the clock set up correctly?)");
 894 +}
 895 +
 896 +/* Initiates a programmed read into the read FIFO. It is up to the caller to
 897 + * read data from the FIFO -  either via paced DMA transfer,
 898 + * or polling SMICS_RXD to check whether data is available.
 899 + * SMICS_ACTIVE will go low upon completion. */
 900 +static void smi_init_programmed_read(struct bcm2835_smi_instance *inst,
 901 +       int num_transfers)
 902 +{
 903 +       int smics_temp;
 904 +
 905 +       /* Disable the peripheral: */
 906 +       smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE);
 907 +       write_smi_reg(inst, smics_temp, SMICS);
 908 +       while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
 909 +               ;
 910 +
 911 +       /* Program the transfer count: */
 912 +       write_smi_reg(inst, num_transfers, SMIL);
 913 +
 914 +       /* re-enable and start: */
 915 +       smics_temp |= SMICS_ENABLE;
 916 +       write_smi_reg(inst, smics_temp, SMICS);
 917 +       smics_temp |= SMICS_CLEAR;
 918 +       /* Just to be certain: */
 919 +       mb();
 920 +       while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
 921 +               ;
 922 +       write_smi_reg(inst, smics_temp, SMICS);
 923 +       smics_temp |= SMICS_START;
 924 +       write_smi_reg(inst, smics_temp, SMICS);
 925 +}
 926 +
 927 +/* Initiates a programmed write sequence, using data from the write FIFO.
 928 + * It is up to the caller to initiate a DMA transfer before calling,
 929 + * or use another method to keep the write FIFO topped up.
 930 + * SMICS_ACTIVE will go low upon completion.
 931 + */
 932 +static void smi_init_programmed_write(struct bcm2835_smi_instance *inst,
 933 +       int num_transfers)
 934 +{
 935 +       int smics_temp;
 936 +
 937 +       /* Disable the peripheral: */
 938 +       smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
 939 +       write_smi_reg(inst, smics_temp, SMICS);
 940 +       while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
 941 +               ;
 942 +
 943 +       /* Program the transfer count: */
 944 +       write_smi_reg(inst, num_transfers, SMIL);
 945 +
 946 +       /* setup, re-enable and start: */
 947 +       smics_temp |= SMICS_WRITE | SMICS_ENABLE;
 948 +       write_smi_reg(inst, smics_temp, SMICS);
 949 +       smics_temp |= SMICS_START;
 950 +       write_smi_reg(inst, smics_temp, SMICS);
 951 +}
 952 +
 953 +/* Initiate a read and then poll FIFO for data, reading out as it appears. */
 954 +static void smi_read_fifo(struct bcm2835_smi_instance *inst,
 955 +       uint32_t *dest, int n_bytes)
 956 +{
 957 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
 958 +               smi_dump_context_labelled(inst,
 959 +                       "WARNING: read FIFO not empty at start of read call.");
 960 +               while (read_smi_reg(inst, SMICS))
 961 +                       ;
 962 +       }
 963 +
 964 +       /* Dispatch the read: */
 965 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
 966 +               smi_init_programmed_read(inst, n_bytes);
 967 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
 968 +               smi_init_programmed_read(inst, n_bytes / 2);
 969 +       else {
 970 +               dev_err(inst->dev, "Unsupported data width for read.");
 971 +               return;
 972 +       }
 973 +
 974 +       /* Poll FIFO to keep it empty */
 975 +       while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
 976 +               if (read_smi_reg(inst, SMICS) & SMICS_RXD)
 977 +                       *dest++ = read_smi_reg(inst, SMID);
 978 +
 979 +       /* Ensure that the FIFO is emptied */
 980 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
 981 +               int fifo_count;
 982 +
 983 +               fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD),
 984 +                       SMIFD_FCNT);
 985 +               while (fifo_count--)
 986 +                       *dest++ = read_smi_reg(inst, SMID);
 987 +       }
 988 +
 989 +       if (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
 990 +               smi_dump_context_labelled(inst,
 991 +                       "WARNING: transaction finished but done bit not set.");
 992 +
 993 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD)
 994 +               smi_dump_context_labelled(inst,
 995 +                       "WARNING: read FIFO not empty at end of read call.");
 996 +
 997 +}
 998 +
 999 +/* Initiate a write, and then keep the FIFO topped up. */
1000 +static void smi_write_fifo(struct bcm2835_smi_instance *inst,
1001 +       uint32_t *src, int n_bytes)
1002 +{
1003 +       int i, timeout = 0;
1004 +
1005 +       /* Empty FIFOs if not already so */
1006 +       if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) {
1007 +               smi_dump_context_labelled(inst,
1008 +                   "WARNING: write fifo not empty at start of write call.");
1009 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR,
1010 +                       SMICS);
1011 +       }
1012 +
1013 +       /* Initiate the transfer */
1014 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1015 +               smi_init_programmed_write(inst, n_bytes);
1016 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1017 +               smi_init_programmed_write(inst, n_bytes / 2);
1018 +       else {
1019 +               dev_err(inst->dev, "Unsupported data width for write.");
1020 +               return;
1021 +       }
1022 +       /* Fill the FIFO: */
1023 +       for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) {
1024 +               while (!(read_smi_reg(inst, SMICS) & SMICS_TXD))
1025 +                       ;
1026 +               write_smi_reg(inst, *src++, SMID);
1027 +       }
1028 +       /* Busy wait... */
1029 +       while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout <
1030 +               1000000)
1031 +               ;
1032 +       if (timeout >= 1000000)
1033 +               smi_dump_context_labelled(inst,
1034 +                       "Timed out on write operation!");
1035 +       if (!(read_smi_reg(inst, SMICS) & SMICS_TXE))
1036 +               smi_dump_context_labelled(inst,
1037 +                       "WARNING: FIFO not empty at end of write operation.");
1038 +}
1039 +
1040 +/****************************************************************************
1041 +*
1042 +*   SMI DMA operations
1043 +*
1044 +***************************************************************************/
1045 +
1046 +/* Disable SMI and put it into the correct direction before doing DMA setup.
1047 +   Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */
1048 +static void smi_disable(struct bcm2835_smi_instance *inst,
1049 +       enum dma_transfer_direction direction)
1050 +{
1051 +       int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
1052 +
1053 +       if (direction == DMA_DEV_TO_MEM)
1054 +               smics_temp &= ~SMICS_WRITE;
1055 +       else
1056 +               smics_temp |= SMICS_WRITE;
1057 +       write_smi_reg(inst, smics_temp, SMICS);
1058 +       while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
1059 +               ;
1060 +}
1061 +
1062 +static struct scatterlist *smi_scatterlist_from_buffer(
1063 +       struct bcm2835_smi_instance *inst,
1064 +       dma_addr_t buf,
1065 +       size_t len,
1066 +       struct scatterlist *sg)
1067 +{
1068 +       sg_init_table(sg, 1);
1069 +       sg_dma_address(sg) = buf;
1070 +       sg_dma_len(sg) = len;
1071 +       return sg;
1072 +}
1073 +
1074 +static void smi_dma_callback_user_copy(void *param)
1075 +{
1076 +       /* Notify the bottom half that a chunk is ready for user copy */
1077 +       struct bcm2835_smi_instance *inst =
1078 +               (struct bcm2835_smi_instance *)param;
1079 +
1080 +       up(&inst->bounce.callback_sem);
1081 +}
1082 +
1083 +/* Creates a descriptor, assigns the given callback, and submits the
1084 +   descriptor to dmaengine. Does not block - can queue up multiple
1085 +   descriptors and then wait for them all to complete.
1086 +   sg_len is the number of control blocks, NOT the number of bytes.
1087 +   dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM.
1088 +   callback can be NULL - in this case it is not called. */
1089 +static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl(
1090 +       struct bcm2835_smi_instance *inst,
1091 +       struct scatterlist *sgl,
1092 +       size_t sg_len,
1093 +       enum dma_transfer_direction dir,
1094 +       dma_async_tx_callback callback)
1095 +{
1096 +       struct dma_async_tx_descriptor *desc;
1097 +
1098 +       desc = dmaengine_prep_slave_sg(inst->dma_chan,
1099 +                                      sgl,
1100 +                                      sg_len,
1101 +                                      dir,
1102 +                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK |
1103 +                                      DMA_PREP_FENCE);
1104 +       if (!desc) {
1105 +               dev_err(inst->dev, "read_sgl: dma slave preparation failed!");
1106 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE,
1107 +                       SMICS);
1108 +               while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
1109 +                       cpu_relax();
1110 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE,
1111 +                       SMICS);
1112 +               return NULL;
1113 +       }
1114 +       desc->callback = callback;
1115 +       desc->callback_param = inst;
1116 +       if (dmaengine_submit(desc) < 0)
1117 +               return NULL;
1118 +       return desc;
1119 +}
1120 +
1121 +/* NB this function blocks until the transfer is complete */
1122 +static void
1123 +smi_dma_read_sgl(struct bcm2835_smi_instance *inst,
1124 +       struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
1125 +{
1126 +       struct dma_async_tx_descriptor *desc;
1127 +
1128 +       /* Disable SMI and set to read before dispatching DMA - if SMI is in
1129 +        * write mode and TX fifo is empty, it will generate a DREQ which may
1130 +        * cause the read DMA to complete before the SMI read command is even
1131 +        * dispatched! We want to dispatch DMA before SMI read so that reading
1132 +        * is gapless, for logic analyser.
1133 +        */
1134 +
1135 +       smi_disable(inst, DMA_DEV_TO_MEM);
1136 +
1137 +       desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL);
1138 +       dma_async_issue_pending(inst->dma_chan);
1139 +
1140 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1141 +               smi_init_programmed_read(inst, n_bytes);
1142 +       else
1143 +               smi_init_programmed_read(inst, n_bytes / 2);
1144 +
1145 +       if (dma_wait_for_async_tx(desc) == DMA_ERROR)
1146 +               smi_dump_context_labelled(inst, "DMA timeout!");
1147 +}
1148 +
1149 +static void
1150 +smi_dma_write_sgl(struct bcm2835_smi_instance *inst,
1151 +       struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
1152 +{
1153 +       struct dma_async_tx_descriptor *desc;
1154 +
1155 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1156 +               smi_init_programmed_write(inst, n_bytes);
1157 +       else
1158 +               smi_init_programmed_write(inst, n_bytes / 2);
1159 +
1160 +       desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL);
1161 +       dma_async_issue_pending(inst->dma_chan);
1162 +
1163 +       if (dma_wait_for_async_tx(desc) == DMA_ERROR)
1164 +               smi_dump_context_labelled(inst, "DMA timeout!");
1165 +       else
1166 +               /* Wait for SMI to finish our writes */
1167 +               while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
1168 +                       cpu_relax();
1169 +}
1170 +
1171 +ssize_t bcm2835_smi_user_dma(
1172 +       struct bcm2835_smi_instance *inst,
1173 +       enum dma_transfer_direction dma_dir,
1174 +       char __user *user_ptr, size_t count,
1175 +       struct bcm2835_smi_bounce_info **bounce)
1176 +{
1177 +       int chunk_no = 0, chunk_size, count_left = count;
1178 +       struct scatterlist *sgl;
1179 +       void (*init_trans_func)(struct bcm2835_smi_instance *, int);
1180 +
1181 +       spin_lock(&inst->transaction_lock);
1182 +
1183 +       if (dma_dir == DMA_DEV_TO_MEM)
1184 +               init_trans_func = smi_init_programmed_read;
1185 +       else
1186 +               init_trans_func = smi_init_programmed_write;
1187 +
1188 +       smi_disable(inst, dma_dir);
1189 +
1190 +       sema_init(&inst->bounce.callback_sem, 0);
1191 +       if (bounce)
1192 +               *bounce = &inst->bounce;
1193 +       while (count_left) {
1194 +               chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
1195 +                       DMA_BOUNCE_BUFFER_SIZE : count_left;
1196 +               if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) {
1197 +                       sgl =
1198 +                       &inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
1199 +               } else {
1200 +                       sgl = smi_scatterlist_from_buffer(
1201 +                               inst,
1202 +                               inst->bounce.phys[
1203 +                                       chunk_no % DMA_BOUNCE_BUFFER_COUNT],
1204 +                               chunk_size,
1205 +                               &inst->buffer_sgl);
1206 +               }
1207 +
1208 +               if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir,
1209 +                       smi_dma_callback_user_copy
1210 +               )) {
1211 +                       dev_err(inst->dev, "sgl submit failed");
1212 +                       count = 0;
1213 +                       goto out;
1214 +               }
1215 +               count_left -= chunk_size;
1216 +               chunk_no++;
1217 +       }
1218 +       dma_async_issue_pending(inst->dma_chan);
1219 +
1220 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1221 +               init_trans_func(inst, count);
1222 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1223 +               init_trans_func(inst, count / 2);
1224 +out:
1225 +       spin_unlock(&inst->transaction_lock);
1226 +       return count;
1227 +}
1228 +EXPORT_SYMBOL(bcm2835_smi_user_dma);
1229 +
1230 +
1231 +/****************************************************************************
1232 +*
1233 +*   High level buffer transfer functions - for use by other drivers
1234 +*
1235 +***************************************************************************/
1236 +
1237 +/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */
1238 +void bcm2835_smi_write_buf(
1239 +       struct bcm2835_smi_instance *inst,
1240 +       const void *buf, size_t n_bytes)
1241 +{
1242 +       int odd_bytes = n_bytes & 0x3;
1243 +
1244 +       n_bytes -= odd_bytes;
1245 +
1246 +       spin_lock(&inst->transaction_lock);
1247 +
1248 +       if (n_bytes > DMA_THRESHOLD_BYTES) {
1249 +               dma_addr_t phy_addr = dma_map_single(
1250 +                       inst->dev,
1251 +                       (void *)buf,
1252 +                       n_bytes,
1253 +                       DMA_MEM_TO_DEV);
1254 +               struct scatterlist *sgl =
1255 +                       smi_scatterlist_from_buffer(inst, phy_addr, n_bytes,
1256 +                               &inst->buffer_sgl);
1257 +
1258 +               if (!sgl) {
1259 +                       smi_dump_context_labelled(inst,
1260 +                       "Error: could not create scatterlist for write!");
1261 +                       goto out;
1262 +               }
1263 +               smi_dma_write_sgl(inst, sgl, 1, n_bytes);
1264 +
1265 +               dma_unmap_single
1266 +                       (inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV);
1267 +       } else if (n_bytes) {
1268 +               smi_write_fifo(inst, (uint32_t *) buf, n_bytes);
1269 +       }
1270 +       buf += n_bytes;
1271 +
1272 +       if (inst->settings.data_width == SMI_WIDTH_8BIT) {
1273 +               while (odd_bytes--)
1274 +                       smi_write_single_word(inst, *(uint8_t *) (buf++));
1275 +       } else {
1276 +               while (odd_bytes >= 2) {
1277 +                       smi_write_single_word(inst, *(uint16_t *)buf);
1278 +                       buf += 2;
1279 +                       odd_bytes -= 2;
1280 +               }
1281 +               if (odd_bytes) {
1282 +                       /* Reading an odd number of bytes on a 16 bit bus is
1283 +                          a user bug. It's kinder to fail early and tell them
1284 +                          than to e.g. transparently give them the bottom byte
1285 +                          of a 16 bit transfer. */
1286 +                       dev_err(inst->dev,
1287 +               "WARNING: odd number of bytes specified for wide transfer.");
1288 +                       dev_err(inst->dev,
1289 +               "At least one byte dropped as a result.");
1290 +                       dump_stack();
1291 +               }
1292 +       }
1293 +out:
1294 +       spin_unlock(&inst->transaction_lock);
1295 +}
1296 +EXPORT_SYMBOL(bcm2835_smi_write_buf);
1297 +
1298 +void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst,
1299 +       void *buf, size_t n_bytes)
1300 +{
1301 +
1302 +       /* SMI is inherently 32-bit, which causes surprising amounts of mess
1303 +          for bytes % 4 != 0. Easiest to avoid this mess altogether
1304 +          by handling remainder separately. */
1305 +       int odd_bytes = n_bytes & 0x3;
1306 +
1307 +       spin_lock(&inst->transaction_lock);
1308 +       n_bytes -= odd_bytes;
1309 +       if (n_bytes > DMA_THRESHOLD_BYTES) {
1310 +               dma_addr_t phy_addr = dma_map_single(inst->dev,
1311 +                                                    buf, n_bytes,
1312 +                                                    DMA_DEV_TO_MEM);
1313 +               struct scatterlist *sgl = smi_scatterlist_from_buffer(
1314 +                       inst, phy_addr, n_bytes,
1315 +                       &inst->buffer_sgl);
1316 +               if (!sgl) {
1317 +                       smi_dump_context_labelled(inst,
1318 +                       "Error: could not create scatterlist for read!");
1319 +                       goto out;
1320 +               }
1321 +               smi_dma_read_sgl(inst, sgl, 1, n_bytes);
1322 +               dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM);
1323 +       } else if (n_bytes) {
1324 +               smi_read_fifo(inst, (uint32_t *)buf, n_bytes);
1325 +       }
1326 +       buf += n_bytes;
1327 +
1328 +       if (inst->settings.data_width == SMI_WIDTH_8BIT) {
1329 +               while (odd_bytes--)
1330 +                       *((uint8_t *) (buf++)) = smi_read_single_word(inst);
1331 +       } else {
1332 +               while (odd_bytes >= 2) {
1333 +                       *(uint16_t *) buf = smi_read_single_word(inst);
1334 +                       buf += 2;
1335 +                       odd_bytes -= 2;
1336 +               }
1337 +               if (odd_bytes) {
1338 +                       dev_err(inst->dev,
1339 +               "WARNING: odd number of bytes specified for wide transfer.");
1340 +                       dev_err(inst->dev,
1341 +               "At least one byte dropped as a result.");
1342 +                       dump_stack();
1343 +               }
1344 +       }
1345 +out:
1346 +       spin_unlock(&inst->transaction_lock);
1347 +}
1348 +EXPORT_SYMBOL(bcm2835_smi_read_buf);
1349 +
1350 +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
1351 +       unsigned int address)
1352 +{
1353 +       spin_lock(&inst->transaction_lock);
1354 +       smi_set_address(inst, address);
1355 +       spin_unlock(&inst->transaction_lock);
1356 +}
1357 +EXPORT_SYMBOL(bcm2835_smi_set_address);
1358 +
1359 +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node)
1360 +{
1361 +       struct platform_device *pdev;
1362 +
1363 +       if (!node)
1364 +               return NULL;
1365 +
1366 +       pdev = of_find_device_by_node(node);
1367 +       if (!pdev)
1368 +               return NULL;
1369 +
1370 +       return platform_get_drvdata(pdev);
1371 +}
1372 +EXPORT_SYMBOL(bcm2835_smi_get);
1373 +
1374 +/****************************************************************************
1375 +*
1376 +*   bcm2835_smi_probe - called when the driver is loaded.
1377 +*
1378 +***************************************************************************/
1379 +
1380 +static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst)
1381 +{
1382 +       int i, rv = 0;
1383 +
1384 +       inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx");
1385 +
1386 +       inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1387 +       inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1388 +       inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID;
1389 +       inst->dma_config.dst_addr = inst->dma_config.src_addr;
1390 +       /* Direction unimportant - always overridden by prep_slave_sg */
1391 +       inst->dma_config.direction = DMA_DEV_TO_MEM;
1392 +       dmaengine_slave_config(inst->dma_chan, &inst->dma_config);
1393 +       /* Alloc and map bounce buffers */
1394 +       for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) {
1395 +               inst->bounce.buffer[i] =
1396 +               dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE,
1397 +                               &inst->bounce.phys[i],
1398 +                               GFP_KERNEL);
1399 +               if (!inst->bounce.buffer[i]) {
1400 +                       dev_err(inst->dev, "Could not allocate buffer!");
1401 +                       rv = -ENOMEM;
1402 +                       break;
1403 +               }
1404 +               smi_scatterlist_from_buffer(
1405 +                       inst,
1406 +                       inst->bounce.phys[i],
1407 +                       DMA_BOUNCE_BUFFER_SIZE,
1408 +                       &inst->bounce.sgl[i]
1409 +               );
1410 +       }
1411 +
1412 +       return rv;
1413 +}
1414 +
1415 +static int bcm2835_smi_probe(struct platform_device *pdev)
1416 +{
1417 +       int err;
1418 +       struct device *dev = &pdev->dev;
1419 +       struct device_node *node = dev->of_node;
1420 +       struct resource *ioresource;
1421 +       struct bcm2835_smi_instance *inst;
1422 +       const __be32 *addr;
1423 +
1424 +       /* We require device tree support */
1425 +       if (!node)
1426 +               return -EINVAL;
1427 +       /* Allocate buffers and instance data */
1428 +       inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance),
1429 +               GFP_KERNEL);
1430 +       if (!inst)
1431 +               return -ENOMEM;
1432 +
1433 +       inst->dev = dev;
1434 +       spin_lock_init(&inst->transaction_lock);
1435 +
1436 +       ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1437 +       inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
1438 +       if (IS_ERR(inst->smi_regs_ptr)) {
1439 +               err = PTR_ERR(inst->smi_regs_ptr);
1440 +               goto err;
1441 +       }
1442 +       addr = of_get_address(node, 0, NULL, NULL);
1443 +       inst->smi_regs_busaddr = be32_to_cpu(*addr);
1444 +
1445 +       err = bcm2835_smi_dma_setup(inst);
1446 +       if (err)
1447 +               goto err;
1448 +
1449 +       /* request clock */
1450 +       inst->clk = devm_clk_get(dev, NULL);
1451 +       if (!inst->clk)
1452 +               goto err;
1453 +       clk_prepare_enable(inst->clk);
1454 +
1455 +       /* Finally, do peripheral setup */
1456 +       smi_setup_regs(inst);
1457 +
1458 +       platform_set_drvdata(pdev, inst);
1459 +
1460 +       dev_info(inst->dev, "initialised");
1461 +
1462 +       return 0;
1463 +err:
1464 +       kfree(inst);
1465 +       return err;
1466 +}
1467 +
1468 +/****************************************************************************
1469 +*
1470 +*   bcm2835_smi_remove - called when the driver is unloaded.
1471 +*
1472 +***************************************************************************/
1473 +
1474 +static int bcm2835_smi_remove(struct platform_device *pdev)
1475 +{
1476 +       struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev);
1477 +       struct device *dev = inst->dev;
1478 +
1479 +       dmaengine_terminate_all(inst->dma_chan);
1480 +       dma_release_channel(inst->dma_chan);
1481 +
1482 +       clk_disable_unprepare(inst->clk);
1483 +
1484 +       dev_info(dev, "SMI device removed - OK");
1485 +       return 0;
1486 +}
1487 +
1488 +/****************************************************************************
1489 +*
1490 +*   Register the driver with device tree
1491 +*
1492 +***************************************************************************/
1493 +
1494 +static const struct of_device_id bcm2835_smi_of_match[] = {
1495 +       {.compatible = "brcm,bcm2835-smi",},
1496 +       { /* sentinel */ },
1497 +};
1498 +
1499 +MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match);
1500 +
1501 +static struct platform_driver bcm2835_smi_driver = {
1502 +       .probe = bcm2835_smi_probe,
1503 +       .remove = bcm2835_smi_remove,
1504 +       .driver = {
1505 +                  .name = DRIVER_NAME,
1506 +                  .owner = THIS_MODULE,
1507 +                  .of_match_table = bcm2835_smi_of_match,
1508 +                  },
1509 +};
1510 +
1511 +module_platform_driver(bcm2835_smi_driver);
1512 +
1513 +MODULE_ALIAS("platform:smi-bcm2835");
1514 +MODULE_LICENSE("GPL");
1515 +MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface");
1516 +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
1517 --- /dev/null
1518 +++ b/include/linux/broadcom/bcm2835_smi.h
1519 @@ -0,0 +1,391 @@
1520 +/**
1521 + * Declarations and definitions for Broadcom's Secondary Memory Interface
1522 + *
1523 + * Written by Luke Wren <luke@raspberrypi.org>
1524 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
1525 + * Copyright (c) 2010-2012 Broadcom. All rights reserved.
1526 + *
1527 + * Redistribution and use in source and binary forms, with or without
1528 + * modification, are permitted provided that the following conditions
1529 + * are met:
1530 + * 1. Redistributions of source code must retain the above copyright
1531 + *    notice, this list of conditions, and the following disclaimer,
1532 + *    without modification.
1533 + * 2. Redistributions in binary form must reproduce the above copyright
1534 + *    notice, this list of conditions and the following disclaimer in the
1535 + *    documentation and/or other materials provided with the distribution.
1536 + * 3. The names of the above-listed copyright holders may not be used
1537 + *    to endorse or promote products derived from this software without
1538 + *    specific prior written permission.
1539 + *
1540 + * ALTERNATIVELY, this software may be distributed under the terms of the
1541 + * GNU General Public License ("GPL") version 2, as published by the Free
1542 + * Software Foundation.
1543 + *
1544 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
1545 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
1546 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
1547 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
1548 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
1549 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
1550 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
1551 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
1552 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
1553 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1554 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1555 + */
1556 +
1557 +#ifndef BCM2835_SMI_H
1558 +#define BCM2835_SMI_H
1559 +
1560 +#include <linux/ioctl.h>
1561 +
1562 +#ifndef __KERNEL__
1563 +#include <stdint.h>
1564 +#include <stdbool.h>
1565 +#endif
1566 +
1567 +#define BCM2835_SMI_IOC_MAGIC 0x1
1568 +#define BCM2835_SMI_INVALID_HANDLE (~0)
1569 +
1570 +/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */
1571 +#define BCM2835_SMI_IOC_GET_SETTINGS    _IO(BCM2835_SMI_IOC_MAGIC, 0)
1572 +#define BCM2835_SMI_IOC_WRITE_SETTINGS  _IO(BCM2835_SMI_IOC_MAGIC, 1)
1573 +#define BCM2835_SMI_IOC_ADDRESS         _IO(BCM2835_SMI_IOC_MAGIC, 2)
1574 +#define BCM2835_SMI_IOC_MAX         2
1575 +
1576 +#define SMI_WIDTH_8BIT 0
1577 +#define SMI_WIDTH_16BIT 1
1578 +#define SMI_WIDTH_9BIT 2
1579 +#define SMI_WIDTH_18BIT 3
1580 +
1581 +/* max number of bytes where DMA will not be used */
1582 +#define DMA_THRESHOLD_BYTES 128
1583 +#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)
1584 +#define DMA_BOUNCE_BUFFER_COUNT 3
1585 +
1586 +
1587 +struct smi_settings {
1588 +       int data_width;
1589 +       /* Whether or not to pack multiple SMI transfers into a
1590 +          single 32 bit FIFO word */
1591 +       bool pack_data;
1592 +
1593 +       /* Timing for reads (writes the same but for WE)
1594 +        *
1595 +        * OE ----------+          +--------------------
1596 +        *              |          |
1597 +        *              +----------+
1598 +        * SD -<==============================>-----------
1599 +        * SA -<=========================================>-
1600 +        *    <-setup->  <-strobe ->  <-hold ->  <- pace ->
1601 +        */
1602 +
1603 +       int read_setup_time;
1604 +       int read_hold_time;
1605 +       int read_pace_time;
1606 +       int read_strobe_time;
1607 +
1608 +       int write_setup_time;
1609 +       int write_hold_time;
1610 +       int write_pace_time;
1611 +       int write_strobe_time;
1612 +
1613 +       bool dma_enable;                /* DREQs */
1614 +       bool dma_passthrough_enable;    /* External DREQs */
1615 +       int dma_read_thresh;
1616 +       int dma_write_thresh;
1617 +       int dma_panic_read_thresh;
1618 +       int dma_panic_write_thresh;
1619 +};
1620 +
1621 +/****************************************************************************
1622 +*
1623 +*   Declare exported SMI functions
1624 +*
1625 +***************************************************************************/
1626 +
1627 +#ifdef __KERNEL__
1628 +
1629 +#include <linux/dmaengine.h> /* for enum dma_transfer_direction */
1630 +#include <linux/of.h>
1631 +#include <linux/semaphore.h>
1632 +
1633 +struct bcm2835_smi_instance;
1634 +
1635 +struct bcm2835_smi_bounce_info {
1636 +       struct semaphore callback_sem;
1637 +       void *buffer[DMA_BOUNCE_BUFFER_COUNT];
1638 +       dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];
1639 +       struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];
1640 +};
1641 +
1642 +
1643 +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);
1644 +
1645 +struct smi_settings *bcm2835_smi_get_settings_from_regs(
1646 +       struct bcm2835_smi_instance *inst);
1647 +
1648 +void bcm2835_smi_write_buf(
1649 +       struct bcm2835_smi_instance *inst,
1650 +       const void *buf,
1651 +       size_t n_bytes);
1652 +
1653 +void bcm2835_smi_read_buf(
1654 +       struct bcm2835_smi_instance *inst,
1655 +       void *buf,
1656 +       size_t n_bytes);
1657 +
1658 +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
1659 +       unsigned int address);
1660 +
1661 +ssize_t bcm2835_smi_user_dma(
1662 +       struct bcm2835_smi_instance *inst,
1663 +       enum dma_transfer_direction dma_dir,
1664 +       char __user *user_ptr,
1665 +       size_t count,
1666 +       struct bcm2835_smi_bounce_info **bounce);
1667 +
1668 +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);
1669 +
1670 +#endif /* __KERNEL__ */
1671 +
1672 +/****************************************************************
1673 +*
1674 +*      Implementation-only declarations
1675 +*
1676 +****************************************************************/
1677 +
1678 +#ifdef BCM2835_SMI_IMPLEMENTATION
1679 +
1680 +/* Clock manager registers for SMI clock: */
1681 +#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)
1682 +/* Clock manager "password" to protect registers from spurious writes */
1683 +#define CM_PWD (0x5a << 24)
1684 +
1685 +#define CM_SMI_CTL     0x00
1686 +#define CM_SMI_DIV     0x04
1687 +
1688 +#define CM_SMI_CTL_FLIP (1 << 8)
1689 +#define CM_SMI_CTL_BUSY (1 << 7)
1690 +#define CM_SMI_CTL_KILL (1 << 5)
1691 +#define CM_SMI_CTL_ENAB (1 << 4)
1692 +#define CM_SMI_CTL_SRC_MASK (0xf)
1693 +#define CM_SMI_CTL_SRC_OFFS (0)
1694 +
1695 +#define CM_SMI_DIV_DIVI_MASK (0xf <<  12)
1696 +#define CM_SMI_DIV_DIVI_OFFS (12)
1697 +#define CM_SMI_DIV_DIVF_MASK (0xff << 4)
1698 +#define CM_SMI_DIV_DIVF_OFFS (4)
1699 +
1700 +/* SMI register mapping:*/
1701 +#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)
1702 +
1703 +#define SMICS  0x00    /* control + status register            */
1704 +#define SMIL   0x04    /* length/count (n external txfers)     */
1705 +#define SMIA   0x08    /* address register                     */
1706 +#define SMID   0x0c    /* data register                        */
1707 +#define SMIDSR0        0x10    /* device 0 read settings               */
1708 +#define SMIDSW0        0x14    /* device 0 write settings              */
1709 +#define SMIDSR1        0x18    /* device 1 read settings               */
1710 +#define SMIDSW1        0x1c    /* device 1 write settings              */
1711 +#define SMIDSR2        0x20    /* device 2 read settings               */
1712 +#define SMIDSW2        0x24    /* device 2 write settings              */
1713 +#define SMIDSR3        0x28    /* device 3 read settings               */
1714 +#define SMIDSW3        0x2c    /* device 3 write settings              */
1715 +#define SMIDC  0x30    /* DMA control registers                */
1716 +#define SMIDCS 0x34    /* direct control/status register       */
1717 +#define SMIDA  0x38    /* direct address register              */
1718 +#define SMIDD  0x3c    /* direct data registers                */
1719 +#define SMIFD  0x40    /* FIFO debug register                  */
1720 +
1721 +
1722 +
1723 +/* Control and Status register bits:
1724 + * SMICS_RXF   : RX fifo full: 1 when RX fifo is full
1725 + * SMICS_TXE   : TX fifo empty: 1 when empty.
1726 + * SMICS_RXD   : RX fifo contains data: 1 when there is data.
1727 + * SMICS_TXD   : TX fifo can accept data: 1 when true.
1728 + * SMICS_RXR   : RX fifo needs reading: 1 when fifo more than 3/4 full, or
1729 + *               when "DONE" and fifo not emptied.
1730 + * SMICS_TXW   : TX fifo needs writing: 1 when less than 1/4 full.
1731 + * SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written
1732 + *               when full. Write 1 to clear.
1733 + * SMICS_EDREQ : 1 when external DREQ received.
1734 + * SMICS_PXLDAT        :  Pixel data:  write 1 to enable pixel transfer modes.
1735 + * SMICS_SETERR        : 1 if there was an error writing to setup regs (e.g.
1736 + *               tx was in progress). Write 1 to clear.
1737 + * SMICS_PVMODE        : Set to 1 to enable pixel valve mode.
1738 + * SMICS_INTR  : Set to 1 to enable interrupt on RX.
1739 + * SMICS_INTT  : Set to 1 to enable interrupt on TX.
1740 + * SMICS_INTD  : Set to 1 to enable interrupt on DONE condition.
1741 + * SMICS_TEEN  : Tear effect mode enabled: Programmed transfers will wait
1742 + *               for a TE trigger before writing.
1743 + * SMICS_PAD1  : Padding settings for external transfers. For writes: the
1744 + *               number of bytes initially written to  the TX fifo that
1745 + * SMICS_PAD0  : should be ignored. For reads: the number of bytes that will
1746 + *               be read before the data, and should be dropped.
1747 + * SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read
1748 + * SMICS_CLEAR : Write 1 to clear the FIFOs.
1749 + * SMICS_START : Write 1 to start the programmed transfer.
1750 + * SMICS_ACTIVE        : Reads as 1 when a programmed transfer is underway.
1751 + * SMICS_DONE  : Reads as 1 when transfer finished. For RX, not set until
1752 + *               FIFO emptied.
1753 + * SMICS_ENABLE        : Set to 1 to enable the SMI peripheral, 0 to disable.
1754 + */
1755 +
1756 +#define SMICS_RXF      (1 << 31)
1757 +#define SMICS_TXE      (1 << 30)
1758 +#define SMICS_RXD      (1 << 29)
1759 +#define SMICS_TXD      (1 << 28)
1760 +#define SMICS_RXR      (1 << 27)
1761 +#define SMICS_TXW      (1 << 26)
1762 +#define SMICS_AFERR    (1 << 25)
1763 +#define SMICS_EDREQ    (1 << 15)
1764 +#define SMICS_PXLDAT   (1 << 14)
1765 +#define SMICS_SETERR   (1 << 13)
1766 +#define SMICS_PVMODE   (1 << 12)
1767 +#define SMICS_INTR     (1 << 11)
1768 +#define SMICS_INTT     (1 << 10)
1769 +#define SMICS_INTD     (1 << 9)
1770 +#define SMICS_TEEN     (1 << 8)
1771 +#define SMICS_PAD1     (1 << 7)
1772 +#define SMICS_PAD0     (1 << 6)
1773 +#define SMICS_WRITE    (1 << 5)
1774 +#define SMICS_CLEAR    (1 << 4)
1775 +#define SMICS_START    (1 << 3)
1776 +#define SMICS_ACTIVE   (1 << 2)
1777 +#define SMICS_DONE     (1 << 1)
1778 +#define SMICS_ENABLE   (1 << 0)
1779 +
1780 +/* Address register bits: */
1781 +
1782 +#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))
1783 +#define SMIA_DEVICE_OFFS (8)
1784 +#define SMIA_ADDR_MASK (0x3f)  /* bits 5 -> 0 */
1785 +#define SMIA_ADDR_OFFS (0)
1786 +
1787 +/* DMA control register bits:
1788 + * SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued.
1789 + * SMIDC_DMAP  : DMA passthrough: when set to 0, top two data pins are used by
1790 + *               SMI as usual. When set to 1, the top two pins are used for
1791 + *               external DREQs: pin 16 read request, 17 write.
1792 + * SMIDC_PANIC*        : Threshold at which DMA will panic during read/write.
1793 + * SMIDC_REQ*  : Threshold at which DMA will generate a DREQ.
1794 + */
1795 +
1796 +#define SMIDC_DMAEN            (1 << 28)
1797 +#define SMIDC_DMAP             (1 << 24)
1798 +#define SMIDC_PANICR_MASK      (0x3f << 18)
1799 +#define SMIDC_PANICR_OFFS      (18)
1800 +#define SMIDC_PANICW_MASK      (0x3f << 12)
1801 +#define SMIDC_PANICW_OFFS      (12)
1802 +#define SMIDC_REQR_MASK                (0x3f << 6)
1803 +#define SMIDC_REQR_OFFS                (6)
1804 +#define SMIDC_REQW_MASK                (0x3f)
1805 +#define SMIDC_REQW_OFFS                (0)
1806 +
1807 +/* Device settings register bits: same for all 4 (or 3?) device register sets.
1808 + * Device read settings:
1809 + * SMIDSR_RWIDTH       : Read transfer width. 00 = 8bit, 01 = 16bit,
1810 + *                       10 = 18bit, 11 = 9bit.
1811 + * SMIDSR_RSETUP       : Read setup time: number of core cycles between chip
1812 + *                       select/address and read strobe. Min 1, max 64.
1813 + * SMIDSR_MODE68       : 1 for System 68 mode (i.e. enable + direction pins,
1814 + *                       rather than OE + WE pin)
1815 + * SMIDSR_FSETUP       : If set to 1, setup time only applies to first
1816 + *                       transfer after address change.
1817 + * SMIDSR_RHOLD                : Number of core cycles between read strobe going
1818 + *                       inactive and CS/address going inactive. Min 1, max 64
1819 + * SMIDSR_RPACEALL     : When set to 1, this device's RPACE value will always
1820 + *                       be used for the next transaction, even if it is not
1821 + *                       to this device.
1822 + * SMIDSR_RPACE                : Number of core cycles spent waiting between CS
1823 + *                       deassert and start of next transfer. Min 1, max 128
1824 + * SMIDSR_RDREQ                : 1 = use external DMA request on SD16 to pace reads
1825 + *                       from device. Must also set DMAP in SMICS.
1826 + * SMIDSR_RSTROBE      : Number of cycles to assert the read strobe.
1827 + *                       min 1, max 128.
1828 + */
1829 +#define SMIDSR_RWIDTH_MASK     ((1<<31)|(1<<30))
1830 +#define SMIDSR_RWIDTH_OFFS     (30)
1831 +#define SMIDSR_RSETUP_MASK     (0x3f << 24)
1832 +#define SMIDSR_RSETUP_OFFS     (24)
1833 +#define SMIDSR_MODE68          (1 << 23)
1834 +#define SMIDSR_FSETUP          (1 << 22)
1835 +#define SMIDSR_RHOLD_MASK      (0x3f << 16)
1836 +#define SMIDSR_RHOLD_OFFS      (16)
1837 +#define SMIDSR_RPACEALL                (1 << 15)
1838 +#define SMIDSR_RPACE_MASK      (0x7f << 8)
1839 +#define SMIDSR_RPACE_OFFS      (8)
1840 +#define SMIDSR_RDREQ           (1 << 7)
1841 +#define SMIDSR_RSTROBE_MASK    (0x7f)
1842 +#define SMIDSR_RSTROBE_OFFS    (0)
1843 +
1844 +/* Device write settings:
1845 + * SMIDSW_WWIDTH       : Write transfer width. 00 = 8bit, 01 = 16bit,
1846 + *                       10= 18bit, 11 = 9bit.
1847 + * SMIDSW_WSETUP       : Number of cycles between CS assert and write strobe.
1848 + *                       Min 1, max 64.
1849 + * SMIDSW_WFORMAT      : Pixel format of input. 0 = 16bit RGB 565,
1850 + *                       1 = 32bit RGBA 8888
1851 + * SMIDSW_WSWAP                : 1 = swap pixel data bits. (Use with SMICS_PXLDAT)
1852 + * SMIDSW_WHOLD                : Time between WE deassert and CS deassert. 1 to 64
1853 + * SMIDSW_WPACEALL     : 1: this device's WPACE will be used for the next
1854 + *                       transfer, regardless of that transfer's device.
1855 + * SMIDSW_WPACE                : Cycles between CS deassert and next CS assert.
1856 + *                       Min 1, max 128
1857 + * SMIDSW_WDREQ                : Use external DREQ on pin 17 to pace writes. DMAP must
1858 + *                       be set in SMICS.
1859 + * SMIDSW_WSTROBE      : Number of cycles to assert the write strobe.
1860 + *                       Min 1, max 128
1861 + */
1862 +#define SMIDSW_WWIDTH_MASK      ((1<<31)|(1<<30))
1863 +#define SMIDSW_WWIDTH_OFFS     (30)
1864 +#define SMIDSW_WSETUP_MASK     (0x3f << 24)
1865 +#define SMIDSW_WSETUP_OFFS     (24)
1866 +#define SMIDSW_WFORMAT         (1 << 23)
1867 +#define SMIDSW_WSWAP           (1 << 22)
1868 +#define SMIDSW_WHOLD_MASK      (0x3f << 16)
1869 +#define SMIDSW_WHOLD_OFFS      (16)
1870 +#define SMIDSW_WPACEALL                (1 << 15)
1871 +#define SMIDSW_WPACE_MASK      (0x7f << 8)
1872 +#define SMIDSW_WPACE_OFFS      (8)
1873 +#define SMIDSW_WDREQ           (1 << 7)
1874 +#define SMIDSW_WSTROBE_MASK     (0x7f)
1875 +#define SMIDSW_WSTROBE_OFFS     (0)
1876 +
1877 +/* Direct transfer control + status register
1878 + * SMIDCS_WRITE        : Direction of transfer: 1 -> write, 0 -> read
1879 + * SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear.
1880 + * SMIDCS_START        : Write 1 to start a transfer, if one is not already underway.
1881 + * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.
1882 + */
1883 +
1884 +#define SMIDCS_WRITE           (1 << 3)
1885 +#define SMIDCS_DONE            (1 << 2)
1886 +#define SMIDCS_START           (1 << 1)
1887 +#define SMIDCS_ENABLE          (1 << 0)
1888 +
1889 +/* Direct transfer address register
1890 + * SMIDA_DEVICE        : Indicates which of the device settings banks should be used.
1891 + * SMIDA_ADDR  : The value to be asserted on the address pins.
1892 + */
1893 +
1894 +#define SMIDA_DEVICE_MASK      ((1<<9)|(1<<8))
1895 +#define SMIDA_DEVICE_OFFS      (8)
1896 +#define SMIDA_ADDR_MASK                (0x3f)
1897 +#define SMIDA_ADDR_OFFS                (0)
1898 +
1899 +/* FIFO debug register
1900 + * SMIFD_FLVL  : The high-tide mark of FIFO count during the most recent txfer
1901 + * SMIFD_FCNT  : The current FIFO count.
1902 + */
1903 +#define SMIFD_FLVL_MASK                (0x3f << 8)
1904 +#define SMIFD_FLVL_OFFS                (8)
1905 +#define SMIFD_FCNT_MASK                (0x3f)
1906 +#define SMIFD_FCNT_OFFS                (0)
1907 +
1908 +#endif /* BCM2835_SMI_IMPLEMENTATION */
1909 +
1910 +#endif /* BCM2835_SMI_H */