ath79: split dtsi for D-Link COVR-P2500
[openwrt/staging/981213.git] / target / linux / ath79 / dts / qca9563_dlink_covr.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca956x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/mtd/partitions/uimage.h>
9
10 / {
11 keys {
12 compatible = "gpio-keys";
13
14 wps {
15 label = "wps";
16 linux,code = <KEY_WPS_BUTTON>;
17 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
18 };
19
20 reset {
21 label = "reset";
22 linux,code = <KEY_RESTART>;
23 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
24 };
25 };
26
27 virtual_flash {
28 compatible = "mtd-concat";
29
30 devices = <&fwconcat0 &fwconcat1>;
31
32 partitions {
33 compatible = "fixed-partitions";
34 #address-cells = <1>;
35 #size-cells = <1>;
36
37 partition@0 {
38 compatible = "openwrt,uimage", "denx,uimage";
39 openwrt,ih-magic = <0x68737173>;
40 label = "firmware";
41 reg = <0x0 0x0>;
42 };
43 };
44 };
45 };
46
47 &spi {
48 status = "okay";
49
50 flash@0 {
51 compatible = "jedec,spi-nor";
52 reg = <0>;
53 spi-max-frequency = <50000000>;
54
55 partitions {
56 compatible = "fixed-partitions";
57 #address-cells = <1>;
58 #size-cells = <1>;
59
60 partition@0 {
61 label = "u-boot";
62 reg = <0x0 0x40000>;
63 read-only;
64 };
65
66 partition@40000 {
67 label = "u-boot-env";
68 reg = <0x40000 0x10000>;
69 read-only;
70 };
71
72 fwconcat0: partition@50000 {
73 label = "fwconcat0";
74 reg = <0x50000 0xe30000>;
75 };
76
77 partition@e80000 {
78 label = "loader";
79 reg = <0xe80000 0x10000>;
80 read-only;
81 };
82
83 fwconcat1: partition@e90000 {
84 label = "fwconcat1";
85 reg = <0xe90000 0x160000>;
86 };
87
88 art: partition@ff0000 {
89 label = "art";
90 reg = <0xff0000 0x10000>;
91 read-only;
92
93 compatible = "nvmem-cells";
94
95 nvmem-layout {
96 compatible = "fixed-layout";
97 #address-cells = <1>;
98 #size-cells = <1>;
99
100 calibration_ath9k: calibration@1000 {
101 reg = <0x1000 0x440>;
102 };
103
104 precalibration_ath10k: pre-calibration@5000 {
105 reg = <0x5000 0x2f20>;
106 };
107 };
108 };
109 };
110 };
111 };
112
113 &pcie {
114 status = "okay";
115
116 wifi0: wifi@0,0 {
117 compatible = "qcom,ath10k";
118 reg = <0 0 0 0 0>;
119
120 nvmem-cells = <&precalibration_ath10k>;
121 nvmem-cell-names = "pre-calibration";
122 };
123 };
124
125 &gpio {
126 phy-reset {
127 gpio-hog;
128 gpios = <11 GPIO_ACTIVE_LOW>;
129 output-low;
130 line-name = "phy-reset";
131 };
132 };
133
134 &mdio0 {
135 status = "okay";
136
137 phy0: ethernet-phy@0 {
138 reg = <0>;
139 phy-mode = "sgmii";
140 qca,mib-poll-interval = <500>;
141
142 qca,ar8327-initvals = <
143 0x04 0x00080080 /* PORT0 PAD MODE CTRL */
144 0x10 0x81000080 /* POWER_ON_STRAP */
145 0x50 0xcc35cc35 /* LED_CTRL0 */
146 0x54 0xcb37cb37 /* LED_CTRL1 */
147 0x58 0x00000000 /* LED_CTRL2 */
148 0x5c 0x00f3cf00 /* LED_CTRL3 */
149 0x7c 0x0000007e /* PORT0_STATUS */
150 >;
151 };
152 };
153
154 &eth0 {
155 status = "okay";
156
157 pll-data = <0x03000101 0x00000101 0x00001919>;
158
159 phy-mode = "sgmii";
160 phy-handle = <&phy0>;
161 };
162
163 &wmac {
164 status = "okay";
165
166 nvmem-cells = <&calibration_ath9k>;
167 nvmem-cell-names = "calibration";
168 };