package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c

   1 /*
   2  * DO NOT MODIFY
   3  *
   4  * Declares the U_BOOT_DRIVER() records and platform data.
   5  * This was generated by dtoc from a .dtb (device tree binary) file.
   6  */
   7
   8 /* Allow use of U_BOOT_DRVINFO() in this file */
   9 #define DT_PLAT_C
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <dt-structs.h>
  14
  15 /*
  16  * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
  17  *
  18  * idx  driver_info          driver
  19  * ---  -------------------- --------------------
  20  *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
  21  *   1: dmc                  rockchip_rk3328_dmc
  22  *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
  23  *   3: mmc_at_ff520000      rockchip_rk3288_dw_mshc
  24  *   4: serial_at_ff130000   ns16550_serial
  25  *   5: spi_at_ff190000      rockchip_rk3328_spi
  26  *   6: spiflash_at_0        jedec_spi_nor
  27  *   7: syscon_at_ff100000   rockchip_rk3328_grf
  28  * ---  -------------------- --------------------
  29  */
  30
  31 /*
  32  * Node /clock-controller@ff440000 index 0
  33  * driver rockchip_rk3328_cru parent None
  34  */
  35 static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
  36         .reg                    = {0xff440000, 0x1000},
  37         .rockchip_grf           = 0x3b,
  38 };
  39 U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
  40         .name           = "rockchip_rk3328_cru",
  41         .plat           = &dtv_clock_controller_at_ff440000,
  42         .plat_size      = sizeof(dtv_clock_controller_at_ff440000),
  43         .parent_idx     = -1,
  44 };
  45
  46 /*
  47  * Node /dmc index 1
  48  * driver rockchip_rk3328_dmc parent None
  49  */
  50 static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
  51         .reg                    = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
  52                 0xff720000, 0x1000, 0xff798000, 0x1000},
  53         .rockchip_sdram_params  = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
  54                 0x10, 0x10, 0x0, 0x98899459, 0x0, 0x2e, 0x544, 0x15,
  55                 0x432, 0xff, 0x320, 0x6, 0x1, 0x0, 0x1, 0x0,
  56                 0x43041008, 0x64, 0x300054, 0xd0, 0x500002, 0xd4, 0x10000, 0xd8,
  57                 0xe03, 0xdc, 0x43001a, 0xe0, 0x10000, 0xe4, 0xe0005, 0xf4,
  58                 0xf011f, 0x100, 0xb141b11, 0x104, 0x3031a, 0x108, 0x3060809, 0x10c,
  59                 0x606000, 0x110, 0x8020409, 0x114, 0x1010606, 0x118, 0x2020004, 0x120,
  60                 0x404, 0x138, 0x58, 0x180, 0x900024, 0x184, 0x1400000, 0x190,
  61                 0x7050002, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0xa020b28, 0x244,
  62                 0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
  63                 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0xc, 0x2c,
  64                 0x0, 0x30, 0x6, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
  65                 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
  66                 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
  67                 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
  68                 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
  69                 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  70                 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
  71                 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
  72                 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  73                 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
  74                 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
  75                 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
  76                 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
  77                 0x77, 0x77, 0x79, 0x9},
  78 };
  79 U_BOOT_DRVINFO(dmc) = {
  80         .name           = "rockchip_rk3328_dmc",
  81         .plat           = &dtv_dmc,
  82         .plat_size      = sizeof(dtv_dmc),
  83         .parent_idx     = -1,
  84 };
  85
  86 /*
  87  * Node /mmc@ff500000 index 2
  88  * driver rockchip_rk3288_dw_mshc parent None
  89  */
  90 static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
  91         .bus_width              = 0x4,
  92         .cap_mmc_highspeed      = true,
  93         .cap_sd_highspeed       = true,
  94         .clocks                 = {
  95                         {0, {317}},
  96                         {0, {33}},
  97                         {0, {74}},
  98                         {0, {78}},},
  99         .disable_wp             = true,
 100         .fifo_depth             = 0x100,
 101         .interrupts             = {0x0, 0xc, 0x4},
 102         .max_frequency          = 0x8f0d180,
 103         .pinctrl_0              = {0x4a, 0x4b, 0x4c, 0x4d},
 104         .pinctrl_names          = "default",
 105         .reg                    = {0xff500000, 0x4000},
 106         .u_boot_spl_fifo_mode   = true,
 107         .vmmc_supply            = 0x4e,
 108 };
 109 U_BOOT_DRVINFO(mmc_at_ff500000) = {
 110         .name           = "rockchip_rk3288_dw_mshc",
 111         .plat           = &dtv_mmc_at_ff500000,
 112         .plat_size      = sizeof(dtv_mmc_at_ff500000),
 113         .parent_idx     = -1,
 114 };
 115
 116 /*
 117  * Node /mmc@ff520000 index 3
 118  * driver rockchip_rk3288_dw_mshc parent None
 119  */
 120 static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
 121         .bus_width              = 0x8,
 122         .cap_mmc_highspeed      = true,
 123         .clocks                 = {
 124                         {0, {319}},
 125                         {0, {35}},
 126                         {0, {76}},
 127                         {0, {80}},},
 128         .fifo_depth             = 0x100,
 129         .interrupts             = {0x0, 0xe, 0x4},
 130         .max_frequency          = 0x8f0d180,
 131         .mmc_hs200_1_8v         = true,
 132         .non_removable          = true,
 133         .pinctrl_0              = {0x4f, 0x50, 0x51, 0x0},
 134         .pinctrl_names          = "default",
 135         .reg                    = {0xff520000, 0x4000},
 136         .u_boot_spl_fifo_mode   = true,
 137         .vmmc_supply            = 0x1e,
 138         .vqmmc_supply           = 0x1f,
 139 };
 140 U_BOOT_DRVINFO(mmc_at_ff520000) = {
 141         .name           = "rockchip_rk3288_dw_mshc",
 142         .plat           = &dtv_mmc_at_ff520000,
 143         .plat_size      = sizeof(dtv_mmc_at_ff520000),
 144         .parent_idx     = -1,
 145 };
 146
 147 /*
 148  * Node /serial@ff130000 index 4
 149  * driver ns16550_serial parent None
 150  */
 151 static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
 152         .clock_frequency        = 0x16e3600,
 153         .clocks                 = {
 154                         {0, {40}},
 155                         {0, {212}},},
 156         .dma_names              = {"tx", "rx"},
 157         .dmas                   = {0x10, 0x6, 0x10, 0x7},
 158         .interrupts             = {0x0, 0x39, 0x4},
 159         .pinctrl_0              = 0x27,
 160         .pinctrl_names          = "default",
 161         .reg                    = {0xff130000, 0x100},
 162         .reg_io_width           = 0x4,
 163         .reg_shift              = 0x2,
 164 };
 165 U_BOOT_DRVINFO(serial_at_ff130000) = {
 166         .name           = "ns16550_serial",
 167         .plat           = &dtv_serial_at_ff130000,
 168         .plat_size      = sizeof(dtv_serial_at_ff130000),
 169         .parent_idx     = -1,
 170 };
 171
 172 /* Node /spi@ff190000 index 5 */
 173 static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
 174         .clocks                 = {
 175                         {0, {32}},
 176                         {0, {209}},},
 177         .dma_names              = {"tx", "rx"},
 178         .dmas                   = {0x10, 0x8, 0x10, 0x9},
 179         .interrupts             = {0x0, 0x31, 0x4},
 180         .pinctrl_0              = {0x2f, 0x30, 0x31, 0x32},
 181         .pinctrl_names          = "default",
 182         .reg                    = {0xff190000, 0x1000},
 183 };
 184 U_BOOT_DRVINFO(spi_at_ff190000) = {
 185         .name           = "rockchip_rk3328_spi",
 186         .plat           = &dtv_spi_at_ff190000,
 187         .plat_size      = sizeof(dtv_spi_at_ff190000),
 188         .parent_idx     = -1,
 189 };
 190
 191 /*
 192  * Node /spi@ff190000/spiflash@0 index 6
 193  * driver jedec_spi_nor parent None
 194  */
 195 static struct dtd_jedec_spi_nor dtv_spiflash_at_0 = {
 196         .reg                    = {0x0},
 197         .spi_max_frequency      = 0x2faf080,
 198 };
 199 U_BOOT_DRVINFO(spiflash_at_0) = {
 200         .name           = "jedec_spi_nor",
 201         .plat           = &dtv_spiflash_at_0,
 202         .plat_size      = sizeof(dtv_spiflash_at_0),
 203         .parent_idx     = 5,
 204 };
 205
 206 /*
 207  * Node /syscon@ff100000 index 7
 208  * driver rockchip_rk3328_grf parent None
 209  */
 210 static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
 211         .reg                    = {0xff100000, 0x1000},
 212 };
 213 U_BOOT_DRVINFO(syscon_at_ff100000) = {
 214         .name           = "rockchip_rk3328_grf",
 215         .plat           = &dtv_syscon_at_ff100000,
 216         .plat_size      = sizeof(dtv_syscon_at_ff100000),
 217         .parent_idx     = -1,
 218 };
 219