package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c

   1 /*
   2  * DO NOT MODIFY
   3  *
   4  * Declares the U_BOOT_DRIVER() records and platform data.
   5  * This was generated by dtoc from a .dtb (device tree binary) file.
   6  */
   7
   8 /* Allow use of U_BOOT_DRVINFO() in this file */
   9 #define DT_PLAT_C
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <dt-structs.h>
  14
  15 /*
  16  * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
  17  *
  18  * idx  driver_info          driver
  19  * ---  -------------------- --------------------
  20  *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
  21  *   1: dmc                  rockchip_rk3328_dmc
  22  *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
  23  *   3: mmc_at_ff520000      rockchip_rk3288_dw_mshc
  24  *   4: serial_at_ff130000   ns16550_serial
  25  *   5: syscon_at_ff100000   rockchip_rk3328_grf
  26  * ---  -------------------- --------------------
  27  */
  28
  29 /*
  30  * Node /clock-controller@ff440000 index 0
  31  * driver rockchip_rk3328_cru parent None
  32  */
  33 static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
  34         .reg                    = {0xff440000, 0x1000},
  35         .rockchip_grf           = 0x38,
  36 };
  37 U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
  38         .name           = "rockchip_rk3328_cru",
  39         .plat           = &dtv_clock_controller_at_ff440000,
  40         .plat_size      = sizeof(dtv_clock_controller_at_ff440000),
  41         .parent_idx     = -1,
  42 };
  43
  44 /*
  45  * Node /dmc index 1
  46  * driver rockchip_rk3328_dmc parent None
  47  */
  48 static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
  49         .reg                    = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
  50                 0xff720000, 0x1000, 0xff798000, 0x1000},
  51         .rockchip_sdram_params  = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
  52                 0x10, 0x10, 0x0, 0x9028b189, 0x0, 0x21, 0x482, 0x15,
  53                 0x222, 0xff, 0x14d, 0x3, 0x1, 0x0, 0x0, 0x0,
  54                 0x43041001, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x20000, 0xd8,
  55                 0x100, 0xdc, 0x3200000, 0xe0, 0x0, 0xe4, 0x90000, 0xf4,
  56                 0xf011f, 0x100, 0x7090b06, 0x104, 0x50209, 0x108, 0x3030407, 0x10c,
  57                 0x202006, 0x110, 0x3020204, 0x114, 0x3030202, 0x120, 0x903, 0x180,
  58                 0x800020, 0x184, 0x0, 0x190, 0x7010001, 0x198, 0x5001100, 0x1a0,
  59                 0xc0400003, 0x240, 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490,
  60                 0x1, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  61                 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xa, 0x28, 0x6, 0x2c,
  62                 0x0, 0x30, 0x5, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
  63                 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
  64                 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
  65                 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
  66                 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
  67                 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  68                 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
  69                 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
  70                 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  71                 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
  72                 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
  73                 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
  74                 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
  75                 0x77, 0x77, 0x79, 0x9},
  76 };
  77 U_BOOT_DRVINFO(dmc) = {
  78         .name           = "rockchip_rk3328_dmc",
  79         .plat           = &dtv_dmc,
  80         .plat_size      = sizeof(dtv_dmc),
  81         .parent_idx     = -1,
  82 };
  83
  84 /*
  85  * Node /mmc@ff500000 index 2
  86  * driver rockchip_rk3288_dw_mshc parent None
  87  */
  88 static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
  89         .bus_width              = 0x4,
  90         .cap_mmc_highspeed      = true,
  91         .cap_sd_highspeed       = true,
  92         .card_detect_delay      = 0xc8,
  93         .clocks                 = {
  94                         {0, {317}},
  95                         {0, {33}},
  96                         {0, {74}},
  97                         {0, {78}},},
  98         .disable_wp             = true,
  99         .fifo_depth             = 0x100,
 100         .interrupts             = {0x0, 0xc, 0x4},
 101         .max_frequency          = 0x8f0d180,
 102         .num_slots              = 0x1,
 103         .pinctrl_0              = {0x45, 0x46, 0x47, 0x48},
 104         .pinctrl_names          = "default",
 105         .reg                    = {0xff500000, 0x4000},
 106         .supports_sd            = true,
 107         .u_boot_spl_fifo_mode   = true,
 108         .vmmc_supply            = 0x49,
 109 };
 110 U_BOOT_DRVINFO(mmc_at_ff500000) = {
 111         .name           = "rockchip_rk3288_dw_mshc",
 112         .plat           = &dtv_mmc_at_ff500000,
 113         .plat_size      = sizeof(dtv_mmc_at_ff500000),
 114         .parent_idx     = -1,
 115 };
 116
 117 /*
 118  * Node /mmc@ff520000 index 3
 119  * driver rockchip_rk3288_dw_mshc parent None
 120  */
 121 static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
 122         .bus_width              = 0x8,
 123         .cap_mmc_highspeed      = true,
 124         .clocks                 = {
 125                         {0, {319}},
 126                         {0, {35}},
 127                         {0, {76}},
 128                         {0, {80}},},
 129         .disable_wp             = true,
 130         .fifo_depth             = 0x100,
 131         .interrupts             = {0x0, 0xe, 0x4},
 132         .max_frequency          = 0x8f0d180,
 133         .mmc_hs200_1_8v         = true,
 134         .non_removable          = true,
 135         .num_slots              = 0x1,
 136         .pinctrl_0              = {0x4a, 0x4b, 0x4c, 0x0},
 137         .pinctrl_names          = "default",
 138         .reg                    = {0xff520000, 0x4000},
 139         .supports_emmc          = true,
 140         .u_boot_spl_fifo_mode   = true,
 141         .vmmc_supply            = 0x1c,
 142         .vqmmc_supply           = 0x1d,
 143 };
 144 U_BOOT_DRVINFO(mmc_at_ff520000) = {
 145         .name           = "rockchip_rk3288_dw_mshc",
 146         .plat           = &dtv_mmc_at_ff520000,
 147         .plat_size      = sizeof(dtv_mmc_at_ff520000),
 148         .parent_idx     = -1,
 149 };
 150
 151 /*
 152  * Node /serial@ff130000 index 4
 153  * driver ns16550_serial parent None
 154  */
 155 static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
 156         .clock_frequency        = 0x16e3600,
 157         .clocks                 = {
 158                         {0, {40}},
 159                         {0, {212}},},
 160         .dma_names              = {"tx", "rx"},
 161         .dmas                   = {0x10, 0x6, 0x10, 0x7},
 162         .interrupts             = {0x0, 0x39, 0x4},
 163         .pinctrl_0              = 0x24,
 164         .pinctrl_names          = "default",
 165         .reg                    = {0xff130000, 0x100},
 166         .reg_io_width           = 0x4,
 167         .reg_shift              = 0x2,
 168 };
 169 U_BOOT_DRVINFO(serial_at_ff130000) = {
 170         .name           = "ns16550_serial",
 171         .plat           = &dtv_serial_at_ff130000,
 172         .plat_size      = sizeof(dtv_serial_at_ff130000),
 173         .parent_idx     = -1,
 174 };
 175
 176 /*
 177  * Node /syscon@ff100000 index 5
 178  * driver rockchip_rk3328_grf parent None
 179  */
 180 static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
 181         .reg                    = {0xff100000, 0x1000},
 182 };
 183 U_BOOT_DRVINFO(syscon_at_ff100000) = {
 184         .name           = "rockchip_rk3328_grf",
 185         .plat           = &dtv_syscon_at_ff100000,
 186         .plat_size      = sizeof(dtv_syscon_at_ff100000),
 187         .parent_idx     = -1,
 188 };
 189