4 * Declares the U_BOOT_DRIVER() records and platform data.
5 * This was generated by dtoc from a .dtb (device tree binary) file.
8 /* Allow use of U_BOOT_DRVINFO() in this file */
13 #include <dt-structs.h>
16 * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
18 * idx driver_info driver
19 * --- -------------------- --------------------
20 * 0: clock_controller_at_ff440000 rockchip_rk3328_cru
21 * 1: dmc rockchip_rk3328_dmc
22 * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
23 * 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc
24 * 4: serial_at_ff130000 ns16550_serial
25 * 5: syscon_at_ff100000 rockchip_rk3328_grf
26 * --- -------------------- --------------------
30 * Node /clock-controller@ff440000 index 0
31 * driver rockchip_rk3328_cru parent None
33 static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000
= {
34 .reg
= {0xff440000, 0x1000},
37 U_BOOT_DRVINFO(clock_controller_at_ff440000
) = {
38 .name
= "rockchip_rk3328_cru",
39 .plat
= &dtv_clock_controller_at_ff440000
,
40 .plat_size
= sizeof(dtv_clock_controller_at_ff440000
),
46 * driver rockchip_rk3328_dmc parent None
48 static struct dtd_rockchip_rk3328_dmc dtv_dmc
= {
49 .reg
= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
50 0xff720000, 0x1000, 0xff798000, 0x1000},
51 .rockchip_sdram_params
= {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
52 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
53 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
54 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
55 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
56 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
57 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
58 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
59 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
60 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
61 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
62 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
63 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
64 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
65 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
66 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
67 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
68 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
69 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
70 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
71 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
72 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
73 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
74 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
75 0x77, 0x77, 0x79, 0x9},
77 U_BOOT_DRVINFO(dmc
) = {
78 .name
= "rockchip_rk3328_dmc",
80 .plat_size
= sizeof(dtv_dmc
),
85 * Node /mmc@ff500000 index 2
86 * driver rockchip_rk3288_dw_mshc parent None
88 static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000
= {
90 .cap_mmc_highspeed
= true,
91 .cap_sd_highspeed
= true,
99 .interrupts
= {0x0, 0xc, 0x4},
100 .max_frequency
= 0x8f0d180,
101 .pinctrl_0
= {0x47, 0x48, 0x49, 0x4a},
102 .pinctrl_names
= "default",
103 .reg
= {0xff500000, 0x4000},
104 .sd_uhs_sdr104
= true,
105 .sd_uhs_sdr12
= true,
106 .sd_uhs_sdr25
= true,
107 .sd_uhs_sdr50
= true,
108 .u_boot_spl_fifo_mode
= true,
110 .vqmmc_supply
= 0x1e,
112 U_BOOT_DRVINFO(mmc_at_ff500000
) = {
113 .name
= "rockchip_rk3288_dw_mshc",
114 .plat
= &dtv_mmc_at_ff500000
,
115 .plat_size
= sizeof(dtv_mmc_at_ff500000
),
120 * Node /mmc@ff520000 index 3
121 * driver rockchip_rk3288_dw_mshc parent None
123 static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000
= {
125 .cap_mmc_highspeed
= true,
132 .interrupts
= {0x0, 0xe, 0x4},
133 .max_frequency
= 0x8f0d180,
134 .mmc_ddr_1_8v
= true,
135 .mmc_hs200_1_8v
= true,
136 .non_removable
= true,
137 .pinctrl_0
= {0x4c, 0x4d, 0x4e, 0x0},
138 .pinctrl_names
= "default",
139 .reg
= {0xff520000, 0x4000},
140 .u_boot_spl_fifo_mode
= true,
142 .vqmmc_supply
= 0x1d,
144 U_BOOT_DRVINFO(mmc_at_ff520000
) = {
145 .name
= "rockchip_rk3288_dw_mshc",
146 .plat
= &dtv_mmc_at_ff520000
,
147 .plat_size
= sizeof(dtv_mmc_at_ff520000
),
152 * Node /serial@ff130000 index 4
153 * driver ns16550_serial parent None
155 static struct dtd_ns16550_serial dtv_serial_at_ff130000
= {
156 .clock_frequency
= 0x16e3600,
160 .dma_names
= {"tx", "rx"},
161 .dmas
= {0x10, 0x6, 0x10, 0x7},
162 .interrupts
= {0x0, 0x39, 0x4},
164 .pinctrl_names
= "default",
165 .reg
= {0xff130000, 0x100},
169 U_BOOT_DRVINFO(serial_at_ff130000
) = {
170 .name
= "ns16550_serial",
171 .plat
= &dtv_serial_at_ff130000
,
172 .plat_size
= sizeof(dtv_serial_at_ff130000
),
177 * Node /syscon@ff100000 index 5
178 * driver rockchip_rk3328_grf parent None
180 static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000
= {
181 .reg
= {0xff100000, 0x1000},
183 U_BOOT_DRVINFO(syscon_at_ff100000
) = {
184 .name
= "rockchip_rk3328_grf",
185 .plat
= &dtv_syscon_at_ff100000
,
186 .plat_size
= sizeof(dtv_syscon_at_ff100000
),