package/boot/uboot-rockchip/patches/101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch

   1 From 408fd4570c0f1e6b1fe3722998394651144f2a29 Mon Sep 17 00:00:00 2001
   2 From: Tianling Shen <cnsztl@gmail.com>
   3 Date: Sat, 20 May 2023 18:52:14 +0800
   4 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS
   5
   6 The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
   7 the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type
   8 changed from DDR4 to LPDDR3.
   9
  10 The device tree is taken from kernel v6.4-rc1.
  11
  12 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
  13 ---
  14  arch/arm/dts/Makefile                         |   1 +
  15  .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi   |  46 +++++++
  16  arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts  |  40 ++++++
  17  board/rockchip/evb_rk3328/MAINTAINERS         |   6 +
  18  configs/orangepi-r1-plus-lts-rk3328_defconfig | 114 ++++++++++++++++++
  19  5 files changed, 207 insertions(+)
  20  create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
  21  create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
  22  create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
  23
  24 --- a/arch/arm/dts/Makefile
  25 +++ b/arch/arm/dts/Makefile
  26 @@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
  27         rk3328-nanopi-r2c.dtb \
  28         rk3328-nanopi-r2s.dtb \
  29         rk3328-orangepi-r1-plus.dtb \
  30 +       rk3328-orangepi-r1-plus-lts.dtb \
  31         rk3328-roc-cc.dtb \
  32         rk3328-rock64.dtb \
  33         rk3328-rock-pi-e.dtb
  34 --- /dev/null
  35 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
  36 @@ -0,0 +1,46 @@
  37 +// SPDX-License-Identifier: GPL-2.0-or-later
  38 +/*
  39 + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
  40 + * (C) Copyright 2020 David Bauer
  41 + */
  42 +
  43 +#include "rk3328-u-boot.dtsi"
  44 +#include "rk3328-sdram-lpddr3-666.dtsi"
  45 +/ {
  46 +       chosen {
  47 +               u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
  48 +       };
  49 +};
  50 +
  51 +&gpio0 {
  52 +       bootph-pre-ram;
  53 +};
  54 +
  55 +&pinctrl {
  56 +       bootph-pre-ram;
  57 +};
  58 +
  59 +&sdmmc0m1_pin {
  60 +       bootph-pre-ram;
  61 +};
  62 +
  63 +&pcfg_pull_up_4ma {
  64 +       bootph-pre-ram;
  65 +};
  66 +
  67 +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
  68 +&vcc_sd {
  69 +       bootph-pre-ram;
  70 +};
  71 +
  72 +&gmac2io {
  73 +       snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
  74 +       snps,reset-active-low;
  75 +       snps,reset-delays-us = <0 10000 50000>;
  76 +};
  77 +
  78 +&spi0 {
  79 +       spi_flash: spiflash@0 {
  80 +               bootph-all;
  81 +       };
  82 +};
  83 --- /dev/null
  84 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
  85 @@ -0,0 +1,40 @@
  86 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  87 +/*
  88 + * Copyright (c) 2016 Xunlong Software. Co., Ltd.
  89 + * (http://www.orangepi.org)
  90 + *
  91 + * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
  92 + */
  93 +
  94 +/dts-v1/;
  95 +#include "rk3328-orangepi-r1-plus.dts"
  96 +
  97 +/ {
  98 +       model = "Xunlong Orange Pi R1 Plus LTS";
  99 +       compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
 100 +};
 101 +
 102 +&gmac2io {
 103 +       phy-handle = <&yt8531c>;
 104 +       tx_delay = <0x19>;
 105 +       rx_delay = <0x05>;
 106 +
 107 +       mdio {
 108 +               /delete-node/ ethernet-phy@1;
 109 +
 110 +               yt8531c: ethernet-phy@0 {
 111 +                       compatible = "ethernet-phy-ieee802.3-c22";
 112 +                       reg = <0>;
 113 +
 114 +                       motorcomm,clk-out-frequency-hz = <125000000>;
 115 +                       motorcomm,keep-pll-enabled;
 116 +                       motorcomm,auto-sleep-disabled;
 117 +
 118 +                       pinctrl-0 = <&eth_phy_reset_pin>;
 119 +                       pinctrl-names = "default";
 120 +                       reset-assert-us = <15000>;
 121 +                       reset-deassert-us = <50000>;
 122 +                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
 123 +               };
 124 +       };
 125 +};
 126 --- a/board/rockchip/evb_rk3328/MAINTAINERS
 127 +++ b/board/rockchip/evb_rk3328/MAINTAINERS
 128 @@ -24,6 +24,12 @@ S:      Maintained
 129  F:      configs/orangepi-r1-plus-rk3328_defconfig
 130  F:      arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
 131
 132 +ORANGEPI-R1-PLUS-LTS-RK3328
 133 +M:      Tianling Shen <cnsztl@gmail.com>
 134 +S:      Maintained
 135 +F:      configs/orangepi-r1-plus-lts-rk3328_defconfig
 136 +F:      arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
 137 +
 138  ROC-RK3328-CC
 139  M:      Loic Devulder <ldevulder@suse.com>
 140  M:      Chen-Yu Tsai <wens@csie.org>
 141 --- /dev/null
 142 +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
 143 @@ -0,0 +1,114 @@
 144 +CONFIG_ARM=y
 145 +CONFIG_SKIP_LOWLEVEL_INIT=y
 146 +CONFIG_COUNTER_FREQUENCY=24000000
 147 +CONFIG_ARCH_ROCKCHIP=y
 148 +CONFIG_TEXT_BASE=0x00200000
 149 +CONFIG_SPL_GPIO=y
 150 +CONFIG_NR_DRAM_BANKS=1
 151 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 152 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
 153 +CONFIG_ENV_OFFSET=0x3F8000
 154 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
 155 +CONFIG_DM_RESET=y
 156 +CONFIG_ROCKCHIP_RK3328=y
 157 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 158 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
 159 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
 160 +CONFIG_SPL_DRIVERS_MISC=y
 161 +CONFIG_SPL_STACK_R_ADDR=0x600000
 162 +CONFIG_SPL_STACK=0x400000
 163 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 164 +CONFIG_DEBUG_UART_BASE=0xFF130000
 165 +CONFIG_DEBUG_UART_CLOCK=24000000
 166 +CONFIG_SYS_LOAD_ADDR=0x800800
 167 +CONFIG_DEBUG_UART=y
 168 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 169 +CONFIG_FIT=y
 170 +CONFIG_FIT_VERBOSE=y
 171 +CONFIG_SPL_LOAD_FIT=y
 172 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
 173 +# CONFIG_DISPLAY_CPUINFO is not set
 174 +CONFIG_DISPLAY_BOARDINFO_LATE=y
 175 +CONFIG_MISC_INIT_R=y
 176 +CONFIG_SPL_MAX_SIZE=0x40000
 177 +CONFIG_SPL_PAD_TO=0x7f8000
 178 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 179 +CONFIG_SPL_BSS_START_ADDR=0x2000000
 180 +CONFIG_SPL_BSS_MAX_SIZE=0x2000
 181 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 182 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 183 +CONFIG_SPL_STACK_R=y
 184 +CONFIG_SPL_I2C=y
 185 +CONFIG_SPL_POWER=y
 186 +CONFIG_SPL_ATF=y
 187 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 188 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 189 +CONFIG_CMD_BOOTZ=y
 190 +CONFIG_CMD_GPT=y
 191 +CONFIG_CMD_MMC=y
 192 +CONFIG_CMD_USB=y
 193 +# CONFIG_CMD_SETEXPR is not set
 194 +CONFIG_CMD_TIME=y
 195 +CONFIG_SPL_OF_CONTROL=y
 196 +CONFIG_TPL_OF_CONTROL=y
 197 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 198 +CONFIG_TPL_OF_PLATDATA=y
 199 +CONFIG_ENV_IS_IN_MMC=y
 200 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 201 +CONFIG_SYS_MMC_ENV_DEV=1
 202 +CONFIG_NET_RANDOM_ETHADDR=y
 203 +CONFIG_TPL_DM=y
 204 +CONFIG_REGMAP=y
 205 +CONFIG_SPL_REGMAP=y
 206 +CONFIG_TPL_REGMAP=y
 207 +CONFIG_SYSCON=y
 208 +CONFIG_SPL_SYSCON=y
 209 +CONFIG_TPL_SYSCON=y
 210 +CONFIG_CLK=y
 211 +CONFIG_SPL_CLK=y
 212 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
 213 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 214 +CONFIG_ROCKCHIP_GPIO=y
 215 +CONFIG_SYS_I2C_ROCKCHIP=y
 216 +CONFIG_MMC_DW=y
 217 +CONFIG_MMC_DW_ROCKCHIP=y
 218 +CONFIG_SF_DEFAULT_SPEED=20000000
 219 +CONFIG_SPI_FLASH_GIGADEVICE=y
 220 +CONFIG_ETH_DESIGNWARE=y
 221 +CONFIG_GMAC_ROCKCHIP=y
 222 +CONFIG_PINCTRL=y
 223 +CONFIG_SPL_PINCTRL=y
 224 +CONFIG_DM_PMIC=y
 225 +CONFIG_PMIC_RK8XX=y
 226 +CONFIG_SPL_PMIC_RK8XX=y
 227 +CONFIG_SPL_DM_REGULATOR=y
 228 +CONFIG_REGULATOR_PWM=y
 229 +CONFIG_DM_REGULATOR_FIXED=y
 230 +CONFIG_SPL_DM_REGULATOR_FIXED=y
 231 +CONFIG_REGULATOR_RK8XX=y
 232 +CONFIG_PWM_ROCKCHIP=y
 233 +CONFIG_RAM=y
 234 +CONFIG_SPL_RAM=y
 235 +CONFIG_TPL_RAM=y
 236 +CONFIG_BAUDRATE=1500000
 237 +CONFIG_DEBUG_UART_SHIFT=2
 238 +CONFIG_SYS_NS16550_MEM32=y
 239 +CONFIG_ROCKCHIP_SPI=y
 240 +CONFIG_SYSINFO=y
 241 +CONFIG_SYSRESET=y
 242 +# CONFIG_TPL_SYSRESET is not set
 243 +CONFIG_USB=y
 244 +CONFIG_USB_XHCI_HCD=y
 245 +CONFIG_USB_XHCI_DWC3=y
 246 +CONFIG_USB_EHCI_HCD=y
 247 +CONFIG_USB_EHCI_GENERIC=y
 248 +CONFIG_USB_OHCI_HCD=y
 249 +CONFIG_USB_OHCI_GENERIC=y
 250 +CONFIG_USB_DWC2=y
 251 +CONFIG_USB_DWC3=y
 252 +# CONFIG_USB_DWC3_GADGET is not set
 253 +CONFIG_USB_GADGET=y
 254 +CONFIG_USB_GADGET_DWC2_OTG=y
 255 +CONFIG_SPL_TINY_MEMSET=y
 256 +CONFIG_TPL_TINY_MEMSET=y
 257 +CONFIG_ERRNO_STR=y