package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch

   1 From d62b483092035bc86d1db83ea4ac29bfa7bba77d Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 19 Jul 2023 17:17:31 +0800
   4 Subject: [PATCH 24/29] net: mediatek: add USXGMII support
   5
   6 This patch adds support for USXGMII of SoC.
   7
   8 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
   9 ---
  10  drivers/net/mtk_eth.c | 230 +++++++++++++++++++++++++++++++++++++++++-
  11  drivers/net/mtk_eth.h |  24 +++++
  12  2 files changed, 251 insertions(+), 3 deletions(-)
  13
  14 --- a/drivers/net/mtk_eth.c
  15 +++ b/drivers/net/mtk_eth.c
  16 @@ -105,6 +105,11 @@ struct mtk_eth_priv {
  17
  18         struct regmap *infra_regmap;
  19
  20 +       struct regmap *usxgmii_regmap;
  21 +       struct regmap *xfi_pextp_regmap;
  22 +       struct regmap *xfi_pll_regmap;
  23 +       struct regmap *toprgu_regmap;
  24 +
  25         struct mii_dev *mdio_bus;
  26         int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
  27         int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
  28 @@ -989,6 +994,42 @@ static int mt753x_switch_init(struct mtk
  29         return 0;
  30  }
  31
  32 +static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
  33 +{
  34 +       u16 lcl_adv = 0, rmt_adv = 0;
  35 +       u8 flowctrl;
  36 +       u32 mcr;
  37 +
  38 +       mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
  39 +       mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
  40 +
  41 +       if (priv->phydev->duplex) {
  42 +               if (priv->phydev->pause)
  43 +                       rmt_adv = LPA_PAUSE_CAP;
  44 +               if (priv->phydev->asym_pause)
  45 +                       rmt_adv |= LPA_PAUSE_ASYM;
  46 +
  47 +               if (priv->phydev->advertising & ADVERTISED_Pause)
  48 +                       lcl_adv |= ADVERTISE_PAUSE_CAP;
  49 +               if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
  50 +                       lcl_adv |= ADVERTISE_PAUSE_ASYM;
  51 +
  52 +               flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
  53 +
  54 +               if (flowctrl & FLOW_CTRL_TX)
  55 +                       mcr |= XGMAC_FORCE_TX_FC;
  56 +               if (flowctrl & FLOW_CTRL_RX)
  57 +                       mcr |= XGMAC_FORCE_RX_FC;
  58 +
  59 +               debug("rx pause %s, tx pause %s\n",
  60 +                     flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
  61 +                     flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
  62 +       }
  63 +
  64 +       mcr &= ~(XGMAC_TRX_DISABLE);
  65 +       mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
  66 +}
  67 +
  68  static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
  69  {
  70         u16 lcl_adv = 0, rmt_adv = 0;
  71 @@ -1063,8 +1104,12 @@ static int mtk_phy_start(struct mtk_eth_
  72                 return 0;
  73         }
  74
  75 -       if (!priv->force_mode)
  76 -               mtk_phy_link_adjust(priv);
  77 +       if (!priv->force_mode) {
  78 +               if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
  79 +                       mtk_xphy_link_adjust(priv);
  80 +               else
  81 +                       mtk_phy_link_adjust(priv);
  82 +       }
  83
  84         debug("Speed: %d, %s duplex%s\n", phydev->speed,
  85               (phydev->duplex) ? "full" : "half",
  86 @@ -1140,6 +1185,112 @@ static void mtk_sgmii_force_init(struct
  87                         SGMII_PHYA_PWD, 0);
  88  }
  89
  90 +static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
  91 +{
  92 +       u32 val = 0;
  93 +
  94 +       /* Add software workaround for USXGMII PLL TCL issue */
  95 +       regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
  96 +                    RG_XFI_PLL_ANA_SWWA);
  97 +
  98 +       regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
  99 +       val |= RG_XFI_PLL_EN;
 100 +       regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
 101 +}
 102 +
 103 +static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
 104 +{
 105 +       switch (priv->gmac_id) {
 106 +       case 1:
 107 +               regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
 108 +               regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
 109 +               regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
 110 +               regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
 111 +               regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
 112 +               break;
 113 +       case 2:
 114 +               regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
 115 +               regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
 116 +               regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
 117 +               regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
 118 +               regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
 119 +               break;
 120 +       }
 121 +
 122 +       mdelay(10);
 123 +}
 124 +
 125 +static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
 126 +{
 127 +       regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
 128 +       regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
 129 +       regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
 130 +       ndelay(1020);
 131 +       regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
 132 +       ndelay(1020);
 133 +       regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
 134 +
 135 +       regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
 136 +       regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
 137 +       regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
 138 +       regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
 139 +       regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
 140 +       regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
 141 +       regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
 142 +       regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
 143 +       regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
 144 +       regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
 145 +       regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
 146 +       regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
 147 +       regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
 148 +       regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
 149 +       regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
 150 +       regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
 151 +       regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
 152 +       regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
 153 +       regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
 154 +       regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
 155 +       regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
 156 +       regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
 157 +       regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
 158 +       regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
 159 +       ndelay(1020);
 160 +       regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
 161 +       regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
 162 +       regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
 163 +       regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
 164 +       regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
 165 +       regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
 166 +       regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
 167 +       regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
 168 +       regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
 169 +       regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
 170 +       regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
 171 +       regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
 172 +       regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
 173 +       regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
 174 +       udelay(150);
 175 +       regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
 176 +       ndelay(1020);
 177 +       regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
 178 +       udelay(15);
 179 +       regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
 180 +       ndelay(1020);
 181 +       regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
 182 +       udelay(100);
 183 +       regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
 184 +       regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
 185 +       regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
 186 +       udelay(400);
 187 +}
 188 +
 189 +static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
 190 +{
 191 +       mtk_xfi_pll_enable(priv);
 192 +       mtk_usxgmii_reset(priv);
 193 +       mtk_usxgmii_setup_phya_an_10000(priv);
 194 +}
 195 +
 196  static void mtk_mac_init(struct mtk_eth_priv *priv)
 197  {
 198         int i, ge_mode = 0;
 199 @@ -1222,6 +1373,36 @@ static void mtk_mac_init(struct mtk_eth_
 200         }
 201  }
 202
 203 +static void mtk_xmac_init(struct mtk_eth_priv *priv)
 204 +{
 205 +       u32 sts;
 206 +
 207 +       switch (priv->phy_interface) {
 208 +       case PHY_INTERFACE_MODE_USXGMII:
 209 +               mtk_usxgmii_an_init(priv);
 210 +               break;
 211 +       default:
 212 +               break;
 213 +       }
 214 +
 215 +       /* Set GMAC to the correct mode */
 216 +       mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
 217 +                      SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
 218 +                      0);
 219 +
 220 +       if (priv->gmac_id == 1) {
 221 +               mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
 222 +                             NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
 223 +       } else if (priv->gmac_id == 2) {
 224 +               sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id));
 225 +               sts |= XGMAC_FORCE_LINK;
 226 +               mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts);
 227 +       }
 228 +
 229 +       /* Force GMAC link down */
 230 +       mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
 231 +}
 232 +
 233  static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
 234  {
 235         char *pkt_base = priv->pkt_pool;
 236 @@ -1463,7 +1644,10 @@ static int mtk_eth_probe(struct udevice
 237                                 ARCH_DMA_MINALIGN);
 238
 239         /* Set MAC mode */
 240 -       mtk_mac_init(priv);
 241 +       if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
 242 +               mtk_xmac_init(priv);
 243 +       else
 244 +               mtk_mac_init(priv);
 245
 246         /* Probe phy if switch is not specified */
 247         if (priv->sw == SW_NONE)
 248 @@ -1581,6 +1765,46 @@ static int mtk_eth_of_to_plat(struct ude
 249                 }
 250
 251                 priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
 252 +       } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
 253 +               /* get corresponding usxgmii phandle */
 254 +               ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
 255 +                                                NULL, 0, 0, &args);
 256 +               if (ret)
 257 +                       return ret;
 258 +
 259 +               priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
 260 +               if (IS_ERR(priv->usxgmii_regmap))
 261 +                       return PTR_ERR(priv->usxgmii_regmap);
 262 +
 263 +               /* get corresponding xfi_pextp phandle */
 264 +               ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
 265 +                                                NULL, 0, 0, &args);
 266 +               if (ret)
 267 +                       return ret;
 268 +
 269 +               priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
 270 +               if (IS_ERR(priv->xfi_pextp_regmap))
 271 +                       return PTR_ERR(priv->xfi_pextp_regmap);
 272 +
 273 +               /* get corresponding xfi_pll phandle */
 274 +               ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
 275 +                                                NULL, 0, 0, &args);
 276 +               if (ret)
 277 +                       return ret;
 278 +
 279 +               priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
 280 +               if (IS_ERR(priv->xfi_pll_regmap))
 281 +                       return PTR_ERR(priv->xfi_pll_regmap);
 282 +
 283 +               /* get corresponding toprgu phandle */
 284 +               ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
 285 +                                                NULL, 0, 0, &args);
 286 +               if (ret)
 287 +                       return ret;
 288 +
 289 +               priv->toprgu_regmap = syscon_node_to_regmap(args.node);
 290 +               if (IS_ERR(priv->toprgu_regmap))
 291 +                       return PTR_ERR(priv->toprgu_regmap);
 292         }
 293
 294         /* check for switch first, otherwise phy will be used */
 295 --- a/drivers/net/mtk_eth.h
 296 +++ b/drivers/net/mtk_eth.h
 297 @@ -68,6 +68,11 @@ enum mkt_eth_capabilities {
 298  #define ETHSYS_TRGMII_CLK_SEL362_5     BIT(11)
 299
 300  /* Top misc registers */
 301 +#define TOPMISC_NETSYS_PCS_MUX         0x84
 302 +#define NETSYS_PCS_MUX_MASK            GENMASK(1, 0)
 303 +#define MUX_G2_USXGMII_SEL             BIT(1)
 304 +#define MUX_HSGMII1_G1_SEL             BIT(0)
 305 +
 306  #define USB_PHY_SWITCH_REG             0x218
 307  #define QPHY_SEL_MASK                  0x3
 308  #define SGMII_QPHY_SEL                 0x2
 309 @@ -98,6 +103,15 @@ enum mkt_eth_capabilities {
 310  #define SGMSYS_GEN2_SPEED_V2           0x128
 311  #define SGMSYS_SPEED_2500              BIT(2)
 312
 313 +/* USXGMII subsystem config registers */
 314 +/* Register to control USXGMII XFI PLL digital */
 315 +#define XFI_PLL_DIG_GLB8               0x08
 316 +#define RG_XFI_PLL_EN                  BIT(31)
 317 +
 318 +/* Register to control USXGMII XFI PLL analog */
 319 +#define XFI_PLL_ANA_GLB8               0x108
 320 +#define RG_XFI_PLL_ANA_SWWA            0x02283248
 321 +
 322  /* Frame Engine Registers */
 323  #define FE_GLO_MISC_REG                        0x124
 324  #define PDMA_VER_V2                    BIT(4)
 325 @@ -221,6 +235,16 @@ enum mkt_eth_capabilities {
 326  #define TD_DM_DRVP_S                   0
 327  #define TD_DM_DRVP_M                   0x0f
 328
 329 +/* XGMAC Status Registers */
 330 +#define XGMAC_STS(x)                   (((x) == 2) ? 0x001C : 0x000C)
 331 +#define XGMAC_FORCE_LINK               BIT(15)
 332 +
 333 +/* XGMAC Registers */
 334 +#define XGMAC_PORT_MCR(x)              (0x2000 + (((x) - 1) * 0x1000))
 335 +#define XGMAC_TRX_DISABLE              0xf
 336 +#define XGMAC_FORCE_TX_FC              BIT(5)
 337 +#define XGMAC_FORCE_RX_FC              BIT(4)
 338 +
 339  /* MT7530 Registers */
 340
 341  #define PCR_REG(p)                     (0x2004 + (p) * 0x100)