fdts/stm32mp157a-dk1.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2018-2019 - All Rights Reserved
   4  * Author: Alexandre Torgue <alexandre.torgue@st.com>.
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "stm32mp157c.dtsi"
  10 #include "stm32mp157cac-pinctrl.dtsi"
  11
  12 / {
  13         model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
  14         compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
  15
  16         aliases {
  17                 serial0 = &uart4;
  18                 serial1 = &usart3;
  19                 serial2 = &uart7;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26 };
  27
  28 &clk_hse {
  29         st,digbypass;
  30 };
  31
  32 &i2c4 {
  33         pinctrl-names = "default";
  34         pinctrl-0 = <&i2c4_pins_a>;
  35         i2c-scl-rising-time-ns = <185>;
  36         i2c-scl-falling-time-ns = <20>;
  37         status = "okay";
  38
  39         pmic: stpmic@33 {
  40                 compatible = "st,stpmic1";
  41                 reg = <0x33>;
  42                 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
  43                 interrupt-controller;
  44                 #interrupt-cells = <2>;
  45                 status = "okay";
  46
  47                 st,main-control-register = <0x04>;
  48                 st,vin-control-register = <0xc0>;
  49                 st,usb-control-register = <0x20>;
  50
  51                 regulators {
  52                         compatible = "st,stpmic1-regulators";
  53
  54                         ldo1-supply = <&v3v3>;
  55                         ldo3-supply = <&vdd_ddr>;
  56                         ldo6-supply = <&v3v3>;
  57
  58                         vddcore: buck1 {
  59                                 regulator-name = "vddcore";
  60                                 regulator-min-microvolt = <1200000>;
  61                                 regulator-max-microvolt = <1350000>;
  62                                 regulator-always-on;
  63                                 regulator-initial-mode = <0>;
  64                                 regulator-over-current-protection;
  65                         };
  66
  67                         vdd_ddr: buck2 {
  68                                 regulator-name = "vdd_ddr";
  69                                 regulator-min-microvolt = <1350000>;
  70                                 regulator-max-microvolt = <1350000>;
  71                                 regulator-always-on;
  72                                 regulator-initial-mode = <0>;
  73                                 regulator-over-current-protection;
  74                         };
  75
  76                         vdd: buck3 {
  77                                 regulator-name = "vdd";
  78                                 regulator-min-microvolt = <3300000>;
  79                                 regulator-max-microvolt = <3300000>;
  80                                 regulator-always-on;
  81                                 st,mask-reset;
  82                                 regulator-initial-mode = <0>;
  83                                 regulator-over-current-protection;
  84                         };
  85
  86                         v3v3: buck4 {
  87                                 regulator-name = "v3v3";
  88                                 regulator-min-microvolt = <3300000>;
  89                                 regulator-max-microvolt = <3300000>;
  90                                 regulator-always-on;
  91                                 regulator-over-current-protection;
  92                                 regulator-initial-mode = <0>;
  93                         };
  94
  95                         v1v8_audio: ldo1 {
  96                                 regulator-name = "v1v8_audio";
  97                                 regulator-min-microvolt = <1800000>;
  98                                 regulator-max-microvolt = <1800000>;
  99                                 regulator-always-on;
 100                         };
 101
 102                         v3v3_hdmi: ldo2 {
 103                                 regulator-name = "v3v3_hdmi";
 104                                 regulator-min-microvolt = <3300000>;
 105                                 regulator-max-microvolt = <3300000>;
 106                                 regulator-always-on;
 107                         };
 108
 109                         vtt_ddr: ldo3 {
 110                                 regulator-name = "vtt_ddr";
 111                                 regulator-min-microvolt = <500000>;
 112                                 regulator-max-microvolt = <750000>;
 113                                 regulator-always-on;
 114                                 regulator-over-current-protection;
 115                         };
 116
 117                         vdd_usb: ldo4 {
 118                                 regulator-name = "vdd_usb";
 119                                 regulator-min-microvolt = <3300000>;
 120                                 regulator-max-microvolt = <3300000>;
 121                         };
 122
 123                         vdda: ldo5 {
 124                                 regulator-name = "vdda";
 125                                 regulator-min-microvolt = <2900000>;
 126                                 regulator-max-microvolt = <2900000>;
 127                                 regulator-boot-on;
 128                         };
 129
 130                         v1v2_hdmi: ldo6 {
 131                                 regulator-name = "v1v2_hdmi";
 132                                 regulator-min-microvolt = <1200000>;
 133                                 regulator-max-microvolt = <1200000>;
 134                                 regulator-always-on;
 135                         };
 136
 137                         vref_ddr: vref_ddr {
 138                                 regulator-name = "vref_ddr";
 139                                 regulator-always-on;
 140                                 regulator-over-current-protection;
 141                         };
 142                 };
 143         };
 144 };
 145
 146 &iwdg2 {
 147         timeout-sec = <32>;
 148         status = "okay";
 149 };
 150
 151 &pwr {
 152         pwr-regulators {
 153                 vdd-supply = <&vdd>;
 154         };
 155 };
 156
 157 &rng1 {
 158         status = "okay";
 159 };
 160
 161 &rtc {
 162         status = "okay";
 163 };
 164
 165 &sdmmc1 {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&sdmmc1_b4_pins_a>;
 168         broken-cd;
 169         st,neg-edge;
 170         bus-width = <4>;
 171         vmmc-supply = <&v3v3>;
 172         status = "okay";
 173 };
 174
 175 &uart4 {
 176         pinctrl-names = "default";
 177         pinctrl-0 = <&uart4_pins_a>;
 178         status = "okay";
 179 };
 180
 181 &uart7 {
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&uart7_pins_a>;
 184         status = "disabled";
 185 };
 186
 187 &usart3 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&usart3_pins_b>;
 190         status = "disabled";
 191 };
 192
 193 /* ATF Specific */
 194 #include <dt-bindings/clock/stm32mp1-clksrc.h>
 195 #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
 196 #include "stm32mp157c-security.dtsi"
 197
 198 / {
 199         aliases {
 200                 gpio0 = &gpioa;
 201                 gpio1 = &gpiob;
 202                 gpio2 = &gpioc;
 203                 gpio3 = &gpiod;
 204                 gpio4 = &gpioe;
 205                 gpio5 = &gpiof;
 206                 gpio6 = &gpiog;
 207                 gpio7 = &gpioh;
 208                 gpio8 = &gpioi;
 209                 gpio25 = &gpioz;
 210                 i2c3 = &i2c4;
 211         };
 212 };
 213
 214 /* CLOCK init */
 215 &rcc {
 216         secure-status = "disabled";
 217         st,clksrc = <
 218                 CLK_MPU_PLL1P
 219                 CLK_AXI_PLL2P
 220                 CLK_MCU_PLL3P
 221                 CLK_PLL12_HSE
 222                 CLK_PLL3_HSE
 223                 CLK_PLL4_HSE
 224                 CLK_RTC_LSE
 225                 CLK_MCO1_DISABLED
 226                 CLK_MCO2_DISABLED
 227         >;
 228
 229         st,clkdiv = <
 230                 1 /*MPU*/
 231                 0 /*AXI*/
 232                 0 /*MCU*/
 233                 1 /*APB1*/
 234                 1 /*APB2*/
 235                 1 /*APB3*/
 236                 1 /*APB4*/
 237                 2 /*APB5*/
 238                 23 /*RTC*/
 239                 0 /*MCO1*/
 240                 0 /*MCO2*/
 241         >;
 242
 243         st,pkcs = <
 244                 CLK_CKPER_HSE
 245                 CLK_FMC_ACLK
 246                 CLK_QSPI_ACLK
 247                 CLK_ETH_DISABLED
 248                 CLK_SDMMC12_PLL4P
 249                 CLK_DSI_DSIPLL
 250                 CLK_STGEN_HSE
 251                 CLK_USBPHY_HSE
 252                 CLK_SPI2S1_PLL3Q
 253                 CLK_SPI2S23_PLL3Q
 254                 CLK_SPI45_HSI
 255                 CLK_SPI6_HSI
 256                 CLK_I2C46_HSI
 257                 CLK_SDMMC3_PLL4P
 258                 CLK_USBO_USBPHY
 259                 CLK_ADC_CKPER
 260                 CLK_CEC_LSE
 261                 CLK_I2C12_HSI
 262                 CLK_I2C35_HSI
 263                 CLK_UART1_HSI
 264                 CLK_UART24_HSI
 265                 CLK_UART35_HSI
 266                 CLK_UART6_HSI
 267                 CLK_UART78_HSI
 268                 CLK_SPDIF_PLL4P
 269                 CLK_FDCAN_PLL4R
 270                 CLK_SAI1_PLL3Q
 271                 CLK_SAI2_PLL3Q
 272                 CLK_SAI3_PLL3Q
 273                 CLK_SAI4_PLL3Q
 274                 CLK_RNG1_LSI
 275                 CLK_RNG2_LSI
 276                 CLK_LPTIM1_PCLK1
 277                 CLK_LPTIM23_PCLK3
 278                 CLK_LPTIM45_LSE
 279         >;
 280
 281         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 282         pll1: st,pll@0 {
 283                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 284                 frac = < 0x800 >;
 285         };
 286
 287         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 288         pll2: st,pll@1 {
 289                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 290                 frac = < 0x1400 >;
 291         };
 292
 293         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 294         pll3: st,pll@2 {
 295                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 296                 frac = < 0x1a04 >;
 297         };
 298
 299         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 300         pll4: st,pll@3 {
 301                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 302         };
 303 };
 304
 305 &bsec {
 306         board_id: board_id@ec {
 307                 reg = <0xec 0x4>;
 308                 status = "okay";
 309                 secure-status = "okay";
 310         };
 311 };