fdts/stm32mp157-pinctrl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
   7
   8 / {
   9         soc {
  10                 pinctrl: pin-controller@50002000 {
  11                         #address-cells = <1>;
  12                         #size-cells = <1>;
  13                         compatible = "st,stm32mp157-pinctrl";
  14                         ranges = <0 0x50002000 0xa400>;
  15                         pins-are-numbered;
  16
  17                         gpioa: gpio@50002000 {
  18                                 gpio-controller;
  19                                 #gpio-cells = <2>;
  20                                 interrupt-controller;
  21                                 #interrupt-cells = <2>;
  22                                 reg = <0x0 0x400>;
  23                                 clocks = <&rcc GPIOA>;
  24                                 st,bank-name = "GPIOA";
  25                                 status = "disabled";
  26                         };
  27
  28                         gpiob: gpio@50003000 {
  29                                 gpio-controller;
  30                                 #gpio-cells = <2>;
  31                                 interrupt-controller;
  32                                 #interrupt-cells = <2>;
  33                                 reg = <0x1000 0x400>;
  34                                 clocks = <&rcc GPIOB>;
  35                                 st,bank-name = "GPIOB";
  36                                 status = "disabled";
  37                         };
  38
  39                         gpioc: gpio@50004000 {
  40                                 gpio-controller;
  41                                 #gpio-cells = <2>;
  42                                 interrupt-controller;
  43                                 #interrupt-cells = <2>;
  44                                 reg = <0x2000 0x400>;
  45                                 clocks = <&rcc GPIOC>;
  46                                 st,bank-name = "GPIOC";
  47                                 status = "disabled";
  48                         };
  49
  50                         gpiod: gpio@50005000 {
  51                                 gpio-controller;
  52                                 #gpio-cells = <2>;
  53                                 interrupt-controller;
  54                                 #interrupt-cells = <2>;
  55                                 reg = <0x3000 0x400>;
  56                                 clocks = <&rcc GPIOD>;
  57                                 st,bank-name = "GPIOD";
  58                                 status = "disabled";
  59                         };
  60
  61                         gpioe: gpio@50006000 {
  62                                 gpio-controller;
  63                                 #gpio-cells = <2>;
  64                                 interrupt-controller;
  65                                 #interrupt-cells = <2>;
  66                                 reg = <0x4000 0x400>;
  67                                 clocks = <&rcc GPIOE>;
  68                                 st,bank-name = "GPIOE";
  69                                 status = "disabled";
  70                         };
  71
  72                         gpiof: gpio@50007000 {
  73                                 gpio-controller;
  74                                 #gpio-cells = <2>;
  75                                 interrupt-controller;
  76                                 #interrupt-cells = <2>;
  77                                 reg = <0x5000 0x400>;
  78                                 clocks = <&rcc GPIOF>;
  79                                 st,bank-name = "GPIOF";
  80                                 status = "disabled";
  81                         };
  82
  83                         gpiog: gpio@50008000 {
  84                                 gpio-controller;
  85                                 #gpio-cells = <2>;
  86                                 interrupt-controller;
  87                                 #interrupt-cells = <2>;
  88                                 reg = <0x6000 0x400>;
  89                                 clocks = <&rcc GPIOG>;
  90                                 st,bank-name = "GPIOG";
  91                                 status = "disabled";
  92                         };
  93
  94                         gpioh: gpio@50009000 {
  95                                 gpio-controller;
  96                                 #gpio-cells = <2>;
  97                                 interrupt-controller;
  98                                 #interrupt-cells = <2>;
  99                                 reg = <0x7000 0x400>;
 100                                 clocks = <&rcc GPIOH>;
 101                                 st,bank-name = "GPIOH";
 102                                 status = "disabled";
 103                         };
 104
 105                         gpioi: gpio@5000a000 {
 106                                 gpio-controller;
 107                                 #gpio-cells = <2>;
 108                                 interrupt-controller;
 109                                 #interrupt-cells = <2>;
 110                                 reg = <0x8000 0x400>;
 111                                 clocks = <&rcc GPIOI>;
 112                                 st,bank-name = "GPIOI";
 113                                 status = "disabled";
 114                         };
 115
 116                         gpioj: gpio@5000b000 {
 117                                 gpio-controller;
 118                                 #gpio-cells = <2>;
 119                                 interrupt-controller;
 120                                 #interrupt-cells = <2>;
 121                                 reg = <0x9000 0x400>;
 122                                 clocks = <&rcc GPIOJ>;
 123                                 st,bank-name = "GPIOJ";
 124                                 status = "disabled";
 125                         };
 126
 127                         gpiok: gpio@5000c000 {
 128                                 gpio-controller;
 129                                 #gpio-cells = <2>;
 130                                 interrupt-controller;
 131                                 #interrupt-cells = <2>;
 132                                 reg = <0xa000 0x400>;
 133                                 clocks = <&rcc GPIOK>;
 134                                 st,bank-name = "GPIOK";
 135                                 status = "disabled";
 136                         };
 137
 138                         qspi_bk1_pins_a: qspi-bk1-0 {
 139                                 pins1 {
 140                                         pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
 141                                                  <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
 142                                                  <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
 143                                                  <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
 144                                         bias-disable;
 145                                         drive-push-pull;
 146                                         slew-rate = <1>;
 147                                 };
 148                                 pins2 {
 149                                         pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
 150                                         bias-pull-up;
 151                                         drive-push-pull;
 152                                         slew-rate = <1>;
 153                                 };
 154                         };
 155
 156                         qspi_bk2_pins_a: qspi-bk2-0 {
 157                                 pins1 {
 158                                         pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
 159                                                  <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
 160                                                  <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
 161                                                  <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
 162                                         bias-disable;
 163                                         drive-push-pull;
 164                                         slew-rate = <1>;
 165                                 };
 166                                 pins2 {
 167                                         pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
 168                                         bias-pull-up;
 169                                         drive-push-pull;
 170                                         slew-rate = <1>;
 171                                 };
 172                         };
 173
 174                         qspi_clk_pins_a: qspi-clk-0 {
 175                                 pins {
 176                                         pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
 177                                         bias-disable;
 178                                         drive-push-pull;
 179                                         slew-rate = <3>;
 180                                 };
 181                         };
 182
 183                         sdmmc1_b4_pins_a: sdmmc1-b4-0 {
 184                                 pins1 {
 185                                         pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
 186                                                  <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
 187                                                  <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
 188                                                  <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
 189                                                  <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
 190                                         slew-rate = <1>;
 191                                         drive-push-pull;
 192                                         bias-disable;
 193                                 };
 194                                 pins2 {
 195                                         pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
 196                                         slew-rate = <2>;
 197                                         drive-push-pull;
 198                                         bias-disable;
 199                                 };
 200                         };
 201
 202                         sdmmc1_dir_pins_a: sdmmc1-dir-0 {
 203                                 pins1 {
 204                                         pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
 205                                                  <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
 206                                                  <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
 207                                         slew-rate = <1>;
 208                                         drive-push-pull;
 209                                         bias-pull-up;
 210                                 };
 211                                 pins2{
 212                                         pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
 213                                         bias-pull-up;
 214                                 };
 215                         };
 216
 217                         sdmmc2_b4_pins_a: sdmmc2-b4-0 {
 218                                 pins1 {
 219                                         pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
 220                                                  <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
 221                                                  <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
 222                                                  <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
 223                                                  <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
 224                                         slew-rate = <1>;
 225                                         drive-push-pull;
 226                                         bias-pull-up;
 227                                 };
 228                                 pins2 {
 229                                         pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
 230                                         slew-rate = <2>;
 231                                         drive-push-pull;
 232                                         bias-pull-up;
 233                                 };
 234                         };
 235
 236                         sdmmc2_d47_pins_a: sdmmc2-d47-0 {
 237                                 pins {
 238                                         pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
 239                                                  <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
 240                                                  <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
 241                                                  <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
 242                                         slew-rate = <1>;
 243                                         drive-push-pull;
 244                                         bias-pull-up;
 245                                 };
 246                         };
 247
 248                         uart4_pins_a: uart4-0 {
 249                                 pins1 {
 250                                         pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
 251                                         bias-disable;
 252                                         drive-push-pull;
 253                                         slew-rate = <0>;
 254                                 };
 255                                 pins2 {
 256                                         pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
 257                                         bias-disable;
 258                                 };
 259                         };
 260
 261                         uart4_pins_b: uart4-1 {
 262                                 pins1 {
 263                                         pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
 264                                         bias-disable;
 265                                         drive-push-pull;
 266                                         slew-rate = <0>;
 267                                 };
 268                                 pins2 {
 269                                         pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
 270                                         bias-disable;
 271                                 };
 272                         };
 273
 274                         uart7_pins_a: uart7-0 {
 275                                 pins1 {
 276                                         pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
 277                                         bias-disable;
 278                                         drive-push-pull;
 279                                         slew-rate = <0>;
 280                                 };
 281                                 pins2 {
 282                                         pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
 283                                         bias-disable;
 284                                 };
 285                         };
 286
 287                         usart3_pins_a: usart3-0 {
 288                                 pins1 {
 289                                         pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
 290                                                  <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
 291                                         bias-disable;
 292                                         drive-push-pull;
 293                                         slew-rate = <0>;
 294                                 };
 295                                 pins2 {
 296                                         pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
 297                                                  <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
 298                                         bias-disable;
 299                                 };
 300                         };
 301
 302                         usart3_pins_b: usart3-1 {
 303                                 pins1 {
 304                                         pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
 305                                                  <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
 306                                         bias-disable;
 307                                         drive-push-pull;
 308                                         slew-rate = <0>;
 309                                 };
 310                                 pins2 {
 311                                         pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
 312                                                  <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
 313                                         bias-disable;
 314                                 };
 315                         };
 316                 };
 317
 318                 pinctrl_z: pin-controller-z@54004000 {
 319                         #address-cells = <1>;
 320                         #size-cells = <1>;
 321                         compatible = "st,stm32mp157-z-pinctrl";
 322                         ranges = <0 0x54004000 0x400>;
 323                         pins-are-numbered;
 324
 325                         gpioz: gpio@54004000 {
 326                                 gpio-controller;
 327                                 #gpio-cells = <2>;
 328                                 interrupt-controller;
 329                                 #interrupt-cells = <2>;
 330                                 reg = <0 0x400>;
 331                                 clocks = <&rcc GPIOZ>;
 332                                 st,bank-name = "GPIOZ";
 333                                 st,bank-ioport = <11>;
 334                                 status = "disabled";
 335                         };
 336
 337                         i2c4_pins_a: i2c4-0 {
 338                                 pins {
 339                                         pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
 340                                                  <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
 341                                         bias-disable;
 342                                         drive-open-drain;
 343                                         slew-rate = <0>;
 344                                 };
 345                         };
 346                 };
 347         };
 348 };