fdts/fvp-ve-Cortex-A5x1.dts

   1 /*
   2  * Copyright (c) 2019, Arm Limited. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 /dts-v1/;
   8
   9 / {
  10         model = "V2P-CA5s";
  11         compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a5";
  23                         reg = <0>;
  24                 };
  25
  26         };
  27
  28         memory@80000000 {
  29                 device_type = "memory";
  30                 reg = <0x80000000 0x1000000>;
  31         };
  32
  33         hdlcd@2a110000 {
  34                 compatible = "arm,hdlcd";
  35                 reg = <0x2a110000 0x1000>;
  36                 interrupts = <0 85 4>;
  37                 clocks = <&oscclk3>;
  38                 clock-names = "pxlclk";
  39         };
  40
  41         scu@2c000000 {
  42                 compatible = "arm,cortex-a5-scu";
  43                 reg = <0x2c000000 0x58>;
  44         };
  45
  46         watchdog@2c000620 {
  47                 compatible = "arm,cortex-a5-twd-wdt";
  48                 reg = <0x2c000620 0x20>;
  49                 interrupts = <1 14 0x304>;
  50         };
  51
  52         gic: interrupt-controller@2c001000 {
  53                 compatible = "arm,cortex-a9-gic";
  54                 #interrupt-cells = <3>;
  55                 #address-cells = <0>;
  56                 interrupt-controller;
  57                 reg = <0x2c001000 0x1000>,
  58                       <0x2c000100 0x100>;
  59         };
  60
  61         dcc {
  62                 compatible = "arm,vexpress,config-bus";
  63                 arm,vexpress,config-bridge = <&v2m_sysreg>;
  64
  65                 oscclk0: osc@0 {
  66                         /* CPU and internal AXI reference clock */
  67                         compatible = "arm,vexpress-osc";
  68                         arm,vexpress-sysreg,func = <1 0>;
  69                         freq-range = <50000000 100000000>;
  70                         #clock-cells = <0>;
  71                         clock-output-names = "oscclk0";
  72                 };
  73
  74                 oscclk1: osc@1 {
  75                         /* Multiplexed AXI master clock */
  76                         compatible = "arm,vexpress-osc";
  77                         arm,vexpress-sysreg,func = <1 1>;
  78                         freq-range = <5000000 50000000>;
  79                         #clock-cells = <0>;
  80                         clock-output-names = "oscclk1";
  81                 };
  82
  83                 osc@2 {
  84                         /* DDR2 */
  85                         compatible = "arm,vexpress-osc";
  86                         arm,vexpress-sysreg,func = <1 2>;
  87                         freq-range = <80000000 120000000>;
  88                         #clock-cells = <0>;
  89                         clock-output-names = "oscclk2";
  90                 };
  91
  92                 oscclk3: osc@3 {
  93                         /* HDLCD */
  94                         compatible = "arm,vexpress-osc";
  95                         arm,vexpress-sysreg,func = <1 3>;
  96                         freq-range = <23750000 165000000>;
  97                         #clock-cells = <0>;
  98                         clock-output-names = "oscclk3";
  99                 };
 100
 101                 osc@4 {
 102                         /* Test chip gate configuration */
 103                         compatible = "arm,vexpress-osc";
 104                         arm,vexpress-sysreg,func = <1 4>;
 105                         freq-range = <80000000 80000000>;
 106                         #clock-cells = <0>;
 107                         clock-output-names = "oscclk4";
 108                 };
 109
 110                 smbclk: osc@5 {
 111                         /* SMB clock */
 112                         compatible = "arm,vexpress-osc";
 113                         arm,vexpress-sysreg,func = <1 5>;
 114                         freq-range = <25000000 60000000>;
 115                         #clock-cells = <0>;
 116                         clock-output-names = "oscclk5";
 117                 };
 118         };
 119
 120         smb {
 121                 compatible = "simple-bus";
 122
 123                 #address-cells = <2>;
 124                 #size-cells = <1>;
 125                 ranges = <0 0 0x08000000 0x04000000>,
 126                          <1 0 0x14000000 0x04000000>,
 127                          <2 0 0x18000000 0x04000000>,
 128                          <3 0 0x1c000000 0x04000000>,
 129                          <4 0 0x0c000000 0x04000000>,
 130                          <5 0 0x10000000 0x04000000>;
 131
 132                 #interrupt-cells = <1>;
 133                 interrupt-map-mask = <0 0 63>;
 134                 interrupt-map = <0 0  0 &gic 0  0 4>,
 135                                 <0 0  1 &gic 0  1 4>,
 136                                 <0 0  2 &gic 0  2 4>,
 137                                 <0 0  3 &gic 0  3 4>,
 138                                 <0 0  4 &gic 0  4 4>,
 139                                 <0 0  5 &gic 0  5 4>,
 140                                 <0 0 42 &gic 0 42 4>;
 141
 142                 /include/ "rtsm_ve-motherboard-aarch32.dtsi"
 143         };
 144 };