fdts/corstone700.dts

   1 /*
   2  * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 /dts-v1/;
   8
   9 / {
  10         model = "corstone700";
  11         compatible = "arm,Corstone-700";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         chosen {
  17                 bootargs = "console=ttyAMA0 root=/dev/vda2 rw loglevel=9";
  18                 linux,initrd-start = <0x02a00000>;
  19                 linux,initrd-end = <0x04000000>;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,armv8";
  29                         reg = <0>;
  30                         next-level-cache = <&L2_0>;
  31                 };
  32
  33         };
  34
  35         memory@2000000 {
  36                 device_type = "memory";
  37                 reg = <0x02000000 0x02000000>;
  38         };
  39
  40         gic: interrupt-controller@1c000000 {
  41                 compatible = "arm,gic-400";
  42                 #interrupt-cells = <3>;
  43                 #address-cells = <0>;
  44                 interrupt-controller;
  45                 reg =   <0x1c010000 0x1000>,
  46                         <0x1c02f000 0x2000>,
  47                         <0x1c04f000 0x1000>,
  48                         <0x1c06f000 0x2000>;
  49                 interrupts = <1 9 0xf08>;
  50         };
  51
  52         L2_0: l2-cache0 {
  53                 compatible = "cache";
  54         };
  55
  56         refclk100mhz: refclk100mhz {
  57                 compatible = "fixed-clock";
  58                 #clock-cells = <0>;
  59                 clock-frequency = <100000000>;
  60                 clock-output-names = "apb_pclk";
  61         };
  62
  63         smbclk: refclk24mhzx2 {
  64                 /* Reference 24MHz clock x 2 */
  65                 compatible = "fixed-clock";
  66                 #clock-cells = <0>;
  67                 clock-frequency = <48000000>;
  68                 clock-output-names = "smclk";
  69         };
  70
  71
  72         serial0: uart@1a510000 {
  73                 compatible = "arm,pl011", "arm,primecell";
  74                 reg = <0x1a510000 0x1000>;
  75                 interrupt-parent = <&gic>;
  76                 interrupts = <0 19 4>;
  77                 clocks = <&refclk100mhz>, <&smbclk>;
  78                 clock-names = "apb_pclk", "smclk";
  79         };
  80
  81         serial1: uart@1a520000 {
  82                 compatible = "arm,pl011", "arm,primecell";
  83                 reg = <0x1a520000 0x1000>;
  84                 interrupt-parent = <&gic>;
  85                 interrupts = <0 20 4>;
  86                 clocks = <&refclk100mhz>, <&smbclk>;
  87                 clock-names = "apb_pclk", "smclk";
  88         };
  89
  90         timer {
  91                 compatible = "arm,armv8-timer";
  92                 interrupts =    <1 13 0xf08>,
  93                                 <1 14 0xf08>,
  94                                 <1 11 0xf08>,
  95                                 <1 10 0xf08>;
  96                 };
  97
  98         mbox_es0mhu0: mhu@1b000000 {
  99                 compatible = "arm,mhuv2","arm,primecell";
 100                 reg = <0x1b000000 0x1000>,
 101                       <0x1b010000 0x1000>;
 102                 clocks = <&refclk100mhz>;
 103                 clock-names = "apb_pclk";
 104                 interrupts = <0 12 4>;
 105                 interrupt-names = "mhu_rx";
 106                 #mbox-cells = <1>;
 107                 mbox-name = "arm-es0-mhu0";
 108         };
 109
 110         mbox_es0mhu1: mhu@1b020000 {
 111                 compatible = "arm,mhuv2","arm,primecell";
 112                 reg = <0x1b020000 0x1000>,
 113                       <0x1b030000 0x1000>;
 114                 clocks = <&refclk100mhz>;
 115                 clock-names = "apb_pclk";
 116                 interrupts = <0 47 4>;
 117                 interrupt-names = "mhu_rx";
 118                 #mbox-cells = <1>;
 119                 mbox-name = "arm-es0-mhu1";
 120         };
 121
 122         mbox_semhu1: mhu@1b820000 {
 123                 compatible = "arm,mhuv2","arm,primecell";
 124                 reg = <0x1b820000 0x1000>,
 125                       <0x1b830000 0x1000>;
 126                 clocks = <&refclk100mhz>;
 127                 clock-names = "apb_pclk";
 128                 interrupts = <0 45 4>;
 129                 interrupt-names = "mhu_rx";
 130                 #mbox-cells = <1>;
 131                 mbox-name = "arm-se-mhu1";
 132         };
 133
 134         client {
 135                 compatible = "arm,client";
 136                 mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>;
 137                 mbox-names = "es0mhu0", "es0mhu1", "semhu1";
 138         };
 139
 140         extsys0: extsys@1A010310 {
 141                 compatible = "arm,extsys_ctrl";
 142                 reg = <0x1A010310 0x4>,
 143                       <0x1A010314 0x4>;
 144                 reg-names = "rstreg", "streg";
 145         };
 146
 147 };