2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
8 #include <asm_macros.S>
9 #include <common/bl_common.h>
10 #include <common/runtime_svc.h>
12 #include <el3_common_macros.S>
13 #include <lib/xlat_tables/xlat_tables_defs.h>
14 #include <smccc_helpers.h>
15 #include <smccc_macros.S>
17 .globl sp_min_vector_table
18 .globl sp_min_entrypoint
19 .globl sp_min_warm_entrypoint
20 .globl sp_min_handle_smc
21 .globl sp_min_handle_fiq
23 .macro route_fiq_to_sp_min reg
24 /* -----------------------------------------------------
25 * FIQs are secure interrupts trapped by Monitor and non
26 * secure is not allowed to mask the FIQs.
27 * -----------------------------------------------------
30 orr \reg, \reg, #SCR_FIQ_BIT
31 bic \reg, \reg, #SCR_FW_BIT
35 .macro clrex_on_monitor_entry
36 #if (ARM_ARCH_MAJOR == 7)
38 * ARMv7 architectures need to clear the exclusive access when
39 * entering Monitor mode.
45 vector_base sp_min_vector_table
47 b plat_panic_handler /* Undef */
48 b sp_min_handle_smc /* Syscall */
49 b plat_panic_handler /* Prefetch abort */
50 b plat_panic_handler /* Data abort */
51 b plat_panic_handler /* Reserved */
52 b plat_panic_handler /* IRQ */
53 b sp_min_handle_fiq /* FIQ */
57 * The Cold boot/Reset entrypoint for SP_MIN
59 func sp_min_entrypoint
61 /* ---------------------------------------------------------------
62 * Preceding bootloader has populated r0 with a pointer to a
63 * 'bl_params_t' structure & r1 with a pointer to platform
65 * ---------------------------------------------------------------
72 /* ---------------------------------------------------------------------
73 * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
74 * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
75 * and primary/secondary CPU logic should not be executed in this case.
77 * Also, assume that the previous bootloader has already initialised the
78 * SCTLR, including the CPU endianness, and has initialised the memory.
79 * ---------------------------------------------------------------------
81 el3_entrypoint_common \
83 _warm_boot_mailbox=0 \
84 _secondary_cold_boot=0 \
87 _exception_vectors=sp_min_vector_table
89 /* ---------------------------------------------------------------------
90 * Relay the previous bootloader's arguments to the platform layer
91 * ---------------------------------------------------------------------
94 /* ---------------------------------------------------------------------
95 * For RESET_TO_SP_MIN systems which have a programmable reset address,
96 * sp_min_entrypoint() is executed only on the cold boot path so we can
97 * skip the warm boot mailbox mechanism.
98 * ---------------------------------------------------------------------
100 el3_entrypoint_common \
102 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
103 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
106 _exception_vectors=sp_min_vector_table
108 /* ---------------------------------------------------------------------
109 * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
110 * to run so there's no argument to relay from a previous bootloader.
111 * Zero the arguments passed to the platform layer to reflect that.
112 * ---------------------------------------------------------------------
119 #endif /* RESET_TO_SP_MIN */
121 #if SP_MIN_WITH_SECURE_FIQ
122 route_fiq_to_sp_min r4
129 bl sp_min_early_platform_setup2
130 bl sp_min_plat_arch_setup
132 /* Jump to the main function */
135 /* -------------------------------------------------------------
136 * Clean the .data & .bss sections to main memory. This ensures
137 * that any global data which was initialised by the primary CPU
138 * is visible to secondary CPUs before they enable their data
139 * caches and participate in coherency.
140 * -------------------------------------------------------------
142 ldr r0, =__DATA_START__
143 ldr r1, =__DATA_END__
145 bl clean_dcache_range
147 ldr r0, =__BSS_START__
150 bl clean_dcache_range
154 /* r0 points to `smc_ctx_t` */
155 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
157 endfunc sp_min_entrypoint
161 * SMC handling function for SP_MIN.
163 func sp_min_handle_smc
164 /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
165 str lr, [sp, #SMC_CTX_LR_MON]
167 smccc_save_gp_mode_regs
169 clrex_on_monitor_entry
172 * `sp` still points to `smc_ctx_t`. Save it to a register
173 * and restore the C runtime stack pointer to `sp`.
175 mov r2, sp /* handle */
176 ldr sp, [r2, #SMC_CTX_SP_MON]
178 ldr r0, [r2, #SMC_CTX_SCR]
179 and r3, r0, #SCR_NS_BIT /* flags */
181 /* Switch to Secure Mode*/
187 * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode.
188 * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset
189 * and so set to 1 as ARM has deprecated use of PMCR.LC=0.
192 orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT)
195 ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */
196 /* Check whether an SMC64 is issued */
197 tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
199 /* SMC32 is not detected. Return error back to caller */
201 str r0, [r2, #SMC_CTX_GPREG_R0]
205 /* SMC32 is detected */
206 mov r1, #0 /* cookie */
207 bl handle_runtime_svc
209 /* `r0` points to `smc_ctx_t` */
211 endfunc sp_min_handle_smc
214 * Secure Interrupts handling function for SP_MIN.
216 func sp_min_handle_fiq
217 #if !SP_MIN_WITH_SECURE_FIQ
220 /* FIQ has a +4 offset for lr compared to preferred return address */
222 /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
223 str lr, [sp, #SMC_CTX_LR_MON]
225 smccc_save_gp_mode_regs
227 clrex_on_monitor_entry
229 /* load run-time stack */
231 ldr sp, [r2, #SMC_CTX_SP_MON]
233 /* Switch to Secure Mode */
234 ldr r0, [r2, #SMC_CTX_SCR]
240 * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode.
241 * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset
242 * and so set to 1 as ARM has deprecated use of PMCR.LC=0.
245 orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT)
254 endfunc sp_min_handle_fiq
257 * The Warm boot entrypoint for SP_MIN.
259 func sp_min_warm_entrypoint
261 * On the warm boot path, most of the EL3 initialisations performed by
262 * 'el3_entrypoint_common' must be skipped:
264 * - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by
265 * programming the reset address do we need to initialied the SCTLR.
266 * In other cases, we assume this has been taken care by the
269 * - No need to determine the type of boot, we know it is a warm boot.
271 * - Do not try to distinguish between primary and secondary CPUs, this
272 * notion only exists for a cold boot.
274 * - No need to initialise the memory or the C runtime environment,
275 * it has been done once and for all on the cold boot path.
277 el3_entrypoint_common \
278 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
279 _warm_boot_mailbox=0 \
280 _secondary_cold_boot=0 \
283 _exception_vectors=sp_min_vector_table
286 * We're about to enable MMU and participate in PSCI state coordination.
288 * The PSCI implementation invokes platform routines that enable CPUs to
289 * participate in coherency. On a system where CPUs are not
290 * cache-coherent without appropriate platform specific programming,
291 * having caches enabled until such time might lead to coherency issues
292 * (resulting from stale data getting speculatively fetched, among
293 * others). Therefore we keep data caches disabled even after enabling
294 * the MMU for such platforms.
296 * On systems with hardware-assisted coherency, or on single cluster
297 * platforms, such platform specific programming is not required to
298 * enter coherency (as CPUs already are); and there's no reason to have
299 * caches disabled either.
301 #if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
304 mov r0, #DISABLE_DCACHE
306 bl bl32_plat_enable_mmu
308 #if SP_MIN_WITH_SECURE_FIQ
309 route_fiq_to_sp_min r0
314 /* r0 points to `smc_ctx_t` */
315 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
317 endfunc sp_min_warm_entrypoint
320 * The function to restore the registers from SMC context and return
321 * to the mode restored to SPSR.
323 * Arguments : r0 must point to the SMC context to restore from.