target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9131-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         model = "iEi Puzzle-M901";
  14         compatible = "iei,puzzle-m901",
  15                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  16
  17         chosen {
  18                 stdout-path = "serial0:115200n8";
  19         };
  20
  21         aliases {
  22                 i2c0 = &cp1_i2c0;
  23                 i2c1 = &cp0_i2c0;
  24                 ethernet0 = &cp0_eth0;
  25                 ethernet1 = &cp0_eth1;
  26                 ethernet2 = &cp0_eth2;
  27                 ethernet3 = &cp1_eth0;
  28                 ethernet4 = &cp1_eth1;
  29                 ethernet5 = &cp1_eth2;
  30                 gpio1 = &cp0_gpio1;
  31                 gpio2 = &cp0_gpio2;
  32                 gpio3 = &cp1_gpio1;
  33                 gpio4 = &cp1_gpio2;
  34         };
  35
  36         memory@00000000 {
  37                 device_type = "memory";
  38                 reg = <0x0 0x0 0x0 0x80000000>;
  39         };
  40 };
  41
  42 &uart0 {
  43         status = "okay";
  44 };
  45
  46 &cp0_uart0 {
  47         status = "okay";
  48 };
  49
  50 /* on-board eMMC - U9 */
  51 &ap_sdhci0 {
  52         pinctrl-names = "default";
  53         bus-width = <8>;
  54         status = "okay";
  55         mmc-ddr-1_8v;
  56         mmc-hs400-1_8v;
  57 };
  58
  59 &cp0_crypto {
  60         status = "okay";
  61 };
  62
  63 &cp0_xmdio {
  64         status = "okay";
  65         cp0_nbaset_phy0: ethernet-phy@0 {
  66                 compatible = "ethernet-phy-ieee802.3-c45";
  67                 reg = <2>;
  68         };
  69         cp0_nbaset_phy1: ethernet-phy@1 {
  70                 compatible = "ethernet-phy-ieee802.3-c45";
  71                 reg = <0>;
  72         };
  73         cp0_nbaset_phy2: ethernet-phy@2 {
  74                 compatible = "ethernet-phy-ieee802.3-c45";
  75                 reg = <8>;
  76         };
  77 };
  78
  79 &cp0_ethernet {
  80         status = "okay";
  81 };
  82
  83 /* SLM-1521-V2, CON9 */
  84 &cp0_eth0 {
  85         status = "okay";
  86         phy-mode = "2500base-x";
  87         phys = <&cp0_comphy2 0>;
  88         managed = "in-band-status";
  89 };
  90
  91 &cp0_eth1 {
  92         status = "okay";
  93         phy-mode = "2500base-x";
  94         phys = <&cp0_comphy4 1>;
  95         managed = "in-band-status";
  96 };
  97
  98 &cp0_eth2 {
  99         status = "okay";
 100         phy-mode = "2500base-x";
 101         phys = <&cp0_comphy5 2>;
 102         managed = "in-band-status";
 103 };
 104
 105 &cp0_gpio1 {
 106         status = "okay";
 107 };
 108
 109 &cp0_gpio2 {
 110         status = "okay";
 111 };
 112
 113 &cp0_i2c0 {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&cp0_i2c0_pins>;
 116         status = "okay";
 117         clock-frequency = <100000>;
 118         rtc@32 {
 119                 compatible = "epson,rx8130";
 120                 reg = <0x32>;
 121                 wakeup-source;
 122         };
 123 };
 124
 125 /* SLM-1521-V2, CON6 */
 126 &cp0_pcie0 {
 127         status = "okay";
 128         num-lanes = <2>;
 129         num-viewport = <8>;
 130         phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
 131 };
 132
 133 /* U55 */
 134 &cp0_spi1 {
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&cp0_spi0_pins>;
 137         reg = <0x700680 0x50>,          /* control */
 138               <0x2000000 0x1000000>;    /* CS0 */
 139         status = "okay";
 140         spi-flash@0 {
 141                 #address-cells = <0x1>;
 142                 #size-cells = <0x1>;
 143                 compatible = "jedec,spi-nor";
 144                 reg = <0x0>;
 145                 spi-max-frequency = <40000000>;
 146                 partitions {
 147                         compatible = "fixed-partitions";
 148                         #address-cells = <1>;
 149                         #size-cells = <1>;
 150                         partition@0 {
 151                                 label = "U-Boot";
 152                                 reg = <0x0 0x1f0000>;
 153                         };
 154                         partition@1f0000 {
 155                                 label = "U-Boot ENV Factory";
 156                                 reg = <0x1f0000 0x10000>;
 157                         };
 158                         partition@200000 {
 159                                 label = "Reserved";
 160                                 reg = <0x200000 0x1f0000>;
 161                         };
 162                         partition@3f0000 {
 163                                 label = "U-Boot ENV";
 164                                 reg = <0x3f0000 0x10000>;
 165                         };
 166                 };
 167         };
 168 };
 169
 170 &cp0_syscon0 {
 171         cp0_pinctrl: pinctrl {
 172                 compatible = "marvell,cp115-standalone-pinctrl";
 173                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 174                         marvell,pins = "mpp37", "mpp38";
 175                         marvell,function = "i2c0";
 176                 };
 177                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 178                         marvell,pins = "mpp35", "mpp36";
 179                         marvell,function = "i2c1";
 180                 };
 181                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 182                         marvell,pins = "mpp0", "mpp1", "mpp2",
 183                                        "mpp3", "mpp4", "mpp5",
 184                                        "mpp6", "mpp7", "mpp8",
 185                                        "mpp9", "mpp10", "mpp11";
 186                         marvell,function = "ge0";
 187                 };
 188                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 189                         marvell,pins = "mpp44", "mpp45", "mpp46",
 190                                        "mpp47", "mpp48", "mpp49",
 191                                        "mpp50", "mpp51", "mpp52",
 192                                        "mpp53", "mpp54", "mpp55";
 193                         marvell,function = "ge1";
 194                 };
 195                 cp0_spi0_pins: cp0-spi-pins-0 {
 196                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 197                         marvell,function = "spi1";
 198                 };
 199         };
 200 };
 201
 202 /*
 203  * Instantiate the first connected CP115
 204  */
 205
 206 #define CP11X_NAME              cp1
 207 #define CP11X_BASE              f6000000
 208 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
 209 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 210 #define CP11X_PCIE0_BASE        f6600000
 211 #define CP11X_PCIE1_BASE        f6620000
 212 #define CP11X_PCIE2_BASE        f6640000
 213
 214 #include "armada-cp115.dtsi"
 215
 216 #undef CP11X_NAME
 217 #undef CP11X_BASE
 218 #undef CP11X_PCIEx_MEM_BASE
 219 #undef CP11X_PCIEx_MEM_SIZE
 220 #undef CP11X_PCIE0_BASE
 221 #undef CP11X_PCIE1_BASE
 222 #undef CP11X_PCIE2_BASE
 223
 224 &cp1_crypto {
 225         status = "okay";
 226 };
 227
 228 &cp1_xmdio {
 229         status = "okay";
 230         cp1_nbaset_phy0: ethernet-phy@3 {
 231                 compatible = "ethernet-phy-ieee802.3-c45";
 232                 reg = <2>;
 233         };
 234         cp1_nbaset_phy1: ethernet-phy@4 {
 235                 compatible = "ethernet-phy-ieee802.3-c45";
 236                 reg = <0>;
 237         };
 238         cp1_nbaset_phy2: ethernet-phy@5 {
 239                 compatible = "ethernet-phy-ieee802.3-c45";
 240                 reg = <8>;
 241         };
 242 };
 243
 244 &cp1_ethernet {
 245         status = "okay";
 246 };
 247
 248 /* CON50 */
 249 &cp1_eth0 {
 250         status = "okay";
 251         phy-mode = "2500base-x";
 252         phys = <&cp1_comphy2 0>;
 253         managed = "in-band-status";
 254 };
 255
 256 &cp1_eth1 {
 257         status = "okay";
 258         phy-mode = "2500base-x";
 259         phys = <&cp1_comphy4 1>;
 260         managed = "in-band-status";
 261 };
 262
 263 &cp1_eth2 {
 264         status = "okay";
 265         phy-mode = "2500base-x";
 266         phys = <&cp1_comphy5 2>;
 267         managed = "in-band-status";
 268 };
 269
 270 &cp1_sata0 {
 271         status = "okay";
 272         sata-port@1 {
 273                 status = "okay";
 274                 phys = <&cp1_comphy0 1>;
 275         };
 276 };
 277
 278 &cp1_gpio1 {
 279         status = "okay";
 280 };
 281
 282 &cp1_gpio2 {
 283         status = "okay";
 284 };
 285
 286 &cp1_i2c0 {
 287         status = "okay";
 288         pinctrl-names = "default";
 289         pinctrl-0 = <&cp1_i2c0_pins>;
 290         clock-frequency = <100000>;
 291 };
 292
 293 &cp1_syscon0 {
 294         cp1_pinctrl: pinctrl {
 295                 compatible = "marvell,cp115-standalone-pinctrl";
 296                 cp1_i2c0_pins: cp1-i2c-pins-0 {
 297                         marvell,pins = "mpp37", "mpp38";
 298                         marvell,function = "i2c0";
 299                 };
 300                 cp1_spi0_pins: cp1-spi-pins-0 {
 301                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 302                         marvell,function = "spi1";
 303                 };
 304                 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
 305                         marvell,pins = "mpp3";
 306                         marvell,function = "gpio";
 307                 };
 308                 cp1_sfp_pins: sfp-pins {
 309                         marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
 310                         marvell,function = "gpio";
 311                 };
 312         };
 313 };
 314
 315 &cp1_usb3_1 {
 316         status = "okay";
 317         phys = <&cp1_comphy3 1>;
 318         phy-names = "usb";
 319 };