target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2020 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  * Author: Jianhui Zhao <zhaojh329@gmail.com>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/phy/phy.h>
  11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
  12 #include <dt-bindings/reset/mt7986-resets.h>
  13 #include <dt-bindings/pinctrl/mt65xx.h>
  14 #include <dt-bindings/input/linux-event-codes.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/mux/mux.h>
  17
  18 / {
  19         compatible = "mediatek,mt7981";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53";
  31                         enable-method = "psci";
  32                         reg = <0x0>;
  33                 };
  34
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53";
  38                         enable-method = "psci";
  39                         reg = <0x1>;
  40                 };
  41         };
  42
  43         pwm: pwm@10048000 {
  44                 compatible = "mediatek,mt7981-pwm";
  45                 reg = <0 0x10048000 0 0x1000>;
  46                 #pwm-cells = <2>;
  47                 clocks = <&infracfg CLK_INFRA_PWM_STA>,
  48                          <&infracfg CLK_INFRA_PWM_HCK>,
  49                          <&infracfg CLK_INFRA_PWM1_CK>,
  50                          <&infracfg CLK_INFRA_PWM2_CK>,
  51                          <&infracfg CLK_INFRA_PWM3_CK>;
  52                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
  53         };
  54
  55         fan: pwm-fan {
  56                 compatible = "pwm-fan";
  57                 /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */
  58                 cooling-levels = <0 128 192 255>;
  59                 #cooling-cells = <2>;
  60                 status = "disabled";
  61         };
  62
  63         thermal-zones {
  64                 cpu_thermal: cpu-thermal {
  65                         polling-delay-passive = <1000>;
  66                         polling-delay = <1000>;
  67                         thermal-sensors = <&thermal 0>;
  68                         trips {
  69                                 cpu_trip_crit: crit {
  70                                         temperature = <125000>;
  71                                         hysteresis = <2000>;
  72                                         type = "critical";
  73                                 };
  74
  75                                 cpu_trip_hot: hot {
  76                                         temperature = <120000>;
  77                                         hysteresis = <2000>;
  78                                         type = "hot";
  79                                 };
  80
  81                                 cpu_trip_active_high: active-high {
  82                                         temperature = <115000>;
  83                                         hysteresis = <2000>;
  84                                         type = "active";
  85                                 };
  86
  87                                 cpu_trip_active_med: active-med {
  88                                         temperature = <85000>;
  89                                         hysteresis = <2000>;
  90                                         type = "active";
  91                                 };
  92
  93                                 cpu_trip_active_low: active-low {
  94                                         temperature = <60000>;
  95                                         hysteresis = <2000>;
  96                                         type = "active";
  97                                 };
  98                         };
  99
 100                         cooling-maps {
 101                                 cpu-active-high {
 102                                         /* active: set fan to cooling level 3 */
 103                                         cooling-device = <&fan 3 3>;
 104                                         trip = <&cpu_trip_active_high>;
 105                                 };
 106
 107                                 cpu-active-med {
 108                                         /* active: set fan to cooling level 2 */
 109                                         cooling-device = <&fan 2 2>;
 110                                         trip = <&cpu_trip_active_med>;
 111                                 };
 112
 113                                 cpu-active-low {
 114                                         /* passive: set fan to cooling level 1 */
 115                                         cooling-device = <&fan 1 1>;
 116                                         trip = <&cpu_trip_active_low>;
 117                                 };
 118                         };
 119                 };
 120         };
 121
 122         thermal: thermal@1100c800 {
 123                 #thermal-sensor-cells = <1>;
 124                 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
 125                 reg = <0 0x1100c800 0 0x800>;
 126                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 127                 clocks = <&infracfg CLK_INFRA_THERM_CK>,
 128                          <&infracfg CLK_INFRA_ADC_26M_CK>;
 129                 clock-names = "therm", "auxadc";
 130                 mediatek,auxadc = <&auxadc>;
 131                 mediatek,apmixedsys = <&apmixedsys>;
 132                 nvmem-cells = <&thermal_calibration>;
 133                 nvmem-cell-names = "calibration-data";
 134         };
 135
 136         auxadc: adc@1100d000 {
 137                 compatible = "mediatek,mt7981-auxadc",
 138                              "mediatek,mt7986-auxadc",
 139                              "mediatek,mt7622-auxadc";
 140                 reg = <0 0x1100d000 0 0x1000>;
 141                 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
 142                          <&infracfg CLK_INFRA_ADC_FRC_CK>;
 143                 clock-names = "main", "32k";
 144                 #io-channel-cells = <1>;
 145         };
 146
 147         wdma: wdma@15104800 {
 148                 compatible = "mediatek,wed-wdma";
 149                 reg = <0 0x15104800 0 0x400>,
 150                       <0 0x15104c00 0 0x400>;
 151         };
 152
 153         ap2woccif: ap2woccif@151a5000 {
 154                 compatible = "mediatek,ap2woccif";
 155                 reg = <0 0x151a5000 0 0x1000>,
 156                       <0 0x151ad000 0 0x1000>;
 157                 interrupt-parent = <&gic>;
 158                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 160         };
 161
 162         reserved-memory {
 163                 #address-cells = <2>;
 164                 #size-cells = <2>;
 165                 ranges;
 166
 167                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 168                 secmon_reserved: secmon@43000000 {
 169                         reg = <0 0x43000000 0 0x30000>;
 170                         no-map;
 171                 };
 172
 173                 wmcpu_emi: wmcpu-reserved@47c80000 {
 174                         reg = <0 0x47c80000 0 0x100000>;
 175                         no-map;
 176                 };
 177
 178                 wo_emi0: wo-emi@47d80000 {
 179                         reg = <0 0x47d80000 0 0x40000>;
 180                         no-map;
 181                 };
 182
 183                 wo_data: wo-data@47dc0000 {
 184                         reg = <0 0x47dc0000 0 0x240000>;
 185                         no-map;
 186                 };
 187
 188                 wo_ilm0: wo-ilm@151e0000 {
 189                         reg = <0 0x151e0000 0 0x8000>;
 190                         no-map;
 191                 };
 192
 193                 wo_dlm0: wo-dlm@151e8000 {
 194                         reg = <0 0x151e8000 0 0x2000>;
 195                         no-map;
 196                 };
 197
 198                 wo_boot: wo-boot@15194000 {
 199                         reg = <0 0x15194000 0 0x1000>;
 200                         no-map;
 201                 };
 202         };
 203
 204         psci {
 205                 compatible  = "arm,psci-0.2";
 206                 method      = "smc";
 207         };
 208
 209         trng {
 210                 compatible = "mediatek,mt7981-rng";
 211         };
 212
 213         clk40m: oscillator@0 {
 214                 compatible = "fixed-clock";
 215                 #clock-cells = <0>;
 216                 clock-frequency = <40000000>;
 217                 clock-output-names = "clkxtal";
 218         };
 219
 220         infracfg: infracfg@10001000 {
 221                 compatible = "mediatek,mt7981-infracfg", "syscon";
 222                 reg = <0 0x10001000 0 0x1000>;
 223                 #clock-cells = <1>;
 224         };
 225
 226         topckgen: topckgen@1001B000 {
 227                 compatible = "mediatek,mt7981-topckgen", "syscon";
 228                 reg = <0 0x1001B000 0 0x1000>;
 229                 #clock-cells = <1>;
 230         };
 231
 232         apmixedsys: apmixedsys@1001E000 {
 233                 compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
 234                 reg = <0 0x1001E000 0 0x1000>;
 235                 #clock-cells = <1>;
 236         };
 237
 238         timer {
 239                 compatible = "arm,armv8-timer";
 240                 interrupt-parent = <&gic>;
 241                 clock-frequency = <13000000>;
 242                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 243                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 244                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 245                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 246
 247         };
 248
 249         watchdog: watchdog@1001c000 {
 250                 compatible = "mediatek,mt7986-wdt",
 251                              "mediatek,mt6589-wdt";
 252                 reg = <0 0x1001c000 0 0x1000>;
 253                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 254                 #reset-cells = <1>;
 255                 status = "disabled";
 256         };
 257
 258         gic: interrupt-controller@c000000 {
 259                 compatible = "arm,gic-v3";
 260                 #interrupt-cells = <3>;
 261                 interrupt-parent = <&gic>;
 262                 interrupt-controller;
 263                 reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 264                       <0 0x0c080000 0 0x200000>; /* GICR */
 265
 266                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 267         };
 268
 269         uart0: serial@11002000 {
 270                 compatible = "mediatek,mt6577-uart";
 271                 reg = <0 0x11002000 0 0x400>;
 272                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
 274                         <&infracfg CLK_INFRA_UART0_CK>;
 275                 clock-names = "baud", "bus";
 276                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 277                                   <&infracfg CLK_INFRA_UART0_SEL>;
 278                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 279                                          <&topckgen CLK_TOP_UART_SEL>;
 280                 pinctrl-0 = <&uart0_pins>;
 281                 pinctrl-names = "default";
 282                 status = "disabled";
 283         };
 284
 285         uart1: serial@11003000 {
 286                 compatible = "mediatek,mt6577-uart";
 287                 reg = <0 0x11003000 0 0x400>;
 288                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 289                 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
 290                         <&infracfg CLK_INFRA_UART1_CK>;
 291                 clock-names = "baud", "bus";
 292                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 293                                   <&infracfg CLK_INFRA_UART1_SEL>;
 294                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 295                                          <&topckgen CLK_TOP_UART_SEL>;
 296                 status = "disabled";
 297         };
 298
 299         uart2: serial@11004000 {
 300                 compatible = "mediatek,mt6577-uart";
 301                 reg = <0 0x11004000 0 0x400>;
 302                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
 304                         <&infracfg CLK_INFRA_UART2_CK>;
 305                 clock-names = "baud", "bus";
 306                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 307                                   <&infracfg CLK_INFRA_UART2_SEL>;
 308                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 309                                          <&topckgen CLK_TOP_UART_SEL>;
 310                 status = "disabled";
 311         };
 312
 313         i2c0: i2c@11007000 {
 314                 compatible = "mediatek,mt7981-i2c";
 315                 reg = <0 0x11007000 0 0x1000>,
 316                       <0 0x10217080 0 0x80>;
 317                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 318                 clock-div = <1>;
 319                 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
 320                          <&infracfg CLK_INFRA_AP_DMA_CK>;
 321                 clock-names = "main", "dma";
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 status = "disabled";
 325         };
 326
 327         pcie: pcie@11280000 {
 328                 compatible = "mediatek,mt7981-pcie",
 329                              "mediatek,mt7986-pcie";
 330                 device_type = "pci";
 331                 reg = <0 0x11280000 0 0x4000>;
 332                 reg-names = "pcie-mac";
 333                 #address-cells = <3>;
 334                 #size-cells = <2>;
 335                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 336                 bus-range = <0x00 0xff>;
 337                 ranges = <0x82000000 0 0x20000000
 338                           0x0 0x20000000 0 0x10000000>;
 339                 status = "disabled";
 340
 341                 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
 342                          <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
 343                          <&infracfg CLK_INFRA_IPCIER_CK>,
 344                          <&infracfg CLK_INFRA_IPCIEB_CK>;
 345
 346                 phys = <&u3port0 PHY_TYPE_PCIE>;
 347                 phy-names = "pcie-phy";
 348
 349                 #interrupt-cells = <1>;
 350                 interrupt-map-mask = <0 0 0 7>;
 351                 interrupt-map = <0 0 0 1 &pcie_intc 0>,
 352                                 <0 0 0 2 &pcie_intc 1>,
 353                                 <0 0 0 3 &pcie_intc 2>,
 354                                 <0 0 0 4 &pcie_intc 3>;
 355                 pcie_intc: interrupt-controller {
 356                         interrupt-controller;
 357                         #address-cells = <0>;
 358                         #interrupt-cells = <1>;
 359                 };
 360         };
 361
 362         crypto: crypto@10320000 {
 363                 compatible = "inside-secure,safexcel-eip97";
 364                 reg = <0 0x10320000 0 0x40000>;
 365                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 366                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 367                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 368                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 369                 interrupt-names = "ring0", "ring1", "ring2", "ring3";
 370                 clocks = <&topckgen CLK_TOP_EIP97B>;
 371                 clock-names = "top_eip97_ck";
 372                 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
 373                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
 374         };
 375
 376         pio: pinctrl@11d00000 {
 377                 compatible = "mediatek,mt7981-pinctrl";
 378                 reg = <0 0x11d00000 0 0x1000>,
 379                       <0 0x11c00000 0 0x1000>,
 380                       <0 0x11c10000 0 0x1000>,
 381                       <0 0x11d20000 0 0x1000>,
 382                       <0 0x11e00000 0 0x1000>,
 383                       <0 0x11e20000 0 0x1000>,
 384                       <0 0x11f00000 0 0x1000>,
 385                       <0 0x11f10000 0 0x1000>,
 386                       <0 0x1000b000 0 0x1000>;
 387                 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
 388                             "iocfg_rb", "iocfg_lb", "iocfg_bl",
 389                             "iocfg_tm", "iocfg_tl", "eint";
 390                 gpio-controller;
 391                 #gpio-cells = <2>;
 392                 gpio-ranges = <&pio 0 0 56>;
 393                 interrupt-controller;
 394                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 395                 interrupt-parent = <&gic>;
 396                 #interrupt-cells = <2>;
 397
 398                 mdio_pins: mdc-mdio-pins {
 399                         mux {
 400                                 function = "eth";
 401                                 groups = "smi_mdc_mdio";
 402                         };
 403                 };
 404
 405                 uart0_pins: uart0-pins {
 406                         mux {
 407                                 function = "uart";
 408                                 groups = "uart0";
 409                         };
 410                 };
 411
 412                 wifi_dbdc_pins: wifi-dbdc-pins {
 413                         mux {
 414                                 function = "eth";
 415                                 groups = "wf0_mode1";
 416                         };
 417                         conf {
 418                                 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
 419                                        "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
 420                                        "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
 421                                        "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
 422                                        "WF_CBA_RESETB", "WF_DIG_RESETB";
 423                                 drive-strength = <4>;
 424                         };
 425                 };
 426         };
 427
 428         ethsys: syscon@15000000 {
 429                 #address-cells = <1>;
 430                 #size-cells = <1>;
 431                 compatible = "mediatek,mt7981-ethsys",
 432                              "mediatek,mt7986-ethsys",
 433                              "syscon";
 434                 reg = <0 0x15000000 0 0x1000>;
 435                 #clock-cells = <1>;
 436                 #reset-cells = <1>;
 437         };
 438
 439         wed: wed@15010000 {
 440                 compatible = "mediatek,mt7981-wed",
 441                              "mediatek,mt7986-wed",
 442                              "syscon";
 443                 reg = <0 0x15010000 0 0x1000>;
 444                 interrupt-parent = <&gic>;
 445                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 446                 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
 447                                 <&wo_data>, <&wo_boot>;
 448                 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
 449                                       "wo-data", "wo-boot";
 450                 mediatek,wo-ccif = <&wo_ccif0>;
 451         };
 452
 453         eth: ethernet@15100000 {
 454                 compatible = "mediatek,mt7981-eth";
 455                 reg = <0 0x15100000 0 0x80000>;
 456                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 457                                 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 458                                 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 459                                 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 460                 clocks = <&ethsys CLK_ETH_FE_EN>,
 461                         <&ethsys CLK_ETH_GP2_EN>,
 462                         <&ethsys CLK_ETH_GP1_EN>,
 463                         <&ethsys CLK_ETH_WOCPU0_EN>,
 464                         <&sgmiisys0 CLK_SGM0_TX_EN>,
 465                         <&sgmiisys0 CLK_SGM0_RX_EN>,
 466                         <&sgmiisys0 CLK_SGM0_CK0_EN>,
 467                         <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
 468                         <&sgmiisys1 CLK_SGM1_TX_EN>,
 469                         <&sgmiisys1 CLK_SGM1_RX_EN>,
 470                         <&sgmiisys1 CLK_SGM1_CK1_EN>,
 471                         <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
 472                         <&topckgen CLK_TOP_SGM_REG>,
 473                         <&topckgen CLK_TOP_NETSYS_SEL>,
 474                         <&topckgen CLK_TOP_NETSYS_500M_SEL>;
 475                 clock-names = "fe", "gp2", "gp1", "wocpu0",
 476                                         "sgmii_tx250m", "sgmii_rx250m",
 477                                         "sgmii_cdr_ref", "sgmii_cdr_fb",
 478                                         "sgmii2_tx250m", "sgmii2_rx250m",
 479                                         "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 480                                         "sgmii_ck", "netsys0", "netsys1";
 481                 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
 482                                   <&topckgen CLK_TOP_SGM_325M_SEL>;
 483                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
 484                                          <&topckgen CLK_TOP_CB_SGM_325M>;
 485                 mediatek,ethsys = <&ethsys>;
 486                 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
 487                 mediatek,infracfg = <&topmisc>;
 488                 mediatek,wed = <&wed>;
 489                 #reset-cells = <1>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 status = "disabled";
 493
 494                 mdio_bus: mdio-bus {
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497
 498                         int_gbe_phy: ethernet-phy@0 {
 499                                 reg = <0>;
 500                                 compatible = "ethernet-phy-ieee802.3-c22";
 501                                 phy-mode = "gmii";
 502                                 phy-is-integrated;
 503                                 nvmem-cells = <&phy_calibration>;
 504                                 nvmem-cell-names = "phy-cal-data";
 505                         };
 506                 };
 507         };
 508
 509         wo_ccif0: syscon@151a5000 {
 510                 compatible = "mediatek,mt7986-wo-ccif", "syscon";
 511                 reg = <0 0x151a5000 0 0x1000>;
 512                 interrupt-parent = <&gic>;
 513                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 514         };
 515
 516         sgmiisys0: syscon@10060000 {
 517                 compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
 518                 reg = <0 0x10060000 0 0x1000>;
 519                 mediatek,pnswap;
 520                 #clock-cells = <1>;
 521         };
 522
 523         sgmiisys1: syscon@10070000 {
 524                 compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
 525                 reg = <0 0x10070000 0 0x1000>;
 526                 #clock-cells = <1>;
 527         };
 528
 529         topmisc: topmisc@11d10000 {
 530                 compatible = "mediatek,mt7981-topmisc", "syscon";
 531                 reg = <0 0x11d10000 0 0x10000>;
 532                 #clock-cells = <1>;
 533         };
 534
 535         snand: snfi@11005000 {
 536                 compatible = "mediatek,mt7986-snand";
 537                 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
 538                 reg-names = "nfi", "ecc";
 539                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 540                 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
 541                          <&infracfg CLK_INFRA_NFI1_CK>,
 542                          <&infracfg CLK_INFRA_NFI_HCK_CK>;
 543                 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 544                 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
 545                                   <&topckgen CLK_TOP_NFI1X_SEL>;
 546                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
 547                                          <&topckgen CLK_TOP_CB_M_D8>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         mmc0: mmc@11230000 {
 554                 compatible = "mediatek,mt7986-mmc",
 555                                         "mediatek,mt7981-mmc";
 556                 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
 557                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 558                 clocks = <&topckgen CLK_TOP_EMMC_208M>,
 559                                 <&topckgen CLK_TOP_EMMC_400M>,
 560                                 <&infracfg CLK_INFRA_MSDC_CK>;
 561                 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
 562                                   <&topckgen CLK_TOP_EMMC_400M_SEL>;
 563                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
 564                                          <&topckgen CLK_TOP_CB_NET2_D2>;
 565                 clock-names = "source", "hclk", "source_cg";
 566                 status = "disabled";
 567         };
 568
 569         wed_pcie: wed_pcie@10003000 {
 570                 compatible = "mediatek,wed_pcie";
 571                 reg = <0 0x10003000 0 0x10>;
 572         };
 573
 574         spi0: spi@1100a000 {
 575                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 reg = <0 0x1100a000 0 0x100>;
 579                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 580                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 581                          <&topckgen CLK_TOP_SPI_SEL>,
 582                          <&infracfg CLK_INFRA_SPI0_CK>,
 583                          <&infracfg CLK_INFRA_SPI0_HCK_CK>;
 584
 585                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 586                 status = "disabled";
 587         };
 588
 589         spi1: spi@1100b000 {
 590                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 reg = <0 0x1100b000 0 0x100>;
 594                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 595                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 596                          <&topckgen CLK_TOP_SPIM_MST_SEL>,
 597                          <&infracfg CLK_INFRA_SPI1_CK>,
 598                          <&infracfg CLK_INFRA_SPI1_HCK_CK>;
 599                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 600                 status = "disabled";
 601         };
 602
 603         spi2: spi@11009000 {
 604                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 605                 #address-cells = <1>;
 606                 #size-cells = <0>;
 607                 reg = <0 0x11009000 0 0x100>;
 608                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 609                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 610                          <&topckgen CLK_TOP_SPI_SEL>,
 611                          <&infracfg CLK_INFRA_SPI2_CK>,
 612                          <&infracfg CLK_INFRA_SPI2_HCK_CK>;
 613                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 614                 status = "disabled";
 615         };
 616
 617         consys: consys@10000000 {
 618                 compatible = "mediatek,mt7981-consys";
 619                 reg = <0 0x10000000 0 0x8600000>;
 620                 memory-region = <&wmcpu_emi>;
 621         };
 622
 623         xhci: usb@11200000 {
 624                 compatible = "mediatek,mt7986-xhci",
 625                              "mediatek,mtk-xhci";
 626                 reg = <0 0x11200000 0 0x2e00>,
 627                       <0 0x11203e00 0 0x0100>;
 628                 reg-names = "mac", "ippc";
 629                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
 631                          <&infracfg CLK_INFRA_IUSB_CK>,
 632                          <&infracfg CLK_INFRA_IUSB_133_CK>,
 633                          <&infracfg CLK_INFRA_IUSB_66M_CK>,
 634                          <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
 635                 clock-names = "sys_ck",
 636                               "ref_ck",
 637                               "mcu_ck",
 638                               "dma_ck",
 639                               "xhci_ck";
 640                 phys = <&u2port0 PHY_TYPE_USB2>,
 641                        <&u3port0 PHY_TYPE_USB3>;
 642                 vusb33-supply = <&reg_3p3v>;
 643                 status = "disabled";
 644         };
 645
 646         usb_phy: usb-phy@11e10000 {
 647                 compatible = "mediatek,mt7981",
 648                              "mediatek,generic-tphy-v2";
 649                 #address-cells = <1>;
 650                 #size-cells = <1>;
 651                 ranges = <0 0 0x11e10000 0x1700>;
 652                 status = "disabled";
 653
 654                 u2port0: usb-phy@0 {
 655                         reg = <0x0 0x700>;
 656                         clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
 657                         clock-names = "ref";
 658                         #phy-cells = <1>;
 659                 };
 660
 661                 u3port0: usb-phy@700 {
 662                         reg = <0x700 0x900>;
 663                         clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
 664                         clock-names = "ref";
 665                         #phy-cells = <1>;
 666                         mediatek,syscon-type = <&topmisc 0x218 0>;
 667                         status = "okay";
 668                 };
 669         };
 670
 671         reg_3p3v: regulator-3p3v {
 672                 compatible = "regulator-fixed";
 673                 regulator-name = "fixed-3.3V";
 674                 regulator-min-microvolt = <3300000>;
 675                 regulator-max-microvolt = <3300000>;
 676                 regulator-boot-on;
 677                 regulator-always-on;
 678         };
 679
 680         efuse: efuse@11f20000 {
 681                 compatible = "mediatek,mt7981-efuse",
 682                              "mediatek,efuse";
 683                 reg = <0 0x11f20000 0 0x1000>;
 684                 #address-cells = <1>;
 685                 #size-cells = <1>;
 686                 status = "okay";
 687
 688                 thermal_calibration: thermal-calib@274 {
 689                         reg = <0x274 0xc>;
 690                 };
 691
 692                 phy_calibration: phy-calib@8dc {
 693                         reg = <0x8dc 0x10>;
 694                 };
 695
 696                 comb_rx_imp_p0: usb3-rx-imp@8c8 {
 697                         reg = <0x8c8 1>;
 698                         bits = <0 5>;
 699                 };
 700
 701                 comb_tx_imp_p0: usb3-tx-imp@8c8 {
 702                         reg = <0x8c8 2>;
 703                         bits = <5 5>;
 704                 };
 705
 706                 comb_intr_p0: usb3-intr@8c9 {
 707                         reg = <0x8c9 1>;
 708                         bits = <2 6>;
 709                 };
 710         };
 711
 712         afe: audio-controller@11210000 {
 713                 compatible = "mediatek,mt79xx-audio";
 714                 reg = <0 0x11210000 0 0x9000>;
 715                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 716                 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
 717                          <&infracfg CLK_INFRA_AUD_26M_CK>,
 718                          <&infracfg CLK_INFRA_AUD_L_CK>,
 719                          <&infracfg CLK_INFRA_AUD_AUD_CK>,
 720                          <&infracfg CLK_INFRA_AUD_EG2_CK>,
 721                          <&topckgen CLK_TOP_AUD_SEL>;
 722                 clock-names = "aud_bus_ck",
 723                               "aud_26m_ck",
 724                               "aud_l_ck",
 725                               "aud_aud_ck",
 726                               "aud_eg2_ck",
 727                               "aud_sel";
 728                 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
 729                                   <&topckgen CLK_TOP_A1SYS_SEL>,
 730                                   <&topckgen CLK_TOP_AUD_L_SEL>,
 731                                   <&topckgen CLK_TOP_A_TUNER_SEL>;
 732                 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
 733                                          <&topckgen CLK_TOP_APLL2_D4>,
 734                                          <&topckgen CLK_TOP_CB_APLL2_196M>,
 735                                          <&topckgen CLK_TOP_APLL2_D4>;
 736                 status = "disabled";
 737         };
 738
 739         ice: ice_debug {
 740                 compatible = "mediatek,mt7981-ice_debug",
 741                            "mediatek,mt2701-ice_debug";
 742                 clocks = <&infracfg CLK_INFRA_DBG_CK>;
 743                 clock-names = "ice_dbg";
 744         };
 745
 746         wifi: wifi@18000000 {
 747                 compatible = "mediatek,mt7981-wmac";
 748                 resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
 749                 reset-names = "consys";
 750                 pinctrl-0 = <&wifi_dbdc_pins>;
 751                 pinctrl-names = "dbdc";
 752                 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
 753                          <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
 754                 clock-names = "mcu", "ap2conn";
 755                 reg = <0 0x18000000 0 0x1000000>,
 756                       <0 0x10003000 0 0x1000>,
 757                       <0 0x11d10000 0 0x1000>;
 758                 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 759                              <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 760                              <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 761                              <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 762                 memory-region = <&wmcpu_emi>;
 763                 status = "disabled";
 764         };
 765 };