target/linux/mediatek/dts/mt7622-netgear-wax206.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /* Copyright (c) 2022, Marcel Ziswiler <marcel@ziswiler.com> */
   3
   4 /dts-v1/;
   5 #include "mt7622.dtsi"
   6 #include "mt6380.dtsi"
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9
  10 / {
  11         model = "Netgear WAX206";
  12         compatible = "netgear,wax206", "mediatek,mt7622";
  13
  14         aliases {
  15                 ethernet0 = &gmac0;
  16                 led-boot = &led_power_r;
  17                 led-failsafe = &led_power_r;
  18                 led-running = &led_power_g;
  19                 led-upgrade = &led_power_g;
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 reset {
  44                         gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  45                         label = "reset";
  46                         linux,code = <KEY_RESTART>;
  47                 };
  48
  49                 wps {
  50                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  51                         label = "wps";
  52                         linux,code = <KEY_WPS_BUTTON>;
  53                 };
  54         };
  55
  56         gpio-leds {
  57                 compatible = "gpio-leds";
  58
  59                 led_power_r: power_red {
  60                         default-state = "on";
  61                         gpios = <&pio 3 GPIO_ACTIVE_LOW>;
  62                         label = "power:red";
  63                 };
  64
  65                 led_power_g: power_green {
  66                         default-state = "off";
  67                         gpios = <&pio 4 GPIO_ACTIVE_LOW>;
  68                         label = "power:green";
  69                 };
  70
  71                 inet_green {
  72                         default-state = "off";
  73                         gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
  74                         label = "inet:green";
  75                 };
  76
  77                 inet_blue {
  78                         default-state = "off";
  79                         gpios = <&pio 17 GPIO_ACTIVE_LOW>;
  80                         label = "inet:blue";
  81                 };
  82
  83                 wifin_green {
  84                         default-state = "off";
  85                         gpios = <&pio 85 GPIO_ACTIVE_LOW>;
  86                         label = "wifin:green";
  87                 };
  88
  89                 wifin_blue {
  90                         default-state = "off";
  91                         gpios = <&pio 86 GPIO_ACTIVE_LOW>;
  92                         label = "wifin:blue";
  93                 };
  94
  95                 wifia_green {
  96                         default-state = "off";
  97                         gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  98                         label = "wifia:green";
  99                 };
 100
 101                 wifia_blue {
 102                         default-state = "off";
 103                         gpios = <&pio 1 GPIO_ACTIVE_LOW>;
 104                         label = "wifia:blue";
 105                 };
 106         };
 107
 108         memory {
 109                 reg = <0 0x40000000 0 0x40000000>;
 110         };
 111 };
 112
 113 &bch {
 114         status = "okay";
 115 };
 116
 117 &btif {
 118         status = "okay";
 119 };
 120
 121 &cir {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&irrx_pins>;
 124         status = "okay";
 125 };
 126
 127 &eth {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&eth_pins>;
 130         status = "okay";
 131
 132         gmac0: mac@0 {
 133                 compatible = "mediatek,eth-mac";
 134                 nvmem-cells = <&macaddr_factory_7fff4>;
 135                 nvmem-cell-names = "mac-address";
 136                 phy-mode = "2500base-x";
 137                 reg = <0>;
 138
 139                 fixed-link {
 140                         full-duplex;
 141                         pause;
 142                         speed = <2500>;
 143                 };
 144         };
 145
 146         mdio-bus {
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149
 150                 switch@0 {
 151                         compatible = "mediatek,mt7531";
 152                         #interrupt-cells = <1>;
 153                         interrupt-controller;
 154                         interrupt-parent = <&pio>;
 155                         interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 156                         reg = <0>;
 157                         reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
 158
 159                         ports {
 160                                 #address-cells = <1>;
 161                                 #size-cells = <0>;
 162
 163                                 port@1 {
 164                                         label = "lan1";
 165                                         reg = <1>;
 166                                 };
 167
 168                                 port@2 {
 169                                         label = "lan2";
 170                                         reg = <2>;
 171                                 };
 172
 173                                 port@3 {
 174                                         label = "lan3";
 175                                         reg = <3>;
 176                                 };
 177
 178                                 port@4 {
 179                                         label = "lan4";
 180                                         reg = <4>;
 181                                 };
 182
 183                                 wan: port@5 {
 184                                         label = "wan";
 185                                         nvmem-cells = <&macaddr_factory_7fffa>;
 186                                         nvmem-cell-names = "mac-address";
 187                                         phy-handle = <&rtl8221b_phy>;
 188                                         phy-mode = "sgmii";
 189                                         reg = <5>;
 190                                 };
 191
 192                                 port@6 {
 193                                         ethernet = <&gmac0>;
 194                                         label = "cpu";
 195                                         phy-mode = "2500base-x";
 196                                         reg = <6>;
 197
 198                                         fixed-link {
 199                                                 full-duplex;
 200                                                 pause;
 201                                                 speed = <2500>;
 202                                         };
 203                                 };
 204                         };
 205                 };
 206
 207                 rtl8221b_phy: ethernet-phy@7 {
 208                         compatible = "ethernet-phy-id001c.c849";
 209                         reg = <7>;
 210                         reset-gpios = <&pio 101 GPIO_ACTIVE_LOW>;
 211                         interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
 212                         reset-assert-us = <100000>;
 213                         reset-deassert-us = <100000>;
 214                 };
 215         };
 216 };
 217
 218 &pcie0 {
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pcie0_pins>;
 221         status = "okay";
 222 };
 223
 224 &pcie1 {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pcie1_pins>;
 227         status = "okay";
 228 };
 229
 230 &pio {
 231         eth_pins: eth-pins {
 232                 mux {
 233                         function = "eth";
 234                         groups = "mdc_mdio", "rgmii_via_gmac2";
 235                 };
 236         };
 237
 238         irrx_pins: irrx-pins {
 239                 mux {
 240                         function = "ir";
 241                         groups =  "ir_1_rx";
 242                 };
 243         };
 244
 245         irtx_pins: irtx-pins {
 246                 mux {
 247                         function = "ir";
 248                         groups =  "ir_1_tx";
 249                 };
 250         };
 251
 252         pcie0_pins: pcie0-pins {
 253                 mux {
 254                         function = "pcie";
 255                         groups = "pcie0_pad_perst",
 256                                  "pcie0_1_waken",
 257                                  "pcie0_1_clkreq";
 258                 };
 259         };
 260
 261         pcie1_pins: pcie1-pins {
 262                 mux {
 263                         function = "pcie";
 264                         groups = "pcie1_pad_perst",
 265                                  "pcie1_0_waken",
 266                                  "pcie1_0_clkreq";
 267                 };
 268         };
 269
 270         pmic_bus_pins: pmic-bus-pins {
 271                 mux {
 272                         function = "pmic";
 273                         groups = "pmic_bus";
 274                 };
 275         };
 276
 277         pwm7_pins: pwm1-2-pins {
 278                 mux {
 279                         function = "pwm";
 280                         groups = "pwm_ch7_2";
 281                 };
 282         };
 283
 284         wled_pins: wled-pins {
 285                 mux {
 286                         function = "led";
 287                         groups = "wled";
 288                 };
 289         };
 290
 291         /* Serial NAND is shared pin with SPI-NOR */
 292         serial_nand_pins: serial-nand-pins {
 293                 mux {
 294                         function = "flash";
 295                         groups = "snfi";
 296                 };
 297         };
 298
 299         spic0_pins: spic0-pins {
 300                 mux {
 301                         function = "spi";
 302                         groups = "spic0_0";
 303                 };
 304         };
 305
 306         spic1_pins: spic1-pins {
 307                 mux {
 308                         function = "spi";
 309                         groups = "spic1_0";
 310                 };
 311         };
 312
 313         uart0_pins: uart0-pins {
 314                 mux {
 315                         function = "uart";
 316                         groups = "uart0_0_tx_rx";
 317                 };
 318         };
 319
 320         uart2_pins: uart2-pins {
 321                 mux {
 322                         function = "uart";
 323                         groups = "uart2_1_tx_rx";
 324                 };
 325         };
 326
 327         watchdog_pins: watchdog-pins {
 328                 mux {
 329                         function = "watchdog";
 330                         groups = "watchdog";
 331                 };
 332         };
 333 };
 334
 335 &pwm {
 336         pinctrl-names = "default";
 337         pinctrl-0 = <&pwm7_pins>;
 338         status = "okay";
 339 };
 340
 341 &pwrap {
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pmic_bus_pins>;
 344         status = "okay";
 345 };
 346
 347 &rtc {
 348         status = "disabled";
 349 };
 350
 351 &sata {
 352         status = "disabled";
 353 };
 354
 355 &sata_phy {
 356         status = "disabled";
 357 };
 358
 359 &slot0 {
 360         wmac1: mt7915@0,0 {
 361                 reg = <0x0000 0 0 0 0>;
 362                 ieee80211-freq-limit = <5000000 6000000>;
 363         };
 364 };
 365
 366 &snfi {
 367         pinctrl-names = "default";
 368         pinctrl-0 = <&serial_nand_pins>;
 369         status = "okay";
 370
 371         snand: flash@0 {
 372                 compatible = "spi-nand";
 373                 mediatek,bmt-table-size = <0x1000>;
 374                 mediatek,bmt-v2;
 375                 nand-ecc-engine = <&snfi>;
 376                 reg = <0>;
 377                 spi-rx-bus-width = <4>;
 378                 spi-tx-bus-width = <4>;
 379
 380                 partitions {
 381                         compatible = "fixed-partitions";
 382                         #address-cells = <1>;
 383                         #size-cells = <1>;
 384
 385                         partition@0 {
 386                                 label = "Preloader";
 387                                 reg = <0x00000 0x0080000>;
 388                                 read-only;
 389                         };
 390
 391                         partition@80000 {
 392                                 label = "ATF";
 393                                 reg = <0x80000 0x0040000>;
 394                                 read-only;
 395                         };
 396
 397                         partition@c0000 {
 398                                 label = "Bootloader";
 399                                 reg = <0xc0000 0x0080000>;
 400                                 read-only;
 401                         };
 402
 403                         partition@140000 {
 404                                 label = "Config";
 405                                 reg = <0x140000 0x0080000>;
 406                         };
 407
 408                         factory: partition@1c0000 {
 409                                 compatible = "nvmem-cells";
 410                                 label = "Factory";
 411                                 reg = <0x1c0000 0x0100000>;
 412                                 #address-cells = <1>;
 413                                 #size-cells = <1>;
 414                                 read-only;
 415
 416                                 macaddr_factory_7fff4: macaddr@7fff4 {
 417                                         reg = <0x7fff4 0x6>;
 418                                 };
 419
 420                                 macaddr_factory_7fffa: macaddr@7fffa {
 421                                         reg = <0x7fffa 0x6>;
 422                                 };
 423                         };
 424
 425                         partition@2c0000 {
 426                                 label = "firmware";
 427                                 reg = <0x2c0000 0x2600000>;
 428
 429                                 compatible = "fixed-partitions";
 430                                 #address-cells = <1>;
 431                                 #size-cells = <1>;
 432
 433                                 partition@0 {
 434                                         label = "kernel";
 435                                         reg = <0x0 0x600000>;
 436                                 };
 437
 438                                 partition@600000 {
 439                                         label = "ubi";
 440                                         reg = <0x600000 0x2000000>;
 441                                 };
 442                         };
 443
 444                         partition@28c0000 {
 445                                 label = "firmware_backup";
 446                                 reg = <0x28c0000 0x2600000>;
 447                                 read-only;
 448                         };
 449
 450                         partition@4ec0000 {
 451                                 label = "CFG";
 452                                 reg = <0x4ec0000 0x800000>;
 453                                 read-only;
 454                         };
 455
 456                         partition@56c0000 {
 457                                 label = "RAE";
 458                                 reg = <0x56c0000 0x400000>;
 459                                 read-only;
 460                         };
 461
 462                         partition@5ac0000 {
 463                                 label = "POT";
 464                                 reg = <0x5ac0000 0x100000>;
 465                                 read-only;
 466                         };
 467
 468                         partition@5bc0000 {
 469                                 label = "Language";
 470                                 reg = <0x5bc0000 0x400000>;
 471                                 read-only;
 472                         };
 473
 474                         partition@5fc0000 {
 475                                 label = "Traffic";
 476                                 reg = <0x5fc0000 0x200000>;
 477                                 read-only;
 478                         };
 479
 480                         partition@61c0000 {
 481                                 label = "Cert";
 482                                 reg = <0x61c0000 0x100000>;
 483                                 read-only;
 484                         };
 485
 486                         partition@62c0000 {
 487                                 label = "NTGRcryptK";
 488                                 reg = <0x62c0000 0x100000>;
 489                                 read-only;
 490                         };
 491
 492                         partition@63c0000 {
 493                                 label = "NTGRcryptD";
 494                                 reg = <0x63c0000 0x500000>;
 495                                 read-only;
 496                         };
 497
 498                         partition@68c0000 {
 499                                 label = "LOG";
 500                                 reg = <0x68c0000 0x100000>;
 501                                 read-only;
 502                         };
 503
 504                         partition@69c0000 {
 505                                 label = "User_data";
 506                                 reg = <0x69c0000 0x640000>;
 507                                 read-only;
 508                         };
 509
 510                 };
 511         };
 512 };
 513
 514 &spi0 {
 515         pinctrl-names = "default";
 516         pinctrl-0 = <&spic0_pins>;
 517         status = "okay";
 518 };
 519
 520 &spi1 {
 521         pinctrl-names = "default";
 522         pinctrl-0 = <&spic1_pins>;
 523         status = "okay";
 524 };
 525
 526 &ssusb {
 527         status = "disabled";
 528 };
 529
 530 &u3phy {
 531         status = "disabled";
 532 };
 533
 534 &uart0 {
 535         pinctrl-names = "default";
 536         pinctrl-0 = <&uart0_pins>;
 537         status = "okay";
 538 };
 539
 540 &uart2 {
 541         pinctrl-names = "default";
 542         pinctrl-0 = <&uart2_pins>;
 543         status = "okay";
 544 };
 545
 546 &watchdog {
 547         pinctrl-names = "default";
 548         pinctrl-0 = <&watchdog_pins>;
 549         status = "okay";
 550 };
 551
 552 &wmac {
 553         mediatek,mtd-eeprom = <&factory 0x0000>;
 554         status = "okay";
 555 };
 556
 557 &wmac1 {
 558         mediatek,mtd-eeprom = <&factory 0x05000>;
 559 };