target/linux/bcm27xx/patches-6.1/950-1015-vc4-drm-Remove-the-clear-of-SCALER_DISPBKGND_FILL.patch

   1 From e6e0631fdeb0cd7d4c50e629b4b298e0b76e885b Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Wed, 4 Oct 2023 16:02:39 +0100
   4 Subject: [PATCH] vc4/drm: Remove the clear of SCALER_DISPBKGND_FILL
   5
   6 Since "drm/vc4: hvs: Support BCM2712 HVS" booting Pi4
   7 with dual 4kp30 displays connected fails with:
   8 vc4-drm gpu: [drm] *ERROR* [CRTC:107:pixelvalve-4] flip_done timed out
   9
  10 It has been tracked down to the referenced commit adding a
  11 path to clear the SCALER_DISPBKGND_FILL when not required.
  12
  13 Dual 4kp30 works with a core clock of 297MHz when background fill
  14 is enabled, but requires a higher value with it disabled.
  15 320MHz still fails, while 330MHz seems okay.
  16
  17 Lets always enable background fill for Pi0-4.
  18
  19 Fixes: e84da235223d ("drm/vc4: hvs: Support BCM2712 HVS")
  20
  21 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  22 ---
  23  drivers/gpu/drm/vc4/vc4_hvs.c | 20 +++++++++-----------
  24  1 file changed, 9 insertions(+), 11 deletions(-)
  25
  26 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
  27 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
  28 @@ -1349,27 +1349,25 @@ void vc4_hvs_atomic_flush(struct drm_crt
  29         WARN_ON(!vc4_state->mm);
  30         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm->mm_node.size);
  31
  32 -       if (enable_bg_fill) {
  33 +       if (vc4->gen >= VC4_GEN_6) {
  34                 /* This sets a black background color fill, as is the case
  35                  * with other DRM drivers.
  36                  */
  37 -               if (vc4->gen >= VC4_GEN_6)
  38 +               if (enable_bg_fill)
  39                         HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
  40                                   HVS_READ(SCALER6_DISPX_CTRL1(channel)) |
  41                                   SCALER6_DISPX_CTRL1_BGENB);
  42                 else
  43 -                       HVS_WRITE(SCALER_DISPBKGNDX(channel),
  44 -                                 HVS_READ(SCALER_DISPBKGNDX(channel)) |
  45 -                                 SCALER_DISPBKGND_FILL);
  46 -       } else {
  47 -               if (vc4->gen >= VC4_GEN_6)
  48                         HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
  49                                   HVS_READ(SCALER6_DISPX_CTRL1(channel)) &
  50                                   ~SCALER6_DISPX_CTRL1_BGENB);
  51 -               else
  52 -                       HVS_WRITE(SCALER_DISPBKGNDX(channel),
  53 -                                 HVS_READ(SCALER_DISPBKGNDX(channel)) &
  54 -                                 ~SCALER_DISPBKGND_FILL);
  55 +       } else {
  56 +               /* we can actually run with a lower core clock when background
  57 +                * fill is enabled on VC4_GEN_5 so leave it enabled always.
  58 +                */
  59 +               HVS_WRITE(SCALER_DISPBKGNDX(channel),
  60 +                         HVS_READ(SCALER_DISPBKGNDX(channel)) |
  61 +                         SCALER_DISPBKGND_FILL);
  62         }
  63
  64         /* Only update DISPLIST if the CRTC was already running and is not