include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
-PKG_VERSION:=2020.04
+PKG_VERSION:=2022.01
-PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372
+PKG_HASH:=81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413
PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
-@@ -455,6 +455,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
+@@ -549,6 +549,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
+CONFIG_SUNXI_SPI=y
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
-@@ -896,6 +896,14 @@ config VIDEO_LCD_PANEL_I2C_SCL
- Set the SCL pin for the LCD i2c interface. This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+@@ -942,6 +942,14 @@ config VIDEO_DE2
+ Say y here if you want to build DE2 video driver which is present on
+ newer SoCs. Currently only HDMI output is supported.
+choice
+ prompt "Sunxi Board Variant"
+
+endchoice
- # Note only one of these may be selected at a time! But hidden choices are
- # not supported by Kconfig
+ choice
+ prompt "LCD panel support"
+++ /dev/null
-From a58eb20fb80f478038243e9e0f30f6984725e265 Mon Sep 17 00:00:00 2001
-From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
-Date: Tue, 6 Jan 2015 15:47:18 +0100
-Subject: sun6i: Sync PLL1 multipliers/dividers with Boot1
-
-This change syncs up the multipliers and dividers used to initialize
-PLL1 (i.e. the fast clock driving the ARM cores) with the values used
-in Allwinner's Boot1 on sun6i.
-
-More specifically, the following settings are now used:
- * up to 768MHz: mul=2, div=2 (was: mul=1, div=1)
- * up to 1152MHz: mul=3, div=2 (unchanged)
- * above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
-
---- a/arch/arm/mach-sunxi/clock_sun6i.c
-+++ b/arch/arm/mach-sunxi/clock_sun6i.c
-@@ -112,11 +112,12 @@ void clock_set_pll1(unsigned int clk)
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- const int p = 0;
-- int k = 1;
-- int m = 1;
-+ int k = 2;
-+ int m = 2;
-
- if (clk > 1152000000) {
-- k = 2;
-+ k = 4;
-+ m = 2;
- } else if (clk > 768000000) {
- k = 4;
- m = 2;
+++ /dev/null
-From b2b385df5095fff80b4655142f58a2a6801e6c80 Mon Sep 17 00:00:00 2001
-From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
-Date: Tue, 6 Jan 2015 21:26:44 +0100
-Subject: sun6i: Fix and document PLL LDO voltage selection
-
-The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had
-their meaning reversed. This is fixed by this change-set. With this
-changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident
-as setting the voltage to 1.37v (which it had done all along, even
-though stating a different target voltage).
-
-After changing the PLL LDO setting, it will take a little while for
-the voltage output to settle. A sdelay()-based loop waits the same
-order of magnitude as Boot1.
-
-Furthermore, a bit of documentation is added to clarify that the
-required setting for the PLL LDO is 1.37v as per the A31 manual.
-
---- a/arch/arm/mach-sunxi/clock_sun6i.c
-+++ b/arch/arm/mach-sunxi/clock_sun6i.c
-@@ -25,13 +25,26 @@ void clock_init_safe(void)
- struct sunxi_prcm_reg * const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
-
-- /* Set PLL ldo voltage without this PLL6 does not work properly */
-+ /* Set PLL ldo voltage without this PLL6 does not work properly.
-+ *
-+ * As the A31 manual states, that "before enable PLL, PLLVDD
-+ * LDO should be set to 1.37v", we need to configure this to 2.5v
-+ * in the "PLL Input Power Select" (0 << 15) and (7 << 16).
-+ */
- clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
- PRCM_PLL_CTRL_LDO_KEY);
- clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
- PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
-- PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
-+ PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370));
- clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
-+
-+ /* Give the PLL LDO voltage setting some time to take hold.
-+ * Notes:
-+ * 1) We need to use sdelay() as the timers aren't set up yet.
-+ * 2) The 100k iterations come from Boot1, which spin's for 100k
-+ * iterations through a loop.
-+ */
-+ sdelay(100000);
- #endif
-
- #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
---- a/arch/arm/include/asm/arch-sunxi/prcm.h
-+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
-@@ -110,13 +110,13 @@
- #define PRCM_PLL_CTRL_LDO_OUT_MASK \
- __PRCM_PLL_CTRL_LDO_OUT(0x7)
- /* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
--#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
-- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
- #define PRCM_PLL_CTRL_LDO_OUT_H(n) \
-+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
-+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
--#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
-- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
- #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
-+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
-+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
- #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
- #define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
-@@ -726,9 +726,14 @@ static int fit_handle_file(struct image_
+@@ -752,9 +752,14 @@ static int fit_handle_file(struct image_
}
*cmd = '\0';
} else if (params->datafile) {
+++ /dev/null
-From def280c4792262a368c8861312dc6b376181021f Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Mon, 1 Jan 2018 23:10:56 +0100
-Subject: sunxi: deactivate binman
-
-Use the old way to generate the images instead of binman.
-binman needs python with swig to avoid this host tool dependency use the
-old way of generating images.
----
- Makefile | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/Makefile
-+++ b/Makefile
-@@ -1555,8 +1555,10 @@ endif
-
- ifneq ($(CONFIG_ARCH_SUNXI),)
- ifeq ($(CONFIG_ARM64),)
--u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
-- $(call if_changed,binman)
-+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
-+ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
-+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
-+ $(call if_changed,pad_cat)
- else
- u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
- $(call if_changed,cat)
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -962,7 +962,6 @@ config ARCH_SOCFPGA
-
- config ARCH_SUNXI
- bool "Support sunxi (Allwinner) SoCs"
-- select BINMAN
- select CMD_GPIO
- select CMD_MMC if MMC
- select CMD_USB if DISTRO_DEFAULTS
+++ /dev/null
---- a/configs/A13-OLinuXino_defconfig
-+++ b/configs/A13-OLinuXino_defconfig
-@@ -7,7 +7,6 @@ CONFIG_DRAM_EMR1=0
- CONFIG_MMC0_CD_PIN="PG0"
- CONFIG_USB0_VBUS_DET="PG1"
- CONFIG_USB1_VBUS_PIN="PG11"
--CONFIG_AXP_GPIO=y
- # CONFIG_VIDEO_HDMI is not set
- CONFIG_VIDEO_VGA_VIA_LCD=y
- CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
-@@ -21,7 +20,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
- CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
- CONFIG_DFU_RAM=y
- CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
--CONFIG_AXP_ALDO3_VOLT=3300
-+CONFIG_SUNXI_NO_PMIC=y
- CONFIG_CONS_INDEX=2
- CONFIG_USB_EHCI_HCD=y
- CONFIG_USB_OHCI_HCD=y
+++ /dev/null
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -539,7 +539,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
- sun8i-h3-orangepi-plus.dtb \
- sun8i-h3-orangepi-plus2e.dtb \
- sun8i-h3-orangepi-zero-plus2.dtb \
-- sun8i-h3-rervision-dvk.dtb
-+ sun8i-h3-rervision-dvk.dtb \
-+ sun8i-h3-zeropi.dtb
- dtb-$(CONFIG_MACH_SUN8I_R40) += \
- sun8i-r40-bananapi-m2-ultra.dtb \
- sun8i-v40-bananapi-m2-berry.dtb
---- /dev/null
-+++ b/arch/arm/dts/sun8i-h3-zeropi.dts
-@@ -0,0 +1,66 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+
-+#include "sun8i-h3-nanopi.dtsi"
-+
-+/ {
-+ model = "FriendlyElec ZeroPi";
-+ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3";
-+
-+ aliases {
-+ ethernet0 = &emac;
-+ };
-+
-+ reg_gmac_3v3: gmac-3v3 {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac_power_pin_nanopi>;
-+ regulator-name = "gmac-3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <100000>;
-+ enable-active-high;
-+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
-+ };
-+};
-+
-+&ehci0 {
-+ status = "okay";
-+};
-+
-+&ohci0 {
-+ status = "okay";
-+};
-+
-+&pio {
-+ gmac_power_pin_nanopi: gmac_power_pin@0 {
-+ pins = "PD6";
-+ function = "gpio_out";
-+ };
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <7>;
-+ };
-+};
-+
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+
-+ allwinner,leds-active-low;
-+ status = "okay";
-+};
-+
-+&usb_otg {
-+ status = "okay";
-+ dr_mode = "peripheral";
-+};
-+
-+&usbphy {
-+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
-+};
+++ /dev/null
---- /dev/null
-+++ b/configs/zeropi_defconfig
-@@ -0,0 +1,21 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_MACH_SUN8I_H3=y
-+CONFIG_DRAM_CLK=408
-+CONFIG_DRAM_ZQ=3881979
-+CONFIG_DRAM_ODT_EN=y
-+CONFIG_MACPWR="PD6"
-+# CONFIG_VIDEO_DE2 is not set
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_CONSOLE_MUX=y
-+CONFIG_SPL=y
-+CONFIG_SYS_CLK_FREQ=480000000
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+++ /dev/null
-From 0e8043aff1aae95d1f7b7422b91b57d9569860d3 Mon Sep 17 00:00:00 2001
-From: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
-Date: Mon, 12 Oct 2020 18:39:53 +0000
-Subject: [PATCH] sunxi: add support for FriendlyARM NanoPi R1
-
-Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
----
- arch/arm/dts/Makefile | 1 +
- arch/arm/dts/sun8i-h3-nanopi-r1.dts | 146 ++++++++++++++++++++++++++++
- configs/nanopi_r1_defconfig | 22 +++++
- 3 files changed, 169 insertions(+)
- create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
- create mode 100644 configs/nanopi_r1_defconfig
-
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -531,6 +531,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
- sun8i-h3-nanopi-m1-plus.dtb \
- sun8i-h3-nanopi-neo.dtb \
- sun8i-h3-nanopi-neo-air.dtb \
-+ sun8i-h3-nanopi-r1.dtb \
- sun8i-h3-orangepi-2.dtb \
- sun8i-h3-orangepi-lite.dtb \
- sun8i-h3-orangepi-one.dtb \
---- /dev/null
-+++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
-@@ -0,0 +1,146 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>
-+ * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
-+ */
-+
-+/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */
-+#include "sun8i-h3-nanopi.dtsi"
-+
-+/ {
-+ model = "FriendlyARM NanoPi R1";
-+ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3";
-+
-+ reg_gmac_3v3: gmac-3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "gmac-3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <100000>;
-+ enable-active-high;
-+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ vdd_cpux: gpio-regulator {
-+ compatible = "regulator-gpio";
-+ pinctrl-names = "default";
-+ regulator-name = "vdd-cpux";
-+ regulator-type = "voltage";
-+ regulator-boot-on;
-+ regulator-always-on;
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1300000>;
-+ regulator-ramp-delay = <50>;
-+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
-+ gpios-states = <0x1>;
-+ states = <1100000 0x0
-+ 1300000 0x1>;
-+ };
-+
-+ wifi_pwrseq: wifi_pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ pinctrl-names = "default";
-+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
-+ };
-+
-+ leds {
-+ /delete-node/ pwr;
-+ status {
-+ label = "nanopi:red:status";
-+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
-+
-+ wan {
-+ label = "nanopi:green:wan";
-+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ lan {
-+ label = "nanopi:green:lan";
-+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+
-+ r_gpio_keys {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sw_r_npi>;
-+
-+ /delete-node/ k1;
-+ reset {
-+ label = "reset";
-+ linux,code = <KEY_RESTART>;
-+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpux>;
-+};
-+
-+&ehci1 {
-+ status = "okay";
-+};
-+
-+&ehci2 {
-+ status = "okay";
-+};
-+
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <7>;
-+ };
-+};
-+
-+&mmc1 {
-+ vmmc-supply = <®_vcc3v3>;
-+ vqmmc-supply = <®_vcc3v3>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ bus-width = <4>;
-+ non-removable;
-+ status = "okay";
-+
-+ sdio_wifi: sdio_wifi@1 {
-+ reg = <1>;
-+ compatible = "brcm,bcm4329-fmac";
-+ interrupt-parent = <&pio>;
-+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "host-wake";
-+ };
-+};
-+
-+&mmc2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mmc2_8bit_pins>;
-+ vmmc-supply = <®_vcc3v3>;
-+ vqmmc-supply = <®_vcc3v3>;
-+ bus-width = <8>;
-+ non-removable;
-+ status = "okay";
-+};
-+
-+&ohci1 {
-+ status = "okay";
-+};
-+
-+&ohci2 {
-+ status = "okay";
-+};
-+
-+&r_pio {
-+ sw_r_npi: key_pins {
-+ pins = "PL3";
-+ function = "gpio_in";
-+ };
-+};
---- /dev/null
-+++ b/configs/nanopi_r1_defconfig
-@@ -0,0 +1,22 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_SPL=y
-+CONFIG_MACH_SUN8I_H3=y
-+CONFIG_DRAM_CLK=408
-+CONFIG_DRAM_ZQ=3881979
-+CONFIG_DRAM_ODT_EN=y
-+CONFIG_MACPWR="PD6"
-+# CONFIG_VIDEO_DE2 is not set
-+CONFIG_NR_DRAM_BANKS=1
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_CONSOLE_MUX=y
-+CONFIG_SYS_CLK_FREQ=480000000
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_SPL_DOS_PARTITION is not set
-+# CONFIG_SPL_EFI_PARTITION is not set
-+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1"
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+++ /dev/null
-From e7510d24cab4741f72489b9d67c2d42b18fe5374 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sun, 10 Oct 2021 21:36:57 +0800
-Subject: [PATCH] sunxi: Add support for FriendlyARM NanoPi R1S H5
-
-This adds support for the NanoPi R1S H5 board.
-
-Allwinner H5 SoC
-512MB DDR3 RAM
-10/100/1000M Ethernet x 2
-RTL8189ETV WiFi 802.11b/g/n
-USB 2.0 host port (A)
-MicroSD Slot
-Reset button
-Serial Debug Port
-WAN - LAN - SYS LED
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
----
- arch/arm/dts/Makefile | 1 +
- arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 195 +++++++++++++++++++++++
- board/sunxi/MAINTAINERS | 5 +
- configs/nanopi_r1s_h5_defconfig | 14 ++
- 4 files changed, 215 insertions(+)
- create mode 100644 arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
- create mode 100644 configs/nanopi_r1s_h5_defconfig
-
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index b8a382d1539..ed3d360bb10 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -638,6 +638,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
- sun50i-h5-libretech-all-h5-cc.dtb \
- sun50i-h5-nanopi-neo2.dtb \
- sun50i-h5-nanopi-neo-plus2.dtb \
-+ sun50i-h5-nanopi-r1s-h5.dtb \
- sun50i-h5-orangepi-zero-plus.dtb \
- sun50i-h5-orangepi-pc2.dtb \
- sun50i-h5-orangepi-prime.dtb \
-diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
-new file mode 100644
-index 00000000000..55bcdf8d1a0
---- /dev/null
-+++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
-@@ -0,0 +1,190 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
-+ *
-+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
-+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
-+ * Copyright (C) 2016 ARM Ltd.
-+ */
-+
-+/dts-v1/;
-+#include "sun50i-h5.dtsi"
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+ model = "FriendlyARM NanoPi R1S H5";
-+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
-+
-+ aliases {
-+ ethernet0 = &emac;
-+ ethernet1 = &rtl8189etv;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ sys {
-+ label = "nanopi:red:sys";
-+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
-+
-+ lan {
-+ label = "nanopi:green:lan";
-+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ wan {
-+ label = "nanopi:green:wan";
-+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+
-+ r-gpio-keys {
-+ compatible = "gpio-keys";
-+
-+ reset {
-+ label = "reset";
-+ linux,code = <KEY_RESTART>;
-+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ reg_gmac_3v3: gmac-3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "gmac-3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <100000>;
-+ enable-active-high;
-+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ reg_vcc3v3: vcc3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ reg_usb0_vbus: usb0-vbus {
-+ compatible = "regulator-fixed";
-+ regulator-name = "usb0-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
-+ status = "okay";
-+ };
-+
-+ vdd_cpux: gpio-regulator {
-+ compatible = "regulator-gpio";
-+ regulator-name = "vdd-cpux";
-+ regulator-type = "voltage";
-+ regulator-boot-on;
-+ regulator-always-on;
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1300000>;
-+ regulator-ramp-delay = <50>; /* 4ms */
-+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
-+ gpios-states = <0x1>;
-+ states = <1100000 0x0>, <1300000 0x1>;
-+ };
-+
-+ wifi_pwrseq: wifi_pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-+ post-power-on-delay-ms = <200>;
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpux>;
-+};
-+
-+&ehci1 {
-+ status = "okay";
-+};
-+
-+&ehci2 {
-+ status = "okay";
-+};
-+
-+&emac {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_rgmii_pins>;
-+ phy-supply = <®_gmac_3v3>;
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii-id";
-+ status = "okay";
-+};
-+
-+&external_mdio {
-+ ext_rgmii_phy: ethernet-phy@7 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <7>;
-+ };
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ eeprom@51 {
-+ compatible = "microchip,24c02";
-+ reg = <0x51>;
-+ pagesize = <16>;
-+ };
-+};
-+
-+&mmc0 {
-+ vmmc-supply = <®_vcc3v3>;
-+ bus-width = <4>;
-+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-+ status = "okay";
-+};
-+
-+&mmc1 {
-+ vmmc-supply = <®_vcc3v3>;
-+ vqmmc-supply = <®_vcc3v3>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ bus-width = <4>;
-+ non-removable;
-+ status = "okay";
-+
-+ rtl8189etv: sdio_wifi@1 {
-+ reg = <1>;
-+ };
-+};
-+
-+&ohci1 {
-+ status = "okay";
-+};
-+
-+&ohci2 {
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_pa_pins>;
-+ status = "okay";
-+};
-+
-+&usb_otg {
-+ dr_mode = "peripheral";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ /* USB Type-A port's VBUS is always on */
-+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
-+ usb0_vbus-supply = <®_usb0_vbus>;
-+ status = "okay";
-+};
-diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
-index 2543c94de79..56a0ee3689b 100644
---- a/board/sunxi/MAINTAINERS
-+++ b/board/sunxi/MAINTAINERS
-@@ -358,6 +358,11 @@ M: Jelle van der Waa <jelle@vdwaa.nl>
- S: Maintained
- F: configs/nanopi_neo_air_defconfig
-
-+NANOPI-R1S-H5 BOARD
-+M: Chukun Pan <amadeus@jmu.edu.cn>
-+S: Maintained
-+F: configs/nanopi_r1s_h5_defconfig
-+
- NANOPI-A64 BOARD
- M: Jagan Teki <jagan@amarulasolutions.com>
- S: Maintained
-diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig
-new file mode 100644
-index 00000000000..27cf172d72a
---- /dev/null
-+++ b/configs/nanopi_r1s_h5_defconfig
-@@ -0,0 +1,14 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_SPL=y
-+CONFIG_MACH_SUN50I_H5=y
-+CONFIG_DRAM_CLK=672
-+CONFIG_DRAM_ZQ=3881977
-+# CONFIG_DRAM_ODT_EN is not set
-+CONFIG_MACPWR="PD6"
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-r1s-h5"
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_OHCI_HCD=y
--- /dev/null
+--- a/Makefile
++++ b/Makefile
+@@ -1967,26 +1967,7 @@ endif
+ # Check dtc and pylibfdt, if DTC is provided, else build them
+ PHONY += scripts_dtc
+ scripts_dtc: scripts_basic
+- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
+- $(MAKE) $(build)=scripts/dtc; \
+- else \
+- if ! $(DTC) -v >/dev/null; then \
+- echo '*** Failed to check dtc version: $(DTC)'; \
+- false; \
+- else \
+- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
+- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
+- false; \
+- else \
+- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
+- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
+- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
+- false; \
+- fi; \
+- fi; \
+- fi; \
+- fi; \
+- fi
++ $(MAKE) $(build)=scripts/dtc
+
+ # ---------------------------------------------------------------------------
+ quiet_cmd_cpp_lds = LDS $@
projects / openwrt / staging / ynezz.git / commitdiff