target/linux/starfive/patches-6.1/1016-riscv-Implement-non-coherent-DMA-support-via-SiFive-.patch

   1 From d30b864417ea3ad1bc4fcf675ea072cb19011930 Mon Sep 17 00:00:00 2001
   2 From: Emil Renner Berthing <kernel@esmil.dk>
   3 Date: Sat, 12 Jun 2021 16:48:31 -0700
   4 Subject: [PATCH 1016/1024] riscv: Implement non-coherent DMA support via
   5  SiFive cache flushing
   6
   7 This variant is used on the StarFive JH7100 SoC.
   8
   9 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
  10 ---
  11  arch/riscv/Kconfig              |  6 ++++--
  12  arch/riscv/mm/dma-noncoherent.c | 37 +++++++++++++++++++++++++++++++--
  13  2 files changed, 39 insertions(+), 4 deletions(-)
  14
  15 --- a/arch/riscv/Kconfig
  16 +++ b/arch/riscv/Kconfig
  17 @@ -225,12 +225,14 @@ config LOCKDEP_SUPPORT
  18         def_bool y
  19
  20  config RISCV_DMA_NONCOHERENT
  21 -       bool
  22 +       bool "Support non-coherent DMA"
  23 +       default SOC_STARFIVE
  24         select ARCH_HAS_DMA_PREP_COHERENT
  25 +       select ARCH_HAS_DMA_SET_UNCACHED
  26 +       select ARCH_HAS_DMA_CLEAR_UNCACHED
  27         select ARCH_HAS_SYNC_DMA_FOR_DEVICE
  28         select ARCH_HAS_SYNC_DMA_FOR_CPU
  29         select ARCH_HAS_SETUP_DMA_OPS
  30 -       select DMA_DIRECT_REMAP
  31
  32  config AS_HAS_INSN
  33         def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)
  34 --- a/arch/riscv/mm/dma-noncoherent.c
  35 +++ b/arch/riscv/mm/dma-noncoherent.c
  36 @@ -9,14 +9,21 @@
  37  #include <linux/dma-map-ops.h>
  38  #include <linux/mm.h>
  39  #include <asm/cacheflush.h>
  40 +#include <soc/sifive/sifive_ccache.h>
  41
  42  static bool noncoherent_supported;
  43
  44  void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
  45                               enum dma_data_direction dir)
  46  {
  47 -       void *vaddr = phys_to_virt(paddr);
  48 +       void *vaddr;
  49
  50 +       if (sifive_ccache_handle_noncoherent()) {
  51 +               sifive_ccache_flush_range(paddr, size);
  52 +               return;
  53 +       }
  54 +
  55 +       vaddr = phys_to_virt(paddr);
  56         switch (dir) {
  57         case DMA_TO_DEVICE:
  58                 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
  59 @@ -35,8 +42,14 @@ void arch_sync_dma_for_device(phys_addr_
  60  void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
  61                            enum dma_data_direction dir)
  62  {
  63 -       void *vaddr = phys_to_virt(paddr);
  64 +       void *vaddr;
  65 +
  66 +       if (sifive_ccache_handle_noncoherent()) {
  67 +               sifive_ccache_flush_range(paddr, size);
  68 +               return;
  69 +       }
  70
  71 +       vaddr = phys_to_virt(paddr);
  72         switch (dir) {
  73         case DMA_TO_DEVICE:
  74                 break;
  75 @@ -49,10 +62,30 @@ void arch_sync_dma_for_cpu(phys_addr_t p
  76         }
  77  }
  78
  79 +void *arch_dma_set_uncached(void *addr, size_t size)
  80 +{
  81 +       if (sifive_ccache_handle_noncoherent())
  82 +               return sifive_ccache_set_uncached(addr, size);
  83 +
  84 +       return addr;
  85 +}
  86 +
  87 +void arch_dma_clear_uncached(void *addr, size_t size)
  88 +{
  89 +       if (sifive_ccache_handle_noncoherent())
  90 +               sifive_ccache_clear_uncached(addr, size);
  91 +}
  92 +
  93  void arch_dma_prep_coherent(struct page *page, size_t size)
  94  {
  95         void *flush_addr = page_address(page);
  96
  97 +       if (sifive_ccache_handle_noncoherent()) {
  98 +               memset(flush_addr, 0, size);
  99 +               sifive_ccache_flush_range(__pa(flush_addr), size);
 100 +               return;
 101 +       }
 102 +
 103         ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
 104  }
 105