starfive: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0118-driver-regulator-axp20x-Support-AXP15060-variant.patch
1 From 1b017f3376a5df4a2cd5a120c16723e777fc9a36 Mon Sep 17 00:00:00 2001
2 From: "ziv.xu" <ziv.xu@starfive.com>
3 Date: Fri, 4 Aug 2023 13:55:23 +0800
4 Subject: [PATCH 118/122] driver: regulator: axp20x: Support AXP15060 variant.
5
6 Add axp15060 variant support to axp20x
7
8 Signed-off-by: ziv.xu <ziv.xu@starfive.com>
9 ---
10 drivers/regulator/axp20x-regulator.c | 291 ++++++++++++++++++++++++++-
11 1 file changed, 283 insertions(+), 8 deletions(-)
12
13 --- a/drivers/regulator/axp20x-regulator.c
14 +++ b/drivers/regulator/axp20x-regulator.c
15 @@ -134,6 +134,11 @@
16 #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6)
17 #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7)
18
19 +#define AXP313A_DCDC1_NUM_VOLTAGES 107
20 +#define AXP313A_DCDC23_NUM_VOLTAGES 88
21 +#define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0)
22 +#define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0)
23 +
24 #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0)
25 #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1)
26 #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2)
27 @@ -270,6 +275,74 @@
28
29 #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6)
30
31 +#define AXP15060_DCDC1_V_CTRL_MASK GENMASK(4, 0)
32 +#define AXP15060_DCDC2_V_CTRL_MASK GENMASK(6, 0)
33 +#define AXP15060_DCDC3_V_CTRL_MASK GENMASK(6, 0)
34 +#define AXP15060_DCDC4_V_CTRL_MASK GENMASK(6, 0)
35 +#define AXP15060_DCDC5_V_CTRL_MASK GENMASK(6, 0)
36 +#define AXP15060_DCDC6_V_CTRL_MASK GENMASK(4, 0)
37 +#define AXP15060_ALDO1_V_CTRL_MASK GENMASK(4, 0)
38 +#define AXP15060_ALDO2_V_CTRL_MASK GENMASK(4, 0)
39 +#define AXP15060_ALDO3_V_CTRL_MASK GENMASK(4, 0)
40 +#define AXP15060_ALDO4_V_CTRL_MASK GENMASK(4, 0)
41 +#define AXP15060_ALDO5_V_CTRL_MASK GENMASK(4, 0)
42 +#define AXP15060_BLDO1_V_CTRL_MASK GENMASK(4, 0)
43 +#define AXP15060_BLDO2_V_CTRL_MASK GENMASK(4, 0)
44 +#define AXP15060_BLDO3_V_CTRL_MASK GENMASK(4, 0)
45 +#define AXP15060_BLDO4_V_CTRL_MASK GENMASK(4, 0)
46 +#define AXP15060_BLDO5_V_CTRL_MASK GENMASK(4, 0)
47 +#define AXP15060_CLDO1_V_CTRL_MASK GENMASK(4, 0)
48 +#define AXP15060_CLDO2_V_CTRL_MASK GENMASK(4, 0)
49 +#define AXP15060_CLDO3_V_CTRL_MASK GENMASK(4, 0)
50 +#define AXP15060_CLDO4_V_CTRL_MASK GENMASK(5, 0)
51 +#define AXP15060_CPUSLDO_V_CTRL_MASK GENMASK(3, 0)
52 +
53 +#define AXP15060_PWR_OUT_DCDC1_MASK BIT_MASK(0)
54 +#define AXP15060_PWR_OUT_DCDC2_MASK BIT_MASK(1)
55 +#define AXP15060_PWR_OUT_DCDC3_MASK BIT_MASK(2)
56 +#define AXP15060_PWR_OUT_DCDC4_MASK BIT_MASK(3)
57 +#define AXP15060_PWR_OUT_DCDC5_MASK BIT_MASK(4)
58 +#define AXP15060_PWR_OUT_DCDC6_MASK BIT_MASK(5)
59 +#define AXP15060_PWR_OUT_ALDO1_MASK BIT_MASK(0)
60 +#define AXP15060_PWR_OUT_ALDO2_MASK BIT_MASK(1)
61 +#define AXP15060_PWR_OUT_ALDO3_MASK BIT_MASK(2)
62 +#define AXP15060_PWR_OUT_ALDO4_MASK BIT_MASK(3)
63 +#define AXP15060_PWR_OUT_ALDO5_MASK BIT_MASK(4)
64 +#define AXP15060_PWR_OUT_BLDO1_MASK BIT_MASK(5)
65 +#define AXP15060_PWR_OUT_BLDO2_MASK BIT_MASK(6)
66 +#define AXP15060_PWR_OUT_BLDO3_MASK BIT_MASK(7)
67 +#define AXP15060_PWR_OUT_BLDO4_MASK BIT_MASK(0)
68 +#define AXP15060_PWR_OUT_BLDO5_MASK BIT_MASK(1)
69 +#define AXP15060_PWR_OUT_CLDO1_MASK BIT_MASK(2)
70 +#define AXP15060_PWR_OUT_CLDO2_MASK BIT_MASK(3)
71 +#define AXP15060_PWR_OUT_CLDO3_MASK BIT_MASK(4)
72 +#define AXP15060_PWR_OUT_CLDO4_MASK BIT_MASK(5)
73 +#define AXP15060_PWR_OUT_CPUSLDO_MASK BIT_MASK(6)
74 +#define AXP15060_PWR_OUT_SW_MASK BIT_MASK(7)
75 +
76 +#define AXP15060_DCDC23_POLYPHASE_DUAL_MASK BIT_MASK(6)
77 +#define AXP15060_DCDC46_POLYPHASE_DUAL_MASK BIT_MASK(7)
78 +
79 +#define AXP15060_DCDC234_500mV_START 0x00
80 +#define AXP15060_DCDC234_500mV_STEPS 70
81 +#define AXP15060_DCDC234_500mV_END \
82 + (AXP15060_DCDC234_500mV_START + AXP15060_DCDC234_500mV_STEPS)
83 +#define AXP15060_DCDC234_1220mV_START 0x47
84 +#define AXP15060_DCDC234_1220mV_STEPS 16
85 +#define AXP15060_DCDC234_1220mV_END \
86 + (AXP15060_DCDC234_1220mV_START + AXP15060_DCDC234_1220mV_STEPS)
87 +#define AXP15060_DCDC234_NUM_VOLTAGES 88
88 +
89 +#define AXP15060_DCDC5_800mV_START 0x00
90 +#define AXP15060_DCDC5_800mV_STEPS 32
91 +#define AXP15060_DCDC5_800mV_END \
92 + (AXP15060_DCDC5_800mV_START + AXP15060_DCDC5_800mV_STEPS)
93 +#define AXP15060_DCDC5_1140mV_START 0x21
94 +#define AXP15060_DCDC5_1140mV_STEPS 35
95 +#define AXP15060_DCDC5_1140mV_END \
96 + (AXP15060_DCDC5_1140mV_START + AXP15060_DCDC5_1140mV_STEPS)
97 +#define AXP15060_DCDC5_NUM_VOLTAGES 69
98 +
99 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
100 _vmask, _ereg, _emask, _enable_val, _disable_val) \
101 [_family##_##_id] = { \
102 @@ -638,6 +711,48 @@ static const struct regulator_desc axp22
103 .ops = &axp20x_ops_sw,
104 };
105
106 +static const struct linear_range axp313a_dcdc1_ranges[] = {
107 + REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
108 + REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
109 + REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000),
110 +};
111 +
112 +static const struct linear_range axp313a_dcdc2_ranges[] = {
113 + REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
114 + REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
115 +};
116 +
117 +/*
118 + * This is deviating from the datasheet. The values here are taken from the
119 + * BSP driver and have been confirmed by measurements.
120 + */
121 +static const struct linear_range axp313a_dcdc3_ranges[] = {
122 + REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
123 + REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),
124 +};
125 +
126 +static const struct regulator_desc axp313a_regulators[] = {
127 + AXP_DESC_RANGES(AXP313A, DCDC1, "dcdc1", "vin1",
128 + axp313a_dcdc1_ranges, AXP313A_DCDC1_NUM_VOLTAGES,
129 + AXP313A_DCDC1_CONRTOL, AXP313A_DCDC_V_OUT_MASK,
130 + AXP313A_OUTPUT_CONTROL, BIT(0)),
131 + AXP_DESC_RANGES(AXP313A, DCDC2, "dcdc2", "vin2",
132 + axp313a_dcdc2_ranges, AXP313A_DCDC23_NUM_VOLTAGES,
133 + AXP313A_DCDC2_CONRTOL, AXP313A_DCDC_V_OUT_MASK,
134 + AXP313A_OUTPUT_CONTROL, BIT(1)),
135 + AXP_DESC_RANGES(AXP313A, DCDC3, "dcdc3", "vin3",
136 + axp313a_dcdc3_ranges, AXP313A_DCDC23_NUM_VOLTAGES,
137 + AXP313A_DCDC3_CONRTOL, AXP313A_DCDC_V_OUT_MASK,
138 + AXP313A_OUTPUT_CONTROL, BIT(2)),
139 + AXP_DESC(AXP313A, ALDO1, "aldo1", "vin1", 500, 3500, 100,
140 + AXP313A_ALDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK,
141 + AXP313A_OUTPUT_CONTROL, BIT(3)),
142 + AXP_DESC(AXP313A, DLDO1, "dldo1", "vin1", 500, 3500, 100,
143 + AXP313A_DLDO1_CONRTOL, AXP313A_LDO_V_OUT_MASK,
144 + AXP313A_OUTPUT_CONTROL, BIT(4)),
145 + AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800),
146 +};
147 +
148 /* DCDC ranges shared with AXP813 */
149 static const struct linear_range axp803_dcdc234_ranges[] = {
150 REGULATOR_LINEAR_RANGE(500000,
151 @@ -1001,6 +1116,104 @@ static const struct regulator_desc axp81
152 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
153 };
154
155 +static const struct linear_range axp15060_dcdc234_ranges[] = {
156 + REGULATOR_LINEAR_RANGE(500000,
157 + AXP15060_DCDC234_500mV_START,
158 + AXP15060_DCDC234_500mV_END,
159 + 10000),
160 + REGULATOR_LINEAR_RANGE(1220000,
161 + AXP15060_DCDC234_1220mV_START,
162 + AXP15060_DCDC234_1220mV_END,
163 + 20000),
164 +};
165 +
166 +static const struct linear_range axp15060_dcdc5_ranges[] = {
167 + REGULATOR_LINEAR_RANGE(800000,
168 + AXP15060_DCDC5_800mV_START,
169 + AXP15060_DCDC5_800mV_END,
170 + 10000),
171 + REGULATOR_LINEAR_RANGE(1140000,
172 + AXP15060_DCDC5_1140mV_START,
173 + AXP15060_DCDC5_1140mV_END,
174 + 20000),
175 +};
176 +
177 +static const struct regulator_desc axp15060_regulators[] = {
178 + AXP_DESC(AXP15060, DCDC1, "dcdc1", "vin1", 1500, 3400, 100,
179 + AXP15060_DCDC1_V_CTRL, AXP15060_DCDC1_V_CTRL_MASK,
180 + AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC1_MASK),
181 + AXP_DESC_RANGES(AXP15060, DCDC2, "dcdc2", "vin2",
182 + axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,
183 + AXP15060_DCDC2_V_CTRL, AXP15060_DCDC2_V_CTRL_MASK,
184 + AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC2_MASK),
185 + AXP_DESC_RANGES(AXP15060, DCDC3, "dcdc3", "vin3",
186 + axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,
187 + AXP15060_DCDC3_V_CTRL, AXP15060_DCDC3_V_CTRL_MASK,
188 + AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC3_MASK),
189 + AXP_DESC_RANGES(AXP15060, DCDC4, "dcdc4", "vin4",
190 + axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,
191 + AXP15060_DCDC4_V_CTRL, AXP15060_DCDC4_V_CTRL_MASK,
192 + AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC4_MASK),
193 + AXP_DESC_RANGES(AXP15060, DCDC5, "dcdc5", "vin5",
194 + axp15060_dcdc5_ranges, AXP15060_DCDC5_NUM_VOLTAGES,
195 + AXP15060_DCDC5_V_CTRL, AXP15060_DCDC5_V_CTRL_MASK,
196 + AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC5_MASK),
197 + AXP_DESC(AXP15060, DCDC6, "dcdc6", "vin6", 500, 3400, 100,
198 + AXP15060_DCDC6_V_CTRL, AXP15060_DCDC6_V_CTRL_MASK,
199 + AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC6_MASK),
200 + AXP_DESC(AXP15060, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
201 + AXP15060_ALDO1_V_CTRL, AXP15060_ALDO1_V_CTRL_MASK,
202 + AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO1_MASK),
203 + AXP_DESC(AXP15060, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
204 + AXP15060_ALDO2_V_CTRL, AXP15060_ALDO2_V_CTRL_MASK,
205 + AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO2_MASK),
206 + AXP_DESC(AXP15060, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
207 + AXP15060_ALDO3_V_CTRL, AXP15060_ALDO3_V_CTRL_MASK,
208 + AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO3_MASK),
209 + AXP_DESC(AXP15060, ALDO4, "aldo4", "aldoin", 700, 3300, 100,
210 + AXP15060_ALDO4_V_CTRL, AXP15060_ALDO4_V_CTRL_MASK,
211 + AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO4_MASK),
212 + AXP_DESC(AXP15060, ALDO5, "aldo5", "aldoin", 700, 3300, 100,
213 + AXP15060_ALDO5_V_CTRL, AXP15060_ALDO5_V_CTRL_MASK,
214 + AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO5_MASK),
215 + AXP_DESC(AXP15060, BLDO1, "bldo1", "bldoin", 700, 3300, 100,
216 + AXP15060_BLDO1_V_CTRL, AXP15060_BLDO1_V_CTRL_MASK,
217 + AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO1_MASK),
218 + AXP_DESC(AXP15060, BLDO2, "bldo2", "bldoin", 700, 3300, 100,
219 + AXP15060_BLDO2_V_CTRL, AXP15060_BLDO2_V_CTRL_MASK,
220 + AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO2_MASK),
221 + AXP_DESC(AXP15060, BLDO3, "bldo3", "bldoin", 700, 3300, 100,
222 + AXP15060_BLDO3_V_CTRL, AXP15060_BLDO3_V_CTRL_MASK,
223 + AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO3_MASK),
224 + AXP_DESC(AXP15060, BLDO4, "bldo4", "bldoin", 700, 3300, 100,
225 + AXP15060_BLDO4_V_CTRL, AXP15060_BLDO4_V_CTRL_MASK,
226 + AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO4_MASK),
227 + AXP_DESC(AXP15060, BLDO5, "bldo5", "bldoin", 700, 3300, 100,
228 + AXP15060_BLDO5_V_CTRL, AXP15060_BLDO5_V_CTRL_MASK,
229 + AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO5_MASK),
230 + AXP_DESC(AXP15060, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
231 + AXP15060_CLDO1_V_CTRL, AXP15060_CLDO1_V_CTRL_MASK,
232 + AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO1_MASK),
233 + AXP_DESC(AXP15060, CLDO2, "cldo2", "cldoin", 700, 3300, 100,
234 + AXP15060_CLDO2_V_CTRL, AXP15060_CLDO2_V_CTRL_MASK,
235 + AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO2_MASK),
236 + AXP_DESC(AXP15060, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
237 + AXP15060_CLDO3_V_CTRL, AXP15060_CLDO3_V_CTRL_MASK,
238 + AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO3_MASK),
239 + AXP_DESC(AXP15060, CLDO4, "cldo4", "cldoin", 700, 4200, 100,
240 + AXP15060_CLDO4_V_CTRL, AXP15060_CLDO4_V_CTRL_MASK,
241 + AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO4_MASK),
242 + /* Supply comes from DCDC5 */
243 + AXP_DESC(AXP15060, CPUSLDO, "cpusldo", NULL, 700, 1400, 50,
244 + AXP15060_CPUSLDO_V_CTRL, AXP15060_CPUSLDO_V_CTRL_MASK,
245 + AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CPUSLDO_MASK),
246 + /* Supply comes from DCDC1 */
247 + AXP_DESC_SW(AXP15060, SW, "sw", NULL,
248 + AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_SW_MASK),
249 + /* Supply comes from ALDO1 */
250 + AXP_DESC_FIXED(AXP15060, RTC_LDO, "rtc-ldo", NULL, 1800),
251 +};
252 +
253 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
254 {
255 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
256 @@ -1040,6 +1253,16 @@ static int axp20x_set_dcdc_freq(struct p
257 def = 3000;
258 step = 150;
259 break;
260 + case AXP313A_ID:
261 + case AXP15060_ID:
262 + /* The DCDC PWM frequency seems to be fixed to 3 MHz. */
263 + if (dcdcfreq != 0) {
264 + dev_err(&pdev->dev,
265 + "DCDC frequency on this PMIC is fixed to 3 MHz.\n");
266 + return -EINVAL;
267 + }
268 +
269 + return 0;
270 default:
271 dev_err(&pdev->dev,
272 "Setting DCDC frequency for unsupported AXP variant\n");
273 @@ -1145,6 +1368,15 @@ static int axp20x_set_dcdc_workmode(stru
274 workmode <<= id - AXP813_DCDC1;
275 break;
276
277 + case AXP15060_ID:
278 + reg = AXP15060_DCDC_MODE_CTRL2;
279 + if (id < AXP15060_DCDC1 || id > AXP15060_DCDC6)
280 + return -EINVAL;
281 +
282 + mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP15060_DCDC1);
283 + workmode <<= id - AXP15060_DCDC1;
284 + break;
285 +
286 default:
287 /* should not happen */
288 WARN_ON(1);
289 @@ -1164,7 +1396,7 @@ static bool axp20x_is_polyphase_slave(st
290
291 /*
292 * Currently in our supported AXP variants, only AXP803, AXP806,
293 - * and AXP813 have polyphase regulators.
294 + * AXP813 and AXP15060 have polyphase regulators.
295 */
296 switch (axp20x->variant) {
297 case AXP803_ID:
298 @@ -1196,6 +1428,17 @@ static bool axp20x_is_polyphase_slave(st
299 }
300 break;
301
302 + case AXP15060_ID:
303 + regmap_read(axp20x->regmap, AXP15060_DCDC_MODE_CTRL1, &reg);
304 +
305 + switch (id) {
306 + case AXP15060_DCDC3:
307 + return !!(reg & AXP15060_DCDC23_POLYPHASE_DUAL_MASK);
308 + case AXP15060_DCDC6:
309 + return !!(reg & AXP15060_DCDC46_POLYPHASE_DUAL_MASK);
310 + }
311 + break;
312 +
313 default:
314 return false;
315 }
316 @@ -1217,6 +1460,7 @@ static int axp20x_regulator_probe(struct
317 u32 workmode;
318 const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
319 const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
320 + const char *aldo1_name = axp15060_regulators[AXP15060_ALDO1].name;
321 bool drivevbus = false;
322
323 switch (axp20x->variant) {
324 @@ -1232,6 +1476,10 @@ static int axp20x_regulator_probe(struct
325 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
326 "x-powers,drive-vbus-en");
327 break;
328 + case AXP313A_ID:
329 + regulators = axp313a_regulators;
330 + nregulators = AXP313A_REG_ID_MAX;
331 + break;
332 case AXP803_ID:
333 regulators = axp803_regulators;
334 nregulators = AXP803_REG_ID_MAX;
335 @@ -1252,6 +1500,10 @@ static int axp20x_regulator_probe(struct
336 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
337 "x-powers,drive-vbus-en");
338 break;
339 + case AXP15060_ID:
340 + regulators = axp15060_regulators;
341 + nregulators = AXP15060_REG_ID_MAX;
342 + break;
343 default:
344 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
345 axp20x->variant);
346 @@ -1278,8 +1530,9 @@ static int axp20x_regulator_probe(struct
347 continue;
348
349 /*
350 - * Regulators DC1SW and DC5LDO are connected internally,
351 - * so we have to handle their supply names separately.
352 + * Regulators DC1SW, DC5LDO and RTCLDO on AXP15060 are
353 + * connected internally, so we have to handle their supply
354 + * names separately.
355 *
356 * We always register the regulators in proper sequence,
357 * so the supply names are correctly read. See the last
358 @@ -1288,7 +1541,8 @@ static int axp20x_regulator_probe(struct
359 */
360 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
361 (regulators == axp803_regulators && i == AXP803_DC1SW) ||
362 - (regulators == axp809_regulators && i == AXP809_DC1SW)) {
363 + (regulators == axp809_regulators && i == AXP809_DC1SW) ||
364 + (regulators == axp15060_regulators && i == AXP15060_SW)) {
365 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
366 GFP_KERNEL);
367 if (!new_desc)
368 @@ -1300,7 +1554,8 @@ static int axp20x_regulator_probe(struct
369 }
370
371 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
372 - (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
373 + (regulators == axp809_regulators && i == AXP809_DC5LDO) ||
374 + (regulators == axp15060_regulators && i == AXP15060_CPUSLDO)) {
375 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
376 GFP_KERNEL);
377 if (!new_desc)
378 @@ -1311,6 +1566,18 @@ static int axp20x_regulator_probe(struct
379 desc = new_desc;
380 }
381
382 +
383 + if (regulators == axp15060_regulators && i == AXP15060_RTC_LDO) {
384 + new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
385 + GFP_KERNEL);
386 + if (!new_desc)
387 + return -ENOMEM;
388 +
389 + *new_desc = regulators[i];
390 + new_desc->supply_name = aldo1_name;
391 + desc = new_desc;
392 + }
393 +
394 rdev = devm_regulator_register(&pdev->dev, desc, &config);
395 if (IS_ERR(rdev)) {
396 dev_err(&pdev->dev, "Failed to register %s\n",
397 @@ -1329,19 +1596,26 @@ static int axp20x_regulator_probe(struct
398 }
399
400 /*
401 - * Save AXP22X DCDC1 / DCDC5 regulator names for later.
402 + * Save AXP22X DCDC1 / DCDC5 / AXP15060 ALDO1 regulator names for later.
403 */
404 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
405 - (regulators == axp809_regulators && i == AXP809_DCDC1))
406 + (regulators == axp809_regulators && i == AXP809_DCDC1) ||
407 + (regulators == axp15060_regulators && i == AXP15060_DCDC1))
408 of_property_read_string(rdev->dev.of_node,
409 "regulator-name",
410 &dcdc1_name);
411
412 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
413 - (regulators == axp809_regulators && i == AXP809_DCDC5))
414 + (regulators == axp809_regulators && i == AXP809_DCDC5) ||
415 + (regulators == axp15060_regulators && i == AXP15060_DCDC5))
416 of_property_read_string(rdev->dev.of_node,
417 "regulator-name",
418 &dcdc5_name);
419 +
420 + if (regulators == axp15060_regulators && i == AXP15060_ALDO1)
421 + of_property_read_string(rdev->dev.of_node,
422 + "regulator-name",
423 + &aldo1_name);
424 }
425
426 if (drivevbus) {
427 @@ -1364,6 +1638,7 @@ static struct platform_driver axp20x_reg
428 .probe = axp20x_regulator_probe,
429 .driver = {
430 .name = "axp20x-regulator",
431 + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
432 },
433 };
434