target/linux/starfive/patches-6.1/0075-phy-starfive-Add-mipi-dphy-rx-support.patch

   1 From f6fbb431f9e3ac5c9144edf05340db9a96dffa59 Mon Sep 17 00:00:00 2001
   2 From: Changhuang Liang <changhuang.liang@starfivetech.com>
   3 Date: Mon, 29 May 2023 05:15:02 -0700
   4 Subject: [PATCH 075/122] phy: starfive: Add mipi dphy rx support
   5
   6 Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to
   7 transfer CSI camera data.
   8
   9 Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
  10 ---
  11  drivers/phy/Kconfig                         |   1 +
  12  drivers/phy/Makefile                        |   1 +
  13  drivers/phy/starfive/Kconfig                |  13 +
  14  drivers/phy/starfive/Makefile               |   2 +
  15  drivers/phy/starfive/phy-starfive-dphy-rx.c | 301 ++++++++++++++++++++
  16  5 files changed, 318 insertions(+)
  17  create mode 100644 drivers/phy/starfive/Kconfig
  18  create mode 100644 drivers/phy/starfive/Makefile
  19  create mode 100644 drivers/phy/starfive/phy-starfive-dphy-rx.c
  20
  21 --- a/drivers/phy/Kconfig
  22 +++ b/drivers/phy/Kconfig
  23 @@ -91,6 +91,7 @@ source "drivers/phy/rockchip/Kconfig"
  24  source "drivers/phy/samsung/Kconfig"
  25  source "drivers/phy/socionext/Kconfig"
  26  source "drivers/phy/st/Kconfig"
  27 +source "drivers/phy/starfive/Kconfig"
  28  source "drivers/phy/sunplus/Kconfig"
  29  source "drivers/phy/tegra/Kconfig"
  30  source "drivers/phy/ti/Kconfig"
  31 --- a/drivers/phy/Makefile
  32 +++ b/drivers/phy/Makefile
  33 @@ -31,6 +31,7 @@ obj-y                                 += allwinner/   \
  34                                            samsung/     \
  35                                            socionext/   \
  36                                            st/          \
  37 +                                          starfive/    \
  38                                            sunplus/     \
  39                                            tegra/       \
  40                                            ti/          \
  41 --- /dev/null
  42 +++ b/drivers/phy/starfive/Kconfig
  43 @@ -0,0 +1,13 @@
  44 +# SPDX-License-Identifier: GPL-2.0-only
  45 +#
  46 +# Phy drivers for StarFive platforms
  47 +#
  48 +
  49 +config PHY_STARFIVE_DPHY_RX
  50 +       tristate "StarFive D-PHY RX Support"
  51 +       select GENERIC_PHY
  52 +       select GENERIC_PHY_MIPI_DPHY
  53 +       help
  54 +         Choose this option if you have a StarFive D-PHY in your
  55 +         system. If M is selected, the module will be called
  56 +         phy-starfive-dphy-rx.
  57 --- /dev/null
  58 +++ b/drivers/phy/starfive/Makefile
  59 @@ -0,0 +1,2 @@
  60 +# SPDX-License-Identifier: GPL-2.0
  61 +obj-$(CONFIG_PHY_STARFIVE_DPHY_RX)      += phy-starfive-dphy-rx.o
  62 --- /dev/null
  63 +++ b/drivers/phy/starfive/phy-starfive-dphy-rx.c
  64 @@ -0,0 +1,301 @@
  65 +// SPDX-License-Identifier: GPL-2.0+
  66 +/*
  67 + * DPHY driver for the StarFive JH7110 SoC
  68 + *
  69 + * Copyright (C) 2023 StarFive Technology Co., Ltd.
  70 + */
  71 +
  72 +#include <linux/bitfield.h>
  73 +#include <linux/bitops.h>
  74 +#include <linux/clk.h>
  75 +#include <linux/io.h>
  76 +#include <linux/module.h>
  77 +#include <linux/of.h>
  78 +#include <linux/of_device.h>
  79 +#include <linux/phy/phy.h>
  80 +#include <linux/platform_device.h>
  81 +#include <linux/pm_runtime.h>
  82 +#include <linux/reset.h>
  83 +
  84 +#define STF_DPHY_APBCFGSAIF_SYSCFG(x)          (x)
  85 +
  86 +#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN BIT(6)
  87 +#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN GENMASK(12, 7)
  88 +#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN BIT(19)
  89 +#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN GENMASK(25, 20)
  90 +
  91 +#define STF_DPHY_DATA_BUS16_8                  BIT(8)
  92 +#define STF_DPHY_DEBUG_MODE_SEL                        GENMASK(15, 9)
  93 +
  94 +#define STF_DPHY_ENABLE_CLK                    BIT(6)
  95 +#define STF_DPHY_ENABLE_CLK1                   BIT(7)
  96 +#define STF_DPHY_ENABLE_LAN0                   BIT(8)
  97 +#define STF_DPHY_ENABLE_LAN1                   BIT(9)
  98 +#define STF_DPHY_ENABLE_LAN2                   BIT(10)
  99 +#define STF_DPHY_ENABLE_LAN3                   BIT(11)
 100 +#define STF_DPHY_GPI_EN                                GENMASK(17, 12)
 101 +#define STF_DPHY_HS_FREQ_CHANGE_CLK            BIT(18)
 102 +#define STF_DPHY_HS_FREQ_CHANGE_CLK1           BIT(19)
 103 +#define STF_DPHY_LANE_SWAP_CLK                 GENMASK(22, 20)
 104 +#define STF_DPHY_LANE_SWAP_CLK1                        GENMASK(25, 23)
 105 +#define STF_DPHY_LANE_SWAP_LAN0                        GENMASK(28, 26)
 106 +#define STF_DPHY_LANE_SWAP_LAN1                        GENMASK(31, 29)
 107 +
 108 +#define STF_DPHY_LANE_SWAP_LAN2                        GENMASK(2, 0)
 109 +#define STF_DPHY_LANE_SWAP_LAN3                        GENMASK(5, 3)
 110 +#define STF_DPHY_MP_TEST_EN                    BIT(6)
 111 +#define STF_DPHY_MP_TEST_MODE_SEL              GENMASK(11, 7)
 112 +#define STF_DPHY_PLL_CLK_SEL                   GENMASK(21, 12)
 113 +#define STF_DPHY_PRECOUNTER_IN_CLK             GENMASK(29, 22)
 114 +
 115 +#define STF_DPHY_PRECOUNTER_IN_CLK1            GENMASK(7, 0)
 116 +#define STF_DPHY_PRECOUNTER_IN_LAN0            GENMASK(15, 8)
 117 +#define STF_DPHY_PRECOUNTER_IN_LAN1            GENMASK(23, 16)
 118 +#define STF_DPHY_PRECOUNTER_IN_LAN2            GENMASK(31, 24)
 119 +
 120 +#define STF_DPHY_PRECOUNTER_IN_LAN3            GENMASK(7, 0)
 121 +#define STF_DPHY_RX_1C2C_SEL                   BIT(8)
 122 +
 123 +#define STF_MAP_LANES_NUM                      6
 124 +
 125 +struct regval {
 126 +       u32 addr;
 127 +       u32 val;
 128 +};
 129 +
 130 +struct stf_dphy_info {
 131 +       /**
 132 +        * @maps:
 133 +        *
 134 +        * Physical lanes and logic lanes mapping table.
 135 +        *
 136 +        * The default order is:
 137 +        * [clk lane0, data lane 0, data lane 1, data lane 2, date lane 3, clk lane 1]
 138 +        */
 139 +       u8 maps[STF_MAP_LANES_NUM];
 140 +};
 141 +
 142 +struct stf_dphy {
 143 +       struct device *dev;
 144 +       void __iomem *regs;
 145 +       struct clk *cfg_clk;
 146 +       struct clk *ref_clk;
 147 +       struct clk *tx_clk;
 148 +       struct reset_control *rstc;
 149 +       struct regulator *mipi_0p9;
 150 +       struct phy *phy;
 151 +       const struct stf_dphy_info *info;
 152 +};
 153 +
 154 +static const struct regval stf_dphy_init_list[] = {
 155 +       { STF_DPHY_APBCFGSAIF_SYSCFG(4), 0x00000000 },
 156 +       { STF_DPHY_APBCFGSAIF_SYSCFG(8), 0x00000000 },
 157 +       { STF_DPHY_APBCFGSAIF_SYSCFG(12), 0x0000fff0 },
 158 +       { STF_DPHY_APBCFGSAIF_SYSCFG(16), 0x00000000 },
 159 +       { STF_DPHY_APBCFGSAIF_SYSCFG(20), 0x00000000 },
 160 +       { STF_DPHY_APBCFGSAIF_SYSCFG(24), 0x00000000 },
 161 +       { STF_DPHY_APBCFGSAIF_SYSCFG(28), 0x00000000 },
 162 +       { STF_DPHY_APBCFGSAIF_SYSCFG(32), 0x00000000 },
 163 +       { STF_DPHY_APBCFGSAIF_SYSCFG(36), 0x00000000 },
 164 +       { STF_DPHY_APBCFGSAIF_SYSCFG(40), 0x00000000 },
 165 +       { STF_DPHY_APBCFGSAIF_SYSCFG(40), 0x00000000 },
 166 +       { STF_DPHY_APBCFGSAIF_SYSCFG(48), 0x24000000 },
 167 +       { STF_DPHY_APBCFGSAIF_SYSCFG(52), 0x00000000 },
 168 +       { STF_DPHY_APBCFGSAIF_SYSCFG(56), 0x00000000 },
 169 +       { STF_DPHY_APBCFGSAIF_SYSCFG(60), 0x00000000 },
 170 +       { STF_DPHY_APBCFGSAIF_SYSCFG(64), 0x00000000 },
 171 +       { STF_DPHY_APBCFGSAIF_SYSCFG(68), 0x00000000 },
 172 +       { STF_DPHY_APBCFGSAIF_SYSCFG(72), 0x00000000 },
 173 +       { STF_DPHY_APBCFGSAIF_SYSCFG(76), 0x00000000 },
 174 +       { STF_DPHY_APBCFGSAIF_SYSCFG(80), 0x00000000 },
 175 +       { STF_DPHY_APBCFGSAIF_SYSCFG(84), 0x00000000 },
 176 +       { STF_DPHY_APBCFGSAIF_SYSCFG(88), 0x00000000 },
 177 +       { STF_DPHY_APBCFGSAIF_SYSCFG(92), 0x00000000 },
 178 +       { STF_DPHY_APBCFGSAIF_SYSCFG(96), 0x00000000 },
 179 +       { STF_DPHY_APBCFGSAIF_SYSCFG(100), 0x02000000 },
 180 +       { STF_DPHY_APBCFGSAIF_SYSCFG(104), 0x00000000 },
 181 +       { STF_DPHY_APBCFGSAIF_SYSCFG(108), 0x00000000 },
 182 +       { STF_DPHY_APBCFGSAIF_SYSCFG(112), 0x00000000 },
 183 +       { STF_DPHY_APBCFGSAIF_SYSCFG(116), 0x00000000 },
 184 +       { STF_DPHY_APBCFGSAIF_SYSCFG(120), 0x00000000 },
 185 +       { STF_DPHY_APBCFGSAIF_SYSCFG(124), 0x0000000c },
 186 +       { STF_DPHY_APBCFGSAIF_SYSCFG(128), 0x00000000 },
 187 +       { STF_DPHY_APBCFGSAIF_SYSCFG(132), 0xcc500000 },
 188 +       { STF_DPHY_APBCFGSAIF_SYSCFG(136), 0x000000cc },
 189 +       { STF_DPHY_APBCFGSAIF_SYSCFG(140), 0x00000000 },
 190 +       { STF_DPHY_APBCFGSAIF_SYSCFG(144), 0x00000000 },
 191 +};
 192 +
 193 +static int stf_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
 194 +{
 195 +       struct stf_dphy *dphy = phy_get_drvdata(phy);
 196 +       const struct stf_dphy_info *info = dphy->info;
 197 +       int i;
 198 +
 199 +       for (i = 0; i < ARRAY_SIZE(stf_dphy_init_list); i++)
 200 +               writel(stf_dphy_init_list[i].val,
 201 +                      dphy->regs + stf_dphy_init_list[i].addr);
 202 +
 203 +       writel(FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN, 1) |
 204 +              FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN, 0x1b) |
 205 +              FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN, 1) |
 206 +              FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN, 0x1b),
 207 +              dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(0));
 208 +
 209 +       writel(FIELD_PREP(STF_DPHY_DATA_BUS16_8, 0) |
 210 +              FIELD_PREP(STF_DPHY_DEBUG_MODE_SEL, 0x5a),
 211 +              dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(184));
 212 +
 213 +       writel(FIELD_PREP(STF_DPHY_ENABLE_CLK, 1) |
 214 +              FIELD_PREP(STF_DPHY_ENABLE_CLK1, 1) |
 215 +              FIELD_PREP(STF_DPHY_ENABLE_LAN0, 1) |
 216 +              FIELD_PREP(STF_DPHY_ENABLE_LAN1, 1) |
 217 +              FIELD_PREP(STF_DPHY_ENABLE_LAN2, 1) |
 218 +              FIELD_PREP(STF_DPHY_ENABLE_LAN3, 1) |
 219 +              FIELD_PREP(STF_DPHY_GPI_EN, 0) |
 220 +              FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK, 0) |
 221 +              FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK1, 0) |
 222 +              FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) |
 223 +              FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) |
 224 +              FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) |
 225 +              FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]),
 226 +              dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188));
 227 +
 228 +       writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) |
 229 +              FIELD_PREP(STF_DPHY_LANE_SWAP_LAN3, info->maps[4]) |
 230 +              FIELD_PREP(STF_DPHY_MP_TEST_EN, 0) |
 231 +              FIELD_PREP(STF_DPHY_MP_TEST_MODE_SEL, 0) |
 232 +              FIELD_PREP(STF_DPHY_PLL_CLK_SEL, 0x37c) |
 233 +              FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK, 8),
 234 +              dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(192));
 235 +
 236 +       writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK1, 8) |
 237 +              FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN0, 7) |
 238 +              FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN1, 7) |
 239 +              FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN2, 7),
 240 +              dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(196));
 241 +
 242 +       writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN3, 7) |
 243 +              FIELD_PREP(STF_DPHY_RX_1C2C_SEL, 0),
 244 +              dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(200));
 245 +
 246 +       return 0;
 247 +}
 248 +
 249 +static int stf_dphy_power_on(struct phy *phy)
 250 +{
 251 +       struct stf_dphy *dphy = phy_get_drvdata(phy);
 252 +       int ret;
 253 +
 254 +       pm_runtime_get_sync(dphy->dev);
 255 +
 256 +       ret = regulator_enable(dphy->mipi_0p9);
 257 +       if (ret)
 258 +               return ret;
 259 +
 260 +       clk_set_rate(dphy->cfg_clk, 99000000);
 261 +       clk_set_rate(dphy->ref_clk, 49500000);
 262 +       clk_set_rate(dphy->tx_clk, 19800000);
 263 +       reset_control_deassert(dphy->rstc);
 264 +
 265 +       return 0;
 266 +}
 267 +
 268 +static int stf_dphy_power_off(struct phy *phy)
 269 +{
 270 +       struct stf_dphy *dphy = phy_get_drvdata(phy);
 271 +
 272 +       reset_control_assert(dphy->rstc);
 273 +
 274 +       regulator_disable(dphy->mipi_0p9);
 275 +
 276 +       pm_runtime_put_sync(dphy->dev);
 277 +
 278 +       return 0;
 279 +}
 280 +
 281 +static const struct phy_ops stf_dphy_ops = {
 282 +       .configure = stf_dphy_configure,
 283 +       .power_on  = stf_dphy_power_on,
 284 +       .power_off = stf_dphy_power_off,
 285 +};
 286 +
 287 +static int stf_dphy_probe(struct platform_device *pdev)
 288 +{
 289 +       struct phy_provider *phy_provider;
 290 +       struct stf_dphy *dphy;
 291 +
 292 +       dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
 293 +       if (!dphy)
 294 +               return -ENOMEM;
 295 +
 296 +       dphy->info = of_device_get_match_data(&pdev->dev);
 297 +
 298 +       dev_set_drvdata(&pdev->dev, dphy);
 299 +       dphy->dev = &pdev->dev;
 300 +
 301 +       dphy->regs = devm_platform_ioremap_resource(pdev, 0);
 302 +       if (IS_ERR(dphy->regs))
 303 +               return PTR_ERR(dphy->regs);
 304 +
 305 +       dphy->cfg_clk = devm_clk_get(&pdev->dev, "cfg");
 306 +       if (IS_ERR(dphy->cfg_clk))
 307 +               return PTR_ERR(dphy->cfg_clk);
 308 +
 309 +       dphy->ref_clk = devm_clk_get(&pdev->dev, "ref");
 310 +       if (IS_ERR(dphy->ref_clk))
 311 +               return PTR_ERR(dphy->ref_clk);
 312 +
 313 +       dphy->tx_clk = devm_clk_get(&pdev->dev, "tx");
 314 +       if (IS_ERR(dphy->tx_clk))
 315 +               return PTR_ERR(dphy->tx_clk);
 316 +
 317 +       dphy->rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
 318 +       if (IS_ERR(dphy->rstc))
 319 +               return PTR_ERR(dphy->rstc);
 320 +
 321 +       dphy->mipi_0p9 = devm_regulator_get(&pdev->dev, "mipi_0p9");
 322 +       if (IS_ERR(dphy->mipi_0p9))
 323 +               return PTR_ERR(dphy->mipi_0p9);
 324 +
 325 +       dphy->phy = devm_phy_create(&pdev->dev, NULL, &stf_dphy_ops);
 326 +       if (IS_ERR(dphy->phy)) {
 327 +               dev_err(&pdev->dev, "Failed to create PHY\n");
 328 +               return PTR_ERR(dphy->phy);
 329 +       }
 330 +
 331 +       pm_runtime_enable(&pdev->dev);
 332 +
 333 +       phy_set_drvdata(dphy->phy, dphy);
 334 +       phy_provider = devm_of_phy_provider_register(&pdev->dev,
 335 +                                                    of_phy_simple_xlate);
 336 +
 337 +       return PTR_ERR_OR_ZERO(phy_provider);
 338 +}
 339 +
 340 +static const struct stf_dphy_info starfive_dphy_info = {
 341 +       .maps = {4, 0, 1, 2, 3, 5},
 342 +};
 343 +
 344 +static const struct of_device_id stf_dphy_dt_ids[] = {
 345 +       {
 346 +               .compatible = "starfive,jh7110-dphy-rx",
 347 +               .data = &starfive_dphy_info,
 348 +       },
 349 +       { /* sentinel */ },
 350 +};
 351 +MODULE_DEVICE_TABLE(of, stf_dphy_dt_ids);
 352 +
 353 +static struct platform_driver stf_dphy_driver = {
 354 +       .probe = stf_dphy_probe,
 355 +       .driver = {
 356 +               .name   = "starfive-dphy-rx",
 357 +               .of_match_table = stf_dphy_dt_ids,
 358 +       },
 359 +};
 360 +module_platform_driver(stf_dphy_driver);
 361 +
 362 +MODULE_AUTHOR("Jack Zhu <jack.zhu@starfivetech.com>");
 363 +MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
 364 +MODULE_DESCRIPTION("StarFive DPHY RX driver");
 365 +MODULE_LICENSE("GPL");