target/linux/starfive/patches-6.1/0051-dt-bindings-clock-Add-StarFive-JH7110-System-Top-Gro.patch

   1 From 84575863e4cf1a5dd877a11d31115c19004ac36a Mon Sep 17 00:00:00 2001
   2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
   3 Date: Thu, 18 May 2023 18:12:24 +0800
   4 Subject: [PATCH 051/122] dt-bindings: clock: Add StarFive JH7110
   5  System-Top-Group clock and reset generator
   6
   7 Add bindings for the System-Top-Group clock and reset generator (STGCRG)
   8 on the JH7110 RISC-V SoC by StarFive Ltd.
   9
  10 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  11 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  12 ---
  13  .../clock/starfive,jh7110-stgcrg.yaml         | 82 +++++++++++++++++++
  14  .../dt-bindings/clock/starfive,jh7110-crg.h   | 34 ++++++++
  15  .../dt-bindings/reset/starfive,jh7110-crg.h   | 28 +++++++
  16  3 files changed, 144 insertions(+)
  17  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
  18
  19 --- /dev/null
  20 +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
  21 @@ -0,0 +1,82 @@
  22 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  23 +%YAML 1.2
  24 +---
  25 +$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
  26 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  27 +
  28 +title: StarFive JH7110 System-Top-Group Clock and Reset Generator
  29 +
  30 +maintainers:
  31 +  - Xingyu Wu <xingyu.wu@starfivetech.com>
  32 +
  33 +properties:
  34 +  compatible:
  35 +    const: starfive,jh7110-stgcrg
  36 +
  37 +  reg:
  38 +    maxItems: 1
  39 +
  40 +  clocks:
  41 +    items:
  42 +      - description: Main Oscillator (24 MHz)
  43 +      - description: HIFI4 core
  44 +      - description: STG AXI/AHB
  45 +      - description: USB (125 MHz)
  46 +      - description: CPU Bus
  47 +      - description: HIFI4 Axi
  48 +      - description: NOC STG Bus
  49 +      - description: APB Bus
  50 +
  51 +  clock-names:
  52 +    items:
  53 +      - const: osc
  54 +      - const: hifi4_core
  55 +      - const: stg_axiahb
  56 +      - const: usb_125m
  57 +      - const: cpu_bus
  58 +      - const: hifi4_axi
  59 +      - const: nocstg_bus
  60 +      - const: apb_bus
  61 +
  62 +  '#clock-cells':
  63 +    const: 1
  64 +    description:
  65 +      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
  66 +
  67 +  '#reset-cells':
  68 +    const: 1
  69 +    description:
  70 +      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
  71 +
  72 +required:
  73 +  - compatible
  74 +  - reg
  75 +  - clocks
  76 +  - clock-names
  77 +  - '#clock-cells'
  78 +  - '#reset-cells'
  79 +
  80 +additionalProperties: false
  81 +
  82 +examples:
  83 +  - |
  84 +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
  85 +
  86 +    stgcrg: clock-controller@10230000 {
  87 +        compatible = "starfive,jh7110-stgcrg";
  88 +        reg = <0x10230000 0x10000>;
  89 +        clocks = <&osc>,
  90 +                 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
  91 +                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
  92 +                 <&syscrg JH7110_SYSCLK_USB_125M>,
  93 +                 <&syscrg JH7110_SYSCLK_CPU_BUS>,
  94 +                 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
  95 +                 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
  96 +                 <&syscrg JH7110_SYSCLK_APB_BUS>;
  97 +        clock-names = "osc", "hifi4_core",
  98 +                      "stg_axiahb", "usb_125m",
  99 +                      "cpu_bus", "hifi4_axi",
 100 +                      "nocstg_bus", "apb_bus";
 101 +        #clock-cells = <1>;
 102 +        #reset-cells = <1>;
 103 +    };
 104 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
 105 +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
 106 @@ -1,6 +1,7 @@
 107  /* SPDX-License-Identifier: GPL-2.0 OR MIT */
 108  /*
 109   * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
 110 + * Copyright 2022 StarFive Technology Co., Ltd.
 111   */
 112
 113  #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
 114 @@ -224,4 +225,37 @@
 115
 116  #define JH7110_AONCLK_END                      14
 117
 118 +/* STGCRG clocks */
 119 +#define JH7110_STGCLK_HIFI4_CLK_CORE           0
 120 +#define JH7110_STGCLK_USB0_APB                 1
 121 +#define JH7110_STGCLK_USB0_UTMI_APB            2
 122 +#define JH7110_STGCLK_USB0_AXI                 3
 123 +#define JH7110_STGCLK_USB0_LPM                 4
 124 +#define JH7110_STGCLK_USB0_STB                 5
 125 +#define JH7110_STGCLK_USB0_APP_125             6
 126 +#define JH7110_STGCLK_USB0_REFCLK              7
 127 +#define JH7110_STGCLK_PCIE0_AXI_MST0           8
 128 +#define JH7110_STGCLK_PCIE0_APB                        9
 129 +#define JH7110_STGCLK_PCIE0_TL                 10
 130 +#define JH7110_STGCLK_PCIE1_AXI_MST0           11
 131 +#define JH7110_STGCLK_PCIE1_APB                        12
 132 +#define JH7110_STGCLK_PCIE1_TL                 13
 133 +#define JH7110_STGCLK_PCIE_SLV_MAIN            14
 134 +#define JH7110_STGCLK_SEC_AHB                  15
 135 +#define JH7110_STGCLK_SEC_MISC_AHB             16
 136 +#define JH7110_STGCLK_GRP0_MAIN                        17
 137 +#define JH7110_STGCLK_GRP0_BUS                 18
 138 +#define JH7110_STGCLK_GRP0_STG                 19
 139 +#define JH7110_STGCLK_GRP1_MAIN                        20
 140 +#define JH7110_STGCLK_GRP1_BUS                 21
 141 +#define JH7110_STGCLK_GRP1_STG                 22
 142 +#define JH7110_STGCLK_GRP1_HIFI                        23
 143 +#define JH7110_STGCLK_E2_RTC                   24
 144 +#define JH7110_STGCLK_E2_CORE                  25
 145 +#define JH7110_STGCLK_E2_DBG                   26
 146 +#define JH7110_STGCLK_DMA1P_AXI                        27
 147 +#define JH7110_STGCLK_DMA1P_AHB                        28
 148 +
 149 +#define JH7110_STGCLK_END                      29
 150 +
 151  #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
 152 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
 153 +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
 154 @@ -1,6 +1,7 @@
 155  /* SPDX-License-Identifier: GPL-2.0 OR MIT */
 156  /*
 157   * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
 158 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
 159   */
 160
 161  #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
 162 @@ -151,4 +152,31 @@
 163
 164  #define JH7110_AONRST_END                      8
 165
 166 +/* STGCRG resets */
 167 +#define JH7110_STGRST_SYSCON                   0
 168 +#define JH7110_STGRST_HIFI4_CORE               1
 169 +#define JH7110_STGRST_HIFI4_AXI                        2
 170 +#define JH7110_STGRST_SEC_AHB                  3
 171 +#define JH7110_STGRST_E24_CORE                 4
 172 +#define JH7110_STGRST_DMA1P_AXI                        5
 173 +#define JH7110_STGRST_DMA1P_AHB                        6
 174 +#define JH7110_STGRST_USB0_AXI                 7
 175 +#define JH7110_STGRST_USB0_APB                 8
 176 +#define JH7110_STGRST_USB0_UTMI_APB            9
 177 +#define JH7110_STGRST_USB0_PWRUP               10
 178 +#define JH7110_STGRST_PCIE0_AXI_MST0           11
 179 +#define JH7110_STGRST_PCIE0_AXI_SLV0           12
 180 +#define JH7110_STGRST_PCIE0_AXI_SLV            13
 181 +#define JH7110_STGRST_PCIE0_BRG                        14
 182 +#define JH7110_STGRST_PCIE0_CORE               15
 183 +#define JH7110_STGRST_PCIE0_APB                        16
 184 +#define JH7110_STGRST_PCIE1_AXI_MST0           17
 185 +#define JH7110_STGRST_PCIE1_AXI_SLV0           18
 186 +#define JH7110_STGRST_PCIE1_AXI_SLV            19
 187 +#define JH7110_STGRST_PCIE1_BRG                        20
 188 +#define JH7110_STGRST_PCIE1_CORE               21
 189 +#define JH7110_STGRST_PCIE1_APB                        22
 190 +
 191 +#define JH7110_STGRST_END                      23
 192 +
 193  #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */