target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6368-enetsw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * BCM6368 Ethernet Switch Controller Driver
   4  *
   5  * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
   6  * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
   7  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/if_vlan.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/of_clk.h>
  18 #include <linux/of_net.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/reset.h>
  23
  24 /* MTU */
  25 #define ENETSW_TAG_SIZE                 6
  26 #define ENETSW_MTU_OVERHEAD             (VLAN_ETH_HLEN + VLAN_HLEN + \
  27                                          ENETSW_TAG_SIZE)
  28 #define ENETSW_FRAG_SIZE(x)             (SKB_DATA_ALIGN(NET_SKB_PAD + x + \
  29                                          SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
  30
  31 /* default number of descriptor */
  32 #define ENETSW_DEF_RX_DESC              64
  33 #define ENETSW_DEF_TX_DESC              32
  34 #define ENETSW_DEF_CPY_BREAK            128
  35
  36 /* maximum burst len for dma (4 bytes unit) */
  37 #define ENETSW_DMA_MAXBURST             8
  38
  39 /* DMA channels */
  40 #define DMA_CHAN_WIDTH                  0x10
  41
  42 /* Controller Configuration Register */
  43 #define DMA_CFG_REG                     0x0
  44 #define DMA_CFG_EN_SHIFT                0
  45 #define DMA_CFG_EN_MASK                 (1 << DMA_CFG_EN_SHIFT)
  46 #define DMA_CFG_FLOWCH_MASK(x)          (1 << ((x >> 1) + 1))
  47
  48 /* Flow Control Descriptor Low Threshold register */
  49 #define DMA_FLOWCL_REG(x)               (0x4 + (x) * 6)
  50
  51 /* Flow Control Descriptor High Threshold register */
  52 #define DMA_FLOWCH_REG(x)               (0x8 + (x) * 6)
  53
  54 /* Flow Control Descriptor Buffer Alloca Threshold register */
  55 #define DMA_BUFALLOC_REG(x)             (0xc + (x) * 6)
  56 #define DMA_BUFALLOC_FORCE_SHIFT        31
  57 #define DMA_BUFALLOC_FORCE_MASK         (1 << DMA_BUFALLOC_FORCE_SHIFT)
  58
  59 /* Channel Configuration register */
  60 #define DMAC_CHANCFG_REG                0x0
  61 #define DMAC_CHANCFG_EN_SHIFT           0
  62 #define DMAC_CHANCFG_EN_MASK            (1 << DMAC_CHANCFG_EN_SHIFT)
  63 #define DMAC_CHANCFG_PKTHALT_SHIFT      1
  64 #define DMAC_CHANCFG_PKTHALT_MASK       (1 << DMAC_CHANCFG_PKTHALT_SHIFT)
  65 #define DMAC_CHANCFG_BUFHALT_SHIFT      2
  66 #define DMAC_CHANCFG_BUFHALT_MASK       (1 << DMAC_CHANCFG_BUFHALT_SHIFT)
  67 #define DMAC_CHANCFG_CHAINING_SHIFT     2
  68 #define DMAC_CHANCFG_CHAINING_MASK      (1 << DMAC_CHANCFG_CHAINING_SHIFT)
  69 #define DMAC_CHANCFG_WRAP_EN_SHIFT      3
  70 #define DMAC_CHANCFG_WRAP_EN_MASK       (1 << DMAC_CHANCFG_WRAP_EN_SHIFT)
  71 #define DMAC_CHANCFG_FLOWC_EN_SHIFT     4
  72 #define DMAC_CHANCFG_FLOWC_EN_MASK      (1 << DMAC_CHANCFG_FLOWC_EN_SHIFT)
  73
  74 /* Interrupt Control/Status register */
  75 #define DMAC_IR_REG                     0x4
  76 #define DMAC_IR_BUFDONE_MASK            (1 << 0)
  77 #define DMAC_IR_PKTDONE_MASK            (1 << 1)
  78 #define DMAC_IR_NOTOWNER_MASK           (1 << 2)
  79
  80 /* Interrupt Mask register */
  81 #define DMAC_IRMASK_REG                 0x8
  82
  83 /* Maximum Burst Length */
  84 #define DMAC_MAXBURST_REG               0xc
  85
  86 /* Ring Start Address register */
  87 #define DMAS_RSTART_REG                 0x0
  88
  89 /* State Ram Word 2 */
  90 #define DMAS_SRAM2_REG                  0x4
  91
  92 /* State Ram Word 3 */
  93 #define DMAS_SRAM3_REG                  0x8
  94
  95 /* State Ram Word 4 */
  96 #define DMAS_SRAM4_REG                  0xc
  97
  98 struct bcm6368_enetsw_desc {
  99         u32 len_stat;
 100         u32 address;
 101 };
 102
 103 /* control */
 104 #define DMADESC_LENGTH_SHIFT            16
 105 #define DMADESC_LENGTH_MASK             (0xfff << DMADESC_LENGTH_SHIFT)
 106 #define DMADESC_OWNER_MASK              (1 << 15)
 107 #define DMADESC_EOP_MASK                (1 << 14)
 108 #define DMADESC_SOP_MASK                (1 << 13)
 109 #define DMADESC_ESOP_MASK               (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
 110 #define DMADESC_WRAP_MASK               (1 << 12)
 111 #define DMADESC_USB_NOZERO_MASK         (1 << 1)
 112 #define DMADESC_USB_ZERO_MASK           (1 << 0)
 113
 114 /* status */
 115 #define DMADESC_UNDER_MASK              (1 << 9)
 116 #define DMADESC_APPEND_CRC              (1 << 8)
 117 #define DMADESC_OVSIZE_MASK             (1 << 4)
 118 #define DMADESC_RXER_MASK               (1 << 2)
 119 #define DMADESC_CRC_MASK                (1 << 1)
 120 #define DMADESC_OV_MASK                 (1 << 0)
 121 #define DMADESC_ERR_MASK                (DMADESC_UNDER_MASK | \
 122                                          DMADESC_OVSIZE_MASK | \
 123                                          DMADESC_RXER_MASK | \
 124                                          DMADESC_CRC_MASK | \
 125                                          DMADESC_OV_MASK)
 126
 127 struct bcm6368_enetsw {
 128         void __iomem *dma_base;
 129         void __iomem *dma_chan;
 130         void __iomem *dma_sram;
 131
 132         struct device **pm;
 133         struct device_link **link_pm;
 134         int num_pms;
 135
 136         struct clk **clock;
 137         unsigned int num_clocks;
 138
 139         struct reset_control **reset;
 140         unsigned int num_resets;
 141
 142         int copybreak;
 143
 144         int irq_rx;
 145         int irq_tx;
 146
 147         /* hw view of rx & tx dma ring */
 148         dma_addr_t rx_desc_dma;
 149         dma_addr_t tx_desc_dma;
 150
 151         /* allocated size (in bytes) for rx & tx dma ring */
 152         unsigned int rx_desc_alloc_size;
 153         unsigned int tx_desc_alloc_size;
 154
 155         struct napi_struct napi;
 156
 157         /* dma channel id for rx */
 158         int rx_chan;
 159
 160         /* number of dma desc in rx ring */
 161         int rx_ring_size;
 162
 163         /* cpu view of rx dma ring */
 164         struct bcm6368_enetsw_desc *rx_desc_cpu;
 165
 166         /* current number of armed descriptor given to hardware for rx */
 167         int rx_desc_count;
 168
 169         /* next rx descriptor to fetch from hardware */
 170         int rx_curr_desc;
 171
 172         /* next dirty rx descriptor to refill */
 173         int rx_dirty_desc;
 174
 175         /* size of allocated rx buffer */
 176         unsigned int rx_buf_size;
 177
 178         /* size of allocated rx frag */
 179         unsigned int rx_frag_size;
 180
 181         /* list of buffer given to hw for rx */
 182         unsigned char **rx_buf;
 183
 184         /* used when rx buffer allocation failed, so we defer rx queue
 185          * refill */
 186         struct timer_list rx_timeout;
 187
 188         /* lock rx_timeout against rx normal operation */
 189         spinlock_t rx_lock;
 190
 191         /* dma channel id for tx */
 192         int tx_chan;
 193
 194         /* number of dma desc in tx ring */
 195         int tx_ring_size;
 196
 197         /* maximum dma burst size */
 198         int dma_maxburst;
 199
 200         /* cpu view of rx dma ring */
 201         struct bcm6368_enetsw_desc *tx_desc_cpu;
 202
 203         /* number of available descriptor for tx */
 204         int tx_desc_count;
 205
 206         /* next tx descriptor avaiable */
 207         int tx_curr_desc;
 208
 209         /* next dirty tx descriptor to reclaim */
 210         int tx_dirty_desc;
 211
 212         /* list of skb given to hw for tx */
 213         struct sk_buff **tx_skb;
 214
 215         /* lock used by tx reclaim and xmit */
 216         spinlock_t tx_lock;
 217
 218         /* network device reference */
 219         struct net_device *net_dev;
 220
 221         /* platform device reference */
 222         struct platform_device *pdev;
 223
 224         /* dma channel enable mask */
 225         u32 dma_chan_en_mask;
 226
 227         /* dma channel interrupt mask */
 228         u32 dma_chan_int_mask;
 229
 230         /* dma channel width */
 231         unsigned int dma_chan_width;
 232 };
 233
 234 static inline void dma_writel(struct bcm6368_enetsw *priv, u32 val, u32 off)
 235 {
 236         __raw_writel(val, priv->dma_base + off);
 237 }
 238
 239 static inline u32 dma_readl(struct bcm6368_enetsw *priv, u32 off, int chan)
 240 {
 241         return __raw_readl(priv->dma_chan + off + chan * priv->dma_chan_width);
 242 }
 243
 244 static inline void dmac_writel(struct bcm6368_enetsw *priv, u32 val,
 245                                     u32 off, int chan)
 246 {
 247         __raw_writel(val, priv->dma_chan + off + chan * priv->dma_chan_width);
 248 }
 249
 250 static inline void dmas_writel(struct bcm6368_enetsw *priv, u32 val,
 251                                     u32 off, int chan)
 252 {
 253         __raw_writel(val, priv->dma_sram + off + chan * priv->dma_chan_width);
 254 }
 255
 256 /*
 257  * refill rx queue
 258  */
 259 static int bcm6368_enetsw_refill_rx(struct net_device *dev, bool napi_mode)
 260 {
 261         struct bcm6368_enetsw *priv = netdev_priv(dev);
 262
 263         while (priv->rx_desc_count < priv->rx_ring_size) {
 264                 struct bcm6368_enetsw_desc *desc;
 265                 int desc_idx;
 266                 u32 len_stat;
 267
 268                 desc_idx = priv->rx_dirty_desc;
 269                 desc = &priv->rx_desc_cpu[desc_idx];
 270
 271                 if (!priv->rx_buf[desc_idx]) {
 272                         unsigned char *buf;
 273
 274                         if (likely(napi_mode))
 275                                 buf = napi_alloc_frag(priv->rx_frag_size);
 276                         else
 277                                 buf = netdev_alloc_frag(priv->rx_frag_size);
 278
 279                         if (unlikely(!buf))
 280                                 break;
 281
 282                         priv->rx_buf[desc_idx] = buf;
 283                         desc->address = dma_map_single(&priv->pdev->dev,
 284                                                        buf + NET_SKB_PAD,
 285                                                        priv->rx_buf_size,
 286                                                        DMA_FROM_DEVICE);
 287                 }
 288
 289                 len_stat = priv->rx_buf_size << DMADESC_LENGTH_SHIFT;
 290                 len_stat |= DMADESC_OWNER_MASK;
 291                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 292                         len_stat |= DMADESC_WRAP_MASK;
 293                         priv->rx_dirty_desc = 0;
 294                 } else {
 295                         priv->rx_dirty_desc++;
 296                 }
 297                 wmb();
 298                 desc->len_stat = len_stat;
 299
 300                 priv->rx_desc_count++;
 301
 302                 /* tell dma engine we allocated one buffer */
 303                 dma_writel(priv, 1, DMA_BUFALLOC_REG(priv->rx_chan));
 304         }
 305
 306         /* If rx ring is still empty, set a timer to try allocating
 307          * again at a later time. */
 308         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 309                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 310                 priv->rx_timeout.expires = jiffies + HZ;
 311                 add_timer(&priv->rx_timeout);
 312         }
 313
 314         return 0;
 315 }
 316
 317 /*
 318  * timer callback to defer refill rx queue in case we're OOM
 319  */
 320 static void bcm6368_enetsw_refill_rx_timer(struct timer_list *t)
 321 {
 322         struct bcm6368_enetsw *priv = from_timer(priv, t, rx_timeout);
 323         struct net_device *dev = priv->net_dev;
 324
 325         spin_lock(&priv->rx_lock);
 326         bcm6368_enetsw_refill_rx(dev, false);
 327         spin_unlock(&priv->rx_lock);
 328 }
 329
 330 /*
 331  * extract packet from rx queue
 332  */
 333 static int bcm6368_enetsw_receive_queue(struct net_device *dev, int budget)
 334 {
 335         struct bcm6368_enetsw *priv = netdev_priv(dev);
 336         struct device *kdev = &priv->pdev->dev;
 337         int processed = 0;
 338
 339         /* don't scan ring further than number of refilled
 340          * descriptor */
 341         if (budget > priv->rx_desc_count)
 342                 budget = priv->rx_desc_count;
 343
 344         do {
 345                 struct bcm6368_enetsw_desc *desc;
 346                 unsigned int frag_size;
 347                 struct sk_buff *skb;
 348                 unsigned char *buf;
 349                 int desc_idx;
 350                 u32 len_stat;
 351                 unsigned int len;
 352
 353                 desc_idx = priv->rx_curr_desc;
 354                 desc = &priv->rx_desc_cpu[desc_idx];
 355
 356                 /* make sure we actually read the descriptor status at
 357                  * each loop */
 358                 rmb();
 359
 360                 len_stat = desc->len_stat;
 361
 362                 /* break if dma ownership belongs to hw */
 363                 if (len_stat & DMADESC_OWNER_MASK)
 364                         break;
 365
 366                 processed++;
 367                 priv->rx_curr_desc++;
 368                 if (priv->rx_curr_desc == priv->rx_ring_size)
 369                         priv->rx_curr_desc = 0;
 370
 371                 /* if the packet does not have start of packet _and_
 372                  * end of packet flag set, then just recycle it */
 373                 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 374                         dev->stats.rx_dropped++;
 375                         continue;
 376                 }
 377
 378                 /* valid packet */
 379                 buf = priv->rx_buf[desc_idx];
 380                 len = (len_stat & DMADESC_LENGTH_MASK)
 381                       >> DMADESC_LENGTH_SHIFT;
 382                 /* don't include FCS */
 383                 len -= 4;
 384
 385                 if (len < priv->copybreak) {
 386                         unsigned int nfrag_size = ENETSW_FRAG_SIZE(len);
 387                         unsigned char *nbuf = napi_alloc_frag(nfrag_size);
 388
 389                         if (unlikely(!nbuf)) {
 390                                 /* forget packet, just rearm desc */
 391                                 dev->stats.rx_dropped++;
 392                                 continue;
 393                         }
 394
 395                         dma_sync_single_for_cpu(kdev, desc->address,
 396                                                 len, DMA_FROM_DEVICE);
 397                         memcpy(nbuf + NET_SKB_PAD, buf + NET_SKB_PAD, len);
 398                         dma_sync_single_for_device(kdev, desc->address,
 399                                                    len, DMA_FROM_DEVICE);
 400                         buf = nbuf;
 401                         frag_size = nfrag_size;
 402                 } else {
 403                         dma_unmap_single(kdev, desc->address,
 404                                          priv->rx_buf_size, DMA_FROM_DEVICE);
 405                         priv->rx_buf[desc_idx] = NULL;
 406                         frag_size = priv->rx_frag_size;
 407                 }
 408
 409                 skb = napi_build_skb(buf, frag_size);
 410                 if (unlikely(!skb)) {
 411                         skb_free_frag(buf);
 412                         dev->stats.rx_dropped++;
 413                         continue;
 414                 }
 415
 416                 skb_reserve(skb, NET_SKB_PAD);
 417                 skb_put(skb, len);
 418                 skb->protocol = eth_type_trans(skb, dev);
 419                 dev->stats.rx_packets++;
 420                 dev->stats.rx_bytes += len;
 421                 netif_receive_skb(skb);
 422         } while (processed < budget);
 423
 424         priv->rx_desc_count -= processed;
 425
 426         if (processed || !priv->rx_desc_count) {
 427                 bcm6368_enetsw_refill_rx(dev, true);
 428
 429                 /* kick rx dma */
 430                 dmac_writel(priv, priv->dma_chan_en_mask,
 431                             DMAC_CHANCFG_REG, priv->rx_chan);
 432         }
 433
 434         return processed;
 435 }
 436
 437 /*
 438  * try to or force reclaim of transmitted buffers
 439  */
 440 static int bcm6368_enetsw_tx_reclaim(struct net_device *dev, int force)
 441 {
 442         struct bcm6368_enetsw *priv = netdev_priv(dev);
 443         int released = 0;
 444
 445         while (priv->tx_desc_count < priv->tx_ring_size) {
 446                 struct bcm6368_enetsw_desc *desc;
 447                 struct sk_buff *skb;
 448
 449                 /* We run in a bh and fight against start_xmit, which
 450                  * is called with bh disabled */
 451                 spin_lock(&priv->tx_lock);
 452
 453                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 454
 455                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 456                         spin_unlock(&priv->tx_lock);
 457                         break;
 458                 }
 459
 460                 /* ensure other field of the descriptor were not read
 461                  * before we checked ownership */
 462                 rmb();
 463
 464                 skb = priv->tx_skb[priv->tx_dirty_desc];
 465                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 466                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 467                                  DMA_TO_DEVICE);
 468
 469                 priv->tx_dirty_desc++;
 470                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 471                         priv->tx_dirty_desc = 0;
 472                 priv->tx_desc_count++;
 473
 474                 spin_unlock(&priv->tx_lock);
 475
 476                 if (desc->len_stat & DMADESC_UNDER_MASK)
 477                         dev->stats.tx_errors++;
 478
 479                 napi_consume_skb(skb, !force);
 480                 released++;
 481         }
 482
 483         if (netif_queue_stopped(dev) && released)
 484                 netif_wake_queue(dev);
 485
 486         return released;
 487 }
 488
 489 /*
 490  * poll func, called by network core
 491  */
 492 static int bcm6368_enetsw_poll(struct napi_struct *napi, int budget)
 493 {
 494         struct bcm6368_enetsw *priv = container_of(napi, struct bcm6368_enetsw, napi);
 495         struct net_device *dev = priv->net_dev;
 496         int rx_work_done;
 497
 498         /* ack interrupts */
 499         dmac_writel(priv, priv->dma_chan_int_mask,
 500                          DMAC_IR_REG, priv->rx_chan);
 501         dmac_writel(priv, priv->dma_chan_int_mask,
 502                          DMAC_IR_REG, priv->tx_chan);
 503
 504         /* reclaim sent skb */
 505         bcm6368_enetsw_tx_reclaim(dev, 0);
 506
 507         spin_lock(&priv->rx_lock);
 508         rx_work_done = bcm6368_enetsw_receive_queue(dev, budget);
 509         spin_unlock(&priv->rx_lock);
 510
 511         if (rx_work_done >= budget) {
 512                 /* rx queue is not yet empty/clean */
 513                 return rx_work_done;
 514         }
 515
 516         /* no more packet in rx/tx queue, remove device from poll
 517          * queue */
 518         napi_complete_done(napi, rx_work_done);
 519
 520         /* restore rx/tx interrupt */
 521         dmac_writel(priv, priv->dma_chan_int_mask,
 522                          DMAC_IRMASK_REG, priv->rx_chan);
 523         dmac_writel(priv, priv->dma_chan_int_mask,
 524                          DMAC_IRMASK_REG, priv->tx_chan);
 525
 526         return rx_work_done;
 527 }
 528
 529 /*
 530  * rx/tx dma interrupt handler
 531  */
 532 static irqreturn_t bcm6368_enetsw_isr_dma(int irq, void *dev_id)
 533 {
 534         struct net_device *dev = dev_id;
 535         struct bcm6368_enetsw *priv = netdev_priv(dev);
 536
 537         /* mask rx/tx interrupts */
 538         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 539         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 540
 541         napi_schedule(&priv->napi);
 542
 543         return IRQ_HANDLED;
 544 }
 545
 546 /*
 547  * tx request callback
 548  */
 549 static netdev_tx_t
 550 bcm6368_enetsw_start_xmit(struct sk_buff *skb, struct net_device *dev)
 551 {
 552         struct bcm6368_enetsw *priv = netdev_priv(dev);
 553         struct bcm6368_enetsw_desc *desc;
 554         u32 len_stat;
 555         netdev_tx_t ret;
 556
 557         /* lock against tx reclaim */
 558         spin_lock(&priv->tx_lock);
 559
 560         /* make sure the tx hw queue is not full, should not happen
 561          * since we stop queue before it's the case */
 562         if (unlikely(!priv->tx_desc_count)) {
 563                 netif_stop_queue(dev);
 564                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 565                         "available?\n");
 566                 ret = NETDEV_TX_BUSY;
 567                 goto out_unlock;
 568         }
 569
 570         /* pad small packets */
 571         if (skb->len < (ETH_ZLEN + ETH_FCS_LEN)) {
 572                 int needed = (ETH_ZLEN + ETH_FCS_LEN) - skb->len;
 573                 char *data;
 574
 575                 if (unlikely(skb_tailroom(skb) < needed)) {
 576                         struct sk_buff *nskb;
 577
 578                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 579                         if (!nskb) {
 580                                 ret = NETDEV_TX_BUSY;
 581                                 goto out_unlock;
 582                         }
 583
 584                         dev_kfree_skb(skb);
 585                         skb = nskb;
 586                 }
 587                 data = skb_put_zero(skb, needed);
 588         }
 589
 590         /* point to the next available desc */
 591         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 592         priv->tx_skb[priv->tx_curr_desc] = skb;
 593
 594         /* fill descriptor */
 595         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 596                                        DMA_TO_DEVICE);
 597
 598         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 599         len_stat |= DMADESC_ESOP_MASK | DMADESC_APPEND_CRC |
 600                     DMADESC_OWNER_MASK;
 601
 602         priv->tx_curr_desc++;
 603         if (priv->tx_curr_desc == priv->tx_ring_size) {
 604                 priv->tx_curr_desc = 0;
 605                 len_stat |= DMADESC_WRAP_MASK;
 606         }
 607         priv->tx_desc_count--;
 608
 609         /* dma might be already polling, make sure we update desc
 610          * fields in correct order */
 611         wmb();
 612         desc->len_stat = len_stat;
 613         wmb();
 614
 615         /* kick tx dma */
 616         dmac_writel(priv, priv->dma_chan_en_mask, DMAC_CHANCFG_REG,
 617                     priv->tx_chan);
 618
 619         /* stop queue if no more desc available */
 620         if (!priv->tx_desc_count)
 621                 netif_stop_queue(dev);
 622
 623         dev->stats.tx_bytes += skb->len;
 624         dev->stats.tx_packets++;
 625         ret = NETDEV_TX_OK;
 626
 627 out_unlock:
 628         spin_unlock(&priv->tx_lock);
 629         return ret;
 630 }
 631
 632 /*
 633  * disable dma in given channel
 634  */
 635 static void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw *priv, int chan)
 636 {
 637         int limit = 1000;
 638
 639         dmac_writel(priv, 0, DMAC_CHANCFG_REG, chan);
 640
 641         do {
 642                 u32 val;
 643
 644                 val = dma_readl(priv, DMAC_CHANCFG_REG, chan);
 645                 if (!(val & DMAC_CHANCFG_EN_MASK))
 646                         break;
 647
 648                 udelay(1);
 649         } while (limit--);
 650 }
 651
 652 static int bcm6368_enetsw_open(struct net_device *dev)
 653 {
 654         struct bcm6368_enetsw *priv = netdev_priv(dev);
 655         struct device *kdev = &priv->pdev->dev;
 656         int i, ret;
 657         unsigned int size;
 658         void *p;
 659         u32 val;
 660
 661         /* mask all interrupts and request them */
 662         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 663         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 664
 665         ret = request_irq(priv->irq_rx, bcm6368_enetsw_isr_dma,
 666                           0, dev->name, dev);
 667         if (ret)
 668                 goto out_freeirq;
 669
 670         if (priv->irq_tx != -1) {
 671                 ret = request_irq(priv->irq_tx, bcm6368_enetsw_isr_dma,
 672                                   0, dev->name, dev);
 673                 if (ret)
 674                         goto out_freeirq_rx;
 675         }
 676
 677         /* allocate rx dma ring */
 678         size = priv->rx_ring_size * sizeof(struct bcm6368_enetsw_desc);
 679         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 680         if (!p) {
 681                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
 682                 ret = -ENOMEM;
 683                 goto out_freeirq_tx;
 684         }
 685
 686         memset(p, 0, size);
 687         priv->rx_desc_alloc_size = size;
 688         priv->rx_desc_cpu = p;
 689
 690         /* allocate tx dma ring */
 691         size = priv->tx_ring_size * sizeof(struct bcm6368_enetsw_desc);
 692         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 693         if (!p) {
 694                 dev_err(kdev, "cannot allocate tx ring\n");
 695                 ret = -ENOMEM;
 696                 goto out_free_rx_ring;
 697         }
 698
 699         memset(p, 0, size);
 700         priv->tx_desc_alloc_size = size;
 701         priv->tx_desc_cpu = p;
 702
 703         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
 704                                GFP_KERNEL);
 705         if (!priv->tx_skb) {
 706                 dev_err(kdev, "cannot allocate tx skb queue\n");
 707                 ret = -ENOMEM;
 708                 goto out_free_tx_ring;
 709         }
 710
 711         priv->tx_desc_count = priv->tx_ring_size;
 712         priv->tx_dirty_desc = 0;
 713         priv->tx_curr_desc = 0;
 714         spin_lock_init(&priv->tx_lock);
 715
 716         /* init & fill rx ring with buffers */
 717         priv->rx_buf = kzalloc(sizeof(unsigned char *) * priv->rx_ring_size,
 718                                GFP_KERNEL);
 719         if (!priv->rx_buf) {
 720                 dev_err(kdev, "cannot allocate rx buffer queue\n");
 721                 ret = -ENOMEM;
 722                 goto out_free_tx_skb;
 723         }
 724
 725         priv->rx_desc_count = 0;
 726         priv->rx_dirty_desc = 0;
 727         priv->rx_curr_desc = 0;
 728
 729         /* initialize flow control buffer allocation */
 730         dma_writel(priv, DMA_BUFALLOC_FORCE_MASK | 0,
 731                    DMA_BUFALLOC_REG(priv->rx_chan));
 732
 733         if (bcm6368_enetsw_refill_rx(dev, false)) {
 734                 dev_err(kdev, "cannot allocate rx buffer queue\n");
 735                 ret = -ENOMEM;
 736                 goto out;
 737         }
 738
 739         /* write rx & tx ring addresses */
 740         dmas_writel(priv, priv->rx_desc_dma,
 741                     DMAS_RSTART_REG, priv->rx_chan);
 742         dmas_writel(priv, priv->tx_desc_dma,
 743                     DMAS_RSTART_REG, priv->tx_chan);
 744
 745         /* clear remaining state ram for rx & tx channel */
 746         dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->rx_chan);
 747         dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->tx_chan);
 748         dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->rx_chan);
 749         dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->tx_chan);
 750         dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->rx_chan);
 751         dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->tx_chan);
 752
 753         /* set dma maximum burst len */
 754         dmac_writel(priv, priv->dma_maxburst,
 755                     DMAC_MAXBURST_REG, priv->rx_chan);
 756         dmac_writel(priv, priv->dma_maxburst,
 757                     DMAC_MAXBURST_REG, priv->tx_chan);
 758
 759         /* set flow control low/high threshold to 1/3 / 2/3 */
 760         val = priv->rx_ring_size / 3;
 761         dma_writel(priv, val, DMA_FLOWCL_REG(priv->rx_chan));
 762         val = (priv->rx_ring_size * 2) / 3;
 763         dma_writel(priv, val, DMA_FLOWCH_REG(priv->rx_chan));
 764
 765         /* all set, enable mac and interrupts, start dma engine and
 766          * kick rx dma channel
 767          */
 768         wmb();
 769         dma_writel(priv, DMA_CFG_EN_MASK, DMA_CFG_REG);
 770         dmac_writel(priv, DMAC_CHANCFG_EN_MASK,
 771                     DMAC_CHANCFG_REG, priv->rx_chan);
 772
 773         /* watch "packet transferred" interrupt in rx and tx */
 774         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 775                     DMAC_IR_REG, priv->rx_chan);
 776         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 777                     DMAC_IR_REG, priv->tx_chan);
 778
 779         /* make sure we enable napi before rx interrupt  */
 780         napi_enable(&priv->napi);
 781
 782         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 783                     DMAC_IRMASK_REG, priv->rx_chan);
 784         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 785                     DMAC_IRMASK_REG, priv->tx_chan);
 786
 787         netif_carrier_on(dev);
 788         netif_start_queue(dev);
 789
 790         return 0;
 791
 792 out:
 793         for (i = 0; i < priv->rx_ring_size; i++) {
 794                 struct bcm6368_enetsw_desc *desc;
 795
 796                 if (!priv->rx_buf[i])
 797                         continue;
 798
 799                 desc = &priv->rx_desc_cpu[i];
 800                 dma_unmap_single(kdev, desc->address, priv->rx_buf_size,
 801                                  DMA_FROM_DEVICE);
 802                 skb_free_frag(priv->rx_buf[i]);
 803         }
 804         kfree(priv->rx_buf);
 805
 806 out_free_tx_skb:
 807         kfree(priv->tx_skb);
 808
 809 out_free_tx_ring:
 810         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
 811                           priv->tx_desc_cpu, priv->tx_desc_dma);
 812
 813 out_free_rx_ring:
 814         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
 815                           priv->rx_desc_cpu, priv->rx_desc_dma);
 816
 817 out_freeirq_tx:
 818         if (priv->irq_tx != -1)
 819                 free_irq(priv->irq_tx, dev);
 820
 821 out_freeirq_rx:
 822         free_irq(priv->irq_rx, dev);
 823
 824 out_freeirq:
 825         return ret;
 826 }
 827
 828 static int bcm6368_enetsw_stop(struct net_device *dev)
 829 {
 830         struct bcm6368_enetsw *priv = netdev_priv(dev);
 831         struct device *kdev = &priv->pdev->dev;
 832         int i;
 833
 834         netif_stop_queue(dev);
 835         napi_disable(&priv->napi);
 836         del_timer_sync(&priv->rx_timeout);
 837
 838         /* mask all interrupts */
 839         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 840         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 841
 842         /* disable dma & mac */
 843         bcm6368_enetsw_disable_dma(priv, priv->tx_chan);
 844         bcm6368_enetsw_disable_dma(priv, priv->rx_chan);
 845
 846         /* force reclaim of all tx buffers */
 847         bcm6368_enetsw_tx_reclaim(dev, 1);
 848
 849         /* free the rx buffer ring */
 850         for (i = 0; i < priv->rx_ring_size; i++) {
 851                 struct bcm6368_enetsw_desc *desc;
 852
 853                 if (!priv->rx_buf[i])
 854                         continue;
 855
 856                 desc = &priv->rx_desc_cpu[i];
 857                 dma_unmap_single_attrs(kdev, desc->address, priv->rx_buf_size,
 858                                        DMA_FROM_DEVICE,
 859                                        DMA_ATTR_SKIP_CPU_SYNC);
 860                 skb_free_frag(priv->rx_buf[i]);
 861         }
 862
 863         /* free remaining allocated memory */
 864         kfree(priv->rx_buf);
 865         kfree(priv->tx_skb);
 866         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
 867                           priv->rx_desc_cpu, priv->rx_desc_dma);
 868         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
 869                           priv->tx_desc_cpu, priv->tx_desc_dma);
 870         if (priv->irq_tx != -1)
 871                 free_irq(priv->irq_tx, dev);
 872         free_irq(priv->irq_rx, dev);
 873
 874         return 0;
 875 }
 876
 877 static const struct net_device_ops bcm6368_enetsw_ops = {
 878         .ndo_open = bcm6368_enetsw_open,
 879         .ndo_stop = bcm6368_enetsw_stop,
 880         .ndo_start_xmit = bcm6368_enetsw_start_xmit,
 881 };
 882
 883 static int bcm6368_enetsw_probe(struct platform_device *pdev)
 884 {
 885         struct bcm6368_enetsw *priv;
 886         struct device *dev = &pdev->dev;
 887         struct device_node *node = dev->of_node;
 888         struct net_device *ndev;
 889         struct resource *res;
 890         unsigned i;
 891         int ret;
 892
 893         ndev = alloc_etherdev(sizeof(*priv));
 894         if (!ndev)
 895                 return -ENOMEM;
 896
 897         priv = netdev_priv(ndev);
 898
 899         priv->num_pms = of_count_phandle_with_args(node, "power-domains",
 900                                                    "#power-domain-cells");
 901         if (priv->num_pms > 1) {
 902                 priv->pm = devm_kcalloc(dev, priv->num_pms,
 903                                         sizeof(struct device *), GFP_KERNEL);
 904                 if (!priv->pm)
 905                         return -ENOMEM;
 906
 907                 priv->link_pm = devm_kcalloc(dev, priv->num_pms,
 908                                              sizeof(struct device_link *),
 909                                              GFP_KERNEL);
 910                 if (!priv->link_pm)
 911                         return -ENOMEM;
 912
 913                 for (i = 0; i < priv->num_pms; i++) {
 914                         priv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);
 915                         if (IS_ERR(priv->pm[i])) {
 916                                 dev_err(dev, "error getting pm %d\n", i);
 917                                 return -EINVAL;
 918                         }
 919
 920                         priv->link_pm[i] = device_link_add(dev, priv->pm[i],
 921                                 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
 922                                 DL_FLAG_RPM_ACTIVE);
 923                 }
 924         }
 925
 926         pm_runtime_enable(dev);
 927         pm_runtime_no_callbacks(dev);
 928         ret = pm_runtime_get_sync(dev);
 929         if (ret < 0) {
 930                 pm_runtime_disable(dev);
 931                 dev_info(dev, "PM prober defer: ret=%d\n", ret);
 932                 return -EPROBE_DEFER;
 933         }
 934
 935         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 936         priv->dma_base = devm_ioremap_resource(dev, res);
 937         if (IS_ERR(priv->dma_base))
 938                 return PTR_ERR(priv->dma_base);
 939
 940         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 941                                            "dma-channels");
 942         priv->dma_chan = devm_ioremap_resource(dev, res);
 943         if (IS_ERR(priv->dma_chan))
 944                 return PTR_ERR(priv->dma_chan);
 945
 946         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma-sram");
 947         priv->dma_sram = devm_ioremap_resource(dev, res);
 948         if (IS_ERR(priv->dma_sram))
 949                 return PTR_ERR(priv->dma_sram);
 950
 951         priv->irq_rx = platform_get_irq_byname(pdev, "rx");
 952         if (!priv->irq_rx)
 953                 return -ENODEV;
 954
 955         priv->irq_tx = platform_get_irq_byname(pdev, "tx");
 956         if (!priv->irq_tx)
 957                 return -ENODEV;
 958         else if (priv->irq_tx < 0)
 959                 priv->irq_tx = -1;
 960
 961         if (device_property_read_u32(dev, "dma-rx", &priv->rx_chan))
 962                 return -ENODEV;
 963
 964         if (device_property_read_u32(dev, "dma-tx", &priv->tx_chan))
 965                 return -ENODEV;
 966
 967         priv->rx_ring_size = ENETSW_DEF_RX_DESC;
 968         priv->tx_ring_size = ENETSW_DEF_TX_DESC;
 969
 970         priv->dma_maxburst = ENETSW_DMA_MAXBURST;
 971
 972         priv->copybreak = ENETSW_DEF_CPY_BREAK;
 973
 974         priv->dma_chan_en_mask = DMAC_CHANCFG_EN_MASK;
 975         priv->dma_chan_int_mask = DMAC_IR_PKTDONE_MASK;
 976         priv->dma_chan_width = DMA_CHAN_WIDTH;
 977
 978         of_get_mac_address(node, ndev->dev_addr);
 979         if (is_valid_ether_addr(ndev->dev_addr)) {
 980                 dev_info(dev, "mtd mac %pM\n", ndev->dev_addr);
 981         } else {
 982                 random_ether_addr(ndev->dev_addr);
 983                 dev_info(dev, "random mac %pM\n", ndev->dev_addr);
 984         }
 985
 986         priv->rx_buf_size = ALIGN(ndev->mtu + ENETSW_MTU_OVERHEAD,
 987                                   priv->dma_maxburst * 4);
 988
 989         priv->rx_frag_size = ENETSW_FRAG_SIZE(priv->rx_buf_size);
 990
 991         priv->num_clocks = of_clk_get_parent_count(node);
 992         if (priv->num_clocks) {
 993                 priv->clock = devm_kcalloc(dev, priv->num_clocks,
 994                                            sizeof(struct clk *), GFP_KERNEL);
 995                 if (!priv->clock)
 996                         return -ENOMEM;
 997         }
 998         for (i = 0; i < priv->num_clocks; i++) {
 999                 priv->clock[i] = of_clk_get(node, i);
1000                 if (IS_ERR(priv->clock[i])) {
1001                         dev_err(dev, "error getting clock %d\n", i);
1002                         return -EINVAL;
1003                 }
1004
1005                 ret = clk_prepare_enable(priv->clock[i]);
1006                 if (ret) {
1007                         dev_err(dev, "error enabling clock %d\n", i);
1008                         return ret;
1009                 }
1010         }
1011
1012         priv->num_resets = of_count_phandle_with_args(node, "resets",
1013                                                       "#reset-cells");
1014         if (priv->num_resets) {
1015                 priv->reset = devm_kcalloc(dev, priv->num_resets,
1016                                            sizeof(struct reset_control *),
1017                                            GFP_KERNEL);
1018                 if (!priv->reset)
1019                         return -ENOMEM;
1020         }
1021         for (i = 0; i < priv->num_resets; i++) {
1022                 priv->reset[i] = devm_reset_control_get_by_index(dev, i);
1023                 if (IS_ERR(priv->reset[i])) {
1024                         dev_err(dev, "error getting reset %d\n", i);
1025                         return -EINVAL;
1026                 }
1027
1028                 ret = reset_control_reset(priv->reset[i]);
1029                 if (ret) {
1030                         dev_err(dev, "error performing reset %d\n", i);
1031                         return ret;
1032                 }
1033         }
1034
1035         spin_lock_init(&priv->rx_lock);
1036
1037         timer_setup(&priv->rx_timeout, bcm6368_enetsw_refill_rx_timer, 0);
1038
1039         /* register netdevice */
1040         ndev->netdev_ops = &bcm6368_enetsw_ops;
1041         ndev->min_mtu = ETH_ZLEN;
1042         ndev->mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1043         ndev->max_mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1044         netif_napi_add(ndev, &priv->napi, bcm6368_enetsw_poll, 16);
1045         SET_NETDEV_DEV(ndev, dev);
1046
1047         ret = register_netdev(ndev);
1048         if (ret)
1049                 goto out_disable_clk;
1050
1051         netif_carrier_off(ndev);
1052         platform_set_drvdata(pdev, ndev);
1053         priv->pdev = pdev;
1054         priv->net_dev = ndev;
1055
1056         return 0;
1057
1058 out_disable_clk:
1059         for (i = 0; i < priv->num_resets; i++)
1060                 reset_control_assert(priv->reset[i]);
1061
1062         for (i = 0; i < priv->num_clocks; i++)
1063                 clk_disable_unprepare(priv->clock[i]);
1064
1065         return ret;
1066 }
1067
1068 static int bcm6368_enetsw_remove(struct platform_device *pdev)
1069 {
1070         struct device *dev = &pdev->dev;
1071         struct net_device *ndev = platform_get_drvdata(pdev);
1072         struct bcm6368_enetsw *priv = netdev_priv(ndev);
1073         unsigned int i;
1074
1075         unregister_netdev(ndev);
1076
1077         pm_runtime_put_sync(dev);
1078         for (i = 0; priv->pm && i < priv->num_pms; i++) {
1079                 dev_pm_domain_detach(priv->pm[i], true);
1080                 device_link_del(priv->link_pm[i]);
1081         }
1082
1083         for (i = 0; i < priv->num_resets; i++)
1084                 reset_control_assert(priv->reset[i]);
1085
1086         for (i = 0; i < priv->num_clocks; i++)
1087                 clk_disable_unprepare(priv->clock[i]);
1088
1089         free_netdev(ndev);
1090
1091         return 0;
1092 }
1093
1094 static const struct of_device_id bcm6368_enetsw_of_match[] = {
1095         { .compatible = "brcm,bcm6318-enetsw", },
1096         { .compatible = "brcm,bcm6328-enetsw", },
1097         { .compatible = "brcm,bcm6362-enetsw", },
1098         { .compatible = "brcm,bcm6368-enetsw", },
1099         { .compatible = "brcm,bcm63268-enetsw", },
1100         { /* sentinel */ }
1101 };
1102 MODULE_DEVICE_TABLE(of, bcm6368_enetsw_of_match);
1103
1104 static struct platform_driver bcm6368_enetsw_driver = {
1105         .driver = {
1106                 .name = "bcm6368-enetsw",
1107                 .of_match_table = of_match_ptr(bcm6368_enetsw_of_match),
1108         },
1109         .probe  = bcm6368_enetsw_probe,
1110         .remove = bcm6368_enetsw_remove,
1111 };
1112 module_platform_driver(bcm6368_enetsw_driver);