target/linux/mediatek/patches-6.6/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Fri, 4 Sep 2020 18:42:42 +0200
   3 Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
   4
   5 It improves performance by eliminating the need for a cache flush for DMA on
   6 attached devices
   7
   8 Signed-off-by: Felix Fietkau <nbd@nbd.name>
   9 ---
  10
  11 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  12 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  13 @@ -832,6 +832,9 @@
  14                 bus-range = <0x00 0xff>;
  15                 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
  16                 status = "disabled";
  17 +               dma-coherent;
  18 +               mediatek,hifsys = <&hifsys>;
  19 +               mediatek,cci-control = <&cci_control2>;
  20
  21                 #interrupt-cells = <1>;
  22                 interrupt-map-mask = <0 0 0 7>;
  23 @@ -876,6 +879,9 @@
  24                 bus-range = <0x00 0xff>;
  25                 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
  26                 status = "disabled";
  27 +               dma-coherent;
  28 +               mediatek,hifsys = <&hifsys>;
  29 +               mediatek,cci-control = <&cci_control2>;
  30
  31                 #interrupt-cells = <1>;
  32                 interrupt-map-mask = <0 0 0 7>;
  33 @@ -937,7 +943,7 @@
  34         };
  35
  36         hifsys: clock-controller@1af00000 {
  37 -               compatible = "mediatek,mt7622-hifsys";
  38 +               compatible = "mediatek,mt7622-hifsys", "syscon";
  39                 reg = <0 0x1af00000 0 0x70>;
  40                 #clock-cells = <1>;
  41         };
  42 --- a/drivers/pci/controller/pcie-mediatek.c
  43 +++ b/drivers/pci/controller/pcie-mediatek.c
  44 @@ -20,6 +20,7 @@
  45  #include <linux/of_address.h>
  46  #include <linux/of_pci.h>
  47  #include <linux/of_platform.h>
  48 +#include <linux/of_address.h>
  49  #include <linux/pci.h>
  50  #include <linux/phy/phy.h>
  51  #include <linux/platform_device.h>
  52 @@ -139,6 +140,11 @@
  53  #define PCIE_LINK_STATUS_V2    0x804
  54  #define PCIE_PORT_LINKUP_V2    BIT(10)
  55
  56 +/* DMA channel mapping */
  57 +#define HIFSYS_DMA_AG_MAP      0x008
  58 +#define HIFSYS_DMA_AG_MAP_PCIE0        BIT(0)
  59 +#define HIFSYS_DMA_AG_MAP_PCIE1        BIT(1)
  60 +
  61  struct mtk_pcie_port;
  62
  63  /**
  64 @@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci
  65         struct mtk_pcie_port *port, *tmp;
  66         int err, slot;
  67
  68 +       if (of_dma_is_coherent(node)) {
  69 +               struct regmap *con;
  70 +               u32 mask;
  71 +
  72 +               con = syscon_regmap_lookup_by_phandle(node,
  73 +                                                     "mediatek,cci-control");
  74 +               /* enable CPU/bus coherency */
  75 +               if (!IS_ERR(con))
  76 +                       regmap_write(con, 0, 3);
  77 +
  78 +               con = syscon_regmap_lookup_by_phandle(node,
  79 +                                                     "mediatek,hifsys");
  80 +               if (IS_ERR(con)) {
  81 +                       dev_err(dev, "missing hifsys node\n");
  82 +                       return PTR_ERR(con);
  83 +               }
  84 +
  85 +               mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
  86 +               regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
  87 +       }
  88 +
  89         slot = of_get_pci_domain_nr(dev->of_node);
  90         if (slot < 0) {
  91                 for_each_available_child_of_node(node, child) {