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(parent: 57f4b6f) | patch
fdts: stm32mp1: move FDCAN to PLL4_R
authorAntonio Borneo <antonio.borneo@st.com>
Mon, 29 Jul 2019 12:46:16 +0000 (14:46 +0200)
committerYann Gautier <yann.gautier@st.com>
Thu, 3 Oct 2019 09:17:40 +0000 (11:17 +0200)
commit2dc9fe70da6788ff69856ed247b10a59173431c3
treebf9ccdb0c877be6a4d43a097d19f42ad811a21c5tree | snapshot
parent57f4b6f83974b17e0aae04e17f9d95a5659ac88bcommit | diff
fdts: stm32mp1: move FDCAN to PLL4_R

LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.

This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.

Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58
fdts/stm32mp157a-avenger96.dts diff | blob | history
fdts/stm32mp157a-dk1.dts diff | blob | history
fdts/stm32mp157c-ed1.dts diff | blob | history
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