mediatek: mt8183: add MTK uart driver for controlling clock gate

Add uart clock gate contol for suspend/resume scenario.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Id4197b0720630ec6c74aec206a9b206511bf515a

diff --git a/plat/mediatek/mt8183/drivers/uart/uart.c b/plat/mediatek/mt8183/drivers/uart/uart.c
new file mode 100644 (file)
index 0000000..3c6a980
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/uart/uart.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <uart.h>
+
+static struct mt_uart uart_save_addr[DRV_SUPPORT_UART_PORTS];
+
+static const unsigned int uart_base_addr[DRV_SUPPORT_UART_PORTS] = {
+       UART0_BASE,
+       UART1_BASE
+};
+
+void mt_uart_restore(void)
+{
+       int uart_idx = UART_PORT0;
+       struct mt_uart *uart;
+       unsigned long base;
+
+       /* Must NOT print any debug log before UART restore */
+       for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS;
+            uart_idx++) {
+
+               uart = &uart_save_addr[uart_idx];
+               base = uart->base;
+
+               mmio_write_32(UART_LCR(base), UART_LCR_MODE_B);
+               mmio_write_32(UART_EFR(base), uart->registers.efr);
+               mmio_write_32(UART_LCR(base), uart->registers.lcr);
+               mmio_write_32(UART_FCR(base), uart->registers.fcr);
+
+               /* baudrate */
+               mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed);
+               mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l);
+               mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m);
+               mmio_write_32(UART_LCR(base),
+                             uart->registers.lcr | UART_LCR_DLAB);
+               mmio_write_32(UART_DLL(base), uart->registers.dll);
+               mmio_write_32(UART_DLH(base), uart->registers.dlh);
+               mmio_write_32(UART_LCR(base), uart->registers.lcr);
+               mmio_write_32(UART_SAMPLE_COUNT(base),
+                             uart->registers.sample_count);
+               mmio_write_32(UART_SAMPLE_POINT(base),
+                             uart->registers.sample_point);
+               mmio_write_32(UART_GUARD(base), uart->registers.guard);
+
+               /* flow control */
+               mmio_write_32(UART_ESCAPE_EN(base), uart->registers.escape_en);
+               mmio_write_32(UART_MCR(base), uart->registers.mcr);
+               mmio_write_32(UART_IER(base), uart->registers.ier);
+               mmio_write_32(UART_SCR(base), uart->registers.scr);
+       }
+}
+
+void mt_uart_save(void)
+{
+       int uart_idx = UART_PORT0;
+       struct mt_uart *uart;
+       unsigned long base;
+
+       for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS;
+            uart_idx++) {
+
+               uart_save_addr[uart_idx].base = uart_base_addr[uart_idx];
+               base = uart_base_addr[uart_idx];
+               uart = &uart_save_addr[uart_idx];
+               uart->registers.lcr = mmio_read_32(UART_LCR(base));
+
+               mmio_write_32(UART_LCR(base), UART_LCR_MODE_B);
+               uart->registers.efr = mmio_read_32(UART_EFR(base));
+               mmio_write_32(UART_LCR(base), uart->registers.lcr);
+               uart->registers.fcr = mmio_read_32(UART_FCR_RD(base));
+
+               /* baudrate */
+               uart->registers.highspeed = mmio_read_32(UART_HIGHSPEED(base));
+               uart->registers.fracdiv_l = mmio_read_32(UART_FRACDIV_L(base));
+               uart->registers.fracdiv_m = mmio_read_32(UART_FRACDIV_M(base));
+               mmio_write_32(UART_LCR(base),
+                             uart->registers.lcr | UART_LCR_DLAB);
+               uart->registers.dll = mmio_read_32(UART_DLL(base));
+               uart->registers.dlh = mmio_read_32(UART_DLH(base));
+               mmio_write_32(UART_LCR(base), uart->registers.lcr);
+               uart->registers.sample_count = mmio_read_32(
+                                               UART_SAMPLE_COUNT(base));
+               uart->registers.sample_point = mmio_read_32(
+                                               UART_SAMPLE_POINT(base));
+               uart->registers.guard = mmio_read_32(UART_GUARD(base));
+
+               /* flow control */
+               uart->registers.escape_en = mmio_read_32(UART_ESCAPE_EN(base));
+               uart->registers.mcr = mmio_read_32(UART_MCR(base));
+               uart->registers.ier = mmio_read_32(UART_IER(base));
+               uart->registers.scr = mmio_read_32(UART_SCR(base));
+       }
+}
+
+void mt_console_uart_cg(int on)
+{
+       if (on)
+               mmio_write_32(UART_CLOCK_GATE_CLR, UART0_CLOCK_GATE_BIT);
+       else
+               mmio_write_32(UART_CLOCK_GATE_SET, UART0_CLOCK_GATE_BIT);
+}
+
+int mt_console_uart_cg_status(void)
+{
+       return mmio_read_32(UART_CLOCK_GATE_STA) & UART0_CLOCK_GATE_BIT;
+}

diff --git a/plat/mediatek/mt8183/drivers/uart/uart.h b/plat/mediatek/mt8183/drivers/uart/uart.h
new file mode 100644 (file)
index 0000000..be04c35
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/uart/uart.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+#include <platform_def.h>
+
+/* UART HW information */
+#define HW_SUPPORT_UART_PORTS  2
+#define DRV_SUPPORT_UART_PORTS 2
+
+/* console UART clock cg */
+#define UART_CLOCK_GATE_SET            (INFRACFG_AO_BASE + 0x80)
+#define UART_CLOCK_GATE_CLR            (INFRACFG_AO_BASE + 0x84)
+#define UART_CLOCK_GATE_STA            (INFRACFG_AO_BASE + 0x90)
+#define UART0_CLOCK_GATE_BIT           (1U<<22)
+#define UART1_CLOCK_GATE_BIT           (1U<<23)
+
+/* UART registers */
+#define UART_RBR(_baseaddr)                    (_baseaddr + 0x0)
+#define UART_THR(_baseaddr)                    (_baseaddr + 0x0)
+#define UART_IER(_baseaddr)                    (_baseaddr + 0x4)
+#define UART_IIR(_baseaddr)                    (_baseaddr + 0x8)
+#define UART_FCR(_baseaddr)                    (_baseaddr + 0x8)
+#define UART_LCR(_baseaddr)                    (_baseaddr + 0xc)
+#define UART_MCR(_baseaddr)                    (_baseaddr + 0x10)
+#define UART_LSR(_baseaddr)                    (_baseaddr + 0x14)
+#define UART_MSR(_baseaddr)                    (_baseaddr + 0x18)
+#define UART_SCR(_baseaddr)                    (_baseaddr + 0x1c)
+#define UART_DLL(_baseaddr)                    (_baseaddr + 0x0)
+#define UART_DLH(_baseaddr)                    (_baseaddr + 0x4)
+#define UART_EFR(_baseaddr)                    (_baseaddr + 0x8)
+#define UART_XON1(_baseaddr)                   (_baseaddr + 0x10)
+#define UART_XON2(_baseaddr)                   (_baseaddr + 0x14)
+#define UART_XOFF1(_baseaddr)                  (_baseaddr + 0x18)
+#define UART_XOFF2(_baseaddr)                  (_baseaddr + 0x1c)
+#define UART_AUTOBAUD(_baseaddr)               (_baseaddr + 0x20)
+#define UART_HIGHSPEED(_baseaddr)              (_baseaddr + 0x24)
+#define UART_SAMPLE_COUNT(_baseaddr)           (_baseaddr + 0x28)
+#define UART_SAMPLE_POINT(_baseaddr)           (_baseaddr + 0x2c)
+#define UART_AUTOBAUD_REG(_baseaddr)           (_baseaddr + 0x30)
+#define UART_RATE_FIX_REG(_baseaddr)           (_baseaddr + 0x34)
+#define UART_AUTO_BAUDSAMPLE(_baseaddr)                (_baseaddr + 0x38)
+#define UART_GUARD(_baseaddr)                  (_baseaddr + 0x3c)
+#define UART_ESCAPE_DAT(_baseaddr)             (_baseaddr + 0x40)
+#define UART_ESCAPE_EN(_baseaddr)              (_baseaddr + 0x44)
+#define UART_SLEEP_EN(_baseaddr)               (_baseaddr + 0x48)
+#define UART_DMA_EN(_baseaddr)                 (_baseaddr + 0x4c)
+#define UART_RXTRI_AD(_baseaddr)               (_baseaddr + 0x50)
+#define UART_FRACDIV_L(_baseaddr)              (_baseaddr + 0x54)
+#define UART_FRACDIV_M(_baseaddr)              (_baseaddr + 0x58)
+#define UART_FCR_RD(_baseaddr)                 (_baseaddr + 0x5C)
+#define UART_USB_RX_SEL(_baseaddr)             (_baseaddr + 0xB0)
+#define UART_SLEEP_REQ(_baseaddr)              (_baseaddr + 0xB4)
+#define UART_SLEEP_ACK(_baseaddr)              (_baseaddr + 0xB8)
+#define UART_SPM_SEL(_baseaddr)                        (_baseaddr + 0xBC)
+#define UART_LCR_DLAB                          0x0080
+#define UART_LCR_MODE_B                                0x00bf
+
+enum uart_port_ID {
+       UART_PORT0 = 0,
+       UART_PORT1
+};
+
+struct mt_uart_register {
+       unsigned int dll;
+       unsigned int dlh;
+       unsigned int ier;
+       unsigned int lcr;
+       unsigned int mcr;
+       unsigned int fcr;
+       unsigned int lsr;
+       unsigned int scr;
+       unsigned int efr;
+       unsigned int highspeed;
+       unsigned int sample_count;
+       unsigned int sample_point;
+       unsigned int fracdiv_l;
+       unsigned int fracdiv_m;
+       unsigned int escape_en;
+       unsigned int guard;
+       unsigned int rx_sel;
+};
+
+struct mt_uart {
+       unsigned long base;
+       struct mt_uart_register registers;
+};
+
+/* external API */
+void mt_uart_save(void);
+void mt_uart_restore(void);
+void mt_console_uart_cg(int on);
+int mt_console_uart_cg_status(void);
+
+#endif /* __UART_H__ */

diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h
index f802ac2f50364b1f58ce9cf17030286476bd9ec0..dab265b472eb5eb5245c641bdc4f00f4ecd632c9 100644 (file)
--- a/plat/mediatek/mt8183/include/platform_def.h
+++ b/plat/mediatek/mt8183/include/platform_def.h
@@ -87,6 +87,7 @@
  * UART related constants
  ******************************************************************************/
 #define UART0_BASE    (IO_PHYS + 0x01002000)
+#define UART1_BASE    (IO_PHYS + 0x01003000)
 
 #define UART_BAUDRATE 115200
 #define UART_CLOCK    26000000

diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 09fd13319e07bf6bcc80165bd3275ec702872fc1..3053a87f5e71ba345c10744b35e790d462aa3c6b 100644 (file)
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -13,6 +13,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
                  -I${MTK_PLAT_SOC}/drivers/gpio/                  \
                  -I${MTK_PLAT_SOC}/drivers/pmic/                  \
                  -I${MTK_PLAT_SOC}/drivers/rtc/                   \
+                 -I${MTK_PLAT_SOC}/drivers/uart/                  \
                  -I${MTK_PLAT_SOC}/include/
 
 PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c       \
@@ -47,6 +48,7 @@ BL31_SOURCES    += common/desc_image_load.c                              \
                    ${MTK_PLAT_SOC}/drivers/rtc/rtc.c                     \
                    ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c                 \
                    ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
+                   ${MTK_PLAT_SOC}/drivers/uart/uart.c                   \
                    ${MTK_PLAT_SOC}/plat_pm.c                             \
                    ${MTK_PLAT_SOC}/plat_topology.c                       \
                    ${MTK_PLAT_SOC}/plat_mt_gic.c                         \