The patches were upstreamed.
Signed-off-by: Nick Hainke <vincent@systemli.org>
+++ /dev/null
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -43,6 +43,15 @@ err_out:
- return NULL;
- }
-
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data)
-+{
-+ if (!clk_data)
-+ return;
-+
-+ kfree(clk_data->clks);
-+ kfree(clk_data);
-+}
-+
- void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
- int num, struct clk_onecell_data *clk_data)
- {
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str
- struct clk_onecell_data *clk_data);
-
- struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data);
-
- #define HAVE_RST_BAR BIT(0)
- #define PLL_AO BIT(1)
--- /dev/null
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -43,6 +43,15 @@ err_out:
+ return NULL;
+ }
+
++void mtk_free_clk_data(struct clk_onecell_data *clk_data)
++{
++ if (!clk_data)
++ return;
++
++ kfree(clk_data->clks);
++ kfree(clk_data);
++}
++
+ void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
+ int num, struct clk_onecell_data *clk_data)
+ {
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str
+ struct clk_onecell_data *clk_data);
+
+ struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
++void mtk_free_clk_data(struct clk_onecell_data *clk_data);
+
+ #define HAVE_RST_BAR BIT(0)
+ #define PLL_AO BIT(1)
+++ /dev/null
-From: Chuanjia Liu <chuanjia.liu@mediatek.com>
-Date: Mon, 23 Aug 2021 11:27:59 +0800
-Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
-
-There are two independent PCIe controllers in MT2712 and MT7622
-platform. Each of them should contain an independent MSI domain.
-
-In old dts architecture, MSI domain will be inherited from the root
-bridge, and all of the devices will share the same MSI domain.
-Hence that, the PCIe devices will not work properly if the irq number
-which required is more than 32.
-
-Split the PCIe node for MT2712 and MT7622 platform to comply with
-the hardware design and fix MSI issue.
-
-Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
-Acked-by: Ryder Lee <ryder.lee@mediatek.com>
-Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
-@@ -915,64 +915,67 @@
- };
- };
-
-- pcie: pcie@11700000 {
-+ pcie1: pcie@112ff000 {
- compatible = "mediatek,mt2712-pcie";
- device_type = "pci";
-- reg = <0 0x11700000 0 0x1000>,
-- <0 0x112ff000 0 0x1000>;
-- reg-names = "port0", "port1";
-+ reg = <0 0x112ff000 0 0x1000>;
-+ reg-names = "port1";
-+ linux,pci-domain = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
-- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
-- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
-- <&pericfg CLK_PERI_PCIE0>,
-+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pcie_irq";
-+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
- <&pericfg CLK_PERI_PCIE1>;
-- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
-- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
-- phy-names = "pcie-phy0", "pcie-phy1";
-+ clock-names = "sys_ck1", "ahb_ck1";
-+ phys = <&u3port1 PHY_TYPE_PCIE>;
-+ phy-names = "pcie-phy1";
- bus-range = <0x00 0xff>;
-- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
-+ status = "disabled";
-
-- pcie0: pcie@0,0 {
-- device_type = "pci";
-- status = "disabled";
-- reg = <0x0000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-+ <0 0 0 2 &pcie_intc1 1>,
-+ <0 0 0 3 &pcie_intc1 2>,
-+ <0 0 0 4 &pcie_intc1 3>;
-+ pcie_intc1: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-- <0 0 0 2 &pcie_intc0 1>,
-- <0 0 0 3 &pcie_intc0 2>,
-- <0 0 0 4 &pcie_intc0 3>;
-- pcie_intc0: interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- };
- };
-+ };
-+
-+ pcie0: pcie@11700000 {
-+ compatible = "mediatek,mt2712-pcie";
-+ device_type = "pci";
-+ reg = <0 0x11700000 0 0x1000>;
-+ reg-names = "port0";
-+ linux,pci-domain = <0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pcie_irq";
-+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
-+ <&pericfg CLK_PERI_PCIE0>;
-+ clock-names = "sys_ck0", "ahb_ck0";
-+ phys = <&u3port0 PHY_TYPE_PCIE>;
-+ phy-names = "pcie-phy0";
-+ bus-range = <0x00 0xff>;
-+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+ status = "disabled";
-
-- pcie1: pcie@1,0 {
-- device_type = "pci";
-- status = "disabled";
-- reg = <0x0800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-+ <0 0 0 2 &pcie_intc0 1>,
-+ <0 0 0 3 &pcie_intc0 2>,
-+ <0 0 0 4 &pcie_intc0 3>;
-+ pcie_intc0: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-- <0 0 0 2 &pcie_intc1 1>,
-- <0 0 0 3 &pcie_intc1 2>,
-- <0 0 0 4 &pcie_intc1 3>;
-- pcie_intc1: interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- };
- };
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -302,18 +302,16 @@
- };
- };
-
--&pcie {
-+&pcie0 {
- pinctrl-names = "default";
-- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-+ pinctrl-0 = <&pcie0_pins>;
- status = "okay";
-+};
-
-- pcie@0,0 {
-- status = "okay";
-- };
--
-- pcie@1,0 {
-- status = "okay";
-- };
-+&pcie1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie1_pins>;
-+ status = "okay";
- };
-
- &pio {
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -232,18 +232,16 @@
- };
- };
-
--&pcie {
-+&pcie0 {
- pinctrl-names = "default";
-- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-+ pinctrl-0 = <&pcie0_pins>;
- status = "okay";
-+};
-
-- pcie@0,0 {
-- status = "okay";
-- };
--
-- pcie@1,0 {
-- status = "okay";
-- };
-+&pcie1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie1_pins>;
-+ status = "okay";
- };
-
- &pio {
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -808,75 +808,83 @@
- #reset-cells = <1>;
- };
-
-- pcie: pcie@1a140000 {
-+ pciecfg: pciecfg@1a140000 {
-+ compatible = "mediatek,generic-pciecfg", "syscon";
-+ reg = <0 0x1a140000 0 0x1000>;
-+ };
-+
-+ pcie0: pcie@1a143000 {
- compatible = "mediatek,mt7622-pcie";
- device_type = "pci";
-- reg = <0 0x1a140000 0 0x1000>,
-- <0 0x1a143000 0 0x1000>,
-- <0 0x1a145000 0 0x1000>;
-- reg-names = "subsys", "port0", "port1";
-+ reg = <0 0x1a143000 0 0x1000>;
-+ reg-names = "port0";
-+ linux,pci-domain = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
-- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
-- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "pcie_irq";
- clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
-- <&pciesys CLK_PCIE_P1_MAC_EN>,
-- <&pciesys CLK_PCIE_P0_AHB_EN>,
- <&pciesys CLK_PCIE_P0_AHB_EN>,
- <&pciesys CLK_PCIE_P0_AUX_EN>,
-- <&pciesys CLK_PCIE_P1_AUX_EN>,
- <&pciesys CLK_PCIE_P0_AXI_EN>,
-- <&pciesys CLK_PCIE_P1_AXI_EN>,
- <&pciesys CLK_PCIE_P0_OBFF_EN>,
-- <&pciesys CLK_PCIE_P1_OBFF_EN>,
-- <&pciesys CLK_PCIE_P0_PIPE_EN>,
-- <&pciesys CLK_PCIE_P1_PIPE_EN>;
-- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
-- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
-- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
-+ <&pciesys CLK_PCIE_P0_PIPE_EN>;
-+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
-+ "axi_ck0", "obff_ck0", "pipe_ck0";
-+
- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- bus-range = <0x00 0xff>;
-- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
- status = "disabled";
-
-- pcie0: pcie@0,0 {
-- reg = <0x0000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-+ <0 0 0 2 &pcie_intc0 1>,
-+ <0 0 0 3 &pcie_intc0 2>,
-+ <0 0 0 4 &pcie_intc0 3>;
-+ pcie_intc0: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
- #interrupt-cells = <1>;
-- ranges;
-- status = "disabled";
--
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-- <0 0 0 2 &pcie_intc0 1>,
-- <0 0 0 3 &pcie_intc0 2>,
-- <0 0 0 4 &pcie_intc0 3>;
-- pcie_intc0: interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- };
- };
-+ };
-
-- pcie1: pcie@1,0 {
-- reg = <0x0800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- status = "disabled";
-+ pcie1: pcie@1a145000 {
-+ compatible = "mediatek,mt7622-pcie";
-+ device_type = "pci";
-+ reg = <0 0x1a145000 0 0x1000>;
-+ reg-names = "port1";
-+ linux,pci-domain = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "pcie_irq";
-+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
-+ /* designer has connect RC1 with p0_ahb clock */
-+ <&pciesys CLK_PCIE_P0_AHB_EN>,
-+ <&pciesys CLK_PCIE_P1_AUX_EN>,
-+ <&pciesys CLK_PCIE_P1_AXI_EN>,
-+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
-+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
-+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
-+ "axi_ck1", "obff_ck1", "pipe_ck1";
-+
-+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
-+ bus-range = <0x00 0xff>;
-+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
-+ status = "disabled";
-
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-- <0 0 0 2 &pcie_intc1 1>,
-- <0 0 0 3 &pcie_intc1 2>,
-- <0 0 0 4 &pcie_intc1 3>;
-- pcie_intc1: interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- };
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-+ <0 0 0 2 &pcie_intc1 1>,
-+ <0 0 0 3 &pcie_intc1 2>,
-+ <0 0 0 4 &pcie_intc1 3>;
-+ pcie_intc1: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
- };
- };
-
--- /dev/null
+From: Chuanjia Liu <chuanjia.liu@mediatek.com>
+Date: Mon, 23 Aug 2021 11:27:59 +0800
+Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
+
+There are two independent PCIe controllers in MT2712 and MT7622
+platform. Each of them should contain an independent MSI domain.
+
+In old dts architecture, MSI domain will be inherited from the root
+bridge, and all of the devices will share the same MSI domain.
+Hence that, the PCIe devices will not work properly if the irq number
+which required is more than 32.
+
+Split the PCIe node for MT2712 and MT7622 platform to comply with
+the hardware design and fix MSI issue.
+
+Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
+Acked-by: Ryder Lee <ryder.lee@mediatek.com>
+Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+@@ -915,64 +915,67 @@
+ };
+ };
+
+- pcie: pcie@11700000 {
++ pcie1: pcie@112ff000 {
+ compatible = "mediatek,mt2712-pcie";
+ device_type = "pci";
+- reg = <0 0x11700000 0 0x1000>,
+- <0 0x112ff000 0 0x1000>;
+- reg-names = "port0", "port1";
++ reg = <0 0x112ff000 0 0x1000>;
++ reg-names = "port1";
++ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+- <&pericfg CLK_PERI_PCIE0>,
++ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "pcie_irq";
++ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+ <&pericfg CLK_PERI_PCIE1>;
+- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
+- phy-names = "pcie-phy0", "pcie-phy1";
++ clock-names = "sys_ck1", "ahb_ck1";
++ phys = <&u3port1 PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy1";
+ bus-range = <0x00 0xff>;
+- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
++ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
++ status = "disabled";
+
+- pcie0: pcie@0,0 {
+- device_type = "pci";
+- status = "disabled";
+- reg = <0x0000 0 0 0 0>;
+- #address-cells = <3>;
+- #size-cells = <2>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
++ <0 0 0 2 &pcie_intc1 1>,
++ <0 0 0 3 &pcie_intc1 2>,
++ <0 0 0 4 &pcie_intc1 3>;
++ pcie_intc1: interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
+ #interrupt-cells = <1>;
+- ranges;
+- interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+- <0 0 0 2 &pcie_intc0 1>,
+- <0 0 0 3 &pcie_intc0 2>,
+- <0 0 0 4 &pcie_intc0 3>;
+- pcie_intc0: interrupt-controller {
+- interrupt-controller;
+- #address-cells = <0>;
+- #interrupt-cells = <1>;
+- };
+ };
++ };
++
++ pcie0: pcie@11700000 {
++ compatible = "mediatek,mt2712-pcie";
++ device_type = "pci";
++ reg = <0 0x11700000 0 0x1000>;
++ reg-names = "port0";
++ linux,pci-domain = <0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "pcie_irq";
++ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
++ <&pericfg CLK_PERI_PCIE0>;
++ clock-names = "sys_ck0", "ahb_ck0";
++ phys = <&u3port0 PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy0";
++ bus-range = <0x00 0xff>;
++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
++ status = "disabled";
+
+- pcie1: pcie@1,0 {
+- device_type = "pci";
+- status = "disabled";
+- reg = <0x0800 0 0 0 0>;
+- #address-cells = <3>;
+- #size-cells = <2>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
++ <0 0 0 2 &pcie_intc0 1>,
++ <0 0 0 3 &pcie_intc0 2>,
++ <0 0 0 4 &pcie_intc0 3>;
++ pcie_intc0: interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
+ #interrupt-cells = <1>;
+- ranges;
+- interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+- <0 0 0 2 &pcie_intc1 1>,
+- <0 0 0 3 &pcie_intc1 2>,
+- <0 0 0 4 &pcie_intc1 3>;
+- pcie_intc1: interrupt-controller {
+- interrupt-controller;
+- #address-cells = <0>;
+- #interrupt-cells = <1>;
+- };
+ };
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -302,18 +302,16 @@
+ };
+ };
+
+-&pcie {
++&pcie0 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
++};
+
+- pcie@0,0 {
+- status = "okay";
+- };
+-
+- pcie@1,0 {
+- status = "okay";
+- };
++&pcie1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie1_pins>;
++ status = "okay";
+ };
+
+ &pio {
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -232,18 +232,16 @@
+ };
+ };
+
+-&pcie {
++&pcie0 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
++};
+
+- pcie@0,0 {
+- status = "okay";
+- };
+-
+- pcie@1,0 {
+- status = "okay";
+- };
++&pcie1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie1_pins>;
++ status = "okay";
+ };
+
+ &pio {
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -808,75 +808,83 @@
+ #reset-cells = <1>;
+ };
+
+- pcie: pcie@1a140000 {
++ pciecfg: pciecfg@1a140000 {
++ compatible = "mediatek,generic-pciecfg", "syscon";
++ reg = <0 0x1a140000 0 0x1000>;
++ };
++
++ pcie0: pcie@1a143000 {
+ compatible = "mediatek,mt7622-pcie";
+ device_type = "pci";
+- reg = <0 0x1a140000 0 0x1000>,
+- <0 0x1a143000 0 0x1000>,
+- <0 0x1a145000 0 0x1000>;
+- reg-names = "subsys", "port0", "port1";
++ reg = <0 0x1a143000 0 0x1000>;
++ reg-names = "port0";
++ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
++ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-names = "pcie_irq";
+ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+- <&pciesys CLK_PCIE_P1_MAC_EN>,
+- <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AUX_EN>,
+- <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P0_AXI_EN>,
+- <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P0_OBFF_EN>,
+- <&pciesys CLK_PCIE_P1_OBFF_EN>,
+- <&pciesys CLK_PCIE_P0_PIPE_EN>,
+- <&pciesys CLK_PCIE_P1_PIPE_EN>;
+- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
++ <&pciesys CLK_PCIE_P0_PIPE_EN>;
++ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
++ "axi_ck0", "obff_ck0", "pipe_ck0";
++
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
+ status = "disabled";
+
+- pcie0: pcie@0,0 {
+- reg = <0x0000 0 0 0 0>;
+- #address-cells = <3>;
+- #size-cells = <2>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
++ <0 0 0 2 &pcie_intc0 1>,
++ <0 0 0 3 &pcie_intc0 2>,
++ <0 0 0 4 &pcie_intc0 3>;
++ pcie_intc0: interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
+ #interrupt-cells = <1>;
+- ranges;
+- status = "disabled";
+-
+- interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+- <0 0 0 2 &pcie_intc0 1>,
+- <0 0 0 3 &pcie_intc0 2>,
+- <0 0 0 4 &pcie_intc0 3>;
+- pcie_intc0: interrupt-controller {
+- interrupt-controller;
+- #address-cells = <0>;
+- #interrupt-cells = <1>;
+- };
+ };
++ };
+
+- pcie1: pcie@1,0 {
+- reg = <0x0800 0 0 0 0>;
+- #address-cells = <3>;
+- #size-cells = <2>;
+- #interrupt-cells = <1>;
+- ranges;
+- status = "disabled";
++ pcie1: pcie@1a145000 {
++ compatible = "mediatek,mt7622-pcie";
++ device_type = "pci";
++ reg = <0 0x1a145000 0 0x1000>;
++ reg-names = "port1";
++ linux,pci-domain = <1>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-names = "pcie_irq";
++ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
++ /* designer has connect RC1 with p0_ahb clock */
++ <&pciesys CLK_PCIE_P0_AHB_EN>,
++ <&pciesys CLK_PCIE_P1_AUX_EN>,
++ <&pciesys CLK_PCIE_P1_AXI_EN>,
++ <&pciesys CLK_PCIE_P1_OBFF_EN>,
++ <&pciesys CLK_PCIE_P1_PIPE_EN>;
++ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
++ "axi_ck1", "obff_ck1", "pipe_ck1";
++
++ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
++ bus-range = <0x00 0xff>;
++ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
++ status = "disabled";
+
+- interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+- <0 0 0 2 &pcie_intc1 1>,
+- <0 0 0 3 &pcie_intc1 2>,
+- <0 0 0 4 &pcie_intc1 3>;
+- pcie_intc1: interrupt-controller {
+- interrupt-controller;
+- #address-cells = <0>;
+- #interrupt-cells = <1>;
+- };
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
++ <0 0 0 2 &pcie_intc1 1>,
++ <0 0 0 3 &pcie_intc1 2>,
++ <0 0 0 4 &pcie_intc1 3>;
++ pcie_intc1: interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
+ };
+ };
+
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Wed, 4 May 2022 12:03:42 +0200
-Subject: [PATCH] PCI: mediatek-gen3: change driver name to mtk-pcie-gen3
-
-This allows it to coexist with the other mtk pcie driver in the same kernel
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -1025,7 +1025,7 @@ static struct platform_driver mtk_pcie_d
- .probe = mtk_pcie_probe,
- .remove = mtk_pcie_remove,
- .driver = {
-- .name = "mtk-pcie",
-+ .name = "mtk-pcie-gen3",
- .of_match_table = mtk_pcie_of_match,
- .pm = &mtk_pcie_pm_ops,
- },
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 4 May 2022 12:03:42 +0200
+Subject: [PATCH] PCI: mediatek-gen3: change driver name to mtk-pcie-gen3
+
+This allows it to coexist with the other mtk pcie driver in the same kernel
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -1025,7 +1025,7 @@ static struct platform_driver mtk_pcie_d
+ .probe = mtk_pcie_probe,
+ .remove = mtk_pcie_remove,
+ .driver = {
+- .name = "mtk-pcie",
++ .name = "mtk-pcie-gen3",
+ .of_match_table = mtk_pcie_of_match,
+ .pm = &mtk_pcie_pm_ops,
+ },
projects / openwrt / staging / ansuel.git / commitdiff