};
cpu1: cpu@1 {
-@@ -47,17 +47,350 @@
- enable-method = "qcom,kpss-acc-v1";
- device_type = "cpu";
- reg = <1>;
-- next-level-cache = <&L2>;
-- qcom,acc = <&acc1>;
-- qcom,saw = <&saw1>;
-+ next-level-cache = <&L2>;
-+ qcom,acc = <&acc1>;
-+ qcom,saw = <&saw1>;
+@@ -38,14 +50,350 @@
+ next-level-cache = <&L2>;
+ qcom,acc = <&acc1>;
+ qcom,saw = <&saw1>;
+ clocks = <&kraitcc 1>, <&kraitcc 4>;
+ clock-names = "cpu", "l2";
+ clock-latency = <100000>;
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
++ /*
++ * Voltage thresholds are <target min max>
++ */
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <995000 1000000 1005000>;
-+ opp-microvolt-speed0-pvs1-v0 = <920000 925000 930000>;
-+ opp-microvolt-speed0-pvs2-v0 = <870000 875000 880000>;
-+ opp-microvolt-speed0-pvs3-v0 = <795000 800000 805000>;
++ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
++ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
++ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
++ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <0>;
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1045000 1050000 1055000>;
-+ opp-microvolt-speed0-pvs1-v0 = <970000 975000 980000>;
-+ opp-microvolt-speed0-pvs2-v0 = <920000 925000 930000>;
-+ opp-microvolt-speed0-pvs3-v0 = <845000 850000 855000>;
++ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
++ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
++ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
++ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1095000 1100000 1105000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1020000 1025000 1030000>;
-+ opp-microvolt-speed0-pvs2-v0 = <990000 995000 1000000>;
-+ opp-microvolt-speed0-pvs3-v0 = <895000 900000 905000>;
++ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
++ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
++ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
++ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1145000 1150000 1155000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1070000 1075000 1080000>;
-+ opp-microvolt-speed0-pvs2-v0 = <1020000 1025000 1030000>;
-+ opp-microvolt-speed0-pvs3-v0 = <945000 950000 955000>;
++ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
++ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
++ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
++ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1195000 1200000 1205000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1120000 1125000 1130000>;
-+ opp-microvolt-speed0-pvs2-v0 = <1070000 1075000 1080000>;
-+ opp-microvolt-speed0-pvs3-v0 = <995000 1000000 1005000>;
++ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
++ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
++ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
++ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1245000 1250000 1255000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1170000 1175000 1180000>;
-+ opp-microvolt-speed0-pvs2-v0 = <1120000 1125000 1130000>;
-+ opp-microvolt-speed0-pvs3-v0 = <1045000 1050000 1055000>;
++ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
++ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
++ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
++ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
memory {
device_type = "memory";
reg = <0x0 0x0>;
-@@ -93,6 +552,15 @@
+@@ -93,6 +441,15 @@
};
};
firmware {
scm {
compatible = "qcom,scm-ipq806x", "qcom,scm";
-@@ -120,6 +588,78 @@
+@@ -120,6 +477,78 @@
reg-names = "lpass-lpaif";
};
qcom_pinmux: pinmux@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x800000 0x4000>;
-@@ -159,6 +705,15 @@
+@@ -159,6 +588,15 @@
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
-@@ -168,6 +723,53 @@
+@@ -168,6 +606,53 @@
};
};
leds_pins: leds_pins {
mux {
pins = "gpio7", "gpio8", "gpio9",
-@@ -229,6 +831,17 @@
+@@ -230,6 +715,17 @@
clock-output-names = "acpu1_aux";
};
saw0: regulator@2089000 {
compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-@@ -241,6 +854,17 @@
+@@ -242,6 +738,52 @@
regulator;
};
+ compatible = "syscon";
+ reg = <0x12100000 0x10000>;
+ };
++
++ gsbi1: gsbi@12440000 {
++ compatible = "qcom,gsbi-v1.0.0";
++ cell-index = <1>;
++ reg = <0x12440000 0x100>;
++ clocks = <&gcc GSBI1_H_CLK>;
++ clock-names = "iface";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++ status = "disabled";
++
++ syscon-tcsr = <&tcsr>;
++
++ gsbi1_serial: serial@12450000 {
++ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
++ reg = <0x12450000 0x100>,
++ <0x12400000 0x03>;
++ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++ };
++
++ gsbi1_i2c: i2c@12460000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x12460000 0x1000>;
++ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
-@@ -448,6 +1081,95 @@
+@@ -367,6 +909,33 @@
+ };
+ };
+
++ gsbi6: gsbi@16500000 {
++ status = "disabled";
++ compatible = "qcom,gsbi-v1.0.0";
++ cell-index = <6>;
++ reg = <0x16500000 0x100>;
++ clocks = <&gcc GSBI6_H_CLK>;
++ clock-names = "iface";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ syscon-tcsr = <&tcsr>;
++
++ gsbi6_i2c: i2c@16580000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x16580000 0x1000>;
++ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++
++ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++
+ gsbi7: gsbi@16600000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+@@ -388,6 +957,19 @@
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
++
++ gsbi7_i2c: i2c@16680000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x16680000 0x1000>;
++ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++
++ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
+ };
+
+ sata_phy: sata-phy@1b400000 {
+@@ -477,6 +1059,95 @@
#reset-cells = <1>;
};
+
+ hs_phy_0: hs_phy_0 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
-+ reg = <0x110f8800 0x30>;
++ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ ss_phy_0: ss_phy_0 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
-+ reg = <0x110f8830 0x30>;
++ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
-+ usb3_0: usb3@110f8800 {
++ usb3_0: usb3@100f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
-+ reg = <0x110f8800 0x8000>;
++ reg = <0x100f8800 0x8000>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
+
+ status = "disabled";
+
-+ dwc3_0: dwc3@11000000 {
++ dwc3_0: dwc3@10000000 {
+ compatible = "snps,dwc3";
-+ reg = <0x11000000 0xcd00>;
-+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++ reg = <0x10000000 0xcd00>;
++ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_0>, <&ss_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+
+ hs_phy_1: hs_phy_1 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
-+ reg = <0x100f8800 0x30>;
++ reg = <0x110f8800 0x30>;
+ clocks = <&gcc USB30_1_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ ss_phy_1: ss_phy_1 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
-+ reg = <0x100f8830 0x30>;
++ reg = <0x110f8830 0x30>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
-+ usb3_1: usb3@100f8800 {
++ usb3_1: usb3@110f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
-+ reg = <0x100f8800 0x8000>;
++ reg = <0x110f8800 0x8000>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "core";
+
+
+ status = "disabled";
+
-+ dwc3_1: dwc3@10000000 {
++ dwc3_1: dwc3@11000000 {
+ compatible = "snps,dwc3";
-+ reg = <0x10000000 0xcd00>;
-+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++ reg = <0x11000000 0xcd00>;
++ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_1>, <&ss_phy_1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
pcie0: pci@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
-@@ -601,6 +1323,59 @@
- perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+@@ -738,6 +1409,59 @@
+ status = "disabled";
};
+ adm_dma: dma@18300000 {
+ status = "disabled";
+ };
+
-+ nand_controller: nand-controller@1ac00000 {
++ nand: nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
+ reg = <0x1ac00000 0x800>;
+
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
-@@ -676,4 +1559,17 @@
+@@ -813,4 +1537,17 @@
};
};
};
projects / openwrt / staging / aparcar.git / blobdiff