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realtek: Add support for Layer 2 Multicast
[openwrt/staging/zorun.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_debug("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port)
105 {
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
108 */
109 return DSA_TAG_PROTO_TRAILER;
110 }
111
112 /*
113 * Initialize all VLANS
114 */
115 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
116 {
117 struct rtl838x_vlan_info info;
118 int i;
119
120 pr_info("In %s\n", __func__);
121
122 priv->r->vlan_profile_setup(0);
123 priv->r->vlan_profile_setup(1);
124 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
125 priv->r->vlan_profile_dump(0);
126
127 info.fid = 0; // Default Forwarding ID / MSTI
128 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
129 info.hash_mc_fid = false; // Do the same for Multicast packets
130 info.profile_id = 0; // Use default Vlan Profile 0
131 info.tagged_ports = 0; // Initially no port members
132
133 // Initialize all vlans 0-4095
134 for (i = 0; i < MAX_VLANS; i ++)
135 priv->r->vlan_set_tagged(i, &info);
136
137 // Set forwarding action based on inner VLAN tag
138 for (i = 0; i < priv->cpu_port; i++)
139 priv->r->vlan_fwd_on_inner(i, true);
140 }
141
142 static int rtl83xx_setup(struct dsa_switch *ds)
143 {
144 int i;
145 struct rtl838x_switch_priv *priv = ds->priv;
146 u64 port_bitmap = BIT_ULL(priv->cpu_port);
147
148 pr_debug("%s called\n", __func__);
149
150 /* Disable MAC polling the PHY so that we can start configuration */
151 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
152
153 for (i = 0; i < ds->num_ports; i++)
154 priv->ports[i].enable = false;
155 priv->ports[priv->cpu_port].enable = true;
156
157 /* Isolate ports from each other: traffic only CPU <-> port */
158 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
159 * traffic from source port i to destination port j
160 */
161 for (i = 0; i < priv->cpu_port; i++) {
162 if (priv->ports[i].phy) {
163 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
164 priv->r->port_iso_ctrl(i));
165 port_bitmap |= BIT_ULL(i);
166 }
167 }
168 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
169
170 if (priv->family_id == RTL8380_FAMILY_ID)
171 rtl838x_print_matrix();
172 else
173 rtl839x_print_matrix();
174
175 rtl83xx_init_stats(priv);
176
177 rtl83xx_vlan_setup(priv);
178
179 ds->configure_vlan_while_not_filtering = true;
180
181 /* Enable MAC Polling PHY again */
182 rtl83xx_enable_phy_polling(priv);
183 pr_debug("Please wait until PHY is settled\n");
184 msleep(1000);
185 return 0;
186 }
187
188 static int rtl930x_setup(struct dsa_switch *ds)
189 {
190 int i;
191 struct rtl838x_switch_priv *priv = ds->priv;
192 u32 port_bitmap = BIT(priv->cpu_port);
193
194 pr_info("%s called\n", __func__);
195
196 // Enable CSTI STP mode
197 // sw_w32(1, RTL930X_ST_CTRL);
198
199 /* Disable MAC polling the PHY so that we can start configuration */
200 sw_w32(0, RTL930X_SMI_POLL_CTRL);
201
202 // Disable all ports except CPU port
203 for (i = 0; i < ds->num_ports; i++)
204 priv->ports[i].enable = false;
205 priv->ports[priv->cpu_port].enable = true;
206
207 for (i = 0; i < priv->cpu_port; i++) {
208 if (priv->ports[i].phy) {
209 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
210 port_bitmap |= BIT_ULL(i);
211 }
212 }
213 priv->r->traffic_set(priv->cpu_port, port_bitmap);
214
215 rtl930x_print_matrix();
216
217 // TODO: Initialize statistics
218
219 rtl83xx_vlan_setup(priv);
220
221 ds->configure_vlan_while_not_filtering = true;
222
223 rtl83xx_enable_phy_polling(priv);
224
225 return 0;
226 }
227
228 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
229 unsigned long *supported,
230 struct phylink_link_state *state)
231 {
232 struct rtl838x_switch_priv *priv = ds->priv;
233 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
234
235 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
236
237 if (!phy_interface_mode_is_rgmii(state->interface) &&
238 state->interface != PHY_INTERFACE_MODE_NA &&
239 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
240 state->interface != PHY_INTERFACE_MODE_MII &&
241 state->interface != PHY_INTERFACE_MODE_REVMII &&
242 state->interface != PHY_INTERFACE_MODE_GMII &&
243 state->interface != PHY_INTERFACE_MODE_QSGMII &&
244 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
245 state->interface != PHY_INTERFACE_MODE_SGMII) {
246 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
247 dev_err(ds->dev,
248 "Unsupported interface: %d for port %d\n",
249 state->interface, port);
250 return;
251 }
252
253 /* Allow all the expected bits */
254 phylink_set(mask, Autoneg);
255 phylink_set_port_modes(mask);
256 phylink_set(mask, Pause);
257 phylink_set(mask, Asym_Pause);
258
259 /* With the exclusion of MII and Reverse MII, we support Gigabit,
260 * including Half duplex
261 */
262 if (state->interface != PHY_INTERFACE_MODE_MII &&
263 state->interface != PHY_INTERFACE_MODE_REVMII) {
264 phylink_set(mask, 1000baseT_Full);
265 phylink_set(mask, 1000baseT_Half);
266 }
267
268 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
269 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
270 phylink_set(mask, 1000baseX_Full);
271
272 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
273 if (port >=48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
274 phylink_set(mask, 1000baseX_Full);
275
276 phylink_set(mask, 10baseT_Half);
277 phylink_set(mask, 10baseT_Full);
278 phylink_set(mask, 100baseT_Half);
279 phylink_set(mask, 100baseT_Full);
280
281 bitmap_and(supported, supported, mask,
282 __ETHTOOL_LINK_MODE_MASK_NBITS);
283 bitmap_and(state->advertising, state->advertising, mask,
284 __ETHTOOL_LINK_MODE_MASK_NBITS);
285 }
286
287 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
288 struct phylink_link_state *state)
289 {
290 struct rtl838x_switch_priv *priv = ds->priv;
291 u64 speed;
292 u64 link;
293
294 if (port < 0 || port > priv->cpu_port)
295 return -EINVAL;
296
297 /*
298 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
299 * state needs to be read twice in order to read a correct result.
300 * This would not be necessary for ports connected e.g. to RTL8218D
301 * PHYs.
302 */
303 state->link = 0;
304 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
305 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
306 if (link & BIT_ULL(port))
307 state->link = 1;
308 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
309
310 state->duplex = 0;
311 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
312 state->duplex = 1;
313
314 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
315 speed >>= (port % 16) << 1;
316 switch (speed & 0x3) {
317 case 0:
318 state->speed = SPEED_10;
319 break;
320 case 1:
321 state->speed = SPEED_100;
322 break;
323 case 2:
324 state->speed = SPEED_1000;
325 break;
326 case 3:
327 if (priv->family_id == RTL9300_FAMILY_ID
328 && (port == 24 || port == 26)) /* Internal serdes */
329 state->speed = SPEED_2500;
330 else
331 state->speed = SPEED_100; /* Is in fact 500Mbit */
332 }
333
334 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
335 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
336 state->pause |= MLO_PAUSE_RX;
337 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
338 state->pause |= MLO_PAUSE_TX;
339 return 1;
340 }
341
342 static void rtl83xx_config_interface(int port, phy_interface_t interface)
343 {
344 u32 old, int_shift, sds_shift;
345
346 switch (port) {
347 case 24:
348 int_shift = 0;
349 sds_shift = 5;
350 break;
351 case 26:
352 int_shift = 3;
353 sds_shift = 0;
354 break;
355 default:
356 return;
357 }
358
359 old = sw_r32(RTL838X_SDS_MODE_SEL);
360 switch (interface) {
361 case PHY_INTERFACE_MODE_1000BASEX:
362 if ((old >> sds_shift & 0x1f) == 4)
363 return;
364 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
365 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
366 break;
367 case PHY_INTERFACE_MODE_SGMII:
368 if ((old >> sds_shift & 0x1f) == 2)
369 return;
370 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
371 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
372 break;
373 default:
374 return;
375 }
376 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
377 }
378
379 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
380 unsigned int mode,
381 const struct phylink_link_state *state)
382 {
383 struct rtl838x_switch_priv *priv = ds->priv;
384 u32 reg;
385 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
386
387 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
388
389 // BUG: Make this work on RTL93XX
390 if (priv->family_id >= RTL9300_FAMILY_ID)
391 return;
392
393 if (port == priv->cpu_port) {
394 /* Set Speed, duplex, flow control
395 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
396 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
397 * | MEDIA_SEL
398 */
399 if (priv->family_id == RTL8380_FAMILY_ID) {
400 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
401 /* allow CRC errors on CPU-port */
402 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
403 } else {
404 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
405 }
406 return;
407 }
408
409 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
410 /* Auto-Negotiation does not work for MAC in RTL8390 */
411 if (priv->family_id == RTL8380_FAMILY_ID) {
412 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
413 pr_debug("PHY autonegotiates\n");
414 reg |= BIT(2);
415 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
416 rtl83xx_config_interface(port, state->interface);
417 return;
418 }
419 }
420
421 if (mode != MLO_AN_FIXED)
422 pr_debug("Fixed state.\n");
423
424 if (priv->family_id == RTL8380_FAMILY_ID) {
425 /* Clear id_mode_dis bit, and the existing port mode, let
426 * RGMII_MODE_EN bet set by mac_link_{up,down}
427 */
428 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
429
430 if (state->pause & MLO_PAUSE_TXRX_MASK) {
431 if (state->pause & MLO_PAUSE_TX)
432 reg |= TX_PAUSE_EN;
433 reg |= RX_PAUSE_EN;
434 }
435 }
436
437 reg &= ~(3 << speed_bit);
438 switch (state->speed) {
439 case SPEED_1000:
440 reg |= 2 << speed_bit;
441 break;
442 case SPEED_100:
443 reg |= 1 << speed_bit;
444 break;
445 }
446
447 if (priv->family_id == RTL8380_FAMILY_ID) {
448 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
449 if (state->link)
450 reg |= FORCE_LINK_EN;
451 if (state->duplex == DUPLEX_FULL)
452 reg |= DUPLX_MODE;
453 }
454
455 // Disable AN
456 if (priv->family_id == RTL8380_FAMILY_ID)
457 reg &= ~BIT(2);
458 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
459 }
460
461 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
462 unsigned int mode,
463 phy_interface_t interface)
464 {
465 struct rtl838x_switch_priv *priv = ds->priv;
466 /* Stop TX/RX to port */
467 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
468 }
469
470 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
471 unsigned int mode,
472 phy_interface_t interface,
473 struct phy_device *phydev)
474 {
475 struct rtl838x_switch_priv *priv = ds->priv;
476 /* Restart TX/RX to port */
477 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
478 }
479
480 static void rtl83xx_get_strings(struct dsa_switch *ds,
481 int port, u32 stringset, u8 *data)
482 {
483 int i;
484
485 if (stringset != ETH_SS_STATS)
486 return;
487
488 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
489 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
490 ETH_GSTRING_LEN);
491 }
492
493 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
494 uint64_t *data)
495 {
496 struct rtl838x_switch_priv *priv = ds->priv;
497 const struct rtl83xx_mib_desc *mib;
498 int i;
499 u64 h;
500
501 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
502 mib = &rtl83xx_mib[i];
503
504 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
505 if (mib->size == 2) {
506 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
507 data[i] |= h << 32;
508 }
509 }
510 }
511
512 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
513 {
514 if (sset != ETH_SS_STATS)
515 return 0;
516
517 return ARRAY_SIZE(rtl83xx_mib);
518 }
519
520 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
521 struct phy_device *phydev)
522 {
523 struct rtl838x_switch_priv *priv = ds->priv;
524 u64 v;
525
526 pr_debug("%s: %x %d", __func__, (u32) priv, port);
527 priv->ports[port].enable = true;
528
529 /* enable inner tagging on egress, do not keep any tags */
530 if (priv->family_id == RTL9310_FAMILY_ID)
531 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
532 else
533 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
534
535 if (dsa_is_cpu_port(ds, port))
536 return 0;
537
538 /* add port to switch mask of CPU_PORT */
539 priv->r->traffic_enable(priv->cpu_port, port);
540
541 /* add all other ports in the same bridge to switch mask of port */
542 v = priv->r->traffic_get(port);
543 v |= priv->ports[port].pm;
544 priv->r->traffic_set(port, v);
545
546 // TODO: Figure out if this is necessary
547 if (priv->family_id == RTL9300_FAMILY_ID) {
548 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
549 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
550 }
551
552 return 0;
553 }
554
555 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
556 {
557 struct rtl838x_switch_priv *priv = ds->priv;
558 u64 v;
559
560 pr_debug("%s %x: %d", __func__, (u32)priv, port);
561 /* you can only disable user ports */
562 if (!dsa_is_user_port(ds, port))
563 return;
564
565 // BUG: This does not work on RTL931X
566 /* remove port from switch mask of CPU_PORT */
567 priv->r->traffic_disable(priv->cpu_port, port);
568
569 /* remove all other ports in the same bridge from switch mask of port */
570 v = priv->r->traffic_get(port);
571 v &= ~priv->ports[port].pm;
572 priv->r->traffic_set(port, v);
573
574 priv->ports[port].enable = false;
575 }
576
577 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
578 struct ethtool_eee *e)
579 {
580 struct rtl838x_switch_priv *priv = ds->priv;
581
582 if (e->eee_enabled && !priv->eee_enabled) {
583 pr_info("Globally enabling EEE\n");
584 priv->r->init_eee(priv, true);
585 }
586
587 priv->r->port_eee_set(priv, port, e->eee_enabled);
588
589 if (e->eee_enabled)
590 pr_info("Enabled EEE for port %d\n", port);
591 else
592 pr_info("Disabled EEE for port %d\n", port);
593 return 0;
594 }
595
596 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
597 struct ethtool_eee *e)
598 {
599 struct rtl838x_switch_priv *priv = ds->priv;
600
601 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
602
603 priv->r->eee_port_ability(priv, e, port);
604
605 e->eee_enabled = priv->ports[port].eee_enabled;
606
607 e->eee_active = !!(e->advertised & e->lp_advertised);
608
609 return 0;
610 }
611
612 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
613 struct ethtool_eee *e)
614 {
615 struct rtl838x_switch_priv *priv = ds->priv;
616
617 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
618 | SUPPORTED_2500baseX_Full;
619
620 priv->r->eee_port_ability(priv, e, port);
621
622 e->eee_enabled = priv->ports[port].eee_enabled;
623
624 e->eee_active = !!(e->advertised & e->lp_advertised);
625
626 return 0;
627 }
628
629 /*
630 * Set Switch L2 Aging time, t is time in milliseconds
631 * t = 0: aging is disabled
632 */
633 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
634 {
635 struct rtl838x_switch_priv *priv = ds->priv;
636 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
637
638 /* Convert time in mseconds to internal value */
639 if (t > 0x10000000) { /* Set to maximum */
640 t = t_max;
641 } else {
642 if (priv->family_id == RTL8380_FAMILY_ID)
643 t = ((t * 625) / 1000 + 127) / 128;
644 else
645 t = (t * 5 + 2) / 3;
646 }
647 sw_w32(t, priv->r->l2_ctrl_1);
648 return 0;
649 }
650
651 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
652 struct net_device *bridge)
653 {
654 struct rtl838x_switch_priv *priv = ds->priv;
655 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
656 int i;
657
658 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
659 mutex_lock(&priv->reg_mutex);
660 for (i = 0; i < ds->num_ports; i++) {
661 /* Add this port to the port matrix of the other ports in the
662 * same bridge. If the port is disabled, port matrix is kept
663 * and not being setup until the port becomes enabled.
664 */
665 if (dsa_is_user_port(ds, i) && i != port) {
666 if (dsa_to_port(ds, i)->bridge_dev != bridge)
667 continue;
668 if (priv->ports[i].enable)
669 priv->r->traffic_enable(i, port);
670
671 priv->ports[i].pm |= BIT_ULL(port);
672 port_bitmap |= BIT_ULL(i);
673 }
674 }
675
676 /* Add all other ports to this port matrix. */
677 if (priv->ports[port].enable) {
678 priv->r->traffic_enable(priv->cpu_port, port);
679 v = priv->r->traffic_get(port);
680 v |= port_bitmap;
681 priv->r->traffic_set(port, v);
682 }
683 priv->ports[port].pm |= port_bitmap;
684 mutex_unlock(&priv->reg_mutex);
685
686 return 0;
687 }
688
689 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
690 struct net_device *bridge)
691 {
692 struct rtl838x_switch_priv *priv = ds->priv;
693 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
694 int i;
695
696 pr_debug("%s %x: %d", __func__, (u32)priv, port);
697 mutex_lock(&priv->reg_mutex);
698 for (i = 0; i < ds->num_ports; i++) {
699 /* Remove this port from the port matrix of the other ports
700 * in the same bridge. If the port is disabled, port matrix
701 * is kept and not being setup until the port becomes enabled.
702 * And the other port's port matrix cannot be broken when the
703 * other port is still a VLAN-aware port.
704 */
705 if (dsa_is_user_port(ds, i) && i != port) {
706 if (dsa_to_port(ds, i)->bridge_dev != bridge)
707 continue;
708 if (priv->ports[i].enable)
709 priv->r->traffic_disable(i, port);
710
711 priv->ports[i].pm |= BIT_ULL(port);
712 port_bitmap &= ~BIT_ULL(i);
713 }
714 }
715
716 /* Add all other ports to this port matrix. */
717 if (priv->ports[port].enable) {
718 v = priv->r->traffic_get(port);
719 v |= port_bitmap;
720 priv->r->traffic_set(port, v);
721 }
722 priv->ports[port].pm &= ~port_bitmap;
723
724 mutex_unlock(&priv->reg_mutex);
725 }
726
727 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
728 {
729 u32 msti = 0;
730 u32 port_state[4];
731 int index, bit;
732 int pos = port;
733 struct rtl838x_switch_priv *priv = ds->priv;
734 int n = priv->port_width << 1;
735
736 /* Ports above or equal CPU port can never be configured */
737 if (port >= priv->cpu_port)
738 return;
739
740 mutex_lock(&priv->reg_mutex);
741
742 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
743 * have 64 bit fields, 839x and 931x have 128 bit fields
744 */
745 if (priv->family_id == RTL8390_FAMILY_ID)
746 pos += 12;
747 if (priv->family_id == RTL9300_FAMILY_ID)
748 pos += 3;
749 if (priv->family_id == RTL9310_FAMILY_ID)
750 pos += 8;
751
752 index = n - (pos >> 4) - 1;
753 bit = (pos << 1) % 32;
754
755 priv->r->stp_get(priv, msti, port_state);
756
757 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
758 port_state[index] &= ~(3 << bit);
759
760 switch (state) {
761 case BR_STATE_DISABLED: /* 0 */
762 port_state[index] |= (0 << bit);
763 break;
764 case BR_STATE_BLOCKING: /* 4 */
765 case BR_STATE_LISTENING: /* 1 */
766 port_state[index] |= (1 << bit);
767 break;
768 case BR_STATE_LEARNING: /* 2 */
769 port_state[index] |= (2 << bit);
770 break;
771 case BR_STATE_FORWARDING: /* 3*/
772 port_state[index] |= (3 << bit);
773 default:
774 break;
775 }
776
777 priv->r->stp_set(priv, msti, port_state);
778
779 mutex_unlock(&priv->reg_mutex);
780 }
781
782 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
783 {
784 struct rtl838x_switch_priv *priv = ds->priv;
785 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
786
787 pr_debug("FAST AGE port %d\n", port);
788 mutex_lock(&priv->reg_mutex);
789 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
790 * port fields:
791 * 0-4: Replacing port
792 * 5-9: Flushed/replaced port
793 * 10-21: FVID
794 * 22: Entry types: 1: dynamic, 0: also static
795 * 23: Match flush port
796 * 24: Match FVID
797 * 25: Flush (0) or replace (1) L2 entries
798 * 26: Status of action (1: Start, 0: Done)
799 */
800 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
801
802 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
803
804 mutex_unlock(&priv->reg_mutex);
805 }
806
807 void rtl930x_fast_age(struct dsa_switch *ds, int port)
808 {
809 struct rtl838x_switch_priv *priv = ds->priv;
810
811 pr_debug("FAST AGE port %d\n", port);
812 mutex_lock(&priv->reg_mutex);
813 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
814
815 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
816
817 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
818
819 mutex_unlock(&priv->reg_mutex);
820 }
821
822 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
823 bool vlan_filtering)
824 {
825 struct rtl838x_switch_priv *priv = ds->priv;
826
827 pr_debug("%s: port %d\n", __func__, port);
828 mutex_lock(&priv->reg_mutex);
829
830 if (vlan_filtering) {
831 /* Enable ingress and egress filtering
832 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
833 * the filter action:
834 * 0: Always Forward
835 * 1: Drop packet
836 * 2: Trap packet to CPU port
837 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
838 */
839 if (port != priv->cpu_port)
840 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
841 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
842 sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
843 } else {
844 /* Disable ingress and egress filtering */
845 if (port != priv->cpu_port)
846 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
847 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
848 sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
849 }
850
851 /* Do we need to do something to the CPU-Port, too? */
852 mutex_unlock(&priv->reg_mutex);
853
854 return 0;
855 }
856
857 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
858 const struct switchdev_obj_port_vlan *vlan)
859 {
860 struct rtl838x_vlan_info info;
861 struct rtl838x_switch_priv *priv = ds->priv;
862
863 priv->r->vlan_tables_read(0, &info);
864
865 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
866 info.tagged_ports, info.untagged_ports, info.profile_id,
867 info.hash_mc_fid, info.hash_uc_fid, info.fid);
868
869 priv->r->vlan_tables_read(1, &info);
870 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
871 info.tagged_ports, info.untagged_ports, info.profile_id,
872 info.hash_mc_fid, info.hash_uc_fid, info.fid);
873 priv->r->vlan_set_untagged(1, info.untagged_ports);
874 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
875
876 priv->r->vlan_set_tagged(1, &info);
877 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
878
879 mutex_unlock(&priv->reg_mutex);
880 return 0;
881 }
882
883 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
884 const struct switchdev_obj_port_vlan *vlan)
885 {
886 struct rtl838x_vlan_info info;
887 struct rtl838x_switch_priv *priv = ds->priv;
888 int v;
889
890 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
891 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
892
893 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
894 dev_err(priv->dev, "VLAN out of range: %d - %d",
895 vlan->vid_begin, vlan->vid_end);
896 return;
897 }
898
899 mutex_lock(&priv->reg_mutex);
900
901 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
902 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
903 if (!v)
904 continue;
905 /* Set both inner and outer PVID of the port */
906 sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
907 priv->ports[port].pvid = vlan->vid_end;
908 }
909 }
910
911 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
912 if (!v)
913 continue;
914
915 /* Get port memberships of this vlan */
916 priv->r->vlan_tables_read(v, &info);
917
918 /* new VLAN? */
919 if (!info.tagged_ports) {
920 info.fid = 0;
921 info.hash_mc_fid = false;
922 info.hash_uc_fid = false;
923 info.profile_id = 0;
924 }
925
926 /* sanitize untagged_ports - must be a subset */
927 if (info.untagged_ports & ~info.tagged_ports)
928 info.untagged_ports = 0;
929
930 info.tagged_ports |= BIT_ULL(port);
931 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
932 info.untagged_ports |= BIT_ULL(port);
933
934 priv->r->vlan_set_untagged(v, info.untagged_ports);
935 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
936
937 priv->r->vlan_set_tagged(v, &info);
938 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
939 }
940
941 mutex_unlock(&priv->reg_mutex);
942 }
943
944 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
945 const struct switchdev_obj_port_vlan *vlan)
946 {
947 struct rtl838x_vlan_info info;
948 struct rtl838x_switch_priv *priv = ds->priv;
949 int v;
950 u16 pvid;
951
952 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
953 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
954
955 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
956 dev_err(priv->dev, "VLAN out of range: %d - %d",
957 vlan->vid_begin, vlan->vid_end);
958 return -ENOTSUPP;
959 }
960
961 mutex_lock(&priv->reg_mutex);
962 pvid = priv->ports[port].pvid;
963
964 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
965 /* Reset to default if removing the current PVID */
966 if (v == pvid)
967 sw_w32(0, priv->r->vlan_port_pb + (port << 2));
968
969 /* Get port memberships of this vlan */
970 priv->r->vlan_tables_read(v, &info);
971
972 /* remove port from both tables */
973 info.untagged_ports &= (~BIT_ULL(port));
974 /* always leave vid 1 */
975 if (v != 1)
976 info.tagged_ports &= (~BIT_ULL(port));
977
978 priv->r->vlan_set_untagged(v, info.untagged_ports);
979 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
980
981 priv->r->vlan_set_tagged(v, &info);
982 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
983 }
984 mutex_unlock(&priv->reg_mutex);
985
986 return 0;
987 }
988
989 static void dump_l2_entry(struct rtl838x_l2_entry *e)
990 {
991 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
992 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
993 e->vid, e->rvid, e->port, e->valid);
994
995 if (e->type != L2_MULTICAST) {
996 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
997 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
998 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
999 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1000 }
1001 if (e->type == L2_MULTICAST)
1002 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1003 if (e->is_ip_mc || e->is_ipv6_mc)
1004 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1005 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1006 pr_info(" stack_dev: %d\n", e->stack_dev);
1007 if (e->next_hop)
1008 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1009 }
1010
1011 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1012 {
1013 e->is_ip_mc = e->is_ipv6_mc = false;
1014 e->valid = true;
1015 e->age = 3;
1016 e->port = port,
1017 e->vid = vid;
1018 u64_to_ether_addr(mac, e->mac);
1019 }
1020
1021 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1022 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1023 {
1024 e->is_ip_mc = e->is_ipv6_mc = false;
1025 e->valid = true;
1026 e->mc_portmask_index = mc_group;
1027 e->type = L2_MULTICAST;
1028 e->rvid = e->vid = vid;
1029 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1030 u64_to_ether_addr(mac, e->mac);
1031 }
1032
1033 /*
1034 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1035 * over the entries in the bucket until either a matching entry is found or an empty slot
1036 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1037 * when an empty slot was found and must exist is false, the index of the slot is returned
1038 * when no slots are available returns -1
1039 */
1040 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1041 bool must_exist, struct rtl838x_l2_entry *e)
1042 {
1043 int i, idx = -1;
1044 u32 key = priv->r->l2_hash_key(priv, seed);
1045 u64 entry;
1046
1047 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1048 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1049 for (i = 0; i < priv->l2_bucket_size; i++) {
1050 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1051 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1052 if (must_exist && !e->valid)
1053 continue;
1054 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1055 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1056 break;
1057 }
1058 }
1059
1060 return idx;
1061 }
1062
1063 /*
1064 * Uses the seed to identify an entry in the CAM by looping over all its entries
1065 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1066 * when an empty slot was found the index of the slot is returned
1067 * when no slots are available returns -1
1068 */
1069 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1070 bool must_exist, struct rtl838x_l2_entry *e)
1071 {
1072 int i, idx = -1;
1073 u64 entry;
1074
1075 for (i = 0; i < 64; i++) {
1076 entry = priv->r->read_cam(i, e);
1077 if (!must_exist && !e->valid) {
1078 if (idx < 0) /* First empty entry? */
1079 idx = i;
1080 break;
1081 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1082 pr_debug("Found entry in CAM\n");
1083 idx = i;
1084 break;
1085 }
1086 }
1087 return idx;
1088 }
1089
1090 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1091 const unsigned char *addr, u16 vid)
1092 {
1093 struct rtl838x_switch_priv *priv = ds->priv;
1094 u64 mac = ether_addr_to_u64(addr);
1095 struct rtl838x_l2_entry e;
1096 int err = 0, idx;
1097 u64 seed = priv->r->l2_hash_seed(mac, vid);
1098
1099 mutex_lock(&priv->reg_mutex);
1100
1101 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1102
1103 // Found an existing or empty entry
1104 if (idx >= 0) {
1105 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1106 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1107 goto out;
1108 }
1109
1110 // Hash buckets full, try CAM
1111 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1112
1113 if (idx >= 0) {
1114 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1115 priv->r->write_cam(idx, &e);
1116 goto out;
1117 }
1118
1119 err = -ENOTSUPP;
1120 out:
1121 mutex_unlock(&priv->reg_mutex);
1122 return err;
1123 }
1124
1125 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1126 const unsigned char *addr, u16 vid)
1127 {
1128 struct rtl838x_switch_priv *priv = ds->priv;
1129 u64 mac = ether_addr_to_u64(addr);
1130 struct rtl838x_l2_entry e;
1131 int err = 0, idx;
1132 u64 seed = priv->r->l2_hash_seed(mac, vid);
1133
1134 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1135 mutex_lock(&priv->reg_mutex);
1136
1137 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1138
1139 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1140 if (idx >= 0) {
1141 e.valid = false;
1142 dump_l2_entry(&e);
1143 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1144 goto out;
1145 }
1146
1147 /* Check CAM for spillover from hash buckets */
1148 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1149
1150 if (idx >= 0) {
1151 e.valid = false;
1152 priv->r->write_cam(idx, &e);
1153 goto out;
1154 }
1155 err = -ENOENT;
1156 out:
1157 mutex_unlock(&priv->reg_mutex);
1158 return err;
1159 }
1160
1161 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1162 dsa_fdb_dump_cb_t *cb, void *data)
1163 {
1164 struct rtl838x_l2_entry e;
1165 struct rtl838x_switch_priv *priv = ds->priv;
1166 int i;
1167 u32 fid, pkey;
1168 u64 mac;
1169
1170 mutex_lock(&priv->reg_mutex);
1171
1172 for (i = 0; i < priv->fib_entries; i++) {
1173 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1174
1175 if (!e.valid)
1176 continue;
1177
1178 if (e.port == port) {
1179 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1180 mac = ether_addr_to_u64(&e.mac[0]);
1181 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1182 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1183 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1184 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1185 dump_l2_entry(&e);
1186 u64 seed = priv->r->l2_hash_seed(mac, e.rvid);
1187 u32 key = priv->r->l2_hash_key(priv, seed);
1188 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1189 cb(e.mac, e.vid, e.is_static, data);
1190 }
1191 if (e.type == L2_MULTICAST) {
1192 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1193 if (portmask & BIT_ULL(port)) {
1194 dump_l2_entry(&e);
1195 pr_info(" PM: %016llx\n", portmask);
1196 }
1197 }
1198 }
1199
1200 for (i = 0; i < 64; i++) {
1201 priv->r->read_cam(i, &e);
1202
1203 if (!e.valid)
1204 continue;
1205
1206 if (e.port == port)
1207 cb(e.mac, e.vid, e.is_static, data);
1208 }
1209
1210 mutex_unlock(&priv->reg_mutex);
1211 return 0;
1212 }
1213
1214 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1215 const struct switchdev_obj_port_mdb *mdb)
1216 {
1217 struct rtl838x_switch_priv *priv = ds->priv;
1218
1219 if (priv->id >= 0x9300)
1220 return -EOPNOTSUPP;
1221
1222 return 0;
1223 }
1224
1225 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
1226 {
1227 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
1228 u64 portmask;
1229
1230 if (mc_group >= MAX_MC_GROUPS - 1)
1231 return -1;
1232
1233 pr_debug("Using MC group %d\n", mc_group);
1234 set_bit(mc_group, priv->mc_group_bm);
1235 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
1236 portmask = BIT_ULL(port);
1237 priv->r->write_mcast_pmask(mc_group, portmask);
1238
1239 return mc_group;
1240 }
1241
1242 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1243 {
1244 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1245
1246 portmask |= BIT_ULL(port);
1247 priv->r->write_mcast_pmask(mc_group, portmask);
1248
1249 return portmask;
1250 }
1251
1252 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1253 {
1254 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1255
1256 portmask &= ~BIT_ULL(port);
1257 priv->r->write_mcast_pmask(mc_group, portmask);
1258 if (!portmask)
1259 clear_bit(mc_group, priv->mc_group_bm);
1260
1261 return portmask;
1262 }
1263
1264 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1265 const struct switchdev_obj_port_mdb *mdb)
1266 {
1267 struct rtl838x_switch_priv *priv = ds->priv;
1268 u64 mac = ether_addr_to_u64(mdb->addr);
1269 struct rtl838x_l2_entry e;
1270 int err = 0, idx;
1271 int vid = mdb->vid;
1272 u64 seed = priv->r->l2_hash_seed(mac, vid);
1273 int mc_group;
1274
1275 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1276 mutex_lock(&priv->reg_mutex);
1277
1278 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1279
1280 // Found an existing or empty entry
1281 if (idx >= 0) {
1282 if (e.valid) {
1283 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1284 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1285 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1286 } else {
1287 pr_debug("New entry for seed %016llx\n", seed);
1288 mc_group = rtl83xx_mc_group_alloc(priv, port);
1289 if (mc_group < 0) {
1290 err = -ENOTSUPP;
1291 goto out;
1292 }
1293 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1294 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1295 }
1296 goto out;
1297 }
1298
1299 // Hash buckets full, try CAM
1300 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1301
1302 if (idx >= 0) {
1303 if (e.valid) {
1304 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1305 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1306 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1307 } else {
1308 pr_debug("New entry\n");
1309 mc_group = rtl83xx_mc_group_alloc(priv, port);
1310 if (mc_group < 0) {
1311 err = -ENOTSUPP;
1312 goto out;
1313 }
1314 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1315 priv->r->write_cam(idx, &e);
1316 }
1317 goto out;
1318 }
1319
1320 err = -ENOTSUPP;
1321 out:
1322 mutex_unlock(&priv->reg_mutex);
1323 if (err)
1324 dev_err(ds->dev, "failed to add MDB entry\n");
1325 }
1326
1327 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1328 const struct switchdev_obj_port_mdb *mdb)
1329 {
1330 struct rtl838x_switch_priv *priv = ds->priv;
1331 u64 mac = ether_addr_to_u64(mdb->addr);
1332 struct rtl838x_l2_entry e;
1333 int err = 0, idx;
1334 int vid = mdb->vid;
1335 u64 seed = priv->r->l2_hash_seed(mac, vid);
1336 u64 portmask;
1337
1338 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1339 mutex_lock(&priv->reg_mutex);
1340
1341 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1342
1343 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1344 if (idx >= 0) {
1345 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1346 if (!portmask) {
1347 e.valid = false;
1348 // dump_l2_entry(&e);
1349 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1350 }
1351 goto out;
1352 }
1353
1354 /* Check CAM for spillover from hash buckets */
1355 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1356
1357 if (idx >= 0) {
1358 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1359 if (!portmask) {
1360 e.valid = false;
1361 // dump_l2_entry(&e);
1362 priv->r->write_cam(idx, &e);
1363 }
1364 goto out;
1365 }
1366 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1367 out:
1368 mutex_unlock(&priv->reg_mutex);
1369 return err;
1370 }
1371
1372 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1373 struct dsa_mall_mirror_tc_entry *mirror,
1374 bool ingress)
1375 {
1376 /* We support 4 mirror groups, one destination port per group */
1377 int group;
1378 struct rtl838x_switch_priv *priv = ds->priv;
1379 int ctrl_reg, dpm_reg, spm_reg;
1380
1381 pr_debug("In %s\n", __func__);
1382
1383 for (group = 0; group < 4; group++) {
1384 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1385 break;
1386 }
1387 if (group >= 4) {
1388 for (group = 0; group < 4; group++) {
1389 if (priv->mirror_group_ports[group] < 0)
1390 break;
1391 }
1392 }
1393
1394 if (group >= 4)
1395 return -ENOSPC;
1396
1397 ctrl_reg = priv->r->mir_ctrl + group * 4;
1398 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1399 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1400
1401 pr_debug("Using group %d\n", group);
1402 mutex_lock(&priv->reg_mutex);
1403
1404 if (priv->family_id == RTL8380_FAMILY_ID) {
1405 /* Enable mirroring to port across VLANs (bit 11) */
1406 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1407 } else {
1408 /* Enable mirroring to destination port */
1409 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1410 }
1411
1412 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1413 mutex_unlock(&priv->reg_mutex);
1414 return -EEXIST;
1415 }
1416 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1417 mutex_unlock(&priv->reg_mutex);
1418 return -EEXIST;
1419 }
1420
1421 if (ingress)
1422 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1423 else
1424 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1425
1426 priv->mirror_group_ports[group] = mirror->to_local_port;
1427 mutex_unlock(&priv->reg_mutex);
1428 return 0;
1429 }
1430
1431 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1432 struct dsa_mall_mirror_tc_entry *mirror)
1433 {
1434 int group = 0;
1435 struct rtl838x_switch_priv *priv = ds->priv;
1436 int ctrl_reg, dpm_reg, spm_reg;
1437
1438 pr_debug("In %s\n", __func__);
1439 for (group = 0; group < 4; group++) {
1440 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1441 break;
1442 }
1443 if (group >= 4)
1444 return;
1445
1446 ctrl_reg = priv->r->mir_ctrl + group * 4;
1447 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1448 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1449
1450 mutex_lock(&priv->reg_mutex);
1451 if (mirror->ingress) {
1452 /* Ingress, clear source port matrix */
1453 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1454 } else {
1455 /* Egress, clear destination port matrix */
1456 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1457 }
1458
1459 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1460 priv->mirror_group_ports[group] = -1;
1461 sw_w32(0, ctrl_reg);
1462 }
1463
1464 mutex_unlock(&priv->reg_mutex);
1465 }
1466
1467 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1468 {
1469 u32 val;
1470 u32 offset = 0;
1471 struct rtl838x_switch_priv *priv = ds->priv;
1472
1473 if (phy_addr >= 24 && phy_addr <= 27
1474 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1475 if (phy_addr == 26)
1476 offset = 0x100;
1477 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1478 return val;
1479 }
1480
1481 read_phy(phy_addr, 0, phy_reg, &val);
1482 return val;
1483 }
1484
1485 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1486 {
1487 u32 offset = 0;
1488 struct rtl838x_switch_priv *priv = ds->priv;
1489
1490 if (phy_addr >= 24 && phy_addr <= 27
1491 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1492 if (phy_addr == 26)
1493 offset = 0x100;
1494 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1495 return 0;
1496 }
1497 return write_phy(phy_addr, 0, phy_reg, val);
1498 }
1499
1500 const struct dsa_switch_ops rtl83xx_switch_ops = {
1501 .get_tag_protocol = rtl83xx_get_tag_protocol,
1502 .setup = rtl83xx_setup,
1503
1504 .phy_read = dsa_phy_read,
1505 .phy_write = dsa_phy_write,
1506
1507 .phylink_validate = rtl83xx_phylink_validate,
1508 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1509 .phylink_mac_config = rtl83xx_phylink_mac_config,
1510 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1511 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1512
1513 .get_strings = rtl83xx_get_strings,
1514 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1515 .get_sset_count = rtl83xx_get_sset_count,
1516
1517 .port_enable = rtl83xx_port_enable,
1518 .port_disable = rtl83xx_port_disable,
1519
1520 .get_mac_eee = rtl83xx_get_mac_eee,
1521 .set_mac_eee = rtl83xx_set_mac_eee,
1522
1523 .set_ageing_time = rtl83xx_set_l2aging,
1524 .port_bridge_join = rtl83xx_port_bridge_join,
1525 .port_bridge_leave = rtl83xx_port_bridge_leave,
1526 .port_stp_state_set = rtl83xx_port_stp_state_set,
1527 .port_fast_age = rtl83xx_fast_age,
1528
1529 .port_vlan_filtering = rtl83xx_vlan_filtering,
1530 .port_vlan_prepare = rtl83xx_vlan_prepare,
1531 .port_vlan_add = rtl83xx_vlan_add,
1532 .port_vlan_del = rtl83xx_vlan_del,
1533
1534 .port_fdb_add = rtl83xx_port_fdb_add,
1535 .port_fdb_del = rtl83xx_port_fdb_del,
1536 .port_fdb_dump = rtl83xx_port_fdb_dump,
1537
1538 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1539 .port_mdb_add = rtl83xx_port_mdb_add,
1540 .port_mdb_del = rtl83xx_port_mdb_del,
1541
1542 .port_mirror_add = rtl83xx_port_mirror_add,
1543 .port_mirror_del = rtl83xx_port_mirror_del,
1544 };
1545
1546 const struct dsa_switch_ops rtl930x_switch_ops = {
1547 .get_tag_protocol = rtl83xx_get_tag_protocol,
1548 .setup = rtl930x_setup,
1549
1550 .phy_read = dsa_phy_read,
1551 .phy_write = dsa_phy_write,
1552
1553 .phylink_validate = rtl83xx_phylink_validate,
1554 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1555 .phylink_mac_config = rtl83xx_phylink_mac_config,
1556 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1557 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1558
1559 .get_strings = rtl83xx_get_strings,
1560 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1561 .get_sset_count = rtl83xx_get_sset_count,
1562
1563 .port_enable = rtl83xx_port_enable,
1564 .port_disable = rtl83xx_port_disable,
1565
1566 .get_mac_eee = rtl93xx_get_mac_eee,
1567 .set_mac_eee = rtl83xx_set_mac_eee,
1568
1569 .set_ageing_time = rtl83xx_set_l2aging,
1570 .port_bridge_join = rtl83xx_port_bridge_join,
1571 .port_bridge_leave = rtl83xx_port_bridge_leave,
1572 .port_stp_state_set = rtl83xx_port_stp_state_set,
1573 .port_fast_age = rtl930x_fast_age,
1574
1575 .port_vlan_filtering = rtl83xx_vlan_filtering,
1576 .port_vlan_prepare = rtl83xx_vlan_prepare,
1577 .port_vlan_add = rtl83xx_vlan_add,
1578 .port_vlan_del = rtl83xx_vlan_del,
1579
1580 .port_fdb_add = rtl83xx_port_fdb_add,
1581 .port_fdb_del = rtl83xx_port_fdb_del,
1582 .port_fdb_dump = rtl83xx_port_fdb_dump,
1583
1584 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1585 .port_mdb_add = rtl83xx_port_mdb_add,
1586 .port_mdb_del = rtl83xx_port_mdb_del,
1587
1588 };
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